Display driving integrated circuit and control method thereof

Abstract

The application discloses a display driving integrated circuit and a control method thereof, relates to the technical field of display, and mainly aims to; the display driving integrated circuit comprises a bus, a static random access memory divided into multiple storage areas, and multiple transmission lines connected with the bus; wherein each storage area comprises at least two storage blocks; each transmission line is connected with multiple storage blocks respectively, and the storage blocks connected with each transmission line are not repeated.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display driver integrated circuit and its control method. Background Technology

[0002] A display driver integrated circuit (DDIC) is an integrated circuit used to drive display devices such as LCD (liquid crystal display), LED (light emitting diode), and OLED (organic light emitting diode). The DDIC includes a frame memory. The frame memory stores image data transmitted from the host computer at a certain speed. When the display device needs to display data, the stored image data is read and output to the pixel units of the display device for display purposes.

[0003] Currently, static random access memory (SRAM) is typically chosen as the frame memory. Although SRAM can output image data at drive frequencies above 60Hz, its capacity is related to its physical size, and the capacity of the selected SRAM is limited by the size of the area reserved for it by the display driver integrated circuit.

[0004] It is evident that the size of the area reserved for static random access memory (SRAM) by the display driver integrated circuit directly affects the choice of SRAM capacity. Therefore, optimizing the wiring structure of the display driver integrated circuit to utilize the largest possible SRAM capacity within a limited space is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, this application proposes a display driver integrated circuit and its control method, the main purpose of which is to optimize the wiring structure of the display driver integrated circuit in order to apply a static random access memory with the largest possible capacity within a limited space.

[0006] To achieve the above objectives, this application mainly provides the following technical solutions:

[0007] In a first aspect, this application provides a display driver integrated circuit, which includes: a bus, a static random access memory divided into multiple memory areas, and multiple transmission lines connected to the bus; wherein each memory area includes at least two memory blocks; each transmission line is respectively connected to multiple memory blocks, and the memory blocks connected to each transmission line are not repeated.

[0008] In some embodiments, the transmission line is turned on when the storage block connected to it needs to output image data and transmits the image data to the bus; and turned off when the storage block connected to it does not need to output image data; the bus is used for transmitting and processing the image data.

[0009] In some embodiments, the transmission line includes a switch module and a first controller; wherein, the input terminal of the switch module is connected to a corresponding memory block, the output terminal is connected to the bus, and the control terminal is connected to the first controller; the first controller is configured to send an enable signal to the switch module when the memory block connected to the input terminal needs to output image data, and send a disable signal to the switch module when the memory block connected to the input terminal does not need to output image data; the switch module is configured to be enabled by the enable signal and disabled by the disable signal.

[0010] In some embodiments, the switching module is a tri-state buffer or a MOSFET.

[0011] In some embodiments, the total number of transmission lines is a first number, and each storage area includes the first number of storage blocks; the storage blocks in the same storage area have a first order; storage blocks with the same order position in the first order corresponding to each storage area are connected to the same transmission line; wherein, the first order describes the order in which the image data of each storage block in the corresponding storage area is output.

[0012] In some embodiments, the number of transmission lines is the same as the total number of storage areas; storage blocks within the same storage area are connected to the same transmission line, and different storage areas correspond to different transmission lines.

[0013] In some embodiments, the display driver integrated circuit further includes a processing module and a shift register; the processing module is used to receive image data transmitted by the bus, process the image data, and transmit the processed data to the shift register; the shift register is used to store the processed data based on the display timing of the image data in the corresponding pixel unit.

[0014] Secondly, this application provides a control method for a display driver integrated circuit, applied to the display driver integrated circuit as described in the first aspect, the method comprising:

[0015] When it is necessary to scan the rows of pixels to be displayed, the storage blocks in the static random access memory are traversed based on the second sorting, and data reading operations are performed on the currently traversed storage block so that the currently traversed storage block transmits the stored image data to the corresponding connected transmission line.

[0016] Among them, the number of consecutive storage blocks belonging to the same storage area in the second sorting is no greater than the second number, which is a positive integer greater than or equal to 1.

[0017] In some embodiments, the method further includes: when image data storage of the pixel row to be displayed is required, traversing the storage blocks in the static random access memory based on the second sorting, and performing a data writing operation on the currently traversed storage block, so that the currently traversed storage block stores the written image data.

[0018] In some embodiments, when the second quantity is 1 and the storage blocks in the same storage area have a target sort, the second sort is composed of multiple third sorts; all third sorts cover all storage blocks in the static random access memory, and the storage blocks in different third sorts are not repeated; each third sort is composed of storage blocks with the same sort position in the target sort corresponding to each storage area, and the storage blocks involved in the third sort are all sorted according to the traversal order of each storage area.

[0019] In some embodiments, when the second quantity is greater than 1, the second sort is composed of multiple fourth sorts, all of which cover all storage blocks in the static random access memory, and the storage blocks in different fourth sorts are not repeated; each of the fourth sorts is used to define the traversal order of multiple storage blocks; wherein, the multiple storage blocks involve all storage areas of the static random access memory, the multiple storage blocks are sorted according to the traversal order of each storage area, and the storage blocks belonging to the same storage area are sorted consecutively, and the total number of storage blocks belonging to the same storage area is not greater than the second quantity.

[0020] Thirdly, this application provides a frame storage controller for a display driver integrated circuit, wherein the frame storage controller applies the control method for the display driver integrated circuit as described in the second aspect.

[0021] Fourthly, this application provides a display device, the display device comprising: a display driver integrated circuit as described in the first aspect and a frame storage controller applied to the display driver integrated circuit as described in the third aspect.

[0022] The display driver integrated circuit and its control method provided in this application include a bus, a static random access memory (SRAM) divided into multiple memory areas, and multiple transmission lines connected to the bus. Each memory area is divided into at least two memory blocks. Each transmission line is connected to multiple memory blocks, and the memory blocks connected to each transmission line are not duplicated. It is evident that the embodiments of this application have at least the following two beneficial effects: First, by connecting multiple memory blocks to each transmission line and ensuring that all transmission lines are connected to the bus, not only are multiple memory blocks reused on the same transmission line, but all transmission lines also reuse the same bus. Therefore, the solution provided in this application can reduce the number of lines in the display driver integrated circuit, optimize the wiring structure of the display driver integrated circuit, and reserve sufficient placement area for the SRAM. Second, since the SRAM is divided into multiple memory areas, and each memory area is divided into at least two memory blocks, it is possible to write and output image data in units of memory blocks, thereby improving the writing and output speed of image data.

[0023] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of a display driver integrated circuit according to an embodiment of this application is shown;

[0026] Figure 2 This illustration shows a schematic diagram of a display driver integrated circuit that uses dynamic random access memory as a frame memory according to an embodiment of this application;

[0027] Figure 3 This illustration shows a schematic diagram of a display driver integrated circuit that uses static random access memory as a frame memory according to an embodiment of this application;

[0028] Figure 4 A schematic diagram of a display driver integrated circuit provided in another embodiment of this application is shown;

[0029] Figure 5This illustration shows a schematic diagram of the memory area and memory block partitioning of a static random access memory according to an embodiment of this application;

[0030] Figure 6 This illustration shows a schematic diagram of the connection relationship between a transmission line, a bus, and a memory block according to an embodiment of this application;

[0031] Figure 7 This illustration shows a schematic diagram of the connection relationship between a transmission line, a bus, and a memory block according to an embodiment of this application;

[0032] Figure 8 This illustration shows a schematic diagram of the connection relationship between a transmission line, a bus, and a memory block according to another embodiment of this application;

[0033] Figure 9 A schematic diagram of a timing sequence provided in one embodiment of this application is shown;

[0034] Figure 10 A schematic diagram of a display driver integrated circuit according to yet another embodiment of this application is shown;

[0035] Figure 11 A flowchart illustrating a control method for a display driver integrated circuit according to an embodiment of this application is shown;

[0036] Figure 12 A schematic diagram illustrating a data output sorting method according to an embodiment of this application is shown;

[0037] Figure 13 A schematic diagram of a data output sorting method provided in another embodiment of this application is shown. Detailed Implementation

[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0039] Display driver integrated circuits are integrated circuits used to drive display devices such as LCD, LED, and OLED. Display driver integrated circuits include a frame memory. The frame memory stores image data transmitted from the host at a certain speed, and outputs the image data to the pixel units of the display device when the display device needs to display it.

[0040] The following is based on Figure 1 Taking this as an example, the structure of the display driver integrated circuit will be explained in detail: Figure 1 The system includes a host 10, a display driver integrated circuit 11, and a display screen 12. The display driver integrated circuit 11 includes a receiving module 111, a frame storage controller 112, a frame memory 113, a decoder 114, a data processor 115, a timing controller 116, a shift register 117, and a gate controller 118. The host 10 transmits image data to the receiving module 111 at a certain speed via a MIPI TX (Mobile Industry Processor Interface Receiver) module. The receiving module 111 receives the image data via MIPI (Mobile Industry Processor Interface) and transmits the image data to the frame storage controller 112. The frame storage controller 112 writes the image data into the frame memory 113. The frame memory 113 stores the image data written by the frame storage controller 112. When the frame storage controller 112 obtains the row address of the pixel row to be displayed, it reads the image data corresponding to that row address from the frame memory 113 and transmits the read image data to the decoder 114. Decoder 114 decodes the image data and transmits the decoded image data to data processor 115. Image processor 115 performs image quality restoration and other processing on the received image data and transmits the processed image data to timing controller 116. Timing controller 116 generates a clock for the image data and transmits it to shift register 117. Shift register 117 stores the image data based on the clock. Gate controller 118 drives the pixel units in display screen 12 according to the clock. Shift register 117 transmits image data to the pixel units in display screen 12 based on the clock, and the pixel units display the image data transmitted by shift register 117 and driven by gate controller 118.

[0041] The above Figure 1 The frame memory 113 can be either dynamic random access memory or static random access memory.

[0042] The following explains the use of dynamic random access memory (DRAM) for frame memory 113. Compared to static random access memory (SRAM), DRAM of the same capacity has a smaller area, making it more suitable for space-constrained display driver integrated circuits. However, as... Figure 2As shown, when the Dynamic Random Access Memory (DRAM) is used as a frame memory, the buses used for reading and writing the frame memory 113 are not separate; that is, reading and writing share the same bus. Accessing the frame memory 113 for read or write operations is done through the same bus. Therefore, for write requests from the receiving module 111 and read requests from the decoder 114, the storage arbitrator 1121 in the frame memory controller 112 needs to adjust the bus occupancy rights using a priority method. Then, the storage controller 1122 accesses the frame memory 112 according to the arbitration result of the storage arbitrator 1121. In this situation, it may be impossible to complete the read or write operation within the specified time. Due to the physical structure limitations of the DRAM, the above-mentioned defects can only be overcome by increasing the drive frequency. This is because increasing the drive frequency not only increases power consumption but may also lead to timing convergence difficulties.

[0043] At drive frequencies above 60Hz, static random access memory (SRAM) is more suitable as a frame memory than dynamic random access memory (DRAM). The following explains the use of SRAM for frame memory 113. Figure 3 As shown, the frame memory controller 112 includes a memory write control module 1123 and a memory read controller 1124. The memory write control module 1123 controls the writing of the frame memory 113 via the write bus to receive write requests from the receiving module 111, and the memory read control module 1124 controls the reading of the frame memory 113 via the read bus to receive read requests from the decoder 114. It is evident that when static random access memory (SRAM) is selected as the frame memory 113, reading and writing can be configured independently, and it can provide sufficient transmission bandwidth for image data output and writing even at driving frequencies above 60Hz. However, compared to dynamic random access memory (DRAM), the physical size of SRAM is significantly larger than that of DRAM of the same capacity. In order to deploy the relatively large physical size of SRAM in the display driver integrated circuit, it is necessary to optimize the wiring structure of the display driver integrated circuit to leave sufficient space for the placement of SRAM.

[0044] To deploy static random access memory (SRAM) within a limited space, this application provides a display driver integrated circuit (IC) with optimized wiring structure to allocate the largest possible space for SRAM, aiming to utilize the largest possible capacity SRAM within a limited space. Furthermore, this application also provides a control method for the display driver IC, enabling the optimized wiring structure to improve the image data writing and output speed when writing and outputting image data in blocks.

[0045] The display driver integrated circuit provided in this application has an optimized wiring structure, reserving a large enough area for static random access memory. The display driver integrated circuit provided in this application can be applied to display devices such as LCD, LED, and OLED. This application does not specifically limit the type of display device; for example, a mobile phone or tablet computer is used.

[0046] The display driver integrated circuit and its control method provided in the embodiments of this application will be described in detail below:

[0047] like Figure 4 As shown, this application embodiment provides a display driver integrated circuit, which mainly includes: a static random access memory 21 divided into multiple memory areas 211, multiple transmission lines 22 connected to a bus 23, and a bus 23; wherein, each memory area 211 includes at least two memory blocks 2111; each transmission line 22 is respectively connected to multiple memory blocks 2111, and the memory blocks 2111 connected to each transmission line 22 are not repeated.

[0048] The following is a detailed explanation of the specific structure and interaction relationships of the components involved in the display driver integrated circuit:

[0049] Static Random Access Memory 21:

[0050] Static random access memory 21 as Figure 1 The frame memory 113 in the display driver integrated circuit shown is used. The static random access memory 21 is used to store image data written by the frame memory controller 112, and to output image data to the pixel units of the display device when the display device needs to display, so that the pixel units can use it for display.

[0051] The static random access memory 21 is divided into multiple storage areas 211, and each storage area is further divided into at least two storage blocks 2111. Each storage block 2111 has a corresponding physical storage structure within the static random access memory 21. This division method of the static random access memory 21 allows it to store or output image data in units of storage blocks 2111. Each storage block 2111 occupies a smaller physical storage structure, thus improving the speed of storing or outputting image data.

[0052] The number of storage areas 211 divided into the static random access memory 21, and the number of storage blocks 2111 divided into each storage area 211, can be determined based on business requirements. For example, the principle for setting the number of storage blocks 2111 included in the static random access memory 21 is that the number of storage blocks 2111 is sufficient to store all the image data required for displaying one row of pixel units. The static random access memory 21 can write or output the image data required for displaying one row of pixel units at a time.

[0053] Transmission line 22:

[0054] There are multiple transmission lines 22, and all transmission lines 22 are connected to the bus 23. Each transmission line 22 is connected to multiple memory blocks 2111 in the static random access memory 21, and the memory blocks 2111 connected to each transmission line 22 are not duplicated. In order to optimize the wiring structure of the display driver integrated circuit and reserve as much layout space as possible for the static random access memory 21, multiple memory blocks 2111 in the static random access memory 21 share one transmission line 22 to reduce the number of transmission lines 22 used.

[0055] The connection between transmission line 22 and storage block 2111 in static random access memory 21 includes the following two types:

[0056] In the first method, the total number of transmission lines 22 is a first quantity, and each storage area 211 includes a first quantity of storage blocks 2111. The storage blocks 2111 within the same storage area 211 have a first order. Storage blocks 2111 with the same order position in the first order corresponding to each storage area 211 are connected to the same transmission line 22. The first order describes the sequential order in which the image data of each storage block 2111 within the corresponding storage area 211 is output.

[0057] It is important to note that the first sorting defines the order in which the image data is output from each storage block 2111 within the same storage area 211, not the order in which the image data is output from all storage blocks 2111 in the static random access memory 21. Since each storage area 211 contains the same number of storage blocks 2111, the storage blocks 2111 with the same sorting position in the first sorting corresponding to each storage area 211 are all sorted. To reduce the number of wires, the storage blocks 2111 with the same sorting position in the first sorting corresponding to each storage area 211 share the same transmission line 22.

[0058] For example, such as Figure 5As shown, the static random access memory 21 is divided into eight storage areas 211, namely: MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, and MACRO#7. Each storage area 211 is further divided into six storage blocks 2111, namely: SRAM#0, SRAM#1, SRAM#2, SRAM#3, SRAM#4, and SRAM#5. The storage blocks 2111 within each storage area 211 have the same first sorting, and the order of the storage blocks 2111 in the first sorting is: SRAM#0, SRAM#1, SRAM#2, SRAM#3, SRAM#4, and SRAM#5. For any storage area 211, the first sorting describes the order in which the image data is output by its internal storage block 2111. That is, SRAM#0, SRAM#1, SRAM#2, SRAM#3, SRAM#4, and SRAM#5 output the corresponding image data in sequence.

[0059] For example, the number of transmission lines 22 is the same as the number of storage blocks 2111 in the storage area 211, which is 6. To reduce the number of wires, this embodiment uses a multiplexed wiring scheme; therefore, storage blocks 2111 with the same sorting position in the first sorting corresponding to each storage area 211 are connected to the same transmission line 22. For example... Figure 6 As shown, Figure 5 In each storage area 211, the SRAM#0 is located in the first position of its corresponding first sorting. Therefore, the SRAM#0 in each storage area 211, from "MACRO#0 to MACRO#7", is connected to the same transmission line 22. For example, Figure 5 The SRAM#1 in each memory area 211 is located in the second position of the corresponding first sorting, therefore the SRAM#1 in each memory area 211 "MACRO#0 to MACRO#7" is connected to the same transmission line 22. For example, Figure 5 The SRAM#2 in each memory area 211 is located in the third position of the corresponding first sorting, therefore the SRAM#2 in each memory area 211 "MACRO#0 to MACRO#7" is connected to the same transmission line 22. For example, Figure 5 The SRAM#3 in each memory area 211 is located in the fourth position of the corresponding first sorting, therefore the SRAM#3 in each memory area 211 "MACRO#0 to MACRO#7" is connected to the same transmission line 22. For example, Figure 5The SRAM#4 in each memory area 211 is located in the fifth position of the corresponding first sorting, therefore the SRAM#4 in each memory area 211 "MACRO#0 to MACRO#7" is connected to the same transmission line 22. For example, Figure 5 The SRAM#5 in each storage area 211 is located in the sixth position in the corresponding first sorting, so the SRAM#5 in each storage area 211 "MACRO#0 to MACRO#7" is connected to the same transmission line 22.

[0060] It should be noted that the first quantity can be determined based on business needs, and this application embodiment does not impose a specific limitation. For example, the principle for setting the first quantity is to ensure that the number of storage blocks 2111 included in the static random access memory 21 is sufficient to store or output all the image data required for displaying a row of pixel units.

[0061] The second type involves a transmission line 22 with the same number of transmission lines 22 as the total number of storage areas 211 included in the static random access memory 21. Storage blocks 2111 included in the same storage area 211 are connected to the same transmission line 22, and different storage areas 211 correspond to different transmission lines 22.

[0062] The number of transmission lines 22 is the same as the total number of storage areas 211 included in the static random access memory 21. In order to reduce the number of wirings, this embodiment of the application adopts a multiplexing wiring scheme. Therefore, the storage blocks 2111 included in the same storage area 211 are connected to the same transmission line 22.

[0063] For example, such as Figure 7 As shown, Figure 5 In the memory areas 211 involved in the above: MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, and MACRO#7, the memory blocks 2111 included in the same memory area 211 are connected to the same transmission line 22. For example, the memory blocks 2111 "SRAM#0 to SRAM#5" included in memory area MACRO#0 are connected to the same transmission line 22.

[0064] To further optimize the wiring structure of the display driver integrated circuit and reduce the number of wires, all transmission lines 12 are connected to the same bus 13.

[0065] Furthermore, to prevent data transmission conflicts in bus 23, transmission line 22 and the bus have the following functions: transmission line 22 is turned on when the connected storage block 2111 needs to output image data, and transmits the image data to bus 23; it is turned off when the connected storage block 2111 does not need to output image data. Bus 23 is used to process the image data transmitted by transmission line 22.

[0066] All transmission lines 12 share the same bus 13. The transmission line 12 is turned on when the connected storage block 2111 needs to output image data, and turned off when the connected storage block 2111 does not need to output image data. Therefore, it can avoid transmission conflicts of image data transmitted by each transmission line 12 on the bus 23.

[0067] In order for the transmission line 22 to be turned on or off according to the image data transmission status of the storage block 211 to which it is connected, such as Figure 8 As shown, the transmission line 22 includes a switch module 221 and a first controller 222. The input terminal T1 of the switch module 221 is connected to the corresponding storage block 2111, the output terminal T2 is connected to the bus 13, and the control terminal T3 is connected to the first controller 222. The first controller 222 is used to send an enable signal to the switch module 221 when the storage block 2111 connected to the input terminal T1 needs to output image data; and to send a disable signal to the switch module 221 when the storage block 2111 connected to the input terminal T1 does not need to output image data. The switch module 221 is used to be enabled by the enable signal and disabled by the disable signal.

[0068] Through the interaction between the switch module 221 and the first controller 222, each transmission line 22 is turned on only when transmitting data at the time of image data output of its corresponding connected storage block 2111, and remains closed at other times, thereby preventing transmission conflicts of image data transmitted on the bus.

[0069] The specific type of the switch module 221 is not limited in this embodiment, and it can be selected based on business requirements. For example, the switch module 221 is a tri-state buffer or a MOSFET.

[0070] Switch module 221 is a tri-state buffer. Figure 8The switch module 211 shown is a tri-state buffer. When the storage block 2111 connected to the input terminal T1 of the tri-state buffer needs to output image data, the first controller 222 transmits an enable signal to the control terminal T3. Under the enable signal, the tri-state buffer is turned on, and the image data received at its input terminal T1 is directly sent to the output terminal T2 and transmitted to the bus 23. When the storage block 2111 connected to the input terminal T1 of the tri-state buffer does not need to output image data, the first controller 222 transmits a disable signal to the control terminal T3. Under the disable signal, the tri-state buffer is turned off and is in a high-impedance state. Regardless of the data received at its input terminal T1, its output is always in a high-impedance state.

[0071] The following is based on Figure 8 To illustrate the interaction between the switch module 221 and the first controller 222. The first controller 222 is based on... Figure 9 After determining the valid row address of the pixel row to be displayed based on the clock signal, the first controller 222... Figure 9 The timing diagrams for SCAN_en0 to SCAN_en5 shown are directed towards... Figure 8 The tri-state buffers SRAM#0, SRAM#1, SRAM#2, SRAM#3, SRAM#4, and SRAM#5 in "MACRO#0 to MACRO#7" are given enable and disable signals. This ensures that each tri-state buffer is enabled to transmit data only at the image data output time of its corresponding connected storage block 2111, and remains disabled at other times, thereby preventing transmission conflicts of image data on the bus. The scan of storage block 2111 ends when the scan output time expires. Figure 9 SCAN_out in the text indicates that the scan is finished and valid data is output. Here, valid data refers to the image data output by each storage block 2111, that is, the image data corresponding to the valid row address of the pixel row to be displayed.

[0072] The switching module 221 is a MOSFET. When the memory block 2111 connected to the input terminal T1 of the MOSFET needs to output image data, the first controller 222 transmits an enable signal to the control terminal T3. Under the enable signal, the MOSFET is turned on, and the image data received at its input terminal T1 is directly transmitted to the output terminal T2, which then transmits the image data to the bus 23. When the memory block 2111 connected to the input terminal T1 of the MOSFET does not need to output image data, the first controller 222 transmits a disable signal to the control terminal. Under the disable signal, the MOSFET is in the disable state. When the switching module 221 is a MOSFET, its specific connection relationship is determined according to the selected MOSFET type, and will not be described in detail here.

[0073] It should be noted that the specific type of the first controller 222 is not limited in this embodiment, and it can reuse the embodiments of this application. Figure 1 The frame storage controller 112 shown.

[0074] Bus 23:

[0075] To reduce the number of cabling lines, all transmission lines 22 share the same bus 23 and are connected to the same bus 23. Bus 23 is used to process the image data transmitted by the transmission lines 22.

[0076] like Figure 1 As shown, the process of image data transmission and processing by bus 23 can be as follows: the image data is transmitted to decoder 114. Decoder 114 decodes the image data and transmits the decoded image data to data processor 115. Image processor 115 performs image quality restoration and other processing on the received image data and transmits the processed image data to timing controller 116. Timing controller 116 generates a clock for the image data and transmits it to shift register 117. Shift register 117 stores the clock data based on the image data clock.

[0077] The display driver integrated circuit provided in this application includes a bus, a static random access memory (SRAM) divided into multiple memory areas, and multiple transmission lines connected to the bus. Each memory area is divided into at least two memory blocks. Each transmission line connects to multiple memory blocks, and the memory blocks connected to each transmission line are not duplicated. Therefore, this application embodiment has at least two beneficial effects: First, by connecting multiple memory blocks to each transmission line and ensuring that all transmission lines are connected to the bus, not only are multiple memory blocks reused on the same transmission line, but all transmission lines also reuse the same bus. Thus, the solution provided in this application embodiment can reduce the number of lines in the display driver integrated circuit, optimize the wiring structure of the display driver integrated circuit, and reserve sufficient placement area for the SRAM. Second, since the SRAM is divided into multiple memory areas, and each memory area is divided into at least two memory blocks, it is possible to write and output image data in units of memory blocks, thereby improving the speed of image data writing and output.

[0078] Furthermore, another embodiment of this application also provides a display driver integrated circuit, such as... Figure 10 As shown, the display driver integrated circuit includes, in addition to Figure 4 In addition to the static random access memory 21, transmission line 22, and bus 23 shown, the system also includes a shift register 24 and a third controller 25. The specific structure and interaction of the shift register 24 and the third controller 25 are described in detail below:

[0079] Processing module 24 and shift register 25:

[0080] To reduce the number of wires, all transmission lines 22 share the same bus 23 and are connected to the same bus 23. Bus 23 is used to process the image data transmitted by the transmission lines 22. The processing of image data transmitted by the transmission lines 22 by bus 23 essentially involves transmitting the image data to the processing module 25 for processing, and then transmitting the processed image data to the shift register 26 for storage.

[0081] The processing module 25 is used to receive image data transmitted by the bus 23, process the image data, and transmit the processed data to the shift register 26.

[0082] Processing module 25 can be derived from Figure 1The image processing module 114 comprises a decoder 114, a data processor 115, and a timing controller 116. The decoder 114 decodes the image data and transmits the decoded image data to the data processor 115. The image processor 115 performs image quality restoration and other processing on the received image data and transmits the processed image data to the timing controller 116. The timing controller 116 generates a clock for the image data and transmits it to a shift register 217. The shift register 217 stores the processed data based on the display timing of the image data in the corresponding pixel units. To ensure that the pixel units are displayed at the correct time, the shift register 217 stores the processed data based on the display timing of the image data in the corresponding pixel units, so that the image data is provided to the pixel units for display at the correct time.

[0083] Furthermore, another embodiment of this application also provides a control method for a display driver integrated circuit, which is applied to the aforementioned display driver integrated circuit, such as... Figure 11 As shown, the control method of this display driver integrated circuit mainly includes the following steps 301 to 302:

[0084] 301. When it is necessary to scan the rows of pixels to be displayed, the storage blocks in the static random access memory are traversed based on the second sort, wherein the number of storage blocks belonging to the same storage area that are consecutively sorted in the second sort is no greater than the second number, which is a positive integer greater than or equal to 1.

[0085] The static random access memory 21 includes storage blocks 2111 with a second sorting, which defines the image data output order of each storage block 2111 in the static random access memory 21. The principles for setting the second sorting include the following two points: First, since the pixel units in the pixel row to be displayed are scanned one by one, the image data output order of the storage blocks defined by the second sorting needs to be the same as the scanning order of the pixel units to ensure that the pixel unit can apply its corresponding image data when scanning. That is, the setting of the storage block positions in the second sorting should ensure that the pixel units can be scanned in sequence, avoiding confusion in the pixel unit scanning. Second, continuous output of image data from multiple storage blocks within a storage area will cause excessive power consumption, leading to a decrease in image data output speed. Therefore, to avoid a decrease in image data output speed, in the second sorting, the number of storage blocks 2111 belonging to the same storage area 211 consecutively sorted in the second sorting is no greater than a second quantity. The specific value of the second quantity is not limited and can be selected based on business requirements. For example, if the second quantity is 1, that is, in the second sorting, any two adjacent storage blocks 2111 do not belong to the same storage area. For example, if the second quantity is 2, then in the second sorting, there will not be three consecutive adjacent storage blocks 2111 belonging to the same storage area; only two adjacent storage blocks 2111 can belong to the same storage area.

[0086] Based on the above principles for setting the second sorting, the set second sorting can include the following two types:

[0087] In the first case, where the second quantity is 1 and the storage blocks 2111 within the same storage area 211 have a target sort, the second sort is composed of multiple third sorts. All third sorts cover all storage blocks 2111 in the static random access memory 21, and the storage blocks 2111 in different third sorts are not repeated. Each third sort consists of storage blocks 2111 with the same sort position in the target sort corresponding to each storage area 211, and the storage blocks 2111 involved in the third sort are all sorted according to the traversal order of each storage area 211.

[0088] The second sort is composed of multiple third sorts, which are constructed based on the target sort corresponding to each storage area 211. The target sort, the third sort, and the second sort are explained below.

[0089] The target sorting is the ordering of storage blocks 2111 within the same storage area 211, which defines the order in which image data is transmitted among the storage blocks 2111 within the same storage area 211. For example, such as... Figure 5As shown, the storage blocks 2111 within each storage area 211 all have the same target sorting, and the order of the storage blocks 2111 in the target sorting is: SRAM#0, SRAM#1, SRAM#2, SRAM#3, SRAM#4, SRAM#5. Each storage area 211 has its own corresponding target sorting. These target sortings are the basis for setting the third sorting.

[0090] Each third sort is used to perform one traversal of the storage areas 211 included in the static random access memory 21, and limits the traversal order of the storage blocks 211 that need to be traversed in each storage area 211 during this traversal. Since the second quantity is 1, the principle adopted for setting the third sort is: to form a third sort by combining the storage blocks 2111 with the same sorting position in the target sort corresponding to each storage area 211, and the storage blocks 2111 in the formed third sort are all sorted according to the traversal order of each storage area 211.

[0091] For example, the storage blocks 2111 in each storage area 211 all have the same target sorting, and the order of each storage block 2111 in the target sorting is: SRAM#0, SRAM#1, SRAM#2, SRAM#3, SRAM#4, SRAM#5. The SRAM#0 in each storage area 211 is located in the first position in the corresponding target sorting. Therefore, the SRAM#0 in storage area 211 “MACRO#0 to MACRO#7” is constructed as a third sorting, and the SRAM#0 in the constructed third sorting “MACRO#0 to MACRO#7” is sorted according to the traversal order of MACRO#0 to MACRO#7.

[0092] For example, the storage blocks 2111 in each storage area 211 all have the same target sort, and the order of each storage block 2111 in the target sort is: SRAM#0, SRAM#1, SRAM#2, SRAM#3, SRAM#4, SRAM#5. SRAM#1 in each storage area 211 is located in the second position in the corresponding target sort. Therefore, the SRAM#1 in storage area 211 “MACRO#0 to MACRO#7” is constructed into a third sort, and the SRAM#1 in the constructed third sort is sorted according to the traversal order of MACRO#0 to MACRO#7.

[0093] The third sorting, based on the aforementioned third sorting principle, covers all storage blocks 2111 in the static random access memory 21, and storage blocks 2111 in different third sortings are not repeated. Therefore, after forming the second sorting based on these third sorting combinations, when traversing the storage blocks 2111 in the static random access memory 21 using the second sorting, there will be no situation where storage blocks 2111 are missed, nor will a storage block 2111 be subjected to multiple data read operations.

[0094] The established third sort has a sequential order, and the second sort is formed by concatenating the third sort based on this sequential order. The sequential order of the third sort is determined by the position of the storage blocks in the third sort within the corresponding target sort. For example, if a storage block in a third sort 1 is the first storage block in the target sort, and a storage block in a third sort 2 is the second storage block in the target sort, then when concatenating the second sort, the third sort 1 will be placed before the third sort 2.

[0095] For example, with Figure 5 The static random access memory 21 shown will be described in detail. (Regarding...) Figure 5 The static random access memory 21 shown is configured as follows Figure 12 The second sorting is shown. Figure 12 One column in the table corresponds to a third sort. A third sort defines the traversal order of storage area 211 "MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, MACRO#7", and also defines the storage blocks 2111 that need to be traversed within MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, and MACRO#7 in each traversal. From Figure 11As can be seen, in each third sort, the storage blocks 2111 that need to be traversed in each storage area 211 are storage blocks 2111 with the same sequence number. For example, for the first column, following the order MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, MACRO#7, the first storage block SRAM#0 in each storage area 211 is traversed sequentially, and data reading operations are performed on the currently traversed storage block SRAM#0. After traversing SRAM#0 in MACRO#7, the order continues to traverse the second storage block SRAM#1 in each storage area 211 sequentially, following the order MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, MACRO#7, and data reading operations are performed on the currently traversed storage block SRAM#1. The above process is repeated until the last storage block SRAM#5 in MACRO#7 is reached.

[0096] The storage blocks 2111 included in the static random access memory 21 are output according to the second sorting, which not only ensures the line-by-line scanning of pixel units and avoids pixel unit scanning chaos, but also for a storage area, only one storage block is traversed each time, and only one storage block outputs image data. Therefore, it avoids the continuous output of image data by storage blocks in a storage area, thereby reducing storage area output loss and improving the image data output speed.

[0097] In the second scenario, where the second quantity is greater than 1, the second sort is composed of multiple fourth sorts. All fourth sorts cover all storage blocks in the static random access memory (SRAM), and storage blocks in different fourth sorts are not repeated. Each fourth sort is used to define the traversal order of multiple storage blocks. These multiple storage blocks involve all storage areas of the SRAM, and are sorted according to the traversal order of each storage area. Storage blocks belonging to the same storage area are sorted consecutively, and the total number of storage blocks belonging to the same storage area does not exceed the second quantity.

[0098] The second sort is composed of multiple fourth sorts. The fourth and second sorts are explained below.

[0099] Each fourth sort is used to perform one traversal of the storage areas 211 included in the static random access memory 21, and limits the traversal order of the storage blocks 211 to be traversed in each storage area 211 during this traversal. Since the second quantity is a value greater than 1, the principle adopted for setting the fourth sort is as follows: select storage blocks 2111 to participate in the sorting in each storage area 211, and the number of storage blocks 2111 selected in the same storage area 211 is not greater than the second quantity; sort the storage blocks 2111 from the same storage area 211; and then sort and concatenate the sorted storage blocks 2111 according to the traversal order of each storage area 211 to form the fourth sort.

[0100] For example, the storage blocks 2111 in each storage area 211 all have the same target sort, and the order of the storage blocks 2111 in the target sort is: SRAM#0, SRAM#1, SRAM#2, SRAM#3, SRAM#4, SRAM#5. The storage blocks 2111 selected for sorting in each storage area 211 are as follows: storage areas 211 "MACRO#0 to MACRO#7" all select storage blocks 2111 "SRAM#0, SRAM#1" for sorting, resulting in the fourth sort as follows. Figure 13 The first column, as shown, is: "MACRO#0, SRAM#0", "MACRO#0, SRAM#1", "MACRO#1, SRAM#0", "MACRO#1, SRAM#1", "MACRO#2, SRAM#0", "MACRO#2, SRAM#1", "MACRO#3, SRAM#0", "MACRO#3, SRAM#1", "MACRO#4, SRAM#0", "MACRO#4, SRAM#1", "MACRO#5, SRAM#0", "MACRO#5, SRAM#1", "MACRO#6, SRAM#0", "MACRO#6, SRAM#1", "MACRO#7, SRAM#0", "MACRO#7, SRAM#1". This is set according to the above principles. Figure 13 The second and third columns shown correspond to the fourth sorting.

[0101] The fourth sorting, based on the aforementioned fourth sorting principle, covers all storage blocks 2111 in the static random access memory 21, and storage blocks 2111 in different fourth sortings are not repeated. Therefore, after forming the second sorting based on these fourth sorting combinations, when traversing the storage blocks 2111 in the static random access memory 21 using the second sorting, there will be no situation where storage blocks 2111 are missed, nor will a storage block 2111 be subjected to multiple data read operations.

[0102] The fourth sort has a predetermined order, and the second sort is formed by concatenating the fourth sorts based on this order. The order of the fourth sort is determined by the position of the storage blocks in the fourth sort within the corresponding target sort. For example, if a storage block in a fourth sort 1 is the first storage block in the target sort, and a storage block in a fourth sort 2 is the second storage block in the target sort, then when concatenating the second sort, the fourth sort 1 will precede the fourth sort 2.

[0103] For example, static random access memory 21 is provided with such Figure 13 The second sorting is shown. Figure 13 One column in the table corresponds to a fourth sort. A fourth sort defines the traversal order of storage area 211 "MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, MACRO#7", and also defines the storage blocks 2111 that need to be traversed within MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, and MACRO#7 in each traversal. From Figure 13 As can be seen, in each fourth sort, two storage blocks 2111 need to be traversed within each storage area 211. For example, for the first column, following the order MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, MACRO#7, the first storage block SRAM#0 and the second storage block SRAM#1 in each storage area 211 are traversed sequentially, and data reading operations are performed on the currently traversed storage block. After traversing SRAM#0 and SRAM#1 in MACRO#7, the order continues to traverse the third storage block SRAM#2 and SRAM#3 in each storage area 211 sequentially, following the order MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, MACRO#7, and data reading operations are performed on the currently traversed storage block. This process is repeated until the last storage block SRAM#5 in MACRO#7 is reached.

[0104] The storage blocks 2111 included in the static random access memory 21 are output according to the second sorting, which not only ensures the line-by-line scanning of pixel units and avoids pixel unit scanning chaos, but also limits the number of storage blocks for continuous output image data in a storage area, which is no more than the second number, thereby avoiding the situation where the image data output speed decreases due to the increase in storage area output loss.

[0105] 302. Perform a data read operation on the currently traversed storage block so that the currently traversed storage block transmits the stored image data to the corresponding connected transmission line.

[0106] When performing a data read operation on the currently traversed storage block 2111, the currently traversed storage block 2111 transmits the stored image data to the corresponding connected transmission line 22. Then, transmission line 22 is activated, transmitting the image data to bus 23. Bus 23 processes the image data transmitted from transmission line 22, that is, bus 23 transmits the image data to processing module 25 for processing, and then transmits the processed image data to shift register 26 for storage. Shift register 26 provides the corresponding image data to the pixel unit according to the set timing, thereby completing the display output of the pixel unit.

[0107] The control method for the display driver integrated circuit provided in this application, when scanning rows of pixels to be displayed is required, traverses the storage blocks in the static random access memory based on a second sort, and performs data reading operations on the currently traversed storage block, so that the currently traversed storage block transmits the stored image data to the corresponding connected transmission line. It is known that multiple storage blocks within a storage area continuously outputting image data will increase power consumption and reduce the image data output speed. Therefore, this application embodiment controls the number of storage blocks continuously outputting image data within a storage area by controlling the number of storage blocks belonging to the same storage area consecutively sorted in the second sort, thus avoiding the decrease in image data output speed.

[0108] Furthermore, the control method for the display driver integrated circuit provided in this application embodiment may further include the following step 303:

[0109] 303. When it is necessary to store image data for the rows of pixels to be displayed, the storage blocks in the static random access memory are traversed based on the second sorting, and data writing operations are performed on the currently traversed storage block so that the currently traversed storage block stores the written image data.

[0110] The image data stored in the static random access memory 21 follows the first-in-first-out principle. Therefore, when writing image data to the storage block 2111, the storage block 2111 in the static random access memory 21 can also be written according to the second sorting.

[0111] For example, such as Figure 12As shown, firstly, following the order MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, and MACRO#7, the system sequentially traverses the first storage block SRAM#0 in each storage area 211, writing the corresponding image data into the currently traversed storage block 2111. After traversing SRAM#0 in MACRO#7, the system continues to traverse the second storage block SRAM#1 in each storage area 211 in the order MACRO#0, MACRO#1, MACRO#2, MACRO#3, MACRO#4, MACRO#5, MACRO#6, and MACRO#7, writing the corresponding image data into the currently traversed storage block 2111. This process is repeated until the system reaches the last storage block SRAM#5 in MACRO#7. It should be noted that this can be achieved through... Figure 3 The write bus in the memory transmits image data to static random access memory 21.

[0112] The static random access memory 21 includes storage blocks 2111 that write image data according to the second sorting. This not only ensures that data is written in the line-by-line scanning order of pixel units, but also limits the number of storage blocks that continuously write image data within a storage area. This avoids the situation where the image data writing speed decreases due to increased storage area write losses.

[0113] Furthermore, based on the above embodiments, another embodiment of this application provides a frame storage controller applied to a display driver integrated circuit, wherein the frame storage controller applies the control method of the display driver integrated circuit as described above.

[0114] For example, the frame storage controller provided in this application embodiment is Figure 1 The frame storage controller 112 shown.

[0115] The beneficial effects of the frame storage controller for display driver integrated circuits provided in this application embodiment can be referred to the description in the above-described embodiment of the control method for display driver integrated circuits, and will not be repeated here.

[0116] Furthermore, based on the above embodiments, another embodiment of this application also provides a display device, which includes: a display driver integrated circuit as described above and a frame storage controller applied to the display driver integrated circuit as described above.

[0117] The beneficial effects of the display device provided in this application can be referred to the descriptions in the above embodiments of the display driver integrated circuit and the frame storage controller applied to the display driver integrated circuit, which will not be repeated here.

[0118] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0119] It is understood that the relevant features in the above methods and apparatus can be referenced interchangeably. Furthermore, the terms "first," "second," etc., in the above embodiments are used to distinguish between embodiments and do not represent the superiority or inferiority of any particular embodiment.

[0120] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0121] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this application is not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of this application.

[0122] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0123] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0124] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the method, apparatus, and framework for operating the deep neural network model according to the embodiments of this application. This application can also be implemented as a device or apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0125] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. A display driving integrated circuit, characterized by comprising: The display driving integrated circuit comprises a bus, a static random access memory divided into a plurality of storage areas, and a plurality of transmission lines connected with the bus; each of the storage areas comprises at least two storage blocks; each of the transmission lines is connected with a plurality of storage blocks, and the storage blocks connected with each of the transmission lines are not repeated; The storage blocks comprised in the static random access memory have a second order, the second order defines the image data reading order of the storage blocks in the static random access memory, and the number of the storage blocks belonging to the same storage area and continuously ordered in the second order is not greater than a second number, the second number is a positive integer greater than or equal to 1; The total number of the transmission lines is a first number, and the first number of storage blocks are comprised in each of the storage areas; the storage blocks in the same storage area have a first order; the storage blocks having the same order position in the corresponding first order of each of the storage areas are connected with the same transmission line; wherein the first order describes the order of the image data output by the storage blocks in the corresponding storage area.

2. The display driver integrated circuit of claim 1, wherein, The transmission line is turned on when the storage blocks connected with the transmission line need to output image data, and transmits the image data to the bus; the transmission line is turned off when the storage blocks connected with the transmission line do not need to output image data; The bus is used for transmission processing of the image data.

3. The display driver integrated circuit of claim 2, wherein, The transmission line comprises a switch module and a first controller; wherein the input end of the switch module is connected with the corresponding storage block, the output end is connected with the bus, and the control end is connected with the first controller; The first controller is used for issuing an opening signal to the switch module when the storage block connected with the input end needs to output image data, and issuing a closing signal to the switch module when the storage block connected with the input end does not need to output image data; The switch module is used for being turned on under the opening signal and being turned off under the closing signal.

4. The display driver integrated circuit of claim 3, wherein, The switch module is a tri-state buffer or a MOS tube.

5. The display driver integrated circuit of any one of claims 1-4, wherein, The display driving integrated circuit further comprises a processing module and a shift register; The processing module is used for receiving the image data transmitted by the bus, processing the image data, and transmitting the processed data to the shift register; The shift register is used for storing the processed data based on the display timing of the corresponding pixel unit.

6. A control method of a display driving integrated circuit, characterized by, The method is applied to the display driving integrated circuit as claimed in any one of claims 1-5, and the method comprises: When it is needed to scan the pixel row to be displayed, the storage blocks in the static random access memory are traversed based on the second order, and a data reading operation is performed on the currently traversed storage block, so that the currently traversed storage block transmits the stored image data to the transmission line connected therewith; The number of the storage blocks belonging to the same storage area and continuously ordered in the second order is not greater than a second number, and the second number is a positive integer greater than or equal to 1.

7. The method of claim 6, wherein, The method further comprises: when image data storage is required for a pixel row to be displayed, traversing the storage blocks in the static random access memory based on the second order, and performing a data write operation on the currently traversed storage block, so that the currently traversed storage block stores the written image data.

8. The method according to claim 6 or 7, characterized in that, When the second number is 1 and the storage blocks in the same storage area have target orders, the second order is spliced by a plurality of third orders; all the third orders cover all the storage blocks in the static random access memory, and the storage blocks in different third orders are not repeated; each of the third orders is composed of the storage blocks having the same order position in the target orders corresponding to each of the storage areas, and the storage blocks involved in the third order are sorted according to the traversal order of each of the storage areas.

9. The method according to claim 6 or 7, characterized in that, When the second number is greater than 1, the second order is spliced by a plurality of fourth orders, all the fourth orders cover all the storage blocks in the static random access memory, and the storage blocks in different fourth orders are not repeated; each of the fourth orders is used to limit the traversal order of a plurality of storage blocks; wherein the plurality of storage blocks involve all the storage areas of the static random access memory, the plurality of storage blocks are sorted according to the traversal order of each of the storage areas, the storage blocks belonging to the same storage area are sorted continuously, and the total number of the storage blocks belonging to the same storage area is not greater than the second number.

10. A frame memory controller for a display driver integrated circuit, comprising: The frame memory controller applies the control method of the display driving integrated circuit according to any one of claims 6 to 9.

11. A display device, characterized by comprising: The display device comprises the display driving integrated circuit according to any one of claims 1 to 5 and the frame memory controller applied to the display driving integrated circuit according to claim 10.

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