Method and system for generating a physically unclonable function (PUF) bit from a static random-access memory (SRAM)

Abstract

A method for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM) comprising plurality of bitcells arranged in rows and columns is described in an embodiment. The method comprising: (i) receiving a PUF challenge input comprising challenge bits to define a bitcell current type, a bitcell state of a first bitcell, a bitcell state of a second bitcell, an address of the first bitcell and an address of the second bitcell; (ii) obtaining a first replicate current associated with a transistor of the first bitcell, wherein selection of the transistor of the first bitcell is associated with the bitcell current type and the bitcell state of the first bitcell; (iii) obtaining a second replicate current associated with a transistor of the second bitcell, wherein selection of the transistor of the second bitcell is associated with the bitcell current type and the bitcell state of the second bitcell; (iv) digitizing the first replicate current and the second replicate current to form a digitized first replicate current and a digitized second replicate current respectively; and (v) comparing the digitized first replicate current and the digitized second replicate current to generate the PUF bit. A system for generating a PUF bit from a SRAM is also described in an embodiment.

Description

[0001] Method and System for Generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM)

[0002] Technical Field

[0003] The present disclosure relates to a method and system for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM).

[0004] Physically unclonable functions (PUF) are a key building block in today’s secure silicon systems, supporting several security functions such as device identification, cryptographic key generation, and remote authentication. Generally, PUFs extract static entropy (e.g., time-invariant) in the form of unique challenge-response pairs. State-of-the-art PUFs digitize static randomness from regular and compact physical structures such as arbiters, SRAMs, ring oscillators, latches, flip-flops, buskeepers, NAND logic gates, and other methods. Low-cost low-power solutions with high density and high PUF array utilization, together with masking or other bit stabilization techniques, are desirable in today’s secure resource-constrained systems (e.g. loT devices).

[0005] Among available approaches, SRAM PUFs are widely used in commercial silicon systems, thanks to their relatively high bit density, ease of design reuse for both storage and PUF, ubiquitous availability, and seamless system integration. Conventional SRAM PUFs extract 1 -bit static entropy from each bitcell by reading out the natural bitcell state after power-up, for example, using the resolution of crosscoupled inverter pairs from metastable states due to mismatch.

[0006] Conventional single-bit SRAM PUFs suffer from high native instability and high cost of incremental improvements in the PUF-to-SRAM capacity ratio. Stability against noise, supply and temperature fluctuations is achieved by using several methods, including dark-bit masking, temporal majority voting, remapping, and / or much costlier error correcting code (ECC), but these add energy and area overhead. To suppress the typically dominant area and energy of error correcting code (ECC) post-processing, aggressive PUF stabilization techniques are used to achieve ECC-less operation while meeting the required bit error rate target, such as self-checking / healing and hot carrier injection burn-in, but at the costs of increased circuit complexity and testing time (e.g., 10 minutes). Accordingly, state-of-the-art SRAM PUFs require expensive addition of ECC, high post-stabilization energy / bit, additional testing time and cost, additional relatively high supply voltages, and / or no SRAM design reuse due to custom bitcell requirement.

[0007] To improve the PUF capacity and make its ratio with the SRAM storage capacity higher than 100%, multi-bit SRAM PUFs were recently demonstrated. Multi-bit SRAM PUFs break the traditional tradeoff between capacity and energy / area overhead, as they push the PUF-to-SRAM capacity ratio well above 100% and hence remove aggressive post-processing or ECC requirement, while still achieving a better (>100%) ratio. Extraction of multi-bit SRAM PUFs can be achieved using additional and higher-quality entropy by digitizing bitcell read currents or the temporal bitcell resolution transient. ECC-less operation with a bit error rate of ~10-7was achieved by the 2-bit / bitcell SRAM PUFs. However, such multi-bit solutions are currently limited to 2 bit / bitcell due to the much higher stability degradation in higher-order bits, which nullifies the benefits of their extraction.

[0008] It is therefore desirable to provide a method and system for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM) which address the aforementioned problems and / or provide a useful alternative. Further, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.

[0009] Aspects of the present application relate to a method and system for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM).

[0010] In accordance with a first aspect, there is provided a method for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM) comprising a plurality of bitcells arranged in rows and columns, the method comprising: (i) receiving a PUF challenge input for generating the PUF bit, the PUF challenge input comprising challenge bits to define a bitcell current type, a bitcell state of a first bitcell of the plurality of bitcells, a bitcell state of a second bitcell of the plurality of bitcells, an address of the first bitcell and an address of the second bitcell, wherein the address of the first bitcell and the address of the second bitcell are defined using a row and a column associated with each of the first bitcell and the second bitcell; (ii) obtaining a first replicate current associated with a transistor of the first bitcell, wherein selection of the transistor of the first bitcell is associated with the bitcell current type and the bitcell state of the first bitcell; (iii) obtaining a second replicate current associated with a transistor of the second bitcell, wherein selection of the transistor of the second bitcell is associated with the bitcell current type and the bitcell state of the second bitcell; (iv) digitizing the first replicate current and the second replicate current to form a digitized first replicate current and a digitized second replicate current respectively; and (v) comparing the digitized first replicate current and the digitized second replicate current to generate the PUF bit.

[0011] By selecting the transistor of the first bitcell based on the bitcell current type and the bitcell state of the first bitcell and by selecting the transistor of the second bitcell based on the bitcell current type and the bitcell state of the second bitcell, the data stored (i.e. the bitcell state of 1 or 0) in the SRAM first and second bitcells is utilised for generating the PUF bit. The PUF bit generated using the present method therefore incorporates chip-specific fingerprinting of at-rest or in-transit data (e.g., to assess whether a video frame was actually produced / stored in a specific chip and location) for user authentication. Enabling data provenance assurance or data fingerprinting as an extra layer of security in this way uniquely associates each piece of received data to the originating device, including the specific bitcells where data resided (e.g., for data integrity, authenticity, and traceability). This enables establishment of a two-way association between the data received and the origin device, thereby improving security provided by the PUF bit. Further, by comparing the digitized first replicate current and the digitized second replicate current to generate the PUF bit, this differential nature makes the PUF bit generated robust against correlated process, voltage, and temperature variations experienced by the bitcells of the SRAM.

[0012] The method may comprise: replicating, by using a set of current mirrors, a first current associated with the transistor of the first bitcell to obtain the first replicate current; and replicating, by using the set of current mirrors, a second current associated with the transistor of the second bitcell to obtain the second replicate current, wherein the set of current mirrors may comprise a PMOS set of current mirrors and a NMOS set of current mirrors, and selection of the PMOS set of current mirrors or the NMOS set of current mirrors for replicating the first current or the second current may be based on the bitcell current type.

[0013] The method may comprise: under-driving or over-driving a first wordline (WL) voltage associated with the first bitcell based on the bitcell current type for selecting the transistor of the first bitcell; and under-driving or over-driving a second wordline (WL) voltage associated with the second bitcell based on the bitcell current type for selecting the transistor of the second bitcell.

[0014] Wherein the step (iv) of the method may comprise: converting, using a current-starved ring oscillator (CSRO), the first replicate current to form a first frequency and the second replicate current to form a second frequency; and converting, using a time-to-digital converter, oscillations associated with a first time period associated with the first frequency to form the digitized first replicate current and oscillations associated with a second time period associated with the second frequency to form the digitized second replicate current.

[0015] Wherein the CSRO may comprise a first set of current mirror ratio-tunable fingers and a second set of current mirror ratio-tunable fingers, the first set of current mirror ratio-tunable fingers being adapted to receive replicate PMOS currents from the PMOS set of current mirrors, and the second set of current mirror ratio-tunable fingers being adapted to receive replicate NMOS currents from the NMOS set of current mirrors, a magnitude of the replicate PMOS currents and a magnitude of the replicate NMOS currents being dependent on the corresponding bitcell state, the method may comprise: self-calibrating the first set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the first set of current mirror ratio-tunable fingers to minimize bias in the 0 / 1 distribution of the generated PUF bits due to process-induced mismatch in the PMOS set of current mirrors; and self-calibrating the second set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the second set of current mirror ratio-tunable fingers to minimize bias in the 0 / 1 distribution of the generated PUF bits due to process-induced mismatch in the NMOS set of current mirrors.

[0016] Wherein the CSRO may comprise a first set of digital switches connected to the first set of current mirror ratio-tunable fingers and a second set of digital switches connected to the second set of current mirror ratio-tunable fingers, the method may comprise: receiving first digital enablement bits at the first set of digital switches for enabling or disabling the one or more current mirror fingers of the first set of current mirror ratio-tunable fingers; and receiving second digital enablement bits at the second set of digital switches for enabling or disabling the one or more current mirror fingers of the second set of current mirror ratio-tunable fingers.

[0017] Wherein the step (iv) may comprise: controlling, using self-limiting frequency dividers, a number of the oscillations sensed in the first time period associated with the first frequency and a number of the oscillations sensed in the second time period associated with the second frequency.

[0018] The method may comprise: voltage-level shifting, using a level shifter, outputs associated with the first frequency and the second frequency prior to providing the voltage-level shifted outputs to the self-limiting frequency dividers for controlling the number of the oscillations sensed.

[0019] The method may comprise: using the generated PUF bits to form a row address offset to generate a new PUF challenge input internally, the new PUF challenge input comprising a new row address associated with the row address offset, the bitcell current type and new bitcell states for use with a new pair of bitcells associated with the new row address, wherein the new bitcell states corresponds to the bitcell state of the first bitcell and the bitcell state of the second bitcell; and repeating the steps (ii) to (iv) based on the new PUF challenge input to obtain a new PUF bit.

[0020] The new row address maybe within a same SRAM bank of the SRAM as the row of the address of the first bitcell and the row of the address of the second bitcell. In accordance with a second aspect, there is provided a method for generating a Physically Unclonable Function (PUF) bit from a 6-transistor (6T) Static Random-Access Memory (SRAM) comprising a plurality of bitcells arranged in rows and columns, the method comprising: receiving a PUF challenge input for generating the PUF bit, the PUF challenge input comprising challenge bits to define a bitcell current type, a bitcell state of a first bitcell of the plurality of bitcells and a bitcell state of a second bitcell of the plurality of bitcells, an address of the first bitcell and an address of the second bitcell, wherein the address of the first bitcell and the address of the second bitcell are defined using a row and a column associated with each of the first bitcell and the second bitcell; obtaining a first replicate current associated with a transistor of the first bitcell, wherein selection of the transistor of the first bitcell is associated with the bitcell current type and the bitcell state of the first bitcell, the selection of the transistor of the first bitcell includes: under-driving or over-driving a first wordline (WL) voltage associated with the first bitcell based on the bitcell current type; and replicating, by using a set of current mirrors, a first current associated with the transistor of the first bitcell to obtain the first replicate current; obtaining a second replicate current associated with a transistor of the second bitcell, wherein selection of the transistor of the second bitcell is associated with the bitcell current type and the bitcell state of the second bitcell, the selection of the transistor of the second bitcell includes: underdriving or over-driving a second wordline (WL) voltage associated with the second bitcell based on the bitcell current type; and replicating, by using the set of current mirrors, a second current associated with the transistor of the second bitcell to obtain the second replicate current; digitizing the first replicate current and the second replicate current to form a digitized first replicate current and a digitized second replicate current respectively; and comparing the digitized first replicate current and the digitized second replicate current to generate the PUF bit, wherein the set of current mirrors comprises a PMOS set of current mirrors and a NMOS set of current mirrors, and selection of the PMOS set of current mirrors or the NMOS set of current mirrors for replicating the first current or the second current is based on the bitcell current type. Wherein each of the first bitcell and the second bitcell may include a corresponding pair of pull-up (PU) transistors, a corresponding pair of pull-down (PD) transistors and a corresponding pair of pass-gate (PG) transistors with each pair being associated with a corresponding bitcell current type, and each of the PMOS set of current mirrors and the NMOS set of current mirrors may comprise a corresponding pair of current mirrors, the method may comprise: summing a first mirrored current and a second mirrored current obtained using the corresponding pair of current mirrors of the set of current mirrors to form the first replicate current, wherein the first mirrored current and the second mirrored current are associated with a first pair of transistors selected from the corresponding pair of pull-up (PU) transistors, the corresponding pair of pull-down (PD) transistors or the corresponding pair of pass-gate (PG) transistors of the first bitcell based on the bitcell current type comprised in the PUF challenge input, and wherein a magnitude of the first mirrored current and a magnitude of the second mirrored current are dependent on the bitcell state and process-induced random mismatches in the corresponding pair of pull-up (PU) transistors, the corresponding pair of pull-down (PD) transistors and the corresponding pair of pass-gate (PG) transistors of the first bitcell; and summing a third mirrored current and a fourth mirrored current obtained using the corresponding pair of current mirrors of the set of current mirrors to form the second replicate current, wherein the third mirrored current and the fourth mirrored current are associated with a second pair of transistors selected from the corresponding pair of pull-up (PU) transistors, the corresponding pair of pull-down (PD) transistors or the corresponding pair of pass-gate (PG) transistors of the second bitcell based on the bitcell current type comprised in the PUF challenge input, and wherein a magnitude of the third mirrored current and a magnitude of the fourth mirrored current are dependent on the bitcell state and process-induced random mismatches in the corresponding pair of pull-up (PU) transistors, the corresponding pair of pull-down (PD) transistors and the corresponding pair of pass-gate (PG) transistors of the second bitcell.

[0021] In accordance with a third aspect, there is provided a system for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM) comprising a plurality of bitcells arranged in rows and columns, the system comprising a PUF periphery operationally connected to the SRAM and is configured to: (i) receive a PUF challenge input for generating the PUF bit, the PUF challenge input comprising challenge bits to define a bitcell current type, a bitcell state of a first bitcell of the plurality of bitcells and a bitcell state of a second bitcell of the plurality of bitcells, an address of the first bitcell and an address of the second bitcell, wherein the address of the first bitcell and the address of the second bitcell are defined using a row and a column associated with each of the first bitcell and the second bitcell; (ii) obtain a first replicate current associated with a transistor of the first bitcell, wherein selection of the transistor of the first bitcell is associated with the bitcell current type and the bitcell state of the first bitcell; (iii) obtain a second replicate current associated with a transistor of the second bitcell, wherein selection of the transistor of the second bitcell is associated with the bitcell current type and the bitcell state of the second bitcell; (iv) digitize the first replicate current and the second replicate current to form a digitized first replicate current and a digitized second replicate current respectively; and (v) compare the digitized first replicate current and the digitized second replicate current to generate the PUF bit. The PUF periphery may comprise a set of current mirrors, the set of current mirrors may comprise a PMOS set of current mirrors and a NMOS set of current mirrors, the system may be configured to: replicate, by using the set of current mirrors, a first current associated with the transistor of the first bitcell to obtain the first replicate current; and replicate, by using the set of current mirrors, a second current associated with the transistor of the second bitcell to obtain the second replicate current, wherein selection of the PMOS set of current mirrors or the NMOS set of current mirrors for replicating the first current or the second current is based on the bitcell current type. The system may be configured to: under-drive or over-drive a first wordline (WL) voltage associated with the first bitcell based on the bitcell current type for selecting the transistor of the first bitcell; and under-drive or over-drive a second wordline (WL) voltage associated with the second bitcell based on the bitcell current type for selecting the transistor of the second bitcell.

[0022] The system may comprise a current-starved ring oscillator (CSRO) and a time-to-digital converter, the system may be configured to: convert, using the CSRO, the first replicate current to form a first frequency and the second replicate current to form a second frequency; and convert, using the time-to-digital converter, oscillations associated with a first time period associated with the first frequency to form the digitized first replicate current and oscillations associated with a second time period associated with the second frequency to form the digitized second replicate current.

[0023] The CSRO may comprise a first set of current mirror ratio-tunable fingers and a second set of current mirror ratio-tunable fingers, the first set of current mirror ratio-tunable fingers may be adapted to receive replicate PMOS currents from the PMOS set of current mirrors, and the second set of current mirror ratio-tunable fingers may be adapted to receive replicate NMOS currents from the NMOS set of current mirrors, a magnitude of the replicate PMOS currents and a magnitude of the replicate NMOS currents being dependent on the corresponding bitcell state, the system may be configured to: self-calibrate the first set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the first set of current mirror ratio-tunable fingers to minimize bias in the 0 / 1 distribution of the generated PUF bits due to process-induced mismatch in the PMOS set of current mirrors; and self-calibrate the second set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the second set of current mirror ratio-tunable fingers to minimize bias in the 0 / 1 distribution of the generated PUF bits due to process-induced mismatch in the NMOS set of current mirrors.

[0024] The system may comprise self-limiting frequency dividers, the system may be configured to: control, using the self-limiting frequency dividers, a number of the oscillations sensed in the first time period associated with the first frequency and a number of the oscillations sensed in the second time period associated with the second frequency.

[0025] The system may comprise a level shifter, the system may be configured to: voltagelevel shift, using the level shifter, outputs associated with the first frequency and the second frequency prior to providing the voltage level-shifted outputs to the self-limiting frequency dividers for controlling the number of the oscillations sensed.

[0026] The first bitcell and the second bitcell may be from different columns of the SRAM. The system may be configured to: use the generated PUF bit to form a row address offset to generate a new PUF challenge input internally, the new PUF challenge input comprising a new row address associated with the row address offset, the bitcell current type and new bitcell states for use with a new pair of bitcells associated with the new row address, wherein the new bitcell states corresponds to the bitcell state of the first bitcell and the bitcell state of the second bitcell; and repeat the steps (ii) to (iv) based on the new PUF challenge input to obtain a new PUF bit.

[0027] The new row address may be within a same SRAM bank of the SRAM as the row of the address of the first bitcell and the row of the address of the second bitcell.

[0028] The first bitcell and the second bitcell may each comprise a 6-transistors (6T) SRAM cell.

[0029] It should be appreciated that features relating to one aspect may be applicable to the other aspects. Embodiments provide a method and system for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM). Particularly, by selecting the transistor of the first bitcell based on the bitcell current type and the bitcell state of the first bitcell and selecting the transistor of the second bitcell based on the bitcell current type and the bitcell state of the second bitcell, the data stored (i.e. the bitcell state of 1 or 0) in the SRAM bitcells is utilised for generation of the PUF bit. The PUF bit generated using the present method therefore incorporates chip-specific fingerprinting of at-rest or in-transit data (e.g., assessing whether a video frame was actually produced / stored in a specific chip and location) for user authentication. Enabling data provenance assurance or data fingerprinting as an extra layer of security in this way uniquely associates each piece of received data to the originating device, including the specific bitcells where data resided (e.g., for data integrity, authenticity, and traceability). This enables establishment of a two-way association between the data received and the origin device, thereby improving security provided by the PUF bit. Further, by comparing the digitized first replicate current and the digitized second replicate current to generate the PUF bit, this differential nature makes the PUF bit generated robust against correlated process, voltage, and temperature variations experienced by the bitcells of the SRAM. Still further, it is noted that the PUF bit generated using this method has native cryptography-grade quality with no entropy post-processing (e.g. Von Neumann extractor) or ECC stability enhancement. This therefore leads to a low-cost low-power method for generating PUF bits. The PUF periphery for performing the present methods is adapted to work with ubiquitously available SRAMs and so any modification of the SRAM designs is not required for deploying the present method. In an embodiment relating to 6-transistors (6T) SRAM bit cells, six PUF bits can be generated from each SRAM bitcell. Thus, a high PUF to memory capacity ratio is obtained for high bit density and high PUF array utilization.

[0030] Brief description of the

[0031]

[0032] Embodiments will now be described, by way of example only, with reference to the following drawings, in which:

[0033] Figure 1 is a diagram illustrating multi-bit Static Random-Access Memory (SRAM) Physically Unclonable Function (PUF) requirements in a resource-constrained system in accordance with an embodiment;

[0034] Figure 2 is a diagram illustrating features relating to chip embedded roots of trust including PUF and chip- / data-specific data fingerprinting in accordance with an embodiment; Figure 3 is a flowchart of a method for generating a PUF bit from a SRAM in accordance with an embodiment;

[0035] Figure 4 is a flowchart of a method for isolating a transistor in a bitcell using sets of current mirrors in accordance with an embodiment;

[0036] Figure 5 is a flowchart of a method for isolating a transistor in a bitcell by under-driving or over-driving a wordline (WL) voltage of the bitcell in accordance with an embodiment; Figure 6 is a flowchart of a method for digitizing the first replicate current and the second replicate current of the method of Figure 3 in accordance with an embodiment; Figure 7 is a schematic diagram illustrating use of a PUF periphery for performing the method of Figure 3 for a 6-transistors (6T) SRAM in accordance with an embodiment; Figures 8A and 8B are schematics to illustrate mechanisms for isolating pull-down (PD) transistors of the 6T SRAM bitcell of Figure 7 in accordance with an embodiment, where Figure 8A is a schematic to illustrate isolating a PD transistor on a left side connecting to the bit-line (BL) of the bitcell and Figure 8B is a schematic to illustrate isolating a PD transistor on a right side connecting to the bit-line-bar (BLB) of the bitcell; Figures 9A and 9B are schematics to illustrate mechanisms for isolating pass-gate (PG) transistors of the 6T SRAM bitcell of Figure 7 in accordance with an embodiment, where Figure 9A is a schematic to illustrate isolating a PG transistor on a left side connecting to the bit-line (BL) of the bitcell and Figure 9B is a schematic to illustrate isolating a PG transistor on a right side connecting to the bit-line-bar (BLB) of the bitcell; Figures 10A and 10B are schematics to illustrate mechanisms for isolating pull-up (PU) transistors of the 6T SRAM of bitcell Figure 7 in accordance with an embodiment, where Figure 10A is a schematic to illustrate isolating a PU transistor on a left side connecting to the bit-line (BL) of the bitcell and Figure 10B is a schematic to illustrate isolating a PU transistor on a right side connecting to the bit-line-bar (BLB) of the bitcell; Figure 11 shows a schematic to illustrate digitization of the replicate currents from a bitcell (i.e. a first bitcell) and its neighbouring bitcell (i.e. a second bitcell) and comparing the digitized replicate currents to obtain a PUF bit in accordance with an embodiment; Figures 12A and 12B are diagrams to illustrate possible combinations for generating PUF bits using two bitcells in accordance with an embodiment, where Figure 12A is a diagram to illustrate combinations in relation to a bitcell current type and a bitcell state and Figure 12B is a diagram to illustrate the 12 combinations achievable for the two bit cells;

[0037] Figure 13 is a schematic to illustrate a current-starved ring-oscillator (CSRO) based current-to-digital converter in accordance with an embodiment;

[0038] Figure 14 is a schematic to illustrate a self-limiting frequency divider used in the CSRO-based current-to-digital converter of Figure 13 in accordance with an embodiment; Figure 15 is a diagram to illustrate generation of a PUF bit by comparing the digitized replicate currents obtained from two bitcells in accordance with an embodiment;

[0039] Figure 16 is a schematic diagram to illustrate use of current mirror fingers to calibrate a strength of a replicate current in accordance with an embodiment;

[0040] Figure 17 is a flowchart of a method for calibrating a strength of the replicate current using the current mirror fingers of Figure 16 in accordance with an embodiment;

[0041] Figure 18 is a schematic diagram to illustrate a same circuitry relating to self-calibration being re-used for different bitcell current types in accordance with an embodiment; Figure 19 is a graph of probability density versus time-to-digital converter (TDC) counts to illustrate effects of addition or subtraction of current mirror fingers in accordance with an embodiment;

[0042] Figure 20 is a graph of probability density versus bitcell column bias to illustrate effects of addition or subtraction of current mirror fingers in accordance with an embodiment; Figure 21 is a graph of probability density versus column entropy to illustrate an unbiased 0 or 1 digitized output distribution after an one-time self-calibration using the current mirror fingers of Figure 16 in accordance with an embodiment;

[0043] Figure 22 is a graph of occurrences versus normalized measured current-to-digital converter output to illustrate effects of addition or subtraction of current mirror fingers in accordance with an embodiment; Figure 23 is a graph of occurrences versus measured entropy for bitcell columns to illustrate an unbiased 0 or 1 (0 / 1) distribution of the generated digitized output (PUF bits) after an one-time self-calibration using the current mirror fingers of Figure 16 in accordance with an embodiment;

[0044] Figure 24 is a schematic to illustrate no column-to-column correlation in PUF bits generated using the method of Figure 3 in accordance with an embodiment;

[0045] Figure 25 is a flowchart of a method for supressing bit-to-bit correlation using singlecycle re-addressing (SCRA) in accordance with an embodiment;

[0046] Figure 26 is a diagram of two PUF challenge inputs for one common bitcell and bitcell current type for illustrating effects of SCRA with respect to in accordance with an embodiment;

[0047] Figure 27 is a diagram for providing details of the example of Figure 26 to illustrate effects of SCRA with respect to two PUF challenge inputs for one common bitcell and bitcell current type before and after SCRA in accordance with an embodiment;

[0048] Figures 28A, 28B, 28C are circuit diagrams of a bitcell to illustrate effects of SCRA with respect to two PUF challenge inputs for one common bitcell and bitcell current type before and after SCRA in accordance with an embodiment;

[0049] Figure 29 is a schematic diagram to illustrate a closed-loop implementation and an open-loop implementation of SCRA in accordance with embodiments;

[0050] Figure 30 is a work flow for illustrating data fingerprinting in accordance with an embodiment;

[0051] Figure 31 shows a series of photographs of a 28-nm SRAM PUF testchip and testing setup in accordance with an embodiment;

[0052] Figure 32 is a graph of 0 / 1 bias measurements to illustrate the effects of pre- and postself-calibration in accordance with embodiments;

[0053] Figures 33A and 33B are diagrams showing measured speckle patterns from SRAM banks and dice of the 28-nm SRAM PUF testchip of Figure 31 before and after selfcalibration in accordance with an embodiment, where Figure 33A is a diagram of measured speckle pattern before self-calibration and Figure 33B is a diagram of measured speckle pattern after self-calibration;

[0054] Figures 34A and 34B are diagrams showing measured speckle patterns of PUF bitstreams from the 28-nm SRAM PUF testchip of Figure 31 before and after selfcalibration in accordance with an embodiment, where Figure 34A is a diagram of measured speckle pattern before self-calibration and Figure 34B is a diagram of measured speckle pattern after self-calibration;

[0055] Figures 35A, 35B and 35C are diagrams to demonstrate data fingerprints extraction from a stored video frame in accordance with an embodiment, where Figure 35A is a picture of the stored video frame, Figure 35B is a diagram illustrating the data fingerprint on chip 1 extracted from the stored video frame and Figure 35C is a diagram illustrating the data fingerprint on chip 2 extracted from the stored video frame;

[0056] Figure 36 shows graphs of measured correlation coefficient to illustrate inter-column correlation for transistors having a same row number, a same bitcell current type and a same bitcell state across different columns and intra-cell correlation at the same row number and same column across different bitcell configurations with- and without SCRA under closed-loop re-addressing in accordance with an embodiment;

[0057] Figure 37 shows a graph of measured correlation coefficient to illustrate intra-cell correlation at the same row number and same column across different bitcell configurations with- and without SCRA under open-loop re-addressing in accordance with an embodiment;

[0058] Figures 38A, 38B, 38C show plots of measured autocorrelation function across 8000 bits of PU, PD and PG type of PUF bits in accordance with an embodiment, where Figure 38A shows a plot of measured autocorrelation function prior to SCRA, Figure 38B shows a plot of measured autocorrelation function after SCRA closed-loop readdressing, and Figure 38C shows a plot of measured autocorrelation function after SCRA open-loop re-addressing;

[0059] Figures 39A and 39B show graphs of measured probability values (p-values) of randomness tests prior to self-calibration of the 28-nm SRAM PUF testchip of Figure 31 in accordance with an embodiment, where Figure 39A shows a graph of measured average p-values and Figure 39B shows a graph of measured minimum p-values; Figures 40A and 40B show graphs of measured probability values (p-values) of randomness tests post self-calibration of the 28-nm SRAM PUF testchip of Figure 31 in accordance with an embodiment, where Figure 40A shows a graph of measured average p-values and Figure 40B shows a graph of measured minimum p-values; Figure 41 shows a graph of inter- and intra-PUF Hamming distance among all PUF bits generated using the 28-nm SRAM PUF testchip of Figure 31 in accordance with an embodiment;

[0060] Figure 42 shows a plot of measured time-to-digital converter (TDC) counts against pulse width setting in accordance with an embodiment;

[0061] Figure 43 shows a plot of PUF bit instability versus pulse width setting in accordance with an embodiment;

[0062] Figure 44 shows a graph of measured bit error rate and unstable bits versus frequency ratio of a self-limiting frequency divider in accordance with an embodiment;

[0063] Figure 45 shows a graph of normalized energy / bit in current-to-digital converter versus frequency ratio in self-limiting frequency divider in accordance with an embodiment; Figure 46 shows a graph of measured bit error rate and unstable bits for different PUF bit types PD, PG, and PU based on native evaluations or with temporal majority voting with three PUF evaluations (TMV-3) in accordance with embodiments;

[0064] Figure 47 shows a graph of measured average bit error rate and unstable bits across six PUF bits per bitcell against a number of PUF evaluations based on native evaluations or with temporal majority voting with three PUF evaluations (TMV-3) in accordance with embodiments;

[0065] Figure 48 shows a graph of measured unstable bits for different PUF bit types PD, PG, and PU and different testing conditions (of voltage and temperature) based on 1500 PUF evaluations (with TMV-3) in accordance with an embodiment;

[0066] Figure 49 shows a graph of measured energy / bit for different PUF bit types PD, PG, and PU and different testing conditions in accordance with an embodiment; Figure 50 shows a graph of measured post-aging bit error rate and unstable bits against accelerated aging hours based on 300 evaluations (with TMV-3) in accordance with an embodiment; and

[0067] Figure 51 shows a graph of normalised count versus correlation coefficient to illustrate measured correlation between data fingerprint reconstructed by cloud and the actual fingerprint received from edge devices in accordance with an embodiment.

[0068] Detailed description

[0069] Exemplary embodiments relate to a method and system for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM).

[0070] Figure 1 provides some challenges for achieving multi-bit SRAM PUFs. Figure 2 illustrates features relating to chip embedded roots of trust including PUF and chip- / data-specific data fingerprinting. Figures 3 to 6 describe methods and systems for generating a PUF bit from SRAM bitcells, utilising data stored in the specific bitcells to incorporate data fingerprinting in PUF bits generation. Figures 7 to 51 relates to embodiments associated with a six-transistor (6T) SRAM bitcell design, including experimental results obtained using a 28-nm testchip.

[0071] Figure 1 is a diagram 100 illustrating multi-bit Static Random-Access Memory (SRAM) Physically Unclonable Function (PUF) challenges or requirements in a resource-constrained system. As shown in an arrow 102, general considerations of SRAM PUF include (i) an entropy source for generating a PUF bit, (ii) stability improvement of the PUF bit, and (iii) entropy restoration and error-correcting code (ECG) for PUF bit detection. Entropy restoration and ECC add energy and area overhead so these should ideally be avoided. Also shown in Figure 1 is a SRAM array 104 comprising a plurality of bitcells arranged in rows and columns where each bitcell stores 1 data (e.g. 0 or 1) per bitcell. A multi-bit PUF bit map 106 can be formed using the SRAM array 104 having multiple PUF bit per bitcell but this is limited by non-correctable bits in the multibit PUF bit map 106 which has to be masked for stability and thereby degrading the overall PUF bit capacity. A PUF-to-SRAM capacity ratio can be calculated using Equation (1):

[0072] PUF-to-SRAM capacity ratio = SRAM capacity x NPUF bit / bitcellx (1 - masking ratio) (1) Figure 2 is a diagram 200 illustrating features related to chip embedded roots of trust in accordance with an embodiment. In the present disclosure, besides the physically unclonable function 202 arising inherently from the inherent, uncontrollable variations in the manufacturing of e.g. transistors in the SRAM, chip- / data-specific data fingerprinting 204 is also utilised. The diagram 200 provides some illustrations in relation to these two features being considered in the methods and the systems for the present disclosure. Particularly, in the present disclosure, bitcell states of each bitcells are taken into consideration for generating a PUF bit, thereby incorporating data fingerprinting in the present methods and systems and achieving higher PUF-to-SRAM capacity ratio as compared to present art.

[0073] As will be shown in the following embodiments, the methods and systems of the present disclosure are (i) adaptable to commercial or existing SRAMs for PUF bit generation, (ii) able to achieve high PUF-to-SRAM capacity by extracting entropy from every bitcell transistor, (iii) adaptable to enable data fingerprinting, and (iv) able to eliminate entropy restoration or ECC.

[0074] Figure 3 is a flowchart of a method 300 for generating a PUF bit from a SRAM in accordance with an embodiment, where the SRAM comprises a plurality of bitcells arranged in rows and columns for generating the PUF bit. It should be appreciated that the method 300 can be applied in a SRAM with an array of bitcells (e.g. as shown in relation to Figure 1) and thereby generating a plurality of PUF bits per bit cell. In the present embodiment, the method 300 is implemented using a system comprising a PUF periphery operationally connected to the SRAM and so this method 300 can be applied to any commercially available SRAM without the need for customized design. In a step 302, a PUF challenge input for generating the PUF bit is received. The PUF challenge input comprises challenge bits to define a bitcell current type, a bitcell state of a first bitcell of the plurality of bitcells, a bitcell state of a second bitcell of the plurality of bitcells, an address of the first bitcell as defined by its corresponding row and column and an address of the second bitcell as defined by its corresponding row and column. In an embodiment for a 6T-SRAM bitcell, the bitcell current type includes a pull-down (PD) current (i.e. current drawn through PD transistors of the 6T-SRAM bitcell), a passgate (PG) current (i.e. current drawn through PG transistors of the 6T-SRAM bitcell) and a pull-up (PU) current (i.e. current drawn through PU transistors of the 6T-SRAM bitcell). The bitcell state of the first bitcell and the bitcell state of the second bitcell relates to the binary data bit stored in the first bitcell and the second bitcell respectively, and can be in the form of “1” or “0”.

[0075] In a step 304, a first replicate current associated with a transistor of the first bitcell is obtained. Selection of the transistor of the first bitcell is associated with the bitcell current type and the bitcell state of the first bitcell.

[0076] In a step 306, a second replicate current associated with a transistor of the second bitcell is obtained. Selection of the transistor of the second bitcell is associated with the bitcell current type and the bitcell state of the second bitcell.

[0077] In an embodiment for a 6T-SRAM bitcell, the transistor includes a pull-down (PD) transistor, a pass-gate (PG) transistor, or a pull-up (PU) transistor. As there are a pair of PD transistors, a pair of PG transistors and a pair of PU transistors in a 6T-SRAM bitcell, selection of which of the PD transistor (i.e. left or right), which of the PG transistors (i.e. left or right), or which of the PU transistors (i.e. left or right) can further be based on the bitcell state of the 6T-SRAM bitcell. Therefore, in the case of a 6T-SRAM bitcell, the bitcell current type and the bitcell state of the bitcell provide the handles required to isolate a transistor of the bitcell for use in generating a PUF bit. Details of this embodiment will be described in relation to Figures 7 to 10B below. In a step 308, the first replicate current and the second replicate current are digitized to form a digitized first replicate current and a digitized second replicate current respectively. The step 308 about digitizing the first replicate current and the second replicate current is discussed in further details in relation to Figure 6 below. Further, as would be shown in relation to the example for a 6T-SRAM, other functionalities can be included in this step to provide for self-calibration as well as pulse width adjustment to manage an energy-stability tradeoff for PUF bits generation.

[0078] In a step 310, the digitized first replicate current and the digitized second replicate current are compared to generate the PUF bit. The generated PUF bit can then be used for verification, as shown in an example in relation to Figure 30 below.

[0079] Figure 4 is a flowchart of a method 400 for isolating a transistor in a bitcell using sets of current mirrors in accordance with an embodiment. In an embodiment, as shown in relation to the example for a 6T-SRAM below, PMOS current mirrors and NMOS current mirrors are used in the PUF periphery for extracting the desired current type from a 6T-SRAM bitcell.

[0080] In a step 402, a first current associated with the transistor of the first bitcell is replicated using a set of current mirrors to obtain the first replicate current.

[0081] In a step 404, a second current associated with the transistor of the second bitcell is replicated using the set of current mirrors to obtain the second replicate current.

[0082] In an embodiment, the set of current mirrors comprises a PMOS set of current mirrors and a NMOS set of current mirrors, and selection of the PMOS set of current mirrors or the NMOS set of current mirrors for replicating the first current or the second current is based on the corresponding bitcell current type.

[0083] Referring to an embodiment for a 6T-SRAM, the PMOS set of current mirrors can be used to select the PD or PG current type of transistors while the NMOS set of current mirrors can be used to select the PU current type of transistors. This can be applied to each of the first bitcell and the second bitcell.

[0084] Figure 5 is a flowchart of a method 500 for isolating a transistor in a bitcell by underdriving or over-driving a wordline (WL) voltage of the bitcell in accordance with an embodiment. Further to the method 400 as described above, the wordline (WL) voltage of a bitcell can be used as a handle to isolate the desired transistor in the bitcell.

[0085] In a step 502, a first wordline (WL) voltage associated with the first bitcell can be under-driven or over-driven based on the bitcell current type for selecting the transistor of the first bitcell.

[0086] In a step 504, a second wordline (WL) voltage associated with the second bitcell can be under-driven or over-driven based on the bitcell current type for selecting the transistor of the second bitcell.

[0087] In an embodiment for a 6T-SRAM, a WL voltage associated with the first bitcell or the second bitcell can be employed to isolate the PD current type transistors from the PG current type transistors. This is illustrated in relation to Figures 8A to 9B below. Figure 6 is a flowchart of a method 600 for digitizing the first replicate current and the second replicate current of the method 300 of Figure 3 in accordance with an embodiment.

[0088] In a step 602, the first replicate current and the second replicate current are converted, using a current-starved ring oscillator (CSRO), to form a first frequency and a second frequency, respectively. The CSRO is described in more detail in relation to Figure 13 below.

[0089] In a step 604, oscillations associated with a first time period associated with the first frequency and oscillations associated with a second time period associated with the second frequency are converted, using a time-to-digital converter, to form the digitized first replicate current and the digitized second replicate current, respectively.

[0090] In an embodiment, the CSRO comprises a first set of current mirror ratio-tunable fingers and a second set of current mirror ratio-tunable fingers. The first set of current mirror ratio-tunable fingers is adapted to receive replicate PMOS currents from the PMOS set of current mirrors, and the second set of current mirror ratio-tunable fingers is adapted to receive replicate NMOS currents from the NMOS set of current mirrors. As will be made clear in relation to the example described in relation to Figure 7 to 10B, a magnitude of the replicate PMOS currents is dependent on a bitcell state of the bitcell selected for the input challenge. For example, a bitcell state of “1” with over-driven WL would mean the PDrightbitcell current type dominates and a bitcell state of “0” with overdriven WL would mean the PDleftbitcell current type dominates in Ireplica- Similarly, a magnitude of the replicate NMOS currents is also dependent on a bitcell state of the bitcell (e.g. “1” state would mean PUleftbitcell current type dominates and “0” state would mean PUrightbitcell current type dominates). The method 600 further comprises: (a) self-calibrating the first set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the first set of current mirror ratio-tunable fingers to minimize bias with respect to 1 or 0 state of the generated PUF output bits due to process-induced mismatch in the corresponding set of current mirrors, and (b) self-calibrating the second set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the second set of current mirror ratio-tunable fingers to minimize bias with respect to 1 or 0 state of the generated PUF output bits due to process-induced mismatch in the corresponding set of current mirrors. The self-calibration process is repeated for PMOS and NMOS current mirrors, thereby selecting a desirable mirroring ratio configuration. Selfcalibration is thus used to adjust a magnitude of the corresponding replicate currents (i.e. replicate PMOS currents and replicate NMOS currents) to compensate for the effect of mismatch between the left- and right-side current mirrors in the PUF periphery. This removes any skew (i.e., bias) with respect to 1 or 0 outputs of the generated PUF bits across SRAM columns. In the present embodiment, this self-calibration process is a one-time process. Once calibrated, the same setting of the digital enablement bits (or the same mirroring ratio) is used for any subsequent PUF bits generation from the SRAM.

[0091] In an embodiment, a current-to-digital converter of the system for performing the method 600 comprises self-limiting frequency dividers, and the method further comprises controlling, using the self-limiting frequency dividers, a number of the oscillations sensed in the first time period associated with the first frequency and a number of the oscillations sensed in the second time period associated with the second frequency. This allows an output pulse width of the CSRO to be adjustable, thereby providing a handle to adjust a frequency ratio and hence acts as an effective handle to manage energy-stability tradeoff, where a higher frequency ratio allows finer differentiation of slightly different currents but at a cost of higher energy due to higher number of CSRO transitions and counts.

[0092] In an embodiment, the current-to-digital converter of the system further comprises a level shifter, and the method comprises leveling, using the level shifter, outputs associated with the first frequency and the second frequency prior to providing the leveled outputs to the self-limiting frequency dividers for controlling the number of the oscillations sensed. The level shifter in this embodiment can be used to eliminate any switching failures of the self-limiting frequency dividers due to infrequent, incomplete swing output of the CSRO across skewed process corners.

[0093] The general methods and systems for generating a PUF bit from a SRAM have been described above. In the below, specific embodiments relating to a 6T-SRAM are described. The following embodiments relate to a novel SRAM-based PUF for extracting static entropy from every transistor of an unmodified six-transistor (6T) SRAM bitcell for generating 6 PUF bits per bitcell. As illustrated below, this multi-bit SRAM PUF achieves a PUF-to-SRAM capacity of 296%, while not requiring any error correcting code (ECC), retaining its energy and area efficiency at system level. In addition to PUF operation, its data-dependent static entropy extraction enables data fingerprinting capability. The latter represents an additional layer of security providing stored data (physical) provenance assurance, and user authentication in real time or in retrospect. In addition, the PUF output has native cryptographic-grade quality after one-time selfcalibration, uniquely suppressing any entropy post-processing circuitry. If required, the high PUF-to-SRAM capacity provided in the present embodiment also allows for postprocessing stabilization based on conventional bit masking. Competitive 134 F2 / bit area efficiency is demonstrated in 28 nm with minor modification of conventional SRAM periphery.

[0094] The methods 300, 400, 500, 600 as described in relation to Figures 3 to 6 are employed using 6T-SRAM bitcells and these, together with other circuit techniques, are described in relation to Figures 7 to 30. Figures 31 to 51 relate to experimental results or data obtained using a 28-nm test chip employing the methods of the present disclosure.

[0095] Multi-Bit Static Entropy Extraction Method

[0096] A multi-bit static entropy extraction method is discussed in relation to Figures 7 to 10B below.

[0097] Figure 7 is a schematic diagram 700 illustrating use of a PUF periphery for performing the method 300 of Figure 3 for a 6-transistors (6T) SRAM in accordance with an embodiment. An unmodified 6T SRAM array 702 and the PUF periphery 704 are shown in Figure 7. The PUF periphery 704 is part of the system of the present disclosure which can be operationally connected to any commercially available SRAM for performing the methods of the present disclosure.

[0098] As shown in Figure 7, the 6T SRAM array 702 comprises a plurality of bitcells arranged in rows and columns. Row 0 706 to row i 708 for column 0 710 of the 6T SRAM array 702 are shown in Figure 7, with column 1 712 being indicated as a separate plane beneath column 0 710. Although not shown explicitly for succinctness, it should be appreciated that each of the columns of the 6T SRAM array 702 includes row 0 to row i, and each row for each of these columns defines one bitcell as shown in Figure 7. In the example as shown in relation to Figure 7, for the present embodiment of a 6T SRAM bitcell, each bitcell comprises two RD transistors (i.e. PDleftand PDright), two PG transistors (i.e. PGieft and PGright) and two PU transistors (i.e. PUieft and PUright)- The PDieft, PGieft, and PUieft transistors are connected to the bitline (BL) of column 0 710 of the 6T SRAM array while the PDright, PGright, and PUrighttransistors are connected to the bitline-bar (BLB) of column 0 710 of the 6T SRAM array. The present disclosure provides methods to extract static entropy from each of these six transistors to generate a PUF bit. In the present embodiment, the column 0 and column 1 of the SRAM array are connected to a 2:1 column multiplexer 714 for SRAM read / write operations. Also shown in Figure 7 is a SRAM read / write periphery 716 for reading and writing data to the 6T SRAM array.

[0099] Also shown in Figure 7 are the components of the PUF periphery 704. It is noted that switches in the PUF periphery 704 are simplified for succinctness. The PUF periphery 704 of the present embodiment includes a 8:1 column multiplexer 722 for reading PUF from the 6T-SRAM array, a PMOS set of current mirrors 724, a NMOS set of current mirrors 726 and a current-to-digital converter 728. The PMOS set of current mirrors 724 includes a pair of current mirrors 730, 732, where the PMOS current mirror 730 is adapted to be electrically connectable to the BL line for the PDleftand PGlefttransistors of the SRAM columns and the PMOS current mirror 732 is adapted to be electrically connectable to the BLB line for the PDrightand PGright transistors of the SRAM columns. Similarly, the NMOS set of current mirrors 726 includes a pair of current mirrors 734, 736, where the NMOS current mirror 734 is adapted to be electrically connectable to the BL line for the PUlefttransistors of the SRAM columns and the NMOS current mirror 736 is adapted to be electrically connectable to the BLB line for the PUrighttransistors of the SRAM columns. Currents from the relevant transistors are replicated using these current mirrors 730, 732, 734, 736 to obtain or generate the replicate currents accordingly. The current mirrors 730, 732, 734, 736 are reused across the 16 SRAM columns in the present embodiment. For example, the current mirrors 730, 732, 734, 736 are connected to one column for read-out of a current associated a transistor of a first bitcell, and are then connected to another column for read-out of another current associated with a transistor of a second bitcell for forming the replicate currents. The replicate currents are provided to the current-to-digital converter 728 for converting the replicate currents to digitized replicate currents. The current-to-digital converter 728 is also reused across the 16 SRAM columns in the present embodiment.

[0100] Using the SRAM PUF architecture as shown in relation to Figure 7, multi-bit static entropy generation in the SRAM can be obtained by differentially comparing the currents generated by two neighboring bitcells, which can be grouped into nonoverlapping pairs across columns to suppress bit correlation. Digitized replicate currents formed by a pair of bitcells or a pair of neighboring bitcells can be compared to generate a PUF bit 738. In the present embodiment, the PUF periphery 704 can be shared across each group of 16 adjacent SRAM columns. The addition of the currentmode RUF periphery 704 keeps the original column-level readout periphery unmodified, can be easily pitch-matched for seamless adoption in memory compilers, and assures low area overhead thanks to its reuse across columns. Moreover, the present currentmode approach mitigates the impact of parasitic capacitance mismatch at the column level, as opposed to traditional voltage-mode peripherals.

[0101] To generate a PUF bit, a static entropy generation request (e.g., from an encryption engine) determines a PUF challenge input (e.g. in the form of input challenge bits). The PUF challenge input includes challenge bits defining a row and / or column address of the SRAM array, a bitcell current type and bitcell states for each of the pair of bitcells for use in generating a PUF bit. The PUF challenge input is used to determine whether the PMOS set of current mirrors 724 or the NMOS set of current mirrors 726 are activated. The current mirrors replicate the current through the PMOS bitcell transistors (i.e. the PUleftand PUrighttransistors) or NMOS bitcell transistors (i.e. the PDieftand PDrighttransistors or PGiett and PGrigm transistors) and mirror it to the output current Ireplica. A magnitude of the output current Ireplicais dependent on the bitcell state as well as the process-induced random mismatches associated with the pairs of PUieft and PUrighttransistors, PDieft and PDrighttransistors, and PGiett and PGri ht transistors. The replicate currents of two bitcells are digitized by the current-to-digital converter, and digitally compared to generate a 1 -bit PUF output from each of the six bitcell transistors, as discussed below. For simplicity, a single bit is extracted from each transistor in the following, although potentially multiple bits could be generated. To generate 6 PUF bits from a 6T SRAM bitcell, the mismatch or unique variations within each transistor are individually isolated before the above current strength comparison. This is achieved by sensing the pull-up PU (or pull-down PD) current of a selected bitcell transistor via a NMOS (or PMOS) set of current mirrors (sized to prevent read disturbance). The two mirrored currents from PU (PD) replicate the currents flowing from the two sides (BL / BLB) of the bitcell, and are then summed via direct connection. The resulting sum current Ireplicadepends on the mismatch of the targeted bitcell transistors, which can be selected via three binary selection mechanisms as activated accordingly in response to the received challenge bits. The three binary selection mechanism include: (i) PMOS / NMOS type of activated current mirrors (for selecting PD transistors or PG transistors by using PMOS set of current mirrors and for selecting PU transistors by using NMOS set of current mirrors), (ii) under / over-boosted wordline (WL) voltage assist (e.g. by emphasizing the pass-gate PG transistor mismatch via increasing its resistance well above the PU / PD transistor resistance by under-driving the wordline WL or by emphasizing the resistance of the PU / PD transistor mismatch via increasing its resistance well above the PG transistor resistance by over-driving the wordline WL), and (iii) 0 / 1 stored bitcell data (e.g. by selecting the bitcell left (right) side storing a 0 (1), which inherently activates the bitcell read current on the corresponding bitcell side), as discussed below. Such assist techniques are ubiquitously available in modern SRAM memories, regardless of their use as a PUF.

[0102] Figures 8A to 10C below relate to schematics to illustrate mechanisms for isolating the relevant transistors in a bitcell of the 6T SRAM.

[0103] Figures 8A and 8B are schematics 800, 810 to illustrate mechanisms for isolating pulldown (PD) transistors of the 6T SRAM bitcell of Figure 7 in accordance with an embodiment, where Figure 8A is a schematic 800 to illustrate isolating a PD transistor on a left side connecting to the bit-line (BL) of the bitcell and Figure 8B is a schematic 810 to illustrate isolating a PD transistor on a right side connecting to the bit-line-bar (BLB) of the bitcell.

[0104] Figures 9A and 9B are schematics 900, 910 to illustrate mechanisms for isolating passgate (PG) transistors of the 6T SRAM bitcell of Figure 7 in accordance with an embodiment, where Figure 9A is a schematic 900 to illustrate isolating a PG transistor on a left side connecting to the bit-line (BL) of the bitcell and Figure 9B is a schematic 910 to illustrate isolating a PG transistor on a right side connecting to the bit-line-bar (BLB) of the bitcell.

[0105] Figures 10A and 10B are schematics 1000, 1010 to illustrate mechanisms for isolating pull-up (PU) transistors of the 6T SRAM bitcell of Figure 7 in accordance with an embodiment, where Figure 10A is a schematic 1000 to illustrate isolating a PU transistor on a left side connecting to the bit-line (BL) of the bitcell and Figure 10B is a schematic 1010 to illustrate isolating a PU transistor on a right side connecting to the bit-line-bar (BLB) of the bitcell.

[0106] Referring to Figures 8A to 10B, the first mismatch isolation mechanism is determined by the type of activated current mirrors (i.e. the PMOS set of current mirrors 724 or the NMOS set of current mirrors 726) in the PUF periphery 704 and uses the latter as an active load of the bitcell selected within a column of the 6T SRAM array. When activating the PMOS set of current mirrors, the common current of the pull-down and pass-gate transistors (PD and PG) is sensed and mirrored to the readout current Ireplica, as relevant to cases 1-4 (i.e. schematics 800, 810, 900, 910 of Figures 8A, 8B, 9A and 9B). Conversely, activating the NMOS set of current mirrors 726 reads out the current drawn by one of the two pull-up transistors (PU), as shown in relation to cases 5-6 illustrated in schematics 1000, 1010 of Figures 10A and 10B.

[0107] In relation to the schematics 800, 810 of Figures 8A and 8B (i.e. cases 1 and 2), for PD readout, the effect of the PD transistor is isolated by over-boosting the wordline (WL) of the bitcell. This makes the “resistance” of PD transistors dominant over PG transistors and hence makes the mismatch of the PG transistors irrelevant. Conversely, in relation to the schematics 900, 910 of Figures 9A and 9B, for PG readout, the effect of the PG transistor is isolated by under-boosting the wordline (WL) of the bitcell. This makes the “resistance” of PG transistors dominant over PD transistors and hence makes the mismatch of the PD transistors irrelevant. Wordline over- and under-boosting are available in conventional SRAMs as basic assist techniques for restoring write and read margins. This isolation mechanism of the present disclosure can therefore be readily applied to conventionally available SRAMs. The ability to isolate entropy extraction from different transistors was confirmed by Monte Carlo simulations where the standard deviation of dominant PD transistors is responsible for 83% of the total standard deviation from variations in all transistors, and the standard deviation of dominant PG transistors is responsible for 94% of the total standard deviation from variations in all transistors.

[0108] The third mismatch isolation mechanism is the bitcell state or the value Q stored in the bitcell. Particularly, when Q=0, the PD and PG currents on the left bitcell side (i.e. PDleftand PGleft) are read out (e.g. as shown in relation to the schematics 800 and 900), otherwise the PD and PG currents on the right side (i.e. PDrightand PGright) are read out (e.g. as shown in relation to the schematics 810 and 910). Given the complementary nature of the pull-up (PU) transistors, when Q=1, the PU current on the left (i.e. PUleftis read out (as shown in relation to the schematic 1000), otherwise the PU current on the right (i.e. PUright) is read out (as shown in relation to the schematic 1010). The bitcell currents from the left and right sides are summed into a single current output Ireplica, which is essentially equal to the ON current on the selected side where the other contribution is minuscule, being leakage current.

[0109] In the present embodiment, the three binary mechanisms described above (i.e., PMOS current mirrors versus NMOS current mirrors, over / under-boosting WL voltages, and the bitcell data (0 / 1)) are digitally defined by three of the incoming challenge bits. In this case, the PUF challenge input comprises challenge bits related to PMOS / NMOS current and over-driving or under-driving WL voltages for defining the bitcell current type (i.e. to isolate the PD, PG or PU currents) and challenge bits related to the bitcell data (0 / 1) to isolate the left or the right-side read-out of the bit cell. The PUF challenge input may further comprise challenge bits to define the SRAM bank and the row / column being read out for generating a PUF bit.

[0110] Six PUF-bit / bitcell generation

[0111] Readout strategy for 6 PUF bit / bitcell is discussed in relation to Figures 11 to 12B. Figure 11 shows a schematic 1100 to illustrate digitization of the replicate currents Ireplicafrom a bitcell (i.e. a first bitcell) and its neighbouring bitcell (i.e. a second bitcell) (same row but neighbouring column) and comparing the digitized replicate currents to obtain one PUF bit in accordance with an embodiment. Using the methods / mechanisms as described in relation to Figures 7 to 10B above, in the present embodiment, two current mirror output currents Ireplicafrom a pair of bitcells in the same row and neighboring columns of the 6T SRAM array are read out and digitized. The resulting output PUF bit is generated through a two-step comparison, as illustrated in relation to Figure 11. The two currents of the same type (e.g., PD, PG, or PU) are individually digitized, and then digitally compared to produce the output PUF bit. The reuse of the same digitization periphery (i.e. the current-to-digital converter 728) for the two columns inherently suppresses any mismatch-induced offset and halves its area. The differential nature of the above two-step readout from bitcells to digitization makes the PUF bit generated robust against correlated process, voltage, and temperature variations. For example, if a digitized current readout of the first step becomes higher due to an elevated supply voltage, the other digitized current in the second step will undergo the same effects (i.e., Nleftin step 1 1102 and Nrightin step 2 1104 would both increase).

[0112] Figures 12A and 12B are diagrams 1200, 1210 to illustrate possible combinations for generating PUF bits using two bitcells in accordance with an embodiment.

[0113] Figure 12A is a diagram 1200 to illustrate combinations in relation to a bitcell current type and bitcell states, and Figure 12B is a diagram 1210 to illustrate the 12 combinations achievable for the two bitcells. Regarding the number of possible current comparisons between two neighboring bitcells, three types of currents (i.e. PD, PG, and PU currents) 1202, 1212 can be combined with four possible bitcell states (i.e. “0” or “1” values) 1204, 1214 stored in the two bitcells as shown in relation to Figure 11. This results in twelve possible combinations for the two bitcells, and hence enables the generation of 6 bits of static entropy per bitcell (i.e. 12 / 2 = 6 bit / bitcell).

[0114] Current Details on Bitcell Current Digitization

[0115] Details of the PUF periphery circuitry for bitcell current digitization are discussed in relation to Figures 13 to 23.

[0116] Figure 13 is a schematic to illustrate a current-starved ring-oscillator (CSRO) based current-to-digital converter 1300 in accordance with an embodiment. In the present embodiment, the digitization of the current Ireplicaobtained using the PMOS set of current mirrors or the NMOS set of current mirrors for each of the two bitcells is carried out through the current-starved ring oscillator-based (CSRO) current-to-digital converter 1300. The current read out Ireplicafirst undergoes current-to-time conversion 1302, then an output pulse width adjustment 1304, followed by time-to-digital conversion 1306.

[0117] The current-to-time conversion 1302 is based on current-starved ring-oscillators (CSRO) 1308 whose timing is determined by the bitcell current readout. In the current-to-time conversion stage 1302, the frequency of the CSRO 1308 is directly determined by the current Ireplica, which sets the current available to each delay stage and hence the delay itself.

[0118] In the subsequent output pulse width adjustment stage 1304, a self-limiting frequency divider 1310 is used. Figure 14 is a schematic to illustrate the self-limiting frequency divider 1310 used in the CSRO-based current-to-digital converter of Figure 13 in accordance with an embodiment. The self-limiting frequency divider 1310 is configured to divide the CSRO frequency by an adjustable factor from 21to 24, and delivers a first output transition after a number of CSRO transitions equal to the adjusted frequency ratio. After this first transition, the feedback path 1402 as shown in relation to Figure 14 inhibits further counts, generating a pulse whose width is proportional to the adjustable frequency ratio. Higher ratio leads to a higher number of CSRO transitions within the pulse width, which allows for distinguishing finer changes. This makes the adjustable frequency ratio an effective knob to manage the energy-stability tradeoff, as a higher value allows finer differentiation of slightly different currents and better stability, but at higher energy due to the higher number of CSRO transitions and counts. A level shifter 1312 as shown in Figure 13 was placed between the current-to-time conversion stage 1302 and the output pulse width adjustment stage 1304 to eliminate any switching failures of the latter due to infrequent incomplete-swing output of the former across skewed process corners.

[0119] The final time-to-digital conversion 1306 of the adjusted pulse is carried out by counters 1314. Up / down counting control 1316 of the counter 1314 allows difference of the two readouts to be evaluated without an adder. In the present embodiment, an up count for the first digitized current and a down count for the second digitized current therefore allows evaluation of the difference between the two readouts within the same counter 1314, without requiring any additional arithmetic circuitry. The output most significant bit (MSB) of the counter 1314 after the second digitization step (i.e. step 2 1104) represents the sign of the current difference, and hence the PUF output bit 1318. This is illustrated in relation to Figure 15 where generation of a PUF bit (PUFX) can be obtained by comparing the digitized replicate currents N and NRobtained from two bitcells. In the present embodiment as shown in relation to Figure 15, the PUFXis 0 if NL< NRand is 1 if NLs NR. In the present embodiment, the CSRO based current-to-digital converter 1300 is reused twice for each of the two bitcell currents Ireplicabeing compared, thereby eliminating any inherent offsets.

[0120] Within the CSRO 1308, one-time self-calibration of the effective current mirror ratio effectively compensates for the effect of periphery mismatch between the left-side (i.e. the BL side) and the right-side (i.e. the BLB side) of the PMOS current mirrors or the NMOS current mirrors as shown in relation to Figure 7. This compensates for the skew in the 0 / 1 output bit bias induced by these current mirrors across the columns sharing the same current-to-time converter 728 of Figure 7. The present self-calibration pursues unbiased 0 / 1 distribution without any need for a reference. Self-calibration of the PMOS and NMOS sets of current mirrors are necessary as either the PMOS or the NMOS sets of current mirrors are used at any one time across different columns of the SRAM and any mismatch within these sets of current mirrors is undesirable. The digitization circuit as shown in relation to Figure 13, on the other hand, is common for generation of all PUF bit types. This one-time self-calibration is performed using the current mirror fingers comprised in the CSRO based current-to-digital converter 1300 as shown in relation to Figure 16.

[0121] Figure 16 is a schematic diagram 1600 to illustrate use of the current mirror fingers to calibrate a strength of a replicate current in accordance with an embodiment.

[0122] To minimise residual process corner-induced offsets, current mirror self-calibration is carried out via digital transistor finger enablement as shown in relation to Figure 16. Figure 16 shows two sets of current mirror ratio-tunable fingers 1602, 1604 which are adapted to connect to PMOS sets of current mirrors and NMOS sets of current mirrors respectively. As shown in Figure 16, the first set of current mirror ratio-tunable fingers 1602 is adapted to receive a bias voltage Vb,Pfrom PMOS sets of current mirrors at one terminal and digital enablement bits for calibrating the first set of current mirror ratio-tunable fingers 1602 at another terminal 1606, and the second set of current mirror ratio-tunable fingers 1604 is adapted to receive a bias voltage Vb,nfrom NMOS sets of current mirrors at one terminal and digital enablement bits for calibrating the second set of current mirror ratio-tunable fingers 1604 at another terminal 1608. In the present embodiment, the current received from the PMOS set of current mirrors and the current received from the NMOS set of current mirrors are therefore further mirrored using the first set of current mirror ratio-tunable fingers 1602 and the second set of current mirror ratio-tunable fingers 1604 respectively. The first set of current mirror ratio-tunable fingers 1602 and the second set of current mirror ratio-tunable fingers 1604 are calibrated by adjusting their corresponding number of current mirror fingers (or the mirroring ratio) so that the resultant PUF output is unbiased (i.e. has an approximately equal number of 0s and 1s when evaluated several times, e.g. over several rows of each column of the SRAM, and / or over multiple columns of the SRAM). In the present embodiment, the CSRO comprises a first set of digital switches connected to the first set of current mirror ratio-tunable fingers 1602 for receiving the digital enablement bits to calibrate the first set of current mirror ratio-tunable fingers 1602 and a second set of digital switches connected to the second set of current mirror ratio-tunable fingers 1602 for receiving the digital enablement bits to calibrate the second set of current mirror ratio-tunable fingers 1602. Each of the first set of current mirror ratio-tunable fingers 1602 is connected to a digital switch of the first set of digital switches in series and each of the second set of current mirror ratio-tunable fingers 1604 is connected to a digital switch of the second set of digital switches in series to facilitate switching on or off (or enabling or disabling) a corresponding current mirror ratio-tunable finger.

[0123] The self-calibration is performed without requiring a precise reference by using the 0 / 1 PUF output statistics as a proxy for periphery mismatch, across the columns sharing the same PMOS sets of current mirrors and the same NMOS sets of current mirrors as shown in relation to Figure 7. In detail, self-calibration progressively adjusts the effective size (i.e. a number of the current mirror fingers used) of the current mirror ratio-tunable fingers 1602, 1604 via binary search, which converges given the inherently monotonic 0 / 1 count versus the current mirror finger strength. The sets of current mirror ratio-tunable fingers 1602, 1604 above are digitally configurable and are sized to cover ±6o transistor-mismatch induced variations derived from Monte Carlo simulations. In the present embodiment, each elementary current mirror finger of the sets of current mirror ratio-tunable fingers 1602, 1604 affects 1% of the total current mirror ratio for each set 1602, 1604. In the present embodiment, calibration of the first set of current mirror ratio-tunable fingers 1602 and the second set of current mirror ratio-tunable fingers 1604 is done once for usage across all the columns of the SRAM. Resulting settings of the self-calibration can be stored on a chip (e.g., anti-fuse or NVM) and be recalled or selected based on the digital enablement bits received.

[0124] Figure 17 is a flowchart of a method 1700 for calibrating a strength of the replicate current using the current mirror fingers of Figure 16 in accordance with an embodiment. As shown in Figure 17, the RUF column bias x is first measured across multiple columns (or all columns) of the SRAM at a step 1702. In a step 1704, it is determined if x is outside of the target range. If it is determined that x falls outside of the target range in the step 1704, then in a step 1706, the first set of current mirror ratio-tunable fingers 1602 or the second set of current mirror ratio-tunable fingers 1604 (depending on whether the self-calibration is with respect to PMOS or NMOS sets of current mirrors) will be calibrated by enabling I adding or disabling / reducing the number of active current mirror fingers of the corresponding set of current mirror ratio-tunable fingers 1602 or the second set of current mirror ratio-tunable fingers 1604. In the present embodiment where the effective size (i.e. a number of the current mirror fingers used) of the current mirror ratio-tunable fingers 1602, 1604 are adjusted progressively, measurement of the PUF column bias x at the step 1702 will be performed again, and iteratively, until x falls within the target range. If it is determined that x falls within the target range in the step 1704, then the method 1700 will stops at the step 1708. This method 1700 therefore compensates for the skew in the 0 / 1 output of PUF bits (i.e., 0 / 1 bias) induced by current mirrors (i.e. the PMOS set of current mirrors and the NMOS set of current mirrors) across the columns sharing the same current-to-time conversion stage.

[0125] Figure 18 is a schematic diagram 1800 to illustrate a same circuitry relating to selfcalibration being re-used for different bitcell current types in accordance with an embodiment. The circuit diagram 1802 shows a first configuration (config. 1) of the circuitry for PD current or PG current conversion (i.e. using PMOS sets of current mirrors), while the circuit diagram 1804 shows a second configuration (config. 2) of the circuitry for PU current conversion (i.e. using NMOS sets of current mirrors). The calibration process is repeated for the PMOS and NMOS sets of current mirrors, reusing the same circuitry and selecting the correct configuration (i.e. config. 1 or config. 2) via digital bypass switches as in Figure 18.

[0126] Figures 19 to Figures 23 illustrate probability density graphs in relation to the selfcalibration process as described in relation to Figures 16 to 18 above.

[0127] Figure 19 is a graph 1900 of probability density versus time-to-digital converter (TDC) counts to illustrate effects of addition or subtraction of current mirror fingers in accordance with an embodiment. As shown in the graph 1900, the probability density with respect to the TDC counts can be shifted towards lower TDC counts 1902 (i.e. left side of the graph 1900) by reducing the number of active / effective current mirror fingers or can be shifted towards higher TDC counts 1904 (i.e. right side of the graph 1900) by increasing the number of active / effective current mirror fingers. The original curve 1906 is shown as reference.

[0128] Figure 20 is a graph 2000 of probability density versus bitcell column bias (A counts) to illustrate effects of addition or subtraction of current mirror fingers in accordance with an embodiment. Similar to the trends as shown in relation to Figure 19, the probability density with respect to the bitcell column bias is shifted towards lower column bias 2002 (i.e. left side of the graph 2000) by reducing the number of active / effective current mirror fingers or can be shifted towards higher column bias 2004 (i.e. right side of the graph 2000) by increasing the number of active / effective current mirror fingers. The target 2006 is to have a probability density centered at a column bias of 0.5 as shown in Figure 20 for achieving an unbiased 0 / 1 distribution across columns of the SRAM. Figure 21 is a graph 2100 of probability density versus column entropy to illustrate an unbiased 0 or 1 digitized output distribution after an one-time self-calibration using the current mirror fingers of Figure 16 in accordance with an embodiment. Similar to the graphs 1900, 2000, the probability distribution of the digitized output can be calibrated by reducing the number of effective current mirror fingers (c.f. 2102) or increasing the number of effective current mirror fingers (c.f. 2104) until the cumulative number of 0 and 1 outputs is balanced as shown exemplary at 2106. The ideal target (e.g. 0.9999) 2108 is also shown in the graph 2100.

[0129] Figures 22 and 23 show measured current-to-digital converter outputs and measured entropy in PUF columns, respectively, in relation to current mirror finger adjustments. The measurements were made with 0.65 V, 25 °C and ±50% current mirror finger enablement. Details of the measurement setup are discussed in relation to Figure 31 below.

[0130] Figure 22 is a graph 2200 of occurrences versus normalized measured current-to-digital converter output to illustrate effects of addition or subtraction of current mirror fingers in accordance with an embodiment. Similar to the trends shown with respect to the graphs 1900, 2000, the occurrence with respect to the normalized measured current-to-digital converter output can be shifted towards lower normalized measured current-to-digital converter output 2202 (i.e. left side of the graph 2200) by reducing the number of active / effective current mirror fingers or can be shifted towards higher normalized measured current-to-digital converter output 2204 (i.e. right side of the graph 2200) by increasing the number of active / effective current mirror fingers. The plot 2206 after self-calibration is also shown in Figure 2200.

[0131] Figure 23 is a graph 2300 of occurrences versus measured entropy for bitcell columns to illustrate an unbiased 0 or 1 (0 / 1) digitized output distribution after an one-time selfcalibration using the current mirror fingers of Figure 16 in accordance with an embodiment. As shown in the graph 2300, a pre-calibration plot 2302 is shown which has a 0 / 1 bias far from the ideal 0.5. After an one-time self-calibration process by enabling or disenabling current mirror fingers appropriately using the method 1700, the 0 / 1 bias can be adapted to be closed to 0.5 as shown in the dotted line 2304 being in a target range of e.g. > 0.9999. The ideal value 2306 of 1 is also shown in the graph 2300.

[0132] As illustrated in the measurements of Figures 22 and 23, this recenters the distribution of the digitized output until the cumulative number of 0 and 1 outputs is balanced within the entropy target as shown in relation to Figure 23. The calibration process is repeated for PMOS and NMOS current mirrors, reusing the same circuitry and selecting the correct configuration via digital bypass switches as shown in relation to Figure 18. Once the resulting PUF bitstream is de-biased, self-calibration is disabled throughout the chip lifespan, and the current mirror finger setting of the SRAM is permanently fixed without any run-time self-regulation.

[0133] Figure 24 is a schematic to illustrate no column-to-column correlation in PUF bits generated using the method 300 of Figure 3 in accordance with an embodiment. In an embodiment, pairs of bitcells for use in generating PUF bits can be grouped into nonoverlapping bitcell pairs across columns to suppress column-level or column-to-column correlation.

[0134] Re-addressing for residual correlation suppression and data fingerprinting

[0135] As shown in relation to Figure 24 above, in the present embodiment, the column pairs being compared in terms of current are strictly dis-overlapped to suppress correlation among PUF output bits from different columns. However, this does not remove the residual correlation among the six bits derived from the same bitcell pair under different challenges. To suppress such residual correlation, a single-cycle re-addressing (SCRA) technique is introduced, where post-masking readout defined by the challenge bits is reused as address offset to generate the final address for actual readout, effectively suppressing spatial correlation via an offset randomness.

[0136] The main thrust of SCRA is to remap output bits using an unpredictable but repeatable mapping within each bank of the SRAM through non-linear transformation (e.g. scrambling). Unlike conventional digital post processing techniques such as hashing or combination with pseudo-random sequences, SCRA used in the present disclosure is adapted to reutilize randomness coming from the very same bitcell bank to re-map the input challenge (or user challenge or challenge input) for suppressing residual correlation. In other words, not only is the final PUF response generated by using only bitcell transistors as randomness source, but also its mapping (using SCRA) is dictated by the entropy of bitcell transistors.

[0137] Figure 25 is a flowchart of a method 2500 for supressing bit-to-bit correlation using single-cycle re-addressing (SCRA) in accordance with an embodiment.

[0138] In a step 2502, a PUF challenge (user input) is received at the system. The PUF challenge comprises challenge bits for defining row address, bitcell current type and bitcell data stored in relation to the pair of bitcells.

[0139] In a step 2504, an internal post-masking (stable) response derived from PUF readout generated based on the PUF challenge is formed. In a step 2506, this internal post-masking response is used as a row address offset to internally generate a new PUF challenge within the same bank (random but repeatable mapping).

[0140] In a step 2508, a response to the new PUF challenge is generated based on the remapped address, and this response represents the actual output response of the PUF.

[0141] This approach enables reproducible remapping of PUF challenges by leveraging chipspecific randomness and suppressing any residual intra-cell correlation in view of the non-linear nature of the mapping function. In other words, two responses sharing the same bitcells with the same configuration are actually remapped to different rows and hence different bitcells altogether.

[0142] An example of SCRA is described in relation to Figures 26 to 28C. In this case, a worst correlation case is used for illustration where a same bitcell and a same current mirror type (say, NMOS) are activated across two PUF input challenges and then used for generating responses to these two PUF input challenges.

[0143] Figure 26 is a diagram 2600 of two PUF challenge inputs for one common bitcell and bitcell current type for illustrating effects of SCRA in accordance with an embodiment. As described in relation to the method 2500, at the step 2502, a first input challenge comprising challenge bits defining a corresponding subset of bitcells belonging to a given physical SRAM row of the considered bank is first received. For simplicity in the present example, only a first bit of the subset, which is addressed after conventional decoding, is of concern. As shown in the diagram 2600, in the present example, a first challenge 2602 includes challenge bits 2604 defining a pair of bitcells pre-loaded with bitcell state (i.e. stored data) 00, challenge bits 2606 relating to bitcell current type (in this case, defining isolating mismatch in the PUright transistors of the two neighboring bitcells (both in Case 6 of Figure 10B, and illustrated in relation to 2802 of Figure 28A and 2804 of Figure 28B), and challenge bits 2608 relating to a row number of the SRAM (i.e. row #43 in this case). Using the method 300 of Figure 3, replicate currents generated by the designated PUrighttransistors of the pair of bitcells are then digitized and compared to generate a corresponding response bit. Under the same assumptions, a second challenge 2610 includes challenge bits 2614 defining the same row (i.e. row #43 in the present example), challenge bits 2616 defining the two bitcells with 01 bitcell states and challenge bits 2618 defining a bitcell current type (in this case, Case 5 of Figure 10A for one bitcell and Case 6 of Figure 10B for the other, and illustrated in relation to 2802 of Figure 28A and 2806 of Figure 28C respectively). For the second challenge 2610, the comparison involves PUleftof one bitcell and PUrightof the other. Using the illustrated example, as shown in relation to Figure 27, the resulting response bits from the first and the second challenge are inevitably correlated, due to the reuse of the same bitcell in the same configuration across two challenges. The column 2702 provides illustration of this, prior to the use of the SCRA method. In an embodiment where steps 2504 and 2506 of the SCRA method 2500 are applied, this residual correlation is removed. This is shown in relation to the column 2704 where the two response bits that were originally sharing one bitcell configuration are now mapped to different and internally randomized physical addresses and configurations, due to the internally applied row address offset.

[0144] Therefore, as illustrated above, the present SCRA re-addressing method uses an available chip-specific randomness within the SRAM bank(s) to suppress spatial correlation among PUF bits sharing the same bitcells and even the same PUF column, irrespective of the current type used for comparison or the pre-loaded bitcell data configuration.

[0145] The SCRA method can be equivalently applied in a closed- and open-loop fashion. This is illustrated in relation to Figure 29. Figure 29 is a schematic diagram 2900 to illustrate a closed-loop implementation 2902 and an open-loop implementation 2904 of the SCRA method in accordance with embodiments.

[0146] As shown in Figure 29, for the closed-loop implementation 2902, the output bits of SRAM bank A set the address for the subsequent SRAM bank A which generates the PUF response (i.e. within the same bank), while for the opened-loop implementation 2904, the output bits of SRAM bank A set the address for the subsequent SRAM bank B which generates the PUF response. In both cases, no post-processing is introduced. A key difference between these two implementations is that the closed-loop readdressing implementation 2902 improves an area efficiency by 2x at the expense of 2x lower throughput, as compared to the open-loop re-addressing implementation 2904. In relation to the experimental results described in later Figures, most of the results focused on the closed-loop implementation 2902 in view of its area efficiency for low-cost targets.

[0147] Analysis of Bit correlation with and without re-addressing

[0148] In the following, mathematical analysis of residual correlation induced by PUF bitcell read current comparisons with common bitcell transistors (see e.g. Figure 12B), and its suppression in a statistically infrequent case via the re-addressing technique as introduced is discussed.

[0149] First, the correlation of a generic pair (X, Y) of PUF output bits belonging to a small pool of response pairs with a common bitcell transistor configuration (i.e., worst-case correlation), as evaluated before for re-addressing, is considered. The random variables X and Y are determined by the comparison of the bitcell read currents A and B of two different bitcells with a common read current C, where A, B and C are in turn random variables. Assuming A, B and C to have the same statistical distribution and being statistically independent as appropriate for mismatch, X and Y are given by:

[0150] X = I [ < C], Y = I [B < C], (2)

[0151] where I [•] is the truth operator, which evaluates to 0 if the condition under brackets holds, and 1 otherwise. Assuming identically distributed random variables, E[X] = E[Y] = 1 / 2 and E|AT| = 1 / 3, thus the resulting correlation between X and Y is:

[0152] E[XY] — E[X]E[Y]

[0153] Px. Y 0.333.

[0154]

[0155] y / var(X')var(Y') (3)

[0156] Considering that 3 out of 6 of the extracted PUF bits have the above residual correlation and the other three have no correlation, the overall average correlation among response bits with common bitcell is 0.167 before applying the re-addressing technique. Under the SCRA re-addressing method as described, the bitcells are remapped to completely different rows without sharing the common read current C, removing any residual correlation as E[XY] = E[X] = E [Y] = 1 / 2.

[0157] Beyond the above bit-level analysis, the probability of having two correlated responses due to at least one common bitcell is evaluated in the following through combinatorial analysis, assuming 16-bit responses as in the PUF testchip demonstration which will be discussed below. Fundamentally, there are three scenarios when two responses have no correlation: 1) the two responses are generated from two different SRAM addresses, 2) the two responses are generated from the same SRAM address with different PUF bit type (i.e., PD, PG, PU), and 3) the two responses are generated from the same SRAM address with the same type of PUF, while having complementary bitcell pair states (e.g., one response bit has 00 bitcell pair state, while the other has 11 bitcell pair state). For a SRAM PUF with NADDnumber of addresses, the probability that two responses belong to one of the above three scenarios is NADD-t) / NADD, 2 / 3NADD, and V\2NADD. Accordingly, the probability of having two response bits without any correlation is the sum of the above three probabilities: (4NADD-1) / 4NADD. Conversely, the probability of having two 16-bit PUF responses having at least one correlated bit is1-[(4W4DD-1) / 4WI4DD]15= 0.77% for a SRAM with NADD= 512 addresses. In practical multi-bank SRAM memories, such probability is even lower and <0.1% for capacities of 32 kB or higher. This analysis clearly shows that correlated responses due to common bits are statistically infrequent.

[0158] Data Fingerprinting Capability and Other Key Advances

[0159] The intrinsic data dependence of the response from left / right readout across cases 1 -6 as shown in relation to Figures 8A to 10B earlier can be utilized to enable data fingerprinting for data provenance assurance. This is achieved by reading out the PUF bits associated with a given bank state (e.g., video frame of interest) and using them as a digest of the data stored (or appended to the data stored) as evidence that the data is / was physically residing in the SRAM memory of interest. This can be done on-demand (e.g., for occasional events of interest) or on a continuous basis. The data-dependent PUF output bits are appended to the conventionally stored data within the same SRAM bank, and then conventionally encrypted before being sent to the cloud. Figure 30 is a work flow 3000 for illustrating data fingerprinting in accordance with an embodiment. The edge device provides a data fingerprint of the data transiting on the SRAM memory (e.g. by the steps 3002 and 3004), which is then compared with the fingerprint reconstructed by the cloud (see e.g. the step 3006) from the PUF model originally acquired at enrolment time (see e.g. the step 3008). Matching of reconstructed and received fingerprint indicates correct provenance, while mismatching of reconstructed and received fingerprint indicates incorrect provenance. The PUF data dependence for provenance assurance is straightforwardly modeled before encryption at the enrollment phase in a commonly available secure testing environment. The server receiving data from the considered chip can immediately or subsequently perform physically-grounded (i.e., chip-specific) data integrity and provenance verification. As routinely done with any weak PUF, the PUF data is not exposed directly across the successive phases of the device lifespan, but it is instead exported in an encrypted form.

[0160] During in-field operation, the edge device transfers the data stored in the SRAM (e.g., video frame) and the resulting (encrypted) data-dependent PUF readout (or a digest) to the cloud (see the steps 3002 and 3004), which represents the fingerprint of the data being transmitted. Meanwhile, the cloud reconstructs the expected fingerprint from the incoming data based on previously acquired PUF bits map (shared secret), and compares it with the received PUF readout to assess consistency (see e.g. the steps 3006 and 3008). If they match (differ), correct (incorrect) data provenance is assessed. Therefore, based on the PUF bit map securely stored at enrolment time, the receiving server can readily verify whether the data received (e.g., video from camera) comes from the intended device and its integrity even at a later time. Data fingerprinting ultimately certifies the physical origin of data, and the specific user (e.g., by storing the user credentials into the SRAM array and using the same fingerprinting mechanism). Given the ample discrimination margin available e.g. as shown in relation to experimental results obtained in Figures 31 to 51, data provenance assessment is inherently very robust against occasional faults or PUF bit instability.

[0161] Ultimately, data fingerprinting certifies the physical origin of the data. Furthermore, in multi-user devices the same fingerprinting mechanism can be extended to authenticate specific users by storing user credentials within the same SRAM array. Various arrangements of data fingerprinting can be straightforwardly derived by folding the data-dependent PUF output onto a shorter digest, achieving different levels of fingerprinting data granularity and digest length.

[0162] From an applicability standpoint, the multi-bit static entropy extraction of the present disclosure is independent of the specific bitcell design, allowing full compatibility with existing and foundry-qualified bitcells, and memory-compiler SRAM generation. PUF bits can be selectively read out from specific SRAM rows in a single cycle, avoiding the need for conventional SRAM PUF full bank flushing. Accordingly, this allows the coexistence of SRAM bitcells and PUF bitcells in the same bank for flexible usage of the available array, unlike conventional power-up methods that typically erase existing bank data.

[0163] Further, methods and systems of the present disclosure are highly scalable across SRAM sizes, as PUF bit generation is performed within a bank and is hence independent of the array size. Also, all local and intra-bank correlation mechanisms were addressed above, and correlation would certainly not increase in more distant portions of the design. From an interference perspective, larger arrays are no different from individual banks considering that PUF readouts are performed once at a time with no change in row-level activity (i.e., a single bank and single row at a time, as validated in the next sections).

[0164] Measurements

[0165] A 28-nm testchip implementing the proposed SRAM PUF architecture was fabricated and tested, as illustrated in Figure 31. Figure 31 shows a series of photographs of a 28-nm SRAM PUF testchip and testing setup in accordance with an embodiment. In relation to the testing setup, a temperature chamber 3102 is shown in which a testing printed circuit board (PCB) 3104 will be placed. The temperature chamber 3102 provides temperature control during experimentation. Power supplies 3106 and a National Instruments (Nl) test station 3108 are connected to the PCB 3104 for performing the experiments. The test PCB 3104 is connected to analog voltages 3110 and for which a test chip (COB) 3112 is plugged in. A photograph of the 28-nm test chip is also shown as 3114 in Figure 31. Overall, 12 banks were fully characterized across 6 silicon dice, voltages, and temperatures.

[0166] Bitstream Quality Evaluation

[0167] Figure 32 is a graph of 0 / 1 bias measurements to illustrate the effects of pre- and postself-calibration in accordance with embodiments. The 0 / 1 bias of the PUF output bitstreams before and after self-calibration across different columns are shown in relation to a plot 3202, and the 0 / 1 bias of the PUF output bitstreams before and after self-calibration for the same bit position and bitcell configuration across SRAM column(s) (c.f. the 12 comparison cases in relation to Figure 12B) are shown in relation to a plot 3204. The data bar 3206 for pre-calibration is shown on a left-side and the data bar 3208 for post-calibration is shown on a right-side for each data bar pairs. Referring to the plots 3202, 3204, deviation from the ideal value (or the expected convergence (central limit theorem) value of the 0 / 1 bias) of 0.5 after self-calibration is within ±0.01, which represents a more than 20 times (> 20X) improvement over the case without calibration (which is within ±0.2). This shows an effectiveness of the onetime current mirror self-calibration method as described above.

[0168] This can be appreciated visually from the speckle diagrams in Figures 33A and 33B with PUF bits coming from all banks and dice of the SRAM PUF testchip. Figures 33A and 33B are diagrams showing measured speckle patterns from SRAM banks and dice of the 28-nm SRAM PUF testchip of Figure 31 before and after self-calibration in accordance with an embodiment. Figure 33A is a diagram of measured speckle pattern 3300 before self-calibration and Figure 33B is a diagram of measured speckle pattern 3310 after self-calibration. As shown in relation the measured speckle patterns 3300, 3310, this translates into a Shannon entropy better than 0.9999 (with a minimum entropy of 0.9939) after one-time self-calibration as compared to a Shannon entropy of 0.9866 (with a minimum entropy of 0.8165). This confirms cryptographic-grade quality of the present PUF generation methods and the effectiveness of these methods and systems in rejecting an effect of mismatch.

[0169] Figures 34A and 34B are diagrams showing measured speckle patterns of PUF bitstreams from the 28-nm SRAM PUF testchip of Figure 31 before and after selfcalibration in accordance with an embodiment. Figure 34A is a diagram of measured speckle pattern 3400 before self-calibration across PUF of different bitcell current type and Figure 34B is a diagram of measured speckle pattern 3410 after self-calibration across PUF of different bicell current type. Based on the measured speckle patterns 3400, 3410, a mean bias of 0.5678 with a Shannon entropy of 0.9866 before selfcalibration (c.f. measured speckle pattern 3400) were improved to a mean bias of 0.5021 with a Shannon entropy of 0.9999 after self-calibration (c.f. measured speckle pattern 3410).

[0170] Figures 35A, 35B and 35C are diagrams to demonstrate data fingerprints extraction from a stored video frame in accordance with an embodiment. Figure 35A is a picture of the stored video frame 3500. Data fingerprinting from the stored video frame 3500 can be obtained using the work flow 3000 as described in relation to Figure 30.

[0171] Figure 35B is a diagram 3510 illustrating the data fingerprint on chip 1 extracted from the stored video frame and Figure 35C is a diagram 3520 illustrating the data fingerprint on chip 2 extracted from the stored video frame. Based on the measured speckle pattern 3510 of Figure 35B and the measured speckle pattern 3520 of Figure 35C, a bias of 0.5146 with a Shannon entropy of 0.9994 can be obtained in relation to the data fingerprint on chip 1 of Figure 35B and a bias of 0.5066 with a Shannon entropy of > 0.9999 can be obtained in relation to the data fingerprint on chip 2 of Figure 35C.

[0172] Figure 36 shows graphs 3610, 3620 of measured correlation coefficient to illustrate (a) inter-column correlation for transistors having a same row number, a same bitcell current type and a same bitcell state across different columns and (b) intra-cell correlation at the same row number and same column across different bitcell configurations with- and without SCRA under closed-loop re-addressing in accordance with an embodiment. The graph 3610 shows measured correlation coefficient with PUF column pairs being compared while the graph 3620 shows measured correlation coefficient with PUF bit pairs being compared.

[0173] As shown in relation to the graph 3610, inter-column correlation is shown to be negligible as expected from the bitcell being not overlapping the pairs used for PUF response bits (i.e. non-overlapped comparison 3612), as evidenced by the correlation coefficient of +0.024 obtained among PUF bitstreams composed of all the bit types collected from different PUF columns. Overlapped pairs as shown in relation to the overlapped comparison 3614 led to an unacceptably high correlation coefficient in the order of 0.3.

[0174] Given the multi-bit nature of the proposed PUF, the intra-cell correlation was also evaluated by reading out pairs of bitcells where the very same configuration (i.e., PMOS / NMOS current mirror, data stored) is used in one of the two bitcells. This is shown in relation to the graph 3620. The correlation before SCRA is 0.133 (c.f. plot 3622), which is close to the theoretical value of 0.167 as discussed above. The correlation among PUF bits using the same bitcell with different under / over-boosting configuration (i.e., cases 1-2 and 3-4 as shown in relation to Figures 8A to 9B) is respectively 0.13, 0.12, 0.10, 0.11 before SCRA re-addressing. The measured worstcase intra-cell correlation without SCRA re-addressing is expectedly very high at ±0.512 (see reference numeral 3624).

[0175] The above occasional worst-case correlation is suppressed by the adopted SCRA readdressing, as discussed in Figures 25 to 29. Under the adopted closed-loop readdressing 2902 as shown in relation to Figure 29, the proposed single-cycle closed-loop re-addressing brings correlation back to near-zero (±0.038) as evidenced by the plot 3626. This confirms the effectiveness of the spatial randomization enabled by readdressing, while not introducing any intermediate form of post-processing.

[0176] Figure 37 shows a graph 3700 of measured correlation coefficient to illustrate intra-cell correlation at the same row number and same column across different bitcell configurations with- and without SCRA under open-loop re-addressing in accordance with an embodiment.

[0177] As shown in the graph 3700, the worst-case correlation under open-loop re-addressing is ±0.035, which is expectedly in good agreement with the ±0.038 correlation of the closed-loop one as shown in the graph 3620. Even focusing on the correlation between bits coming from the very same bitcell at different under / over-boosting configuration, the worst-case correlation is only 0.015.

[0178] As expected, the entropy before and after re-addressing is the same (>0.9999), considering that bitcells are just reused as shared physical source of entropy for both readout and re-addressing.

[0179] Figures 38A, 38B, 38C show plots of measured autocorrelation function across 8000 bits of PU, PD and PG type of PUF bits in accordance with an embodiment. Figure 38A shows a plot 3800 of measured autocorrelation function prior to SCRA, Figure 38B shows a plot 3810 of measured autocorrelation function after SCRA closed-loop readdressing, and Figure 38C shows a plot 3820 of measured autocorrelation function after SCRA open-loop re-addressing. For the plot 3800, peaks 3802 in the autocorrelation function can be observed for responses with common bitcell(s). Such peaks are not observed or removed after SCRA, as shown in the plots 3810, 3820. From the plots 3800, 3810, 3820, the autocorrelation function from 8,000-bit PUF streams confirms statistically insignificant spatial correlation with a 95% confidence bound of ±0.022 (neglecting the peaks 3802 due to responses with common bitcell(s)). For fair assessment of the proposed multi-bit PUF, the bitstreams were generated by current comparisons determined by distinct bitcell configurations covering all cases 1 -6 in relation to Figures 8A to 10B, and such results are reported individually for the outputs from each transistor type (PD, PG, and PU). From the plots 3800, 3810, 3820, it is shown that all types of transistors have no or negligible spatial correlation under SCRA re-addressing.

[0180] # test param.

[0181] name # test name param.

[0182] frequency - cumulative - 1 6 sums

[0183] block M=128 FFT - 2 frequency 7

[0184] runs - nonm=9

[0185] overlapping

[0186] 3 8 (...)

[0187] longest - serial m=9 4 runs 9

[0188] rank - approximate m=6

[0189]

[0190] 5 10 entropy

[0191] Table 1: NIST SP 800-22 Test Parameters

[0192] Table 1 provides a summary of the test parameters used in the NIST SP 800-22 statistical tests in the present embodiment. The NIST SP 800-22 tests were applied directly on the raw PUF output before any post-processing technique, as necessary to rigorously assess the native randomness, and before the re-addressing as discussed previously in relation to Figures 25 to 29. It is noted that overlapping template matching, universal, random excursions (variant), and linear complexity tests are not applicable given the available sample size in the present NIST SP 800-22 tests.

[0193] Figures 39A and 39B show graphs of measured probability values (p-values) of randomness tests (i.e. NIST SP 800-22 tests) prior to self-calibration of the 28-nm SRAM PUF testchip of Figure 31 in accordance with an embodiment, where Figure 39A shows a graph 3900 of measured average p-values and Figure 39B shows a graph 3920 of measured minimum p-values. The graph 3900 shows the average p-values obtained across ten tests, where an average p-value is obtained across several p-values for each test. The graph 3920 shows the minimum p-value obtained across the ten tests. Referring to the graph 3900, average p-values (in this case, these relate to an average of the average p-values) in relation to PU-PUF 3902, PD-PUF 3904 and PG-PUF 3906 are 0.109, 0.102 and 0.113, respectively. Referring to the graph 3920, all of the precalibration results reported individually for PU-PUF, PD-PUF and PG-PUF do not meet satisfy the p-value of 0.01 (99% confidence) and therefore have failed the randomness tests. Also shown in Figure 39A is that the data bar 3910 (top) is related to PG-PUF, the data bar 3912 (middle) is related to PD-PUF and the data bar 3914 (bottom) is related to PU-PUF of the data bar triplet. This convention, i.e. top (PG-PUF), middle (PD-PUF) and bottom (PU-PUF), relating to data bar triplets is applicable to Figures 39A, 39B, 40A and 40B.

[0194] Figures 40A and 40B show graphs of measured probability values (p-values) of randomness tests post self-calibration of the 28-nm SRAM PUF testchip of Figure 31 in accordance with an embodiment. Figure 40A shows a graph 4000 of measured average p-values and Figure 40B shows a graph 4010 of measured minimum p-values for the NIST SP 800-22 randomness tests performed post self-calibration of the PUF periphery 704.

[0195] PUF Type PU-PUF PD-PUF PG-PUF Avg. p-value (across ten 0.540 0.519 0.484 tests)

[0196] Min. p-value 0.013 0.021 0.019 Pass rate 20 / 20 20 / 20 20 / 20 Pass? Yes Yes Yes

[0197]

[0198] Table 2: NIST SP 800-22 Testing Results

[0199] Table 2 summarizes the outcome of the NIST SP 800-22 tests based on post-self-calibration measurements. Post-self-calibration measurements show that all applicable tests were successfully passed with adequately large average and minimum p-values, as shown in relation to Figures 40A and 40B. This confirms cryptographic-grade quality of the PUF outputs. Figure 41 shows a graph 4100 of inter- and intra-PUF Hamming distance among all PUF bits generated using the 28-nm SRAM PUF testchip of Figure 31 in accordance with an embodiment. As shown in Figure 41, the inter-PUF Hamming distance relating to the plot 4102 among all the PUF bits is 0.4941 and the intra-PUF Hamming distance relating to the plot 4104 among all the PUF bits is 0.0091. This leads to a PUF identifiability of 72× as shown in relation to Figure 41.

[0200] Stability Evaluation

[0201] The PUF energy-stability tradeoff discussed in relation to Figures 13 to 23 above was explored by adjusting the frequency ratio of the self-limiting frequency divider 1310 in the current-to-digital converter 1300. As discussed earlier, adjusting the frequency ratio of the self-limiting frequency divider 1310 effectively adjust a pulse width as the pulse width is proportional to the adjustable frequency ratio.

[0202] Figure 42 shows a plot 4200 of measured time-to-digital converter counts against pulse width setting in accordance with an embodiment. This illustrates that measured TDC counts increases with an increase in the pulse width (or increase in a frequency ratio). Figure 43 shows a plot 4300 of PUF bit instability (%) versus pulse width setting in accordance with an embodiment. The data point plot 4302 relates to unstable bits measured using native evaluations while the data point plot 4304 relates to average bit error rate (BER) measured using native evaluations. As shown in the plot 4300, both the unstable bits and the BER trends to a lower PUF bit instability with increasing pulse width.

[0203] Figure 44 shows a graph 4400 of measured bit error rate (BER) and unstable bits versus frequency ratio of a self-limiting frequency divider in accordance with an embodiment. The measurements were taken at nominal conditions at 0.65 V and 25 °C, with 50 evaluations. The plot 4402 relates to the measured BER and the plot 4404 relates to the measured unstable bits. Referring to the graph 4400, it is shown that a 1.7X improvement (with a frequency ratio from 2 to 22) to a 3.1 X improvement (with a frequency ratio from 2 to 24) in bit error rate and a 1.6X improvement (with a frequency ratio from 2 to 22) to a 2.8X improvement (with a frequency ratio from 2 to 24) in total unstable bits were achieved when the frequency ratio was increased from 2 to 24. Such stability improvements at higher frequency ratios is explained by the proportional increase in the counted CSRO transitions, which allows to distinguish finer current changes. This is also confirmed by measurements, which show that the standard deviation of the count distribution across bitcells increases nearly proportionally to the frequency ratio (e.g., 8.2X when increasing the frequency ratio from 2 to 24, which agrees well with the theoretical 8X increase). As discussed in relation to Figure 14, this stability improvement at higher frequency division ratios comes at the cost of higher energy.

[0204] Figure 45 shows a graph 4500 of normalized energy / bit in current-to-digital converter versus frequency ratio in self-limiting frequency divider in accordance with an embodiment. The graph 4500 shows that energy / bit linearly increases at higher frequency ratios, as the number of CSRO transitions per digitization and count increase accordingly. As shown in the graph 4500, the energy / bit increases from 446 fJ / bit to 3713 fJ / bit when the frequency ratio increases from 2 to 24. The energy / bit has therefore increased by 8x under 8x increase in frequency ratio.

[0205] In addition to the above PUF stabilization knob, the commonly adopted temporal majority voting with three PUF evaluations (TMV-3) was used.

[0206] Figure 46 shows a graph 4600 of measured bit error rate and unstable bits for different PUF bit types PD, PG, and PU based on native evaluations or with temporal majority voting with three PUF (TMV-3) evaluations in accordance with embodiments. The bar charts 4602 and 4604 relate to the unstable bits in percentages for native evaluations and TMV-3 evaluations, respectively. The data point plots 4606 and 4608 relate to the bit error rate in percentages for native evaluations and TMV-3 evaluations, respectively. As shown in the graph 4600, an extra 1.3X to 1,5X improvement in the bit error rate, and an extra 2.5X to 4.5X in unstable bits can be achieved among all the PUF bits when the TMV-3 evaluations were used as compared to the native evaluations.

[0207] Figure 47 shows a graph 4700 of measured average bit error rate and unstable bits across six PUF bits per bit cell against a number of PUF evaluations based on native evaluations or with temporal majority voting with three PUF evaluations (TMV-3) (i.e. the PUF bit was evaluated thrice and the majority of the three outputs was taken as the final output value) in accordance with embodiments. The plots 4702 and 4704 relate to instability in percentages for the unstable bits for native evaluations and TMV-3 evaluations, respectively. The plots 4706 and 4708 relate to instability in percentages for bit error rate (BER) for native evaluations and TMV-3 evaluations, respectively. The results were obtained using a nominal condition at 0.65 V and 25 °C

[0208] Impact of Variations and Data Fingerprinting

[0209] The impact of supply voltage and temperature variations on stability was assessed using the golden bits generated under nominal conditions (0.65 V, 25 °C) across 1,500 PUF evaluations.

[0210] Figure 48 shows a graph 4800 of measured unstable bits for different PUF bit types PD, PG, and PU and different testing conditions based on 1500 evaluations (with TMV-3) in accordance with an embodiment. The bar plot 4802 on a left side of a triplet bar plots for each testing conditions relate to a PD-PUF bit type, the bar plot 4804 in a middle of a triplet bar plots for each testing conditions relate to a PG-PUF bit type and the bar plot 4806 on a right side of a triplet bar plots for each testing conditions relate to a PU-PUF bit type. The measured unstable bits under worst-case voltage variations (±0.1 V, corresponding to a large 15%) and temperature variations (0-70 °C) are shown in the graph 4800 with TMV-3 enabled evaluations.

[0211] Also shown in relation to Figure 48 is a summary 4808 of the results of the unstable bits being assessed for each type of bitcell current PD, PG, PU, which are measured to be 63.27%, 28.60%, and 60.38%, respectively. The significantly more pronounced instability associated with the PD and PU transistors can be explained by considering that these bitcell transistors are routinely designed to have a lower threshold voltage than PG, as required to preserve the read margin (i.e., to hold a “stronger” bit within the cross-coupled inverter gates). The lower threshold voltage of PD and PU is achieved via lower threshold voltage (VTH) implant of dopants, which in turn leads to a lower threshold voltage standard deviation, due to the less pronounced random dopant fluctuation (RDF) effect. The resulting mismatch of PD and PU is less pronounced than PG, making the associated PUF bits more sensitive to noise and voltage / temperature fluctuations, and hence less stable as shown in relation to Figure 48.

[0212] After masking unstable bits across voltage and temperature variations, the resulting bit error rate is less than 2.22×10-7, confirming ECC-less operation. As shown in relation to Figures 1 A and 12B, each bitcell contributes two PUF bits per type, and this results in a 300% ideal increase in PUF capacity over SRAM for the three PUF bit current types. Accordingly, the overall PUF-to-SRAM capacity ratio (using overall stable bits) in this case is 2x(300%-63.27%-60.38%-28.60%), resulting in an unprecedented 296% capacity ratio. In other words, multi-bit SRAM PUF operation improves capacity well beyond the ideal 100% limit of conventional single-bit PUFs, even if the stability of each bit type is not close to 100% (i.e., no aggressive post-processing technique needs to be employed to push each type close to 100%).

[0213] Figure 49 shows a graph 4900 of measured energy / bit for different PUF bit current types PD, PG, and PU and different testing conditions with TMV-3 enabled evaluations in accordance with an embodiment. The data plot 4902 relates to measured energy / bit for the PD-PUF type, the data plot 4904 relates to measured energy / bit for the PG-PUF type and the data plot 4906 relates to measured energy / bit for the PU-PUF type.

[0214] As shown in the graph 4900, the measured minimum energy / bit at the minimum SRAM voltage of 0.55 V and 25 °C is 226 fJ. From simulations, the energy is broken down into SRAM and periphery contribution (42%), current-to-time conversion (35%), time-to-digital conversion (12%), and clocking (11%).

[0215] Further, PUF performance under accelerated aging was evaluated to quantify the effect of the resulting transistor threshold voltage variations due to hot carrier injection and bias temperature instability. The adopted environmental conditions for accelerated aging used a 1.21 V supply voltage, that is 10% above the maximum core voltage in the adopted 28-nm technology, and a temperature of 125 °C. The measurements were conducted under static stress conditions (i.e., without clock toggling) for 10 hours, which are sufficient to induce approximately five years of aging. As common practice, bit instability was evaluated in the form of both BER and unstable bits over the aging process across 300 evaluations and TMV-3 at 0.65 V and temperature within the above range.

[0216] Figure 50 shows a graph 5000 of measured post-aging bit error rate and unstable bits against accelerated aging hours based on 300 TMV-3 evaluations in accordance with an embodiment. The data plot 5002 relates to measured instability in percentage (%) for unstable bits for the PU-PUF type, the data plot 5004 relates to measured instability in percentage (%) for unstable bits for the PG-PUF type and the data plot 5006 relates to measured instability in percentage (%) for unstable bits for the PD-PUF type. On the other hand, the data plot 5012 relates to measured instability in percentage (%) for the bit error rate (BER) for the PU-PUF type, the data plot 5014 relates to measured instability in percentage (%) for the bit error rate (BER) for the PG-PUF type and the data plot 5016 relates to measured instability in percentage (%) for the bit error rate (BER) for the PD-PUF type.

[0217] Referring to the graph 5000, the worst-case post-aging bit error rates (BER) increases by 1.3X to 2.3X among PUF bit types, whereas the worst-case post-aging total unstable bits increases by less than 1.04×. Given the low pre-aging values, the resulting BER and unstable bits can be either absorbed into the PUF performance, or compensated with a minor increase in the masking ratio across voltage and temperature variations. In the latter case, the PUF-to-SRAM capacity ratio was found to be degraded by only 0.28%, 0.13% and 0.28% for pull-down (PD), access / pass-gate (PG) and pull-up (PU) bitcell transistor responses, which leads to the nearly-unaltered PUF-to-SRAM ratio of 68%, 142% and 79%. The cumulative post-aging PUF-to-SRAM ratio is hence 289%, which is very close to the pre-aging value of 296%. Accordingly, the effect of aging is minor and does not affect the conclusions drawn above, as expected by the differential readout nature of the proposed PUF methods in the present disclosure.

[0218] Being based on the underlying PUF, data fingerprinting inherits all its properties in terms of stability, entropy, identifiability, and energy. As experimental evidence, the ability to distinguish the correct data provenance through fingerprinting was verified using four scenarios.

[0219] Figure 51 shows a graph 5100 of normalised count versus correlation coefficient to illustrate measured correlation between data fingerprint reconstructed by cloud and the actual fingerprint received from edge devices in accordance with an embodiment. The four scenarios includes: Case 1 related to the genuine chip and the genuine data stored in its SRAM (shown as data plot 5102), Case 2 related to an illegitimate chip and the genuine data (chip maliciously replaced, shown as data plot 5104), Case 3 related to the genuine chip and inauthentic data (tampered input data, shown as data plot 5106), and Case 4 related to the illegitimate chip and the inauthentic data (shown as data plot 5108). In this experiment, the measured correlation coefficient between reconstructed and actual fingerprint was evaluated by using a stream of 100 video frames being stored in the same SRAM. Case 1 relates to the genuine chip and the genuine data stored in its SRAM, while the other three cases (Cases 2 to 4) refer to the actual fingerprint of an illegitimate chip or inauthentic data which need to be discriminated and detected as incorrect data provenance (i.e., either malicious chip or tampered data, or both). This was carried out by evaluating the correlation coefficient, μ, between the reconstructed and the actual data fingerprint received. The reconstructed fingerprint can be obtained from combining the input data with the PUF bit map that was stored on the server side at enrolment time (and then made inaccessible from the testing interface).

[0220] Referring to the graph 5100, the decision margin between the first and the other cases (i.e. difference between the measured correlation coefficient of Case 1 with the other cases) is typically 0.987 (on average), which is very close to the ideal value of 1. Correct data provenance is assessed when the actual fingerprint matches the reconstructed ones. Referring to the data plots 5104, 5106, 5108, in Cases 2 to 4, the average correlation coefficient is 0.0013 or lower and hence very close to the ideal value of 0. The slight differences from 0 or 1 in the above cases are due to the infrequent bit instability, as typical of PUF-based protocols. This does not pose any issues, as Case 1 can be easily distinguished from Cases 2 to 4, as evidenced in the graph 5100 of Figure 51. Overall, the decision margin between genuine chip / data and malicious chip / data is at least 77 standard deviations. Such very robust decision margin makes discrimination of the provenance of the physical source of data and the data integrity itself very easy and reliable in practical cases (e.g., by placing the discrimination threshold at 0.5). This ultimately establishes the intended two-way association between data and its provenance. Comparison with other PDF Designs

[0221] this [6] [5] [4] [3] [2] [9] [1] [7] [8] disclosure

[0222] technology fnm] 28 28 28 130 130 65 100 180 14 40 differe crossSRAM SRAM SRAM SRAM SRAM SRAM contact type failure ntial coupled 2T cell NAND inverter array size (# of 256x6 256x6 256x3 1,024 32x32 512 256x64 2,080 64x16 64x8 cells) 4 4 2

[0223] thresh mismatch read PMOS old metal- analog in each metasta current metastabil metastabil current metastabil silicon breakdow entropy source voltage bitcell bility mismat Integra ity ity ity n position mismat contact transistor ch tion ch

[0224] unmodified SRAM N / A N / A N / A N / A YES YES YES NO NO NO bitcell

[0225] 2 2 1 1 1 1 1 1 2 PUF bit / bitcell 6

[0226] area / PUF-bit 134(a)442 2,307 1,125 1,410 600 325 20 21,066 1,515 [F2 / bit](b)

[0227] ECC-less YES YES NO YES YES NO NO NO NO NO 0.9999 0.9999

[0228] Shannon entropy 0.9999 0.9999 (all 0.9997 0.9997 - - - - - 0.9996 bits / bitcell)

[0229] 0.55 – 0.75 0.60 – 1.05 0.75 – 0.70 0.5 – 0.7 0.8 – 1.4 1.0 1.5 – 1.9 0.55 – 0.75 1.20 – 1.50 1.35 – 1.6 supply voltage [V] (0 – 70) (0 – 70) (-25 – 70) (-40 – 120) (-15 – -120) (-40 – 85) (-20 – 80) (0 – 70) (-55 – 260) (25 – 110) (25 – 125) (temperature [°C])

[0230] 380 min. energy 226 75 72 16.76 128 (Simula- 50.6 138,000 460 - [fJ / bit] ted)

[0231] peak throughput 60(d)25.6 12,620 96 56 0.01 0.0016 560 - - [Mbps]

[0232] # of evaluations 1,500 1,000 5,000 1,000 2,000 500 1E6 2,000 5,000 5

[0233] 0.937 native BER 2.79% 4.3E-7 1.33% 2.16% (unstable bits) at 1.99% 0.29% 0.21% 6.15% (13.10 (20.75 (5.39% (0.017 (2.71%) (2.14%) (3.27%) nominal (31.51%) (8.45% (-) 7%) %) %) ) conditions(f)%)

[0234] TMV,

[0235] TMV, maskin VSS bias, stabilization TMV, maskin HCI burn- maskin TMV, dark bit maskin - - g> masking in masking techniques g g detection remap g

[0236] Ping

[0237] <2.2E- post-stabilization <43E- 0085 <2.2E-7 <599E-7 <391 E-7 062% 28E-3 - - 7 BER 7 %

[0238] 100% NIST tests YES YES YES YES YES YES YES YES YES - pass

[0239] 05011

[0240] inter-PUF HD 0.4941 0.502 0.4999 0.503 0.4873 0.4923 04975 - - 0.5009

[0241] intra-PUF HD 0.0091 0.0187 – 0.0295 0.0160 – 0.0340 0.0041 0.0030 0.0015 – 1 - 0.0094 - -

[0242] identifiability 72× 27×, 32×, 17× 119× 164× 332× 5292× 148× - - 14×

[0243] post-masking

[0244] 296% 127% PUF-to-array <100% -100% <100% <100% <100% <100% <100% <100% capacity<a|

[0245] data fingerprinting YES N / A N / A N / A N / A NO NO NO NO NO

[0246]

[0247] “The effective PUF density is estimated to be -45 FE / bit if using push-rule array under same area.

[0248] bIncluding peripherals for SRAM and PUF

[0249] “Average measured energy / bit across all PUF bits at 0.55 V, 25 “C (pre-stabil ization for fair comparison with all other 5 work in this table).

[0250] dMeasured at 0.75V, 25°C.ePUF capacity over SRAM capacity (or array size for non-SRAM PUFs).

[0251] fAverage value for multi-bit PUFs

[0252] Table 3: Comparison with Other SRAM PUFs and Single / Multi-Bit PUFs Compared with other PUFs as shown in relation to Table 3, the multi-bit PUF of the present disclosure is adapted to extract 6 PUF-bits / bitcell at a competitively low area overhead of 15% over a single bank with pitch-matched periphery. The area overhead of 15% is concentrated in the periphery for undisturbed array operation. As first benefit, its 134 F2area per bit has been improved over the other SRAM PUFs [2]-[6] by 3.3x (i.e. 3.3 times) to 17.2x (i.e. 17.2 times), based on the available logic-rule bitcells. Note that more pronounced benefit would be achievable under pushed rules. The 13.5 times lower energy / bit in [4] can be explained by its adoption of an extremely small 64 x 16 array size, which is 16x smaller than the present disclosure. Given the approximately linear dependence of the bitline and wordline capacitance and bitcell count on the array size, the lower energy / bit in [4] mostly come from the smaller array size (which should lead to ~16x lower energy). At the same time, the lower energy / bit in [4] comes at the cost of 17x higher area / bit as shown in Table 3.

[0253] Compared to non-SRAM PUFs [7], [9] including the 2-bit / bitcell PUF in [8], the proposed PUF improves the area / bit by 2.4x to 157x. As an only exception, the proposed PUF has 6.7x large area / bit over [1], although the latter has a higher energy / bit by 61 Ox and lower throughput by 37,500x.

[0254] The proposed PUF of the present disclosure is able to operate without ECC as opposed to other SRAM PUFs [2], [5], while simultaneously not requiring extra testing time (e.g., burn-in [4]) and / or bitcell modification (as opposed to [2]-[4]). The poststabilization BER of the proposed PUF is better than 2.22×10-7. The BER is equivalent to prior work in [6], comparable to the native contact failure-based PUF in [9], which however has 2.4x higher area / bit. The proposed multi-bit PUF also improves the BER by 126,126× compared to [7],

[0255] The proposed SRAM PUF yields a 296% PUF-to-SRAM capacity ratio with cryptographic-grade entropy of 0.9999. This ratio improves over that of the state of the art by at least 2.3x over [6], and more than 3x over for all others. In comparison to the prior art [3]-[8] relating to SRAM-based PUF and multibit (per cell) PUF, the methods of the present disclosure demonstrate multi-bit ECC-less SRAM PUF uniquely extracting 6 bit / bitcell from an unmodified 6T bitcell, and achieves 2.3x to 3x higher PUF-to-SRAM capacity than prior art for uncommonly high array utilization. In addition, it enables the unique data fingerprinting capability for an additional layer of security in terms of provenance assurance. In addition, it enables the unique data fingerprinting capability for an additional layer of security in terms of provenance assurance.

[0256] The throughput of the proposed PUF of the present disclosure is lower than the outlier SRAM PUF [5], higher than the [2], and comparable to [3], [4] and [6]. The throughput is hence aligned to most prior SRAM PUFs, but is not best in class due to the readout scheme. The latter requires ring oscillator counting with circuitry sequentially reused over two steps for offset cancellation, and the extra access using the proposed SCRA technique. Overall, the proposed PUF has a very reasonable throughput in line with most prior art, while providing state-of-the-art PUF-to-SRAM capacity ratio, cryptographic-grade quality, unique data fingerprinting capability as additional security layer, while avoiding the substantial cost and complexity of prior techniques requiring extra burn-in time or ECC. Unique data fingerprinting enables a new level of security over weak PUFs in terms of data provenance for at-rest / in-transit data.

[0257] Conclusion

[0258] The present disclosure presents a SRAM PUF with static entropy extraction from every single transistor and data fingerprinting for provenance assurance. 6 bit / bitcell static entropy is demonstrated through simple TMV and masking stabilization. Its ECC-less operation allows to retain its energy and area efficiency at system level. Further, the proposed SRAM PUF utilizes a completely standard-cell-based design that allows adoption of an unmodified bitcell and allows fully automated digital design flow for uncomplicated adoption and system integration with no need for SRAM cell modification.

[0259] The proposed PUF of the present disclosure achieves the highest post-stabilization PUF-to-SRAM capacity ratio of 296%, making it well suited for resource-constrained secure systems. The described static entropy extraction from each bitcell transistor and data dependency allow data fingerprinting which provides an additional layer of security through provenance assurance of data, and user authentication in real time or verification in retrospect. Features of the present methods and their benefits are provided in Table 4 below. Feature Benefit / Advantage

[0260] Above-storage Six PUF bits are generated from each SRAM bitcell. Thus, a high capacity PUF to memory capacity ratio is obtained (i.e., high bit density and high PUF array utilization).

[0261] Data The generated static entropy (PUF bits) is dependent on the data fingerprinting stored in the SRAM cells. This can be utilized to certify the physical capability origin of data and for user authentication.

[0262] SRAM design Present methods are adaptable to the ubiquitously available reuse SRAMs. Any modification of the conventional 6T SRAM bitcell design (i.e., a custom bitcell design) is not required.

[0263] ECC-less The typically dominant area and energy of error correcting code operation (ECC) post-processing is made redundant leading to a low-cost low-power solution.

[0264] CryptographyPUF bits have native cryptography-grade quality with no entropy grade quality post-processing (e.g., Von Neumann extractor) or ECC stability enhancement.

[0265]

[0266] Table 4: Features of present methods and their benefits The methods of the present disclosure are inherently robust against process / voltage / temperature variations because it is 1) differential, and 2) based on the comparison of digitized replicate currents obtained through neighboring bitcells for generating the PUF bit.

[0267] Although the examples as described are based on a 6T SRAM design, it should be appreciated other SRAM designs, for example, a 4T SRAM design may be used. Alternative embodiments may include: (i) applying the described methods, e.g. use of replicate currents by PMOS / NMOS sets of current mirrors, over-driving or under-driving of WL voltages or use of bitcell state for extracting the PUF bits, to other SRAM designs with other number of transistors (e.g. 4T SRAM); (ii) use of other circuitry designs, e.g. besides CSRO, for the current-to-digital conversion for forming digitized replicate currents; and (iii) comparing static entropy for generating a PUF bit from bitcells of the same row across different columns of a SRAM array, or comparing static entropy for generating a PUF bit from bitcells of the same column across different rows of a SRAM array or across different columns or different rows (this will require modifications to the examples presented).

[0268] Although only certain embodiments of the present invention have been described in detail, many variations are possible in accordance with the appended claims. For example, features described in relation to one embodiment may be incorporated into one or more other embodiments and vice versa.

[0269] References

[0270] [1] J. Lee, M. Kim, M. Jeong, G. Shin and Y. Lee, " A 20F2 / Bit Current-Integration-Based Differential NAND-Structured PUF for Stable and V / T Variation-Tolerant Low-Cost loT Security," IEEE J. Solid-State Circuits, vol. 57, no. 10, pp. 2957-2968, Oct. 2022.

[0271] [2] J. Li, T. Yang, M. Yang, P. R. Kinget, and M. Seok, “An Area-Efficient Microprocessor-Based SoC with an Instruction-Cache Transformable to an Ambient Temperature Sensor and a Physically Unclonable Function,” IEEE J. Solid-State Circuits, vol. 53, no. 3, pp. 728–737, Mar.

[0272] 2018.

[0273] [3] K. Liu, et al., “A 373-F20.21%-Native-BER EE SRAM Physically Unclonable Function with 2-D Power-Gated Bit Cells and Vss Bias-Based Dark-Bit Detection,” IEEE J. Solid-State Circuits, vol. 55, no. 6, pp. 1719-1732, Jun. 2020.

[0274] [4] K. Liu et aL, “A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement,” IEEE J. Solid-State Circuits, vol. 56, no. 7, pp.

[0275] 2193-2204, Jul. 2021.

[0276] [5] S. Taneja, V. K. Rajanna, and M. Alioto, “In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security,” IEEE J. Solid-State Circuits, vol. 57, no. 1, pp. 153–166, Jan.

[0277] 2022.

[0278] [6] J. Basu, S. Taneja, V. K. Rajanna, T. Wang and M. Alioto, “ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm,” in Proc. Symp. VLSI Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2. [7] S. K. Satpathy et al., “An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-Gate CMOS,” IEEE J. Solid-State Circuits, vol. 54, no. 4, pp. 1074–1085, Apr. 2019.

[0279] [8] K.-H. Chuang, et al., “A Multi-bit / cell PUF Using Analog Breakdown Positions in CMOS,” in Proc. of IEEE Int. Rel. Phys. Symp. (IRPS), Burlingame, USA, Mar. 2018, pp. P-CR.2-1–P-CR.2-5.

[0280] [9] D. Jeon, D. Lee, D. K. Kim, and B. -D. Choi, “A 325F2Physical Unclonable Function Based on Contact Failure Probability With Bit Error Rate < 0.43 ppm After Preselection With 0.0177% Discard Ratio,” IEEE J. Solid-State Circuits, vol. 58, no. 4, pp. 1185-1196, Apr. 2023.

Claims

Claims1. A method for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM) comprising a plurality of bitcells arranged in rows and columns, the method comprising:(i) receiving a PUF challenge input for generating the PUF bit, the PUF challenge input comprising challenge bits to define a bitcell current type, a bitcell state of a first bitcell of the plurality of bitcells and a bitcell state of a second bitcell of the plurality of bitcells, an address of the first bitcell and an address of the second bitcell, wherein the address of the first bitcell and the address of the second bitcell are defined using a row and a column associated with each of the first bitcell and the second bitcell;(ii) obtaining a first replicate current associated with a transistor of the first bitcell, wherein selection of the transistor of the first bitcell is associated with the bitcell current type and the bitcell state of the first bitcell;(iii) obtaining a second replicate current associated with a transistor of the second bitcell, wherein selection of the transistor of the second bitcell is associated with the bitcell current type and the bitcell state of the second bitcell;(iv) digitizing the first replicate current and the second replicate current to form a digitized first replicate current and a digitized second replicate current respectively; and (v) comparing the digitized first replicate current and the digitized second replicate current to generate the PUF bit.

2. The method of claim 1, further comprising:replicating, by using a set of current mirrors, a first current associated with the transistor of the first bitcell to obtain the first replicate current; andreplicating, by using the set of current mirrors, a second current associated with the transistor of the second bitcell to obtain the second replicate current,wherein the set of current mirrors comprises a PMOS set of current mirrors and a NMOS set of current mirrors, and selection of the PMOS set of current mirrors or the NMOS set of current mirrors for replicating the first current or the second current is based on the bitcell current type.

3. The method of claim 2, further comprising:under-driving or over-driving a first wordline (WL) voltage associated with the first bitcell based on the bitcell current type for selecting the transistor of the first bitcell; andunder-driving or over-driving a second wordline (WL) voltage associated with the second bitcell based on the bitcell current type for selecting the transistor of the second bitcell.

4. The method claim 2 or claim 3, wherein the step (iv) comprises:converting, using a current-starved ring oscillator (CSRO), the first replicate current to form a first frequency and the second replicate current to form a second frequency; andconverting, using a time-to-digital converter, oscillations associated with a first time period associated with the first frequency to form the digitized first replicate current and oscillations associated with a second time period associated with the second frequency to form the digitized second replicate current.

5. The method of claim 4, wherein the CSRO comprises a first set of current mirror ratio-tunable fingers and a second set of current mirror ratio-tunable fingers, the first set of current mirror ratio-tunable fingers being adapted to receive replicate PMOS currents from the PMOS set of current mirrors, and the second set of current mirror ratio-tunable fingers being adapted to receive replicate NMOS currents from the NMOS set of current mirrors, a magnitude of the replicate PMOS currents and a magnitude of the replicate NMOS currents being dependent on the corresponding bitcell state, the method further comprising:self-calibrating the first set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the first set of current mirror ratio-tunable fingers to minimize bias in 0 / 1 distribution of generated PUF bits due to process-induced mismatch in the PMOS set of current mirrors; andself-calibrating the second set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the second set of current mirror ratio-tunable fingers to minimize bias in 0 / 1 distribution of generated PUF bits due to process-induced mismatch in the NMOS set of current mirrors.

6. The method of claim 5, wherein the CSRO further comprises a first set of digital switches connected to the first set of current mirror ratio-tunable fingers and a second set of digital switches connected to the second set of current mirror ratio-tunable fingers, the method further comprising:receiving first digital enablement bits at the first set of digital switches for enabling or disabling the one or more current mirror fingers of the first set of current mirror ratio-tunable fingers; andreceiving second digital enablement bits at the second set of digital switches for enabling or disabling the one or more current mirror fingers of the second set of current mirror ratio-tunable fingers.

7. The method of any one of claims 4 to 6, wherein the step (iv) further comprises: controlling, using self-limiting frequency dividers, a number of the oscillations sensed in the first time period associated with the first frequency and a number of the oscillations sensed in the second time period associated with the second frequency.

8. The method of claim 7, further comprising:voltage-level shifting, using a level shifter, outputs associated with the first frequency and the second frequency prior to providing the voltage-level shifted outputs to the self-limiting frequency dividers for controlling the number of the oscillations sensed.

9. The method of any one of claims 1 to 8, wherein the first bitcell and the second bitcell are from different columns of the SRAM.

10. The method of claim 9, the method further comprising:using the generated RUF bit to form a row address offset to generate a new PUF challenge input internally, the new PUF challenge input comprising a new row address associated with the row address offset, the bitcell current type and new bitcell states for use with a new pair of bitcells associated with the new row address, wherein the new bitcell states corresponds to the bitcell state of the first bitcell and the bitcell state of the second bitcell; andrepeating the steps (ii) to (iv) based on the new PUF challenge input to obtain a new PUF bit.

11. The method of claim 10, wherein the new row address is within a same SRAM bank of the SRAM as the row of the address of the first bitcell and the row of the address of the second bitcell.

12. The method of any one of the preceding claims, wherein the first bitcell and the second bitcell each comprises a 6-transistors (6T) SRAM cell.

13. A method for generating a Physically Unclonable Function (PUF) bit from a 6-transistor (6T) Static Random-Access Memory (SRAM) comprising a plurality of bitcells arranged in rows and columns, the method comprising:receiving a PUF challenge input for generating the PUF bit, the PUF challenge input comprising challenge bits to define a bitcell current type, a bitcell state of a first bitcell of the plurality of bitcells and a bitcell state of a second bitcell of the plurality of bitcells, an address of the first bitcell and an address of the second bitcell, wherein the address of the first bitcell and the address of the second bitcell are defined using a row and a column associated with each of the first bitcell and the second bitcell;obtaining a first replicate current associated with a transistor of the first bitcell, wherein selection of the transistor of the first bitcell is associated with the bitcell current type and the bitcell state of the first bitcell, the selection of the transistor of the first bitcell includes:under-driving or over-driving a first wordline (WL) voltage associated with the first bitcell based on the bitcell current type; andreplicating, by using a set of current mirrors, a first current associated with the transistor of the first bitcell to obtain the first replicate current;obtaining a second replicate current associated with a transistor of the second bitcell, wherein selection of the transistor of the second bitcell is associated with the bitcell current type and the bitcell state of the second bitcell, the selection of the transistor of the second bitcell includes:under-driving or over-driving a second wordline (WL) voltage associated with the second bitcell based on the bitcell current type; andreplicating, by using the set of current mirrors, a second current associated with the transistor of the second bitcell to obtain the second replicate current;digitizing the first replicate current and the second replicate current to form a digitized first replicate current and a digitized second replicate current respectively; and comparing the digitized first replicate current and the digitized second replicate current to generate the PUF bit,wherein the set of current mirrors comprises a PMOS set of current mirrors and a NMOS set of current mirrors, and selection of the PMOS set of current mirrors or the NMOS set of current mirrors for replicating the first current or the second current is based on the bitcell current type.

14. The method of claim 13, wherein each of the first bitcell and the second bitcell includes a corresponding pair of pull-up (PU) transistors, a corresponding pair of pulldown (PD) transistors and a corresponding pair of pass-gate (PG) transistors with each pair being associated with a corresponding bitcell current type, and each of the PMOS set of current mirrors and the NMOS set of current mirrors comprises a corresponding pair of current mirrors, the method further comprising:summing a first mirrored current and a second mirrored current obtained using the corresponding pair of current mirrors of the set of current mirrors to form the first replicate current, wherein the first mirrored current and the second mirrored current are associated with a first pair of transistors selected from the corresponding pair of pull-up (PU) transistors, the corresponding pair of pull-down (PD) transistors or the corresponding pair of pass-gate (PG) transistors of the first bitcell based on the bitcell current type comprised in the PUF challenge input, and wherein a magnitude of the first mirrored current and a magnitude of the second mirrored current are dependent on the bitcell state and process-induced random mismatches in the corresponding pair of pull-up (PU) transistors, the corresponding pair of pull-down (PD) transistors and the corresponding pair of pass-gate (PG) transistors of the first bitcell; andsumming a third mirrored current and a fourth mirrored current obtained using the corresponding pair of current mirrors of the set of current mirrors to form the second replicate current, wherein the third mirrored current and the fourth mirrored current are associated with a second pair of transistors selected from the corresponding pair of pull-up (PU) transistors, the corresponding pair of pull-down (PD) transistors or the corresponding pair of pass-gate (PG) transistors of the second bitcell based on the bitcell current type comprised in the PUF challenge input, and wherein a magnitude of the third mirrored current and a magnitude of the fourth mirrored currentare dependent on the bitcell state and process-induced random mismatches in the corresponding pair of pull-up (PU) transistors, the corresponding pair of pull-down (PD) transistors and the corresponding pair of pass-gate (PG) transistors of the second bitcell.

15. A system for generating a Physically Unclonable Function (PUF) bit from a Static Random-Access Memory (SRAM) comprising a plurality of bitcells arranged in rows and columns, the system comprising a PUF periphery operationally connected to the SRAM and is configured to:(i) receive a PUF challenge input for generating the PUF bit, the PUF challenge input comprising challenge bits to define a bitcell current type, a bitcell state of a first bitcell of the plurality of bitcells and a bitcell state of a second bitcell of the plurality of bitcells, an address of the first bitcell and an address of the second bitcell, wherein the address of the first bitcell and the address of the second bitcell are defined using a row and a column associated with each of the first bitcell and the second bitcell;(ii) obtain a first replicate current associated with a transistor of the first bitcell, wherein selection of the transistor of the first bitcell is associated with the bitcell current type and the bitcell state of the first bitcell;(iii) obtain a second replicate current associated with a transistor of the second bitcell, wherein selection of the transistor of the second bitcell is associated with the bitcell current type and the bitcell state of the second bitcell;(iv) digitize the first replicate current and the second replicate current to form a digitized first replicate current and a digitized second replicate current respectively; and (v) compare the digitized first replicate current and the digitized second replicate current to generate the PUF bit.

16. The system of claim 15, wherein the PUF periphery comprises a set of current mirrors, the set of current mirrors comprises a PMOS set of current mirrors and a NMOS set of current mirrors, the system is further configured to:replicate, by using the set of current mirrors, a first current associated with the transistor of the first bit cell to obtain the first replicate current; andreplicate, by using the set of current mirrors, a second current associated with the transistor of the second bit cell to obtain the second replicate current,wherein selection of the PMOS set of current mirrors or the NMOS set of current mirrors for replicating the first current or the second current is based on the bitcell current type.

17. The system of claim 16, further configured to:under-drive or over-drive a first wordline (WL) voltage associated with the first bitcell based on the bitcell current type for selecting the transistor of the first bitcell; and under-drive or over-drive a second wordline (WL) voltage associated with the second bitcell based on the bitcell current type for selecting the transistor of the second bitcell.

18. The system of claim 16 or claim 17, wherein the system further comprises a current-starved ring oscillator (CSRO) and a time-to-digital converter, the system is further configured to:convert, using the CSRO, the first replicate current to form a first frequency and the second replicate current to form a second frequency; andconvert, using the time-to-digital converter, oscillations associated with a first time period associated with the first frequency to form the digitized first replicate current and oscillations associated with a second time period associated with the second frequency to form the digitized second replicate current.

19. The system of claim 18, wherein the CSRO comprises a first set of current mirror ratio-tunable fingers and a second set of current mirror ratio-tunable fingers, the first set of current mirror ratio-tunable fingers being adapted to receive replicate PMOS currents from the PMOS set of current mirrors, and the second set of current mirror ratio-tunable fingers being adapted to receive replicate NMOS currents from the NMOS set of current mirrors, a magnitude of the replicate PMOS currents and a magnitude of the replicate NMOS currents being dependent on the corresponding bitcell state, the system is further configured to:self-calibrate the first set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the first set of current mirror ratio-tunable fingers to minimize bias in 0 / 1 distribution of generated PUF bits due to process-induced mismatch in the PMOS set of current mirrors; andself-calibrate the second set of current mirror ratio-tunable fingers by enabling or disabling one or more current mirror fingers of the second set of current mirror ratio-tunable fingers to minimize bias in 0 / 1 distribution of generated PUF bits due to process-induced mismatch in the NMOS set of current mirrors.

20. The system of claim 18 or claim 19, wherein the system further comprises selflimiting frequency dividers, the system is further configured to:control, using the self-limiting frequency dividers, a number of the oscillations sensed in the first time period associated with the first frequency and a number of the oscillations sensed in the second time period associated with the second frequency.

21. The system of claim 20, wherein the system further comprises a level shifter, the system is further configured to:voltage-level shift, using the level shifter, outputs associated with the first frequency and the second frequency prior to providing the voltage level-shifted outputs to the self-limiting frequency dividers for controlling the number of the oscillations sensed.

22. The system of any one of claims 15 to 21, wherein the first bitcell and the second bitcell are from different columns of the SRAM.

23. The system of claim 22, the system is further configured to:use the generated PUF bit to form a row address offset to generate a new PUF challenge input internally, the new PUF challenge input comprising a new row address associated with the row address offset, the bitcell current type and new bitcell states for use with a new pair of bitcells associated with the new row address, wherein the new bitcell states corresponds to the bitcell state of the first bitcell and the bitcell state of the second bitcell; andrepeat the steps (ii) to (iv) based on the new PUF challenge input to obtain a new PUF bit.

24. The system of claim 23, wherein the new row address is within a same SRAM bank of the SRAM as the row of the address of the first bitcell and the row of the address of the second bitcell.

25. The system of any one of claims 15 to 24, wherein the first bitcell and the second bitcell each comprises a 6-transistors (6T) SRAM cell.

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