Temperature tracking dynamic retainer implementation for read operations

Abstract

The present application relates to temperature tracking dynamic keeper for implementing read operations. A static random access memory (SRAM) system includes a plurality of SRAM memory cells, each of the plurality of SRAM memory cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper supporting read operations for a first temperature range and a second keeper supporting read operations for a second temperature range, and a temperature sensitive control circuit that selects the first keeper or the second keeper based on temperature.

Description

[0001] Related Applications

[0002] This application claims the benefit of Indian Application No. 201911053697 filed on December 24, 2019, and incorporates it by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to static random access memory (SRAM), and more specifically, to systems and methods for providing a temperature tracking dynamic keeper implementation to enable read / write operations of SRAM at low voltage and / or high temperature. BACKGROUND

[0004] A typical six-transistor (6T) SRAM can experience operational failures at low voltage due to degradation of various design parameters, such as static noise margin (SNM), poor read and write margins, and exponentially increasing sensitivity to process, voltage, and temperature (PVT) fluctuations. State-of-the-art ultra-low voltage SRAM design techniques circumvent these limitations of traditional 6T SRAM by using an eight-transistor (8T) SRAM cell with independent read ports for decoupling read and write operations. However, the 8T SRAM cell suffers from data-dependent read bit line (RBL) leakage through its read port, which worsens the read sense margin in terms of voltage and time window, caused by a small current ratio of on and off states (ION / IOFF) at ultra-low voltage.

[0005] A typical solution to this problem involves using a fixed strength keeper or a larger bit cell (10T cell). Fixed strength keepers introduce problems at low voltage / low temperature or high voltage / high temperature. Using a larger bit cell increases area and thus is not a practical solution. SUMMARY

[0006] A static random access memory (SRAM) system includes a plurality of SRAM memory cells and a dynamic keeper coupled to a read bit line. The dynamic keeper includes a first keeper supporting read operations for a first temperature range and a second keeper supporting read operations for a second temperature range, and a temperature sensitive control circuit to select the first keeper or the second keeper based on temperature.

[0007] A method of providing a dynamic keeper to hold a signal in a static random access memory (SRAM) read bit line includes coupling a dynamic keeper to the read bit line, the dynamic keeper including a first keeper and a second keeper. The method further includes receiving a signal from a temperature sensitive control circuit to select the first keeper for a first temperature range or the second keeper for a second temperature range based on temperature. The dynamic keeper is designed to provide support for the read bit line. Attached Figure Description

[0008] This disclosure will be more fully understood from the following detailed description and the accompanying drawings illustrating embodiments of the present disclosure. The drawings are provided to give knowledge and understanding of embodiments of the present disclosure and are not intended to limit the scope of the disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0009] Figure 1 This is a schematic diagram of an 8T SRAM with decoupled read ports.

[0010] Figure 2 This is a schematic diagram of an 8T SRAM with a fixed strength retainer.

[0011] Figure 3 This is a block diagram of one embodiment of an SRAM with a dynamic hold implementation.

[0012] Figure 4 This is a flowchart of an embodiment using a dynamic retainer.

[0013] Figure 5 This is a circuit diagram of one embodiment of a dynamic hold mechanism implementation.

[0014] Figure 6 This is a circuit diagram of one embodiment of a temperature-sensitive delay circuit.

[0015] Figure 7 It shows Figure 5 The signal diagram of the signal timing in the implementation of the dynamic hold mechanism.

[0016] Figure 8 This is a circuit diagram of another embodiment of a dynamic hold mechanism.

[0017] Figure 9 This is a circuit diagram of another embodiment of a dynamic hold mechanism.

[0018] Figure 10 An abstract diagram of an exemplary computer system in which embodiments of the present disclosure may operate is depicted. Detailed Implementation

[0019] Aspects of the present disclosure relate to temperature tracking dynamic keeper implementations to enable ultra-low voltage read operations for SRAM. Ultra-low voltage is a technical term that can refer to voltages in the range of 0.6V to 0.4V, for example. In this design implementation, the strength of the keeper dynamically changes based on the current design requirements. An 8T static random access memory (SRAM) based high density 1R / 1W SRAM macro supports low voltage read 1 / read 0 operations as low as 0.5v. In one embodiment between -40°C to 150°C for sub-10nm FinFET technology, the dynamic strength keeper design supports reliable read operations over a large temperature range. The self-adjusting dynamic strength keeper has a temperature-adjusted based drive strength. In this way, both read 1 disturbance at high temperatures and read 0 disturbance at cold temperatures are mitigated, thereby extending reliable read operations over a wide temperature range and increasing performance gains in access time and cycle time of the memory.

[0020] Figure 1 A typical 8T SRAM organization is shown. Each row of cells 110A / 110C and 110B / 110D has a read word line (RWL) 120A / 120B attached to the read port and a write word line (WWL) 130A / 130B attached to the write port of the 6T (6 transistor) SRAM cell 110A-110D. Each column has a pair of complementary write bit lines (WBL and WBLB) 125A, 125B and 135A, 135B for writing to the cells 110A-110D, and a read bit line (RBL) 140, 145 for reading from the cells 110A-110D. The write operation of the 8T SRAM is the same as that of the 6T SRAM cell, and their read operation is performed through the read port. The read port provides decoupling from the cell 110A through transistors M0 and Ml.

[0021] During standby, all RBLs are precharged to VDD by using a precharge positive metal oxide semiconductor (PMOS) device 150A / 150B. When the read cycle is activated, the precharge PMOS 150A / 150B is turned off, leaving the read bit line (RBL) floating. If the accessed cell 110A stores a “0”, the RBL 140 discharges to ground, otherwise it remains at VDD.

[0022] As Figure 1As shown in the middle, there are four currents associated with the read bit line: Icelll, Icell0, Ileakl, and IleakO, where Icelll and IcellO are the respective read currents absorbed by the accessed cell 110A when storing "1" and "0", and Ileakl and IleakO are the leakage currents flowing through other unaccessed cells 110B storing "1" and "0", respectively. Note that when the cell 110A stores "1" (i.e., QB = "1"), its complementary bit (i.e., QB = "0") is applied to the gate of the pull-down negative metal oxide semiconductor (NMOS) M0 in the read port. But when the write word line 130A is turned on for the same row, the voltage of QB rises to a relatively small voltage (100-200 mV), and the weakly conducting Figure 1 The pull-down "M0" NMOS as shown in the middle. Icelll is a weak sub-threshold current and is smaller than IcellO. The leakage currents IleakO and Ileakl are non-negligible and become more significant at low voltage (low VDD), high temperature, and / or with a large number of cells per read bit line. The leakage currents IleakO and Ileakl of unselected cells can discharge the read bit line. The combination of the read current Icelll absorbed by the accessed cell plus the leakage current Ileak of unaccessed cells can discharge the RBL.

[0023] One approach to solve this problem is to insert a keeper in the SRAM. The keeper is configured to hold the voltage level on the read bit line during a read operation. The use of keeper circuits or keepers is a common technique for 8T SRAM single bit line read architecture. The keeper is a feedback circuit that helps the read bit line to stay at full rail to compensate for the leakage current of unselected bit cells during a read-1 operation. However, the keeper over-compensation is at risk. In a read-1 operation (reading value "1" from the SRAM cells 110A-110D), the read bit line must not discharge below the trip point of the inverter. If the current on the read bit line is reduced due to leakage paths, the inverter trips and captures the wrong data at the output. The read-1 failure occurs at higher temperatures because higher temperatures cause higher leakage. To prevent the read-1 failure, the keeper must be able to hold the RBL value, i.e., it must be strong enough to fight the leakage IleakO / Ileakl.

[0024] When there is a strong keeper on the read bit line during a read 0 operation, then it destabilizes the read 0 operation (reading a value of "0" from the SRAM cell 110A-110D). In a read 0 operation, the read port of the bit cell discharges the read bit line, and if a strong keeper is used in the design, it slows down the discharge, which is also known as fighting the bit cell read current during a read 0 cycle. These read 0 failures are particularly prominent at low temperatures. For a successful read 0 operation, a very weak keeper on the read bit line is preferred during low temperatures. The requirements for the keeper design for read 0 and read 1 are contradictory to each other. Therefore, optimizing the keeper in 8T SRAM is very complex and requires that the efforts be focused mainly on the design aspect. Furthermore, this contradictory requirement limits the minimum operating voltage and degrades the performance in the normal voltage range.

[0025] Figure 2 A large signal sensing through the sense INV inverter and weak PMOS keeper 240 (N-series PMOS) of the 8T SRAM cell 210 is depicted. This conventional scheme has difficulty performing a read "0" at SF (slow NMOS fast PMOS) corner and low temperatures, which limits the minimum operating voltage and degrades the performance in the normal operating range. Typically, a stronger PMOS keeper is needed at higher temperatures, and a weaker PMOS keeper works well at lower temperatures. But as noted above, a stronger PMOS keeper impacts the 8T SRAM performance and limits the lower functional voltage at the SF / low temperature corner.

[0026] As discussed above, there are four currents associated with the read bit line: Icelll, Icell0, Ileakl, and Ileak0, where Icelll and Icell0 are the read currents drawn by the accessed cell when storing "1" and "0", respectively, and Ileakl and Ileak0 are the leakage currents flowing through other unaccessed cells storing "1" and "0", respectively. A "read 1" occurs in the bit cell when the stored value QT = 1 (QB = 0) and the RBL is held at logic 1, while a "read 0" occurs when QT = 0 (QB = 1), which enables the RBL to discharge through the discharge path sensed by the inverter sense logic.

[0027] The keeper is configured to hold the voltage level on the read bit line during the read 1 operation. In the present system, a dynamic keeper (instead of a fixed strength keeper) is implemented, where the keeper strength varies based on the current temperature and voltage, so the keeper strength adjusts its strength with temperature to achieve the preferred performance. In one embodiment, this dynamic keeper contains two keeper configurations, such that the appropriate strength keeper activates based on temperature. When the read is a 1, the keeper supports the read 1 by "holding" the RBL charged (= power supply voltage level). Therefore, the keeper circuit should be strong enough to resist noise and leakage, otherwise it will cause false discharge to low level state, which will trigger the sense inverter trip. However, the keeper should be weak enough to support the read 0 by allowing the RBL to discharge quickly when the read is a 0, especially at low temperature. A fixed strength keeper is difficult to perform well at different temperature ranges, because the keeper strength is relatively weak at low temperature, and relatively strong at higher temperature, to achieve the best performance and support ultra-low voltage operation.

[0028] A dynamic keeper is used due to the higher leakage current Ileak1 and Ileak0 and the strength subthreshold current Icell1 at higher temperature. The leakage current at higher temperature is 10-15 times higher than the leakage current at lower temperature. At low temperature, "Ileak1 and Ileak0" are very small, and no keeper is needed. The keeper is mainly used to fight the weak subthreshold current Icell1. Icell1 is very small at low temperature, and a very weak keeper is needed. Because in a typical design, the keeper is set for high temperature requirement, a stronger keeper at low temperature will limit the minimum functional operating voltage, and reduce the operating frequency in the normal voltage range. Therefore, the present design employs a dynamic keeper implementation, where the keeper strength dynamically changes according to the design requirement. This enables a stronger keeper at higher temperature to compensate for the stronger leakage Ileak1 and Ileak0 and the stronger subthreshold Icell1 discharge path, and a weaker keeper at low temperature to support the weak subthreshold Icell1.

[0029] In one embodiment, a series of PMOS are used as a keeper to support "Icelll + Ileak_total". In one embodiment, a temperature sensor (in one embodiment a PMOS diode) is used to dynamically change the stack of the PMOS. In one embodiment, a "X+Y" series keeper or a "1 NMOS and X PMOS" series keeper is used at lower temperatures. In one embodiment when slow NMOS / fast PMOS (SF), fast NMOS / fast PMOS (FF), slow NMOS / slow PMOS (SS), or typical corner (TT) are at low temperatures, a lower drive keeper is used in one embodiment between -40C and moderate (55C-85C), (SF_-40c / FF_-40c / SS_-40c / TT_-40c). In one embodiment, a stronger "X PMOS" series keeper is used at high temperatures (in one embodiment between moderate (55C-85C) to high temperature (150C)) to address leakage issues.

[0030] Figure 3 is a block diagram of one embodiment of a system. One or more SRAM cells 310 are coupled to a read bit line 320. The read bit line is coupled directly to a weak keeper 330 or through a weak keeper 330 to a strong keeper 340. The weak keeper 330 and / or the strong keeper 340 are enabled by a control circuit 350. In one embodiment, the control circuit 350 enables the keepers with Tkeep and inverted Tkeep (Tkeep!). In one embodiment, the control circuit 350 can be a temperature sensitive delay circuit, as described below. In one embodiment, when the temperature is low (in one embodiment between -40C and moderate (55C-85C)), the weak keeper 330 is enabled, while at high temperatures (moderate temperature (55C-85C) to high temperature (150C)), the strong keeper 340 is enabled. In one embodiment, the keepers comprise a series of PMOS elements. In one embodiment, the system contains three to six PMOS for one keeper. In some embodiments, the keeper can contain a single PMOS and NMOS. The keeper is designed to provide support to the RBL line to enable a read 0 without instability and to enable a read 1 without leakage that causes an erroneous read.

[0031] In one embodiment, the difference between the keepers is the strength of the PMOS circuit. In one embodiment, the strength of the keeper varies by enabling different threshold PMOS stacked keepers, for example, for a point within the first temperature range (low (-40C) to moderate range (55C-85C)), a first PMOS stack with higher threshold PMOS devices is enabled, while for a point within the second temperature range (moderate range (55C-85C) to high (150C)), a second PMOS stack with lower threshold PMOS keeper is enabled by the Tkeep signal. In one embodiment, which keeper is enabled in the moderate temperature range depends on the operating conditions; however, either one can be enabled without affecting the read 0 / read 1 operation. Depending on the operating conditions, the strength of the lower threshold PMOS devices is 1.5 to 4 times the strength of the higher threshold devices. The strength of the keepers can also be controlled by having larger device sizes for the stronger keeper and smaller device sizes for the weaker keeper.

[0032] In one embodiment, the keeper strength varies by changing the number of PMOS elements of the keeper, for example, for the first temperature range (low (-40C) to moderate (55C-85C)), an "m" number of stacked PMOS will be enabled by the Tkeepb signal, while for the second temperature range (moderate (55C-85C) to high (150C)), a lesser number of PMOS will be enabled by the Tkeep signal. In one embodiment, the number of PMOS is "m-2", for example, two PMOS less than the first temperature range.

[0033] Figure 4 is a flowchart of one embodiment of using dynamic keepers. The process begins at block 410. At block 420, the system has temperature dependent control signals. At block 430, the temperature dependent control signals are received. In one embodiment, the temperature dependent control signals are received from a temperature sensitive delay circuit. In one embodiment, the temperature dependent control signals are received from a temperature regulated copy of the read bit line.

[0034] At block 440, the keeper path of the appropriate keeper is selected by the control signals.

[0035] At block 450, the read operation is protected using the selected keeper path. This enables the system to use a stronger keeper at hotter temperatures to compensate for a larger leakage path, ensuring that the RBL is held at a high value during the read 1 operation. However, because a lower power keeper is selected when a high power keeper is not needed, the system can ensure that the read 0 operation is successful at cooler temperatures. The process continues to monitor the temperature and selectively enable the appropriate keeper to ensure that each read operation is successful.

[0036] Figure 5 is a circuit diagram of one embodiment of a dynamic keeper implementation. To make the keeper work at low voltages, the keeper strength is dynamically changed to have a higher yield for the combined read 0 / 1 operation. As known in the art, the system contains a 6T SRAM 510 coupled to a read bit line (RBL) 520. A click / write line / precharge generation 560 is coupled to a temperature sensitive delay circuit 550. The input is a signal diode input. The output of the temperature sensitive delay circuit 550 is a signal diode output. In one embodiment, the signal diode output passes through a buffer 555. The output of the buffer 555 is a Tkeep! (inverted Tkeep) signal, which controls the stacked keeper 530.

[0037] In one embodiment, two different PMOS keeper stack configurations are used. Standard VT PMOS 545 contains a set of standard threshold PMOS, MKS1-MKSn, which create a strong keeper path and are enabled by the Tkeep signal at high temperatures. High VT PMOS 540 contains PMOS MKW1-MKWn, which are high threshold voltage transistors that create a weak PMOS keeper 540. The activation of the PMOS keepers 540, 545 dynamically switches between the standard threshold devices (strong keeper path) 545 and the high threshold devices (weak keeper path) 540. At high temperatures, the temperature sensitive delay circuit 550 turns on the standard threshold "MKS1-MKSn" PMOS transistors in the strong keeper path 545 to prevent large leakage on the RBL from causing read "1" failures. At the beginning of the read cycle, the weak strength PMOS keeper 540 is coupled into the system to support leakage. The gate of the last PMOS in the standard PMOS keeper 545 is coupled to the gate of the last PMOS in the high VT PMOS 540 to provide a feedback loop to disable the keeper after the read 0 is complete.

[0038] The signal "Tkeep" is generated through the temperature sensitive delay circuit 550. The "Tkeep" signal activates the strong keeper path 540 after a delay of "Temp_delay" and concurrently disables the weak PMOS keeper 545. The delay from the temperature sensitive delay circuit 550 creates a longer delay at cold temperatures ("Temp_delay@-40c » Temp_delay@150c") such that the weak PMOS keeper path is effective in the read 0 cycle.

[0039] Figure 6is a circuit diagram of an embodiment of a temperature sensitive delay circuit. The diode configuration (gate and drain shorted) of NMOS and PMOS transistors 630 is used to create a temperature sensitive delay in the circuit, NMOS 630A and PMOS 630B balance the system during skew.

[0040] When the 8T SRAM is operated at cold temperature and low voltage, the threshold voltage of transistor 630 increases and the reduced effective VGS of transistor 630 changes the delay of the signal. In one embodiment, the temperature delay circuit 550 is activated on the rising edge of the external signal CLK. The diode input signal 610 provides the activation. In one embodiment, the output signal "Tkeep" of this circuit is used to activate the strong PMOS keeper circuit. The circuit delay at low temperature is almost 10 times or so of the circuit delay at high temperature. This is enough to keep the stronger PMOS keeper disabled during the read "0" operation at cold temperature. MN1 625 activates the delay circuit for the read operation, MP1 620 does not activate the delay circuit in static.

[0041] Figure 7 is a signal diagram showing the signal timing in the dynamic keeper implementation of Figure 5 The clock signal CLK 710 triggers the global clock GCLK 720, the read word line signal (RWL) 730 and the pre-charge signal (PRCH) 735. The time between the diode input signal to the temperature delay circuit 550 and the moment when the diode output is turned on depends on the temperature. The output (diode output low temperature 760 or diode output high temperature 765) is turned on at different times. The delays 770, 780 show that at high temperature, the short delay 770 means that the strong keeper is turned on quickly, while at low temperature, the delay 780 is long enough so that the weak keeper is used.

[0042] The "Tkeep" signal creates a delay equivalent to the normal buffer delay at hot temperature ("Temp_delay" = ~2*inverter delay), which activates the stronger keeper path to maintain the leakage path. With the proposed dynamic keeper implementation, the PMOS keeper strength is adaptively changed with temperature to enable reliable read 0 and read 1 operations, thus enabling low voltage functionality. It can be seen that the diode output is delayed more when the temperature is lower than when the temperature is higher.

[0043] A qualitative comparison with existing methods is shown in Table 1. The design shows better Vmin and is able to operate at low voltage of 0.5v without increasing the area of the bitcell.

[0044]

[0045] Figure 8is a circuit diagram of another embodiment of a dynamic keeper implementation. The system includes a temperature sensitive delay circuit 820 that receives a diode input signal from a CLK / WL / precharge generator 840. The output of the temperature sensitive delay circuit 820 is a diode output signal that passes through a buffer 830.

[0046] The output of the buffer 830 passes through an inverter 835. The output of the inverter 835 is the Tkeep signal. The Tkeep signal controls a dual keeper 850. The Tkeep signal controls a high VT keeper 860. The inverse Tkeep signal (Tkeepb) controls a standard VT keeper 880. When the inverse Tkeep signal (Tkeepb) controls the PMOS switch 870 of the dual keeper 850, the switch turns on the high VT (weak) keeper 860. The high VT keeper 860 is activated by the PMOS switch 870. When it is active, the NMOS keeper 875 is activated and the high VT keeper 860 is active. The Tkeep signal activates the standard (strong) keeper 880 when the temperature is high. The PMOS stack in the standard keeper 880 provides support at high temperatures. The gate of the NMOS keeper 875 is coupled to the gate of the last PMOS element in the strong keeper 880 through an inverter 865.

[0047] Figure 9 is a circuit diagram of another embodiment of a dynamic keeper implementation. The system includes a temperature sensitive delay circuit 920 that receives a diode input signal from a CLK / WL / precharge generator 940. The output of the temperature sensitive delay circuit 920 is a diode output signal that passes through a buffer 930. The output of the buffer 930 passes through an inverter 935. The output of the inverter 935 is the Tkeep signal. The Tkeep signal controls a dynamic keeper 950.

[0048] The Tkeep signal controls a PMOS switch 960, which activates the path for the high temperature path through the dynamic keeper 950, e.g., the strong keeper 970. When the PMOS switch 960 is on, the signal flows through a subset of series keeper PMOS elements, shown here as MKS4, MKW3, MKW2, MKW1. The inverse Tkeepb signal activates the full set of series PMOS keepers MKW1 through MKWn for the low temperature path, e.g., the weak keeper 980. The lower number of stacked PMOS in the high temperature path provides a lower resistance path (which results in higher current) to fight leakage on unselected bit cells. In this embodiment, the stack size (e.g., the number of PMOS elements in the keeper) is used to create strong and weak keepers, rather than high VT / standard VT PMOS elements. Those skilled in the art will appreciate that the number of PMOS per keeper and the use of high VT / standard VT PMOS can both be varied in each of the above embodiments to provide the desired level of keeper support.

[0049] Figure 10 An abstracted diagram of an exemplary computer system in which embodiments of the disclosure can operate is depicted. A computer system 1000 is described that can execute a set of instructions. In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0050] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any system that can execute a set of instructions (sequential or otherwise) that specify actions to be taken by that system. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0051] The exemplary computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1018, which communicate with each other via a bus 1030.

[0052] The processing device 1002 represents one or more processors such as microprocessors, central processing units (CPUs), and the like. More particularly, the processing device can be complex instruction set computing (CISC) microprocessors, reduced instruction set computing (RISC) microprocessors, very long instruction word (VLIW) microprocessors, or processors implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 1002 can also be one or more special-purpose processing devices such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, and the like. The processing device 1002 can be configured to execute instructions 1026 for performing the operations and steps described herein.

[0053] The computer system 1000 can further include a network interface device 1008 to communicate over the network 1020. The computer system 1000 also can include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), a graphics processing unit 1022, a video processing unit 1028, and an audio processing unit 1032.

[0054] The data storage device 1018 can include a machine-readable storage medium 1024 (also known as a computer-readable medium) on which is stored one or more sets of instructions 1026 or software embodying any one or more of the methodologies or functions described herein. The instructions 1026 can also reside, completely or at least partially, within the main memory 1004 and / or within the processing device 1002 during execution thereof by the computer system 1000, the main memory 1004 and the processing device 1002 also constituting machine-readable storage media.

[0055] In some embodiments, the instructions 1026 include instructions to implement functionality corresponding to the methods described herein. While the machine-readable storage medium 1024 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and the processing device 1002 to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0056] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm can be a sequence of operations leading to a desired result. The operations require physical manipulations of physical quantities. Such quantities can take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0057] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the prior discussion, it is appreciated that throughout the description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

[0058] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0059] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0060] The present disclosure can be provided as a computer program product or software, which can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0061] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to particular exemplary embodiments. It is readily apparent to those skilled in the art that various modifications can be made to the embodiments without departing from the spirit and scope of the present disclosure as set forth in the following claims. Where the present disclosure refers to some elements in the singular, more than one element can be depicted in the figures and like elements are labeled with like numerals. The present disclosure and figures are therefore considered to be illustrative rather than restrictive.

Claims

1. A static random access memory (SRAM) system, the SRAM system comprising: a plurality of SRAM memory cells, each of the plurality of SRAM memory cells coupled to a respective read bit line; a dynamic keeper circuit coupled to the read bit line, the dynamic keeper circuit comprising a first keeper circuit and a second keeper circuit, the first keeper circuit enabled to support the read bit line during a read 1 operation of a first temperature range, and the second keeper circuit enabled to support the read bit line during a read 0 operation of a second temperature range, wherein the second temperature range is higher than the first temperature range; and a temperature sensitive control circuit to enable one of the first keeper circuit or the second keeper circuit based on a temperature within the second temperature range and the first temperature range.

2. The SRAM system of claim 1, wherein the temperature sensitive control circuit comprises a temperature sensitive delay circuit to delay an output based on the temperature.

3. The SRAM system of claim 2, wherein the temperature sensitive delay circuit comprises: a diode configuration of N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) transistors to generate a temperature sensitive delay in the output of the temperature sensitive delay circuit.

4. The SRAM system of claim 3, wherein for the first temperature range, the temperature sensitive delay circuit has a long delay such that the read 0 operation can be performed at ultra-low voltage, and for the second temperature range, the temperature sensitive delay circuit has a short delay such that the dynamic keeper circuit can support the read 1 operation.

5. The SRAM system of claim 2, wherein the first keeper circuit comprises: a PMOS switch controlled by an inverted Tkeep signal output by the temperature sensitive delay circuit; and a weak NMOS keeper circuit to support a read 0 operation of the first temperature range.

6. The SRAM system of claim 1, wherein the second keeper circuit comprises: a plurality of PMOS controlled by a Tkeep signal.

7. The SRAM system of claim 1, wherein the first keeper circuit comprises a first series of PMOS elements activated by an inverted Tkeep signal output by the temperature sensitive control circuit; and the second keeper circuit comprises a second series of PMOS elements activated by a Tkeep signal output by the temperature sensitive control circuit.

8. The SRAM system of claim 7, wherein the first series of PMOS elements is smaller than the second series of PMOS elements. ​ ​ 9. The SRAM system of claim 7, wherein the first series of PMOS elements is a subset of the second series of PMOS elements.

10. The SRAM system of claim 1, wherein the dynamic keeper circuit comprises: a PMOS switch; a full set of PMOS elements, the full set of PMOS elements comprising the second keeper circuit; and a subset of the full set of PMOS elements, the subset of the full set of PMOS elements comprising the first keeper circuit, wherein the PMOS switch determines whether the full set or the subset is selected.

11. The SRAM system of claim 1, wherein the first keeper circuit is activated at temperatures between -40 degrees Celsius and a medium temperature, and the second keeper circuit is activated at temperatures higher than the medium temperature and lower than 150 degrees Celsius, wherein the medium temperature is between 55 degrees Celsius and 85 degrees Celsius.

12. A method of providing a dynamic keeper circuit to hold a signal in a static random access memory (SRAM) read bit line, the method comprising: coupling a dynamic keeper circuit to the read bit line, the dynamic keeper circuit comprising a first keeper circuit and a second keeper circuit; receiving a signal from a temperature sensitive control circuit, the signal based on temperature; selecting the first keeper circuit of a first temperature range to support the read bit line during a read 1 operation or selecting the second keeper circuit of a second temperature range to enable the second keeper circuit to support the read bit line during a read 0 operation, wherein the second temperature range is higher than the first temperature range.

13. The method of claim 12, wherein the temperature sensitive control circuit comprises a temperature sensitive delay circuit to delay an output based on temperature.

14. The method of claim 13, further comprising: generating a temperature sensitive delay in the output of the temperature sensitive delay circuit.

15. The method of claim 14, wherein for the first temperature range, the temperature sensitive delay circuit has a long delay such that the read 0 operation can be performed at ultra low voltages, and for the second temperature range, the temperature sensitive delay circuit has a short delay such that the dynamic keeper circuit can support the read 1 operation.

16. The method of claim 13, wherein the first keeper circuit comprises a PMOS switch controlled by an inverted Tkeep signal output by the temperature sensitive delay circuit and a weak NMOS keeper circuit that supports a read 0 operation at the first temperature range, and the second keeper circuit comprises a plurality of PMOS controlled by a Tkeep signal. ​ 17. The method of claim 12, wherein the first keeper circuit comprises a first series of PMOS elements activated by an inverted Tkeep signal output by the temperature sensitive control circuit, and the second keeper circuit comprises a second series of PMOS elements activated by a Tkeep signal output by the temperature sensitive control circuit.

18. The method of claim 17, wherein one or more of: the first series of PMOS elements is smaller than the second series of PMOS elements, and the first series of PMOS elements is a subset of the second series of PMOS elements.

19. The method of claim 17, wherein selecting the first keeper circuit or the second keeper circuit in the dynamic keeper circuit comprises one of: switching a full set of the PMOS elements to select the second keeper circuit; or switching a subset of the PMOS elements to select the first keeper circuit.

20. The method of claim 12, wherein the first keeper circuit is activated at temperatures between -40 degrees Celsius to a medium temperature, and the second keeper circuit is activated at temperatures higher than the medium temperature and lower than 150 degrees Celsius, wherein the medium temperature is between 55 degrees Celsius to 85 degrees Celsius.

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