Read Time Overhead and Power Optimization for Command Queues in Memory Devices

Abstract

The present disclosure relates to read time overhead and power optimization for command queues in a memory device. An apparatus includes: a memory cell array having a first word line coupled to at least a subset of the array; a queue; and control logic. The control logic: detects a first read command to read first data from a first page of the subset; accesses a second read command in the queue, the second read command being to read second data from a second page of the subset; causes a voltage applied to the word line to ramp up to an initial value; causes the voltage to move to a target value; directs a page buffer to sense the first data from a first bit line coupled to the first page of the subset; directs the page buffer to sense the second data from a second bit line coupled to the second page of the subset; and causes the word line to discharge.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to read time overhead and power optimization for command queues in memory devices. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, the present disclosure is directed to an apparatus that includes: an array of memory cells including a first word line coupled to at least a subset of the array of memory cells; a queue implemented within the array of memory cells; and control logic coupled to the first word line and the queue, the control logic performing operations including: detecting a first read command to read first data from a first page of the subset of the array; accessing a second read command in the queue, the second read command being to read second data from a second page of the subset of the array; causing a voltage applied to the first word line to ramp up to an initial value; causing the voltage applied to the first word line to move to a target value to set up a read operation; guiding a page buffer to sense the first data from a first bit line coupled to the first page of the subset of the array; guiding the page buffer to sense the second data from a second bit line coupled to the second page of the subset of the array; and causing the first word line to discharge.

[0004] In another aspect, the present disclosure is directed to a method that includes: detecting, by control logic coupled to a first word line and a queue within a memory device, a first read command to read first data from a first page of a subset of an array of memory cells; accessing, by the control logic, a second read command in the queue, the second read command being to read second data from a second page of the subset of the array; causing, by the control logic, a voltage applied to the first word line to ramp up to an initial value; causing, by the control logic, the voltage applied to the first word line to move to a target value to set up a read operation; guiding, by the control logic, a page buffer to sense the first data from a first bit line coupled to the first page of the subset of the array; guiding, by the control logic, the page buffer to sense the second data from a second bit line coupled to the second page of the subset of the array; and causing, by the control logic, the first word line to discharge.

[0005] In another aspect, the present disclosure is directed to a method that includes: detecting, by control logic coupled to a three-level cell (TLC) word line and a queue within a memory device, a first set of read commands to read first data from a first lower page of a first TLC of a memory cell array; accessing, by the control logic, a second set of read commands within the queue to read second data from a second lower page of a second TLC of the memory cell array; causing, by the control logic, a voltage applied to the TLC word line to ramp up to an initial value; causing, by the control logic, the voltage applied to the TLC word line to move to a target value to set up a read operation; guiding, by the control logic, a page buffer to sense a first portion of the first data from a first bit line of the first lower page of the first TLC coupled to the array; guiding, by the control logic, the page buffer to sense a second portion of the first data from a second bit line of the first lower page of the first TLC; and causing, by the control logic, the voltage applied to the TLC word line to move to the target value again to set up the read operation again. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description given below and from the accompanying drawings of some embodiments of the disclosure.

[0007] Figure 1A Illustrate an example computing system that includes a memory subsystem in accordance with some embodiments.

[0008] Figure 1B is a block diagram of a memory device that communicates with a memory subsystem controller of a memory subsystem in accordance with an embodiment.

[0009] Figures 2A - 2C is for reference in accordance with an embodiment Figure 1B a schematic diagram of a portion of a memory cell array in a memory of the type described.

[0010] Figure 3 is for use in reference in accordance with an embodiment Figure 1B a schematic block diagram of a portion of a memory cell array that can be used in a memory of the type described.

[0011] Figure 4 is a conceptual depiction of the threshold voltage distribution of multiple memory cells of a memory array in accordance with an embodiment.

[0012] Figure 5 is a conceptual description of the threshold voltage distribution of multiple memory cells at a stage after programming for use with various embodiments.

[0013] Figure 6Is a diagram illustrating voltage waveforms associated with a single read command for single-level cells in certain memory devices according to an embodiment.

[0014] Figure 7 Is a diagram illustrating voltage waveforms associated with a combined read operation of two read commands for two single-level cells of a memory device according to an embodiment.

[0015] Figure 8 Is a diagram illustrating threshold voltage distributions associated with three possible pages to which a three-level cell of a memory device can be programmed according to an exemplary embodiment.

[0016] Figures 9A - 9B Is a diagram illustrating voltage waveforms associated with a combined read operation of multiple read commands for pages of multiple three-level cells from a memory device according to an embodiment.

[0017] Figure 10 Is a diagram illustrating voltage waveforms associated with a combined read operation of two read commands executed to process different blocks in a plane of a memory device according to an embodiment.

[0018] Figure 11 Is a diagram illustrating command timing waveforms associated with voltage waveforms for a single read command and a combined read operation of multiple read commands according to an embodiment.

[0019] Figure 12 Is a flowchart of an example method for performing a combined read operation of two read commands to process two single-level cells according to some embodiments.

[0020] Figure 13 Is a flowchart of an example method for performing a combined read operation of two read commands to process pages of multiple three-level cells according to some embodiments.

[0021] Figure 14 Is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Description

[0022] Embodiments of the present disclosure relate to read time overhead and power optimization for command queues in memory devices. In some memory devices, a memory subsystem controller includes a command queue in which commands from a host system or locally generated by the memory subsystem controller are buffered and processed generally in a first-in, first-out order. Such commands include erase commands to erase physical blocks of memory, write commands to program certain data (e.g., one page at a time) to one or more dies (or planes) of the memory device, or read commands to read out certain data output from one or more dies (or planes) of the memory device (e.g., one page at a time). In some such memory devices, as a read command reaches the top of the command queue, it is sent to a target die to read data from the address included in the read command.

[0023] In various embodiments, each read command includes a specific overhead, including a certain amount of time (e.g., a "time period") for each of the following phases of the read operation. The first is a time period to cause the voltage applied to all word lines of the die to ramp up to an initial voltage. The second is a time period to cause the voltage applied to the selected word line to move to a target value for the word line set for the read operation. The third is a time period to precharge the bit lines of the page (addressed in the read command) of the memory cell array of the die coupled to the plane. The fourth is a time period to sense the data stored in the page and thus read the data into a latch or register of the page buffer. In some embodiments, the precharge time period is eliminated where the bit lines are already charged or the data sensing involves simultaneous charging sufficient to read the memory cell. The fifth is a recovery time period in which the word lines and bit lines are discharged of the previously applied voltage. Because these time periods apply to the processing of each read command through each target die, processing multiple read commands causes this time overhead to accumulate into a significant cumulative overhead.

[0024] Aspects of the present disclosure address the above and other deficiencies by employing a queue (e.g., a command queue) stored in a die or in a plane of the memory device that is receiving commands to be processed. Because read commands following the current command being processed by the memory device are stored locally in the command queue, the memory device can perform a combined read operation that processes each of the current (or first) read command and a subsequent (or second) read command during the same (e.g., combined) read operation. Embodiments of the present invention achieve very good overhead savings when the first and second read commands are consecutive read commands on the same word line. For example, in one embodiment, the first and second read commands point to two different memory cells coupled to the same word line.

[0025] In these embodiments, a memory device includes a memory cell array that includes a first word line coupled to at least a subset of the memory cell array. A queue may also be located (or implemented) within the array, such as within a plane or die targeted by certain read commands. The control logic of the memory device may be coupled to the first word line and the queue. The control logic may be adapted to orchestrate a combined read operation that is performed generally as follows, but will be discussed in more detail later. The control logic may detect a first read command to read first data from a first page of the array subset. The control logic may access a second read command in the queue that is to read second data from a second page of the array subset. The control logic may cause the voltage applied to the first word line to ramp up to an initial value and then cause the voltage applied to the first word line to move to a target value to set up the read operation. The control logic may direct the page buffer to precharge the first bit lines coupled to the first page of the array subset and sense the first data. The control logic may direct the page buffer to precharge the second bit lines coupled to the second page of the array subset and sense the second data. The control logic may cause the first word line and the bit lines to discharge.

[0026] In this manner, the phases of word line voltage ramping, word line voltage moving to the target value, and word line voltage discharging can overlap for the two read commands, thereby saving the overhead time associated with these actions when performing the combined read operation. The word line discharging can be part of a recovery period that is the time between when the data is ready to be read and when the next read command is started to be processed. In different embodiments, the combination of time savings for all three of these time periods involves a savings between one-third and one-half of the overall read operation time period. In the case of performing a combined read operation for three, four, or more consecutive read commands that target the same word line, the overhead savings can become complicated.

[0027] Accordingly, advantages of the systems and methods implemented in accordance with some embodiments of the present disclosure include, but are not limited to, reducing the cumulative overhead time required to process read commands, specifically consecutive read commands in a queue that target the same word line. Reducing the overhead time for processing multiple read commands can extend from reads applied to single-level cells (SLCs) to reads applied to three-level cells (TLCs), quad-level cells (QLCs), and so on, as will be discussed in more detail. As will also be discussed later, some overhead time savings can also be achieved when performing selected combined read operations for processing random read commands. Those skilled in the art will appreciate other advantages of the read command handling optimizations within the memory device discussed below.

[0028] Figure 1ADescribe an example computing system 100 that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module.

[0029] The memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a "NAND" (negative-AND) memory device. A non-volatile memory device is a package of one or more dies. Each die may include one or more planes. A plane may be divided into logical unit (LUN) components. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a collection of physical blocks. Each block includes a collection of pages. Each page includes a set of memory cells (the "cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and have various logical states associated with the number of bits stored. The logical states may be represented by binary values (e.g., "0" and "1" or combinations of such values).

[0030] The memory device 130 may be composed of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells of a memory device, which are used together with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell.

[0031] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs), universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0032] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device (e.g., a processor).

[0033] The computing system 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A An example of a host system 120 coupled to one memory subsystem 110 is illustrated. The host system 120 can provide data to be stored at the memory subsystem 110 and can request to retrieve data from the memory subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0034] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 writes data to and reads data from the memory subsystem 110 using, for example, the memory subsystem 110.

[0035] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include but are not limited to a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), etc. The physical host interface can be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize a Non-Volatile Memory Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface can provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120.Figure 1A Describe the memory subsystem 110 as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0036] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory device 140) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0037] Some examples of non-volatile memory devices (e.g., the memory device 130) include "NAND" (Negative AND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are arrays of cross-points of non-volatile memory cells. The array of cross-points of non-volatile memory cells can perform bit storage based on a change in bulk resistance in combination with a stackable cross-gridded data access array. Additionally, compared with many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0038] Each of the memory devices 130 can include one or more memory cell arrays. One type of memory cell, e.g., single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), can store multiple bits per cell. In some embodiments, each memory device 130 can include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device can include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 can be grouped into pages, which can refer to the logical units of the memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0039] Although non-volatile memory components such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 can be based on any other type of non-volatile memory such as read-only memory (ROM), phase change memory (PCM), select-in memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0040] Memory subsystem controller 115 (controller 115 for simplicity) can communicate with memory device 130 to perform operations such as reading data, writing data, or erasing data at memory device 130 and other such operations. Memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or combinations thereof. The hardware can include digital circuitry with dedicated (i.e., hard-wired) logic to perform the operations described herein. Memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0041] Memory subsystem controller 115 can include processing means that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, local memory 119 of memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of memory subsystem 110 (including handling communication between memory subsystem 110 and host system 120).

[0042] In some embodiments, local memory 119 can include memory registers that store memory pointers, fetched data, etc. Local memory 119 can also include read-only memory (ROM) for storing microcode. Although in Figure 1A the example memory subsystem 110 has been illustrated as including memory subsystem controller 115, in another embodiment of the present disclosure, memory subsystem 110 does not include memory subsystem controller 115 and instead can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0043] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 can be responsible for other operations, such as wear-leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (such as logical block addresses (LBAs), namespaces) associated with the memory device 130 and physical addresses (e.g., physical block addresses). The memory subsystem controller 115 can further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions for accessing the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0044] The memory subsystem 110 can also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0045] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is an original memory device 130 having control logic (e.g., local media controller 135) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0046] In some embodiments, the memory device 130 includes a page buffer 152 that may provide circuitry for programming data into and reading data from the memory cells of the memory device 130. The memory device 130 may additionally include a queue 131 (e.g., a command queue) stored within the memory array of the memory device 130, such as within a die or plane of the memory device 130. In alternative embodiments, the queue 131 may be located on a local media buffer external to the memory array. The control logic of the local media controller 135 may be adapted to read commands buffered within the queue 131, identify subsequent commands that target the same word line as the current command being processed, and direct a combined read operation in which the current command and the subsequent command are processed simultaneously, such as as part of the combined read operation.

[0047] Figure 1B is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 of a memory subsystem (e.g., Figure 1A the memory subsystem 110). Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0048] The memory device 130 includes a memory cell array 104 that is logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line may be associated with memory cells of more than one logical row, and a single data line may be associated with memory cells of more than one logical column. At least a portion of the memory cells of the memory cell array 104 ( Figure 1B not shown) are capable of being programmed to one of at least two target data states. In some embodiments, the memory cell array 104 includes a queue 131 implemented within the memory cells of the memory cell array 104. The queue 131 may also be located within the local media buffer or local memory of the local media controller 135 (illustrated in dashed lines). The queue 131 may refer to the command queue mentioned herein.

[0049] A row decoding circuit system 108 and a column decoding circuit system 111 are provided to decode an address signal. The address signal is received and decoded to access the memory cell array 104. The memory device 130 further includes an input / output (I / O) control circuit system 112 for managing the input of commands, addresses, and data to the memory device 130 and the output of data and status information from the memory device 130. The address register 114 communicates with the I / O control circuit system 112, the row decoding circuit system 108, and the column decoding circuit system 111 to latch the address signal before decoding. The command register 124 communicates with the I / O control circuit system 112 and the local media controller 135 to latch incoming commands.

[0050] A controller (e.g., the local media controller 135 inside the memory device 130) controls access to the memory cell array 104 in response to a command and generates status information for the external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on the memory cell array 104. The local media controller 135 communicates with the row decoding circuit system 108 and the column decoding circuit system 111 to control the row decoding circuit system 108 and the column decoding circuit system 111 in response to an address.

[0051] The local media controller 135 also communicates with the cache register 118 and the data register 121. The cache register 118 latches incoming or outgoing data as directed by the local media controller 135 to temporarily store the data while the memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data can be transferred from the cache register 118 to the data register 121 for transfer to the memory cell array 104; then new data can be latched in the cache register 118 from the I / O control circuit 112. During a read operation, data can be transferred from the cache register 118 to the I / O control circuit 112 for output to the memory subsystem controller 115; then new data can be transferred from the data register 121 to the cache register 118. The cache register 118 and / or the data register 121 can form the page buffer 152 of the memory device 130 (e.g., can form at least a part thereof). The page buffer 152 can further include sensing means (e.g., sense amplifiers) to sense the data state of the memory cells of the memory cell array 104, e.g., by sensing the state of the data lines connected to the memory cells. The status register 122 can communicate with the I / O control circuit system 112 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0052] Memory device 130 receives control signals at memory subsystem controller 115 from local media controller 135 via control link 132. For example, the control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received via control link 132. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from memory subsystem controller 115 via a multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0053] For example, a command may be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. An address may be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data may be received at I / O control circuit 112 via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device and then written to cache register 118. The data may then be written to data register 121 for programming memory cell array 104.

[0054] In an embodiment, cache register 118 may be omitted and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference is made to I / O pins, it may include any conductive node that enables electrical connection to memory device 130 by an external device (e.g., memory subsystem controller 115), such as a common conductive pad or conductive bump.

[0055] Those skilled in the art will appreciate that additional circuitry and signals may be provided and the memory device 130 has been simplified Figure 1B of. It should be recognized that the functionality of the various block components described with reference to Figure 1B need not be separated from different components or portions of a component of an integrated circuit device. For example, a single component or portion of a component of an integrated circuit device may be adapted to perform Figure 1BAlternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1B Additionally, although specific I / O pins are described according to prevailing conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0056] Figures 2A - 2C is, for example, a part of the memory cell array 104 according to an embodiment in reference to Figure 1B Schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in a memory of the type described. The memory array 200A includes, for example, word lines 2020 to 202 N The access lines and bit lines 2040 to 204 M The word lines 202 can be connected to the data lines in a many-to-one relationship. Figure 2A For some embodiments, memory array 200A may be formed over a semiconductor that may be conductively doped to have a conductivity type such as p-type conductivity, for example, to form a p-well, or n-type conductivity, for example, to form an n-well.

[0057] The memory array 200A can be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can include a string of memory cells (eg, nonvolatile memory cells) connected in series, such as NAND strings 2060-206 M Each NAND string 206 can be connected (eg, selectively connected) to a common source (SRC) 216 and can include memory cells 2080-208 N Memory cells 208 may represent nonvolatile memory cells for storing data. Memory cells 208 in each NAND string 206 may be connected in series to select gates 210 (eg, field effect transistors) (eg, select gates 2100 to 2101). M One of the transistors (eg, which may be a source select transistor, often referred to as a select gate source) and a select gate 212 (eg, a field effect transistor) (eg, select gates 2120 to 212 M One of the select transistors 2100 to 210 (eg, which may be a drain select transistor, often referred to as a select gate drain)). M can be commonly connected to a select line 214, such as a source select line (SGS), and select transistors 2120 through 212 Mcan be commonly connected to a selection line 215, such as a source - gate - drain (SGD). Although depicted as a conventional field - effect transistor, the select gates 210 and 212 can utilize a structure similar to (e.g., the same as) that of the memory cell 208. The select gates 210 and 212 can represent several select gates connected in series, and each select gate is configured in series to receive the same or independent control signals.

[0058] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 in the corresponding NAND string 206. For example, the drain of the select gate 2100 can be connected to the memory cell 2080 in the corresponding NAND string 2060. Thus, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the selection line 214.

[0059] The drain of each select gate 212 can be connected to the bit line 204 for the corresponding NAND string 206. For example, the drain of the select gate 2120 can be connected to the bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 in the corresponding NAND string 206 N For example, the source of the select gate 2120 can be connected to the memory cell 208 in the corresponding NAND string 206 N Thus, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the selection line 215.

[0060] Figure 2A The memory array 200A in can be a quasi - two - dimensional memory array and can have a generally planar structure, such as where the common source 216, the NAND strings 206, and the bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2A The memory array 200A in can be a three - dimensional memory array, such as where the NAND strings 206 can extend in a manner generally perpendicular to the plane containing the common source 216 and generally perpendicular to the plane containing the bit lines 204, and the bit lines 204 can be generally parallel to the plane containing the common source 216.

[0061] A typical configuration of the memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trapping, etc.) that can determine the data state of the memory cell (e.g., by a change in the threshold voltage) and a control gate 236, as Figure 2Aas shown. The data storage structure 234 can include both a conductive structure and a dielectric structure, and the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 can additionally have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases, forms) the word line 202.

[0062] The column of memory cells 208 can be one NAND string 206 or several NAND strings 206 selectively connected to a given bit line 204. The row of memory cells 208 can be memory cells 208 commonly connected to a given word line 202. The row of memory cells 208 can (but need not) include all memory cells 208 commonly connected to a given word line 202. The row of memory cells 208 can generally be divided into one or more groups of physical pages of memory cells 208, and the physical page of memory cells 208 generally includes every other memory cell 208 commonly connected to a given word line 202. For example, the memory cells 208 N that are commonly connected to the word line 202 N and selectively connected to even bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be one physical page of memory cells 208 (e.g., even memory cells), and the memory cells 208

[0063] Although Figure 2A bit lines 2043 and 2045 are not explicitly depicted in, it is obvious from the figure that the bit lines 204 of the memory cell array 200A can be numbered continuously from bit line 2040 to bit line 204 M Other groupings of memory cells 208 commonly connected to a given word line 202 can also define the physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line can be considered a physical page of memory cells. The portion (e.g., the upper or lower page of memory cells) of the physical page of memory cells (which can still be the entire row in some embodiments) that is read during a single read operation or programmed during a single programming operation can be considered a logical page of memory cells. A memory cell block can include those memory cells configured to be erased together, such as those connected to word lines 2020 - 202 NAll memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cells of the logical page of the memory cell. Although described in connection with NAND flash memory Figure 2A examples, the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0064] Figure 2B is, for example, another schematic view of a portion of a memory cell array 200B that can be used in a memory of the type described as part of a memory cell array 104 in Figure 1B the reference. Figure 2B Elements with the same number in Figure 2A correspond to the description provided in Figure 2B Additional details of an example of a three-dimensional NAND memory array structure are provided. The three-dimensional NAND memory array 200B can incorporate a vertical structure that can include semiconductor pillars, where a portion of the pillars can serve as the channel regions of the memory cells of the NAND strings 206. The NAND strings 206 can each be selectively connected to bit lines 2040 - 204 M through a select transistor 212 (e.g., can be a drain select transistor, commonly referred to as a select gate drain), and selectively connected to a common source 216 through a select transistor 210 (e.g., can be a source select transistor, commonly referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of the NAND strings 206 can be connected to their respective bit lines 204 by applying a bias voltage to select lines 2150 - 215 K to selectively activate a particular select transistor 212 between the NAND string 206 and the bit line 204 respectively. The select transistor 210 can be activated by applying a bias voltage to the select line 214. Each word line 202 can be connected to multiple rows of memory cells of the memory array 200B. The rows of memory cells connected to each other through a particular sub-word line 202 can be collectively referred to as a layer.

[0065] Figure 2C is, for example, another schematic view of a portion of a memory cell array 200C that can be used in a memory of the type described as part of a memory cell array 104 in Figure 1B the reference. Figure 2C Elements with the same number in Figure 2A correspond to the description provided in Figure 2AThe series-connected memory cell strings (e.g., NAND strings) 206, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and source 216 depicted therein. For example, a portion of the memory cell array 200A can be a portion of the memory cell array 200C.

[0066] Figure 2C Depicting the grouping of NAND strings 206 into memory cell blocks 250, such as memory cell blocks 2500 to 250 L . The memory cell block 250 can be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 can represent those NAND strings 206 that are commonly associated with a single select line 215, such as select line 2150. The source 216 of the memory cell block 2500 can be the same source as the source 216 of the memory cell block 250 L . For example, each of the memory cell blocks 2500 - 250 L can be selectively and commonly connected to the source 216. The access line 202 and select lines 214 and 215 of one memory cell block 250 have no direct connection to the access line 202 and select lines 214 and 215 of any other memory cell block among the memory cell blocks 2500 - 250 L .

[0067] Bit lines 2040 to 204 M can be connected (e.g., selectively connected) to a buffer portion 240 that can be part of the page buffer 152 of the memory device 130. The buffer portion 240 can correspond to a memory plane (e.g., a set of the memory cell blocks 2500 - 250 L ). The buffer portion 240 can include sensing circuitry (which can include sense amplifiers) for sensing the data values indicated on the corresponding bit lines 204.

[0068] Figure 3 is a block diagram of a portion of a memory cell array 300 in a type of memory as can be used for reference Figure 1B as described. The memory cell array 300 is depicted as having four memory planes 350 (e.g., memory planes 3500 - 3503), each of which communicates with a corresponding buffer portion 240, which can together form a page buffer 352. Although four memory planes 350 are depicted, other numbers of memory planes 350 can communicate with the page buffer 352 together. Each memory plane 350 is depicted as including L + 1 memory cell blocks 250 (e.g., memory cell blocks 2500 - 250 L ).

[0069] Figure 4 is a conceptual depiction of the threshold voltage ranges of multiple memory cells. Figure 4 Illustrates an example of the threshold voltage ranges and their distribution for a population of sixteen-level memory cells, such as QLC memory cells. For example, such memory cells can be programmed to have a threshold voltage (Vt) within one of sixteen different threshold voltage ranges 4300 to 430 15 and each threshold voltage range is used to represent a data state corresponding to a four-bit bit pattern. The width of threshold voltage range 4300 is typically greater than the remaining threshold voltage ranges 4301 - 430 15 because the memory cells are typically all in the data state corresponding to threshold voltage range 4300 and then subsequently a subset of those memory cells are programmed to have a threshold voltage within one of the threshold voltage ranges 4301 - 430 15 Since programming operations are generally controlled in a more incremental manner compared to erase operations, these threshold voltage ranges 4301 - 430 15 can tend to have a more tightly packed distribution.

[0070] The threshold voltage ranges 4300, 4301, 4302, 4303, 4304, 4305, 4306, 4307, 4308, 4309, 430 10 、430 11 、430 12 、430 13 、430 14 and 430 15 can each represent a corresponding data state, such as L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15, respectively. As an example, if the threshold voltage of a memory cell is within the first threshold voltage range of the sixteen threshold voltage ranges 4300, then the memory cell can store the data state L0 with a data value having the logic '1111' in this case and is typically referred to as the erased state of the memory cell. If the threshold voltage is within the second threshold voltage range of the sixteen threshold voltage ranges 4301, then the memory cell can store the data state L1 with a data value having the logic '0111' in this case. If the threshold voltage is within the third threshold voltage range of the sixteen threshold voltage ranges 4302, then the memory cell can store the data state L2 with a data value having the logic '0011' in this case, and so on. Table 1 provides one possible correspondence between the data states and their corresponding logic data values. Other assignments of data states to logic data values are known or conceivable. As used herein, a memory cell maintained in the lowest data state (e.g., the erased state or L0 data state) will be considered programmed to the lowest data state.

[0071]

[0072] Table 1

[0073] Figure 5 is a conceptual description of the threshold voltage distribution of multiple memory cells after programming. Figure 5 The threshold voltage distribution 530 d -530 d+1 can represent when the programming operation of the memory cell is completed Figure 4 The threshold voltage range 4300 - 430 15 of a certain part of the distribution. Refer to Figure 5 , when programming is completed, adjacent threshold voltage distributions 530 are usually separated by a certain tolerance 532 (e.g., dead space). Applying a sense voltage (e.g., read voltage) within the tolerance 532 to the control gates of multiple memory cells can be used to distinguish the memory cells of the threshold voltage distribution 530 d (and any lower threshold voltage distribution) from the memory cells of the threshold voltage distribution 530 d+1 (and any higher threshold voltage distribution).

[0074] Figure 6 is a diagram illustrating a voltage waveform associated with a single read command for single - level cells in certain memory devices according to an embodiment. For example, each read command includes a specific overhead, including a certain amount of time for each of the following phases of the read operation. During a first time period (T1), control logic (e.g., of the local media controller 135) causes the voltage applied to all word lines of a plane or die to ramp up to an initial voltage. During a second time period (T2), the control logic causes the voltage applied to the selected word line (WLsel) to move to a target value (V target ). Also, during the second time period (T2), the control logic causes the unselected word lines (WLunsel) to continue increasing in voltage so that the NAND string (e.g., NAND string 206) can be turned on when selected.

[0075] Further refer to Figure 6In an embodiment, during a third time period (T3), control logic causes precharging of bit lines (BLs) of a page (addressed in a read command) of a memory cell array coupled to a die or plane. Control logic may of course also cause precharging of the set of BLs associated with the page. Additionally, during the third time period, control logic causes a page buffer to sense data stored in the page, thus reading the data into a latch or register of the page buffer. In some embodiments, the third time period does not include precharging in cases where the bit lines are already charged or data sensing involves simultaneous charging sufficient to read the memory cells. Precharging as a specific or separate operation may thus be considered optional, although it is illustrated and discussed throughout this disclosure. Finally, during a fourth time period (T4), control logic causes discharge of selected and unselected word lines and bit lines for recovery purposes before another read command for the array can be processed. Also, during the fourth time period, a control signal (R / B#) identifying the word line moves to a high value, indicating that the memory device is ready for a new command (as compared to being busy). Additionally, during the fourth time period, a read port (array R / B#) of the memory cell array (coupled to word lines and bit lines) indicates that there is data ready to be read before starting to process the next read command. In one embodiment, this read port is on the die being read.

[0076] Figure 7 is a diagram illustrating voltage waveforms associated with a combined read operation for processing two read commands of two single-level cells of a memory device according to an embodiment. Thus, in some embodiments, Figure 7 the selected word lines in are single-level cell word lines. Although the second time period (T2) may take more time than the indicated time, the marked second time period does not include any overlap with the third time period (T3) because the third time period will be reused for processing subsequent commands. In one embodiment, only the third time period is repeated, indicated by T3', for processing the second read command. Thus, during the T3' time period, control logic optionally precharges at least a second bit line (BL) of a second page (addressed in the second read command retrieved from queue 131) of the memory cell array coupled to the die or plane. Additionally, during the T3' time period, control logic causes the page buffer to sense second data stored in the second page, thus reading the second data into a latch or register of the page buffer. These third time periods T3 and T3' may have different lengths. For example, in one embodiment, the T3 time period is 1 - 4 microseconds (μs) shorter than T3'. In Figure 7 an embodiment, the fourth time period (T4) reserved for recovery instead follows the second third time period or T3'.

[0077] In one embodiment, further reference is made to Figure 6 [[ID=??]]andFigure 7 , T1 is approximately 10 microseconds (μs), T2 is approximately 5.9 μs, T3 is approximately 14.4 μs, T3' is approximately 18.1 μs, and T4 is approximately 6.8 μs. Thus, in embodiments where the first, second, and fourth time periods overlap for the combined read operation, when two read commands are processed as a combined read operation, the total time overhead savings is approximately 22.7 μs. These are estimated values for reducing the time overhead; different varying time values for these time periods are expected in other embodiments or for other sizes of memory cells. This time savings can be considered to be approximately 55% for reading the second SLC. Since the time periods T1 through T4 apply to the handling of each read command for each target die, combining three or more read commands into a single read operation is expected to significantly increase the reduction in time overhead.

[0078] Figure 8 is a graph illustrating the threshold voltage distributions associated with three possible pages to which a three-level cell (TLC) of a memory device can be programmed. These three pages include a lower page (LP), an upper page (UP), and an extra page (XP), each having eight voltage distributions within which a plurality of TLCs can be programmed. As can be observed, to read data from these three pages of a plurality of TLCs, two read commands are processed for the LP, three read commands are processed for the UP, and two read commands are processed for the XP. Since a single word line can be coupled to multiple TLC pages, the word line can be coupled to more than one TLC. Thus, the present disclosure can be applied to reading data outputs from two LPs of two different TLCs, from two UPs of two different TLCs, or from two XPs of two different TLCs in a combined read operation.

[0079] Moreover, as will be discussed with reference to Figures 9A - 9B the combined read operation disclosed herein can be performed when processing consecutive read commands associated with reading data from pages of a plurality of TLCs. Thus, in some embodiments, Figure 7 the selected word line is a three-level cell word line, a first read command will perform a first read operation on the lower page of a plurality of TLCs, and a second read command will perform a second read operation on the lower page. In other embodiments, the first read command will perform a first read operation on the extra page of a plurality of TLCs, and the second read command will perform a second read operation on the extra page. In another embodiment, the first read command will perform a first read operation on one of the lower page or the upper page of a plurality of TLCs, and the second read command will perform a second read operation on the one of the lower page or the upper page.

[0080] Figures 9A - 9BIt is a diagram showing voltage waveforms associated with a combined read operation for processing multiple read commands for pages of multiple triple-level cells (TLCs) from a memory device according to an embodiment. As referred to Figure 8 As discussed, these multiple read commands can be two read commands for the lower page, upper page, or additional page of multiple TLCs. Figures 9A - 9B The waveforms of Figures 9A - 9B illustrate the execution of a combined read operation for any two pages of a multi-level cell (such as MLC, QLC, PLC, etc.). In various embodiments, the waveform progresses through eight time periods, and the first four time periods are those that can overlap with the four time periods discussed with reference to Figure 7 Figure 7 .

[0081] More specifically, the control logic can detect a first set of read commands to read first data from a first lower page of a first TLC of a memory cell array. The control logic can further access a second set of read commands to read second data from a second lower page of a second TLC of the memory cell array. The first set of read commands can be processed via Figure 9A the first four time periods illustrated in Figure 9A in a first combined read operation. In this TLC embodiment, the control logic causes the voltage applied to the TLC word line to ramp up to an initial value during a first time period (T1). The control logic causes the voltage applied to the TLC word line to move to a target value during a second time period (T2) to set up the read operation. The control logic guides the page buffer to optionally pre-charge the first bit line coupled to the first lower page of the first TLC of the array and sense the first part of the first data during a third time period (T3). Similar to the reference Figure 7 Figure 7 , the second and third time periods can overlap, but are illustrated as non-overlapping for simplicity, and thus the third time period is equivalent to the fourth time period. Additionally, the control logic guides the page buffer to optionally pre-charge the second bit line coupled to the first lower page of the first TLC and sense the second part of the first data during a fourth time period (T4).

[0082] Additionally referring to Figure 9B , according to some embodiments, the control logic can be at Figures 9A - 9BProcess the second read command set in the second half of the combined read operation. In these embodiments, the control logic causes the voltage applied to the TLC word line to move back to the target value during a fifth time period (T5) to re-set the read operation. The control logic further guides the page buffer to optionally pre-charge the third bit line of the second lower page of the second TLC coupled to the array and sense the first part of the second data during a sixth time period (T6). The control logic may further guide the page buffer to optionally pre-charge the fourth bit line of the second lower page of the second TLC coupled to the array and sense the second part of the second data during a seventh time period (T7). Finally, the control logic may cause the TLC word line to discharge and further cause the unselected word lines and bit lines to discharge during a recovery or eighth time period (T8). Since four read commands pointing to the same word line are processed, the first time period and the eighth time period are used only once (instead of four times) and the second time period is used only twice, such as T2 and T5, instead of four times, thereby achieving a significant reduction in the time overhead for reading two LPs of multiple TLCs (or two UPs or two XPs of multiple TLCs).

[0083] Figure 10 is a diagram illustrating voltage waveforms associated with performing a combined read operation for processing two read commands directed to different blocks in a plane of a memory device. Although Figure 10 the embodiments of Figure 7 are similar to Figure 6 the embodiments of Figure 6 the difference is that consecutive read commands (from queue 131) do not point to the same word line. Thus, after processing the first read command (in accordance with

[0084] ), the control logic may cause the unselected word lines and the selected word line to float when processing the second read command (in accordance with

[0085] Figure 11 ) directed to another block in the plane. Thus, data can be read during the combined read operation and multiple word lines (associated with pages of both different read commands) and bit lines that have been pre-charged can be discharged simultaneously. This can save the time required for the recovery period for the second (or any subsequent) read command. ), the control logic may cause the unselected word lines and the selected word line to float when processing the second read command directed to another block in the plane. Thus, data can be read during the combined read operation and multiple word lines (associated with pages of both different read commands) and bit lines that have been pre-charged can be discharged simultaneously. This can save the time required for the recovery period for the second (or any subsequent) read command. If the unselected word lines are held at a high voltage (due to floating word lines), the memory cells in the previously selected block are stressed, which can cause read interference in those memory cells. Thus, to reduce the potential read interference effect on nearby cells before moving to read from the next block, the control logic may slightly discharge the word lines, for example, from 8V to 7V in one embodiment. The probability of read interference can be further reduced by causing a recovery operation to be performed after a threshold number of consecutive read commands are executed across multiple word lines. The control logic may further turn off the block selector without loss of time.

[0085] Figure 11It is a diagram showing command timing waveforms associated with a voltage waveform for processing a single read command and a combined read operation of multiple read commands according to an embodiment. In one embodiment, by way of example only, the control logic may direct a first read operation to retrieve page_N, a second read operation to retrieve page_N+1, and a combined third read operation to retrieve page_N+2 and page_N+3. As illustrated, the values of each incoming read command R / B#, array R / B, internal page data, unselected WL, selected WL, secondary data cache (SDC) data, and primary data cache (PDC) data are shown as control signal waveforms, voltage waveforms, and block waveforms, respectively. In various embodiments, the controller 115 sends a read command (30h) to the control logic (e.g., local media controller 135) of the memory device 130 instead of interleaving the read command (30h) with a cache command (31h).

[0086] In this way, the control logic is allowed to more independently control the cache (associated with the page buffers 152 and 352) and simplify the control sequence, thereby enabling data transfer to be hidden during the WL recovery period. For example, as will be explained, the management of internal data movement by the memory device 130 can be dynamic based on latch availability. Additionally, the PDC may not be counted in the data transfer.

[0087] As Figure 11 illustrated, the internal page can be read out from the memory cells during the recovery period, thereby enabling data transfer to be hidden during this time period. Sometimes later, the data stored in the latch of the SDC may be transferred out of the memory device 130. Since the transfer of the SDC data out of the die is performed when the select gate has timed out, the controller 115 can send a cache release command to the die when the select gate has timed out and then release a specific SDC latch for use in storing new data from the die. In this way, the read data timing output can be decoupled from the presentation of subsequent commands (different from the usual way of handling cache management).

[0088] Therefore, with additional reference to Figure 7 , the control logic may additionally receive a first cache release command associated with the latch of the page buffer and cause a first data to be stored in the latch of the page buffer. The control logic may additionally receive a second cache release command associated with the latch and cause a second data to be stored in the latch of the page buffer. These actions may be taken with reference to the memory device 130, thereby transferring data out of the cache to release the latch (of the SDC) for use in storing additional data being read out from the memory cell array. In one embodiment, the second cache release command is received after the first cache release command.

[0089] In addition, with further reference Figures 9A - 9B , after the first four time periods, the control logic may additionally receive a first cache release command associated with the latch of the page buffer, causing a first portion of the first data to be stored in the latch, receive a second cache release command associated with the latch of the page buffer, and cause a second portion of the first data to be stored in the latch. In one embodiment, the second cache release command is received after the first cache release command. Additionally, after the second four time periods, the control logic may additionally receive a third cache release command associated with the latch of the page buffer, causing a first portion of the second data to be stored in the latch, receive a fourth cache release command associated with the latch of the page buffer, and cause a second portion of the second data to be stored in the latch. In one embodiment, the fourth cache release command is received after the third cache release command. In this way, the same page buffer and latch can be shared when reading data from the SDC.

[0090] Figure 12 is a flowchart of an example method 1200 for performing a combined read operation that processes two read commands for two single-level cells according to some embodiments. Method 1200 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 1200 is performed by Figures 1A - 1B a local media controller 135 coupled to a page buffer (e.g., page buffer 152) and a queue (e.g., queue 131). Although shown in a particular order or sequence, the order of the processing procedures may be modified unless otherwise specified. Accordingly, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0091] At operation 1210, a first command is detected. For example, the processing logic detects a first read command to read first data from a first page of a subset of the memory cell array. The memory cell array may be coupled to a first word line and the previously mentioned queue.

[0092] At operation 1220, a second command is accessed. For example, the processing logic accesses a second read command in the queue, the second read command being to read second data from a second page of the array subset. In some embodiments, the second read command is chained in the queue with the first read command.

[0093] At operation 1230, a voltage ramp is performed. For example, the processing logic causes the voltage applied to the first word line to ramp up to an initial value.

[0094] At operation 1240, the voltage is shifted. For example, the processing logic causes the voltage applied to the first word line to shift to a target value to set up a read operation.

[0095] At operation 1250, a bit line is sensed. For example, the processing logic directs the page buffer to sense first data from a first bit line of a first page coupled to a subset of the array. In some embodiments, the processing logic also first directs the page buffer to precharge the first bit line before sensing the first data.

[0096] At operation 1260, another bit line is sensed. For example, the processing logic directs the page buffer to sense second data from a second bit line of a second page coupled to a subset of the array. In some embodiments, the processing logic also first directs the page buffer to precharge the second bit line before sensing the second data.

[0097] At operation 1270, the word line is discharged. For example, the processing logic causes the first word line and the bit line to be discharged. In various embodiments, the operations of ramping up the voltage applied to the first word line, shifting the voltage applied to the first word line to a target value, and discharging the first word line will be performed only once when processing both the first read command and the second read command.

[0098] Figure 13 is a flowchart of an example method 1300 that performs a combined read operation for processing pages of multiple three-level cells according to some embodiments. Method 1300 may be executed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 1300 is performed by Figures 1A - 1B a local media controller 135 coupled to a page buffer (e.g., page buffer 152) and a queue (e.g., queue 131). Although shown in a particular order or sequence, the order of the processing routines may be modified unless otherwise specified. Thus, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0099] At operation 1310, a first command is detected. For example, the processing logic detects a first set of read commands to read first data from a first lower page of a first TLC of the memory cell array. The first TLC may be coupled to a three-level cell (TCL) word line and a queue.

[0100] At operation 1320, a second command is accessed. For example, the processing logic accesses a second set of read commands in the queue to read second data from a second lower page of a second TLC of the memory cell array. In one embodiment, the second set of read commands is linked to the first set of read commands.

[0101] At operation 1330, a voltage ramp is performed. For example, the processing logic causes the voltage applied to the TLC word line to ramp up to an initial value.

[0102] At operation 1340, the voltage is shifted. For example, the processing logic causes the voltage applied to the TLC word line to shift to a target value to set up a read operation.

[0103] At operation 1350, the bit line is sensed. For example, the processing logic directs the page buffer to sense a first portion of the first data from a first bit line of the first lower page of the first TLC coupled to the array. In some embodiments, the processing logic also first directs the page buffer to precharge the first bit line before sensing the first portion of the first data.

[0104] At operation 1360, another bit line is sensed. For example, the processing logic directs the page buffer to sense a second portion of the first data from a second bit line of the first lower page of the first TLC coupled to the array. In some embodiments, the processing logic also first directs the page buffer to precharge the second bit line before sensing the second portion of the first data.

[0105] At operation 1370, the word line is discharged. For example, the processing logic causes the voltage applied to the TLC word line to shift to the target value again to set up a read operation again. In other embodiments, method 1300 is applied to upper pages (UP) of multiple TLCs or to extra pages (XP) of multiple TLCs.

[0106] In additional embodiments, the processing logic directs the page buffer to precharge a third bit line of the second lower page of the second TLC coupled to the array and sense a first portion of the second data. The processing logic directs the page buffer to precharge a fourth bit line of the second lower page of the second TLC coupled to the array and sense a second portion of the second data. The processing logic causes the TLC word line and the bit lines to be discharged to perform a recovery operation.

[0107] Figure 14Describe an example machine of computer system 1400, in which an instruction set executable to cause the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 1400 may correspond to a host system (e.g., Figure 1A 's host system 120), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A 's memory subsystem 110), or can be used to perform the operations of a controller (e.g., to execute an operating system to perform the operations corresponding to Figure 1A 's memory subsystem controller 115). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate in the capacity of a server or client machine in a client-server network environment as a peer machine in a peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment.

[0108] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) an instruction set specifying the actions to be taken by the machine. Additionally, although a single machine is described, the term "machine" should also be considered to include any collection of machines that, individually or jointly, execute one (or more) instruction sets to perform any one or more of the methods discussed herein.

[0109] Example computer system 1400 includes a processing device 1402, a main memory 1404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1410 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1418, which communicate with each other via a bus 1430.

[0110] The processing device 1402 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 1402 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, and so on. The processing device 1402 is configured to execute instructions 1428 for performing the operations and steps discussed herein. The computer system 1400 may further include a network interface device 1412 for communicating over the network 1420.

[0111] The data storage system 1418 may include a machine-readable storage medium 1424 (also referred to as a computer-readable medium) having stored thereon one or more instruction sets 1428 or software embodying any one or more of the methods or functions described herein. The data storage system 1418 may further include the local media controller 135, the page buffer 152 or 352, and the queue 131 discussed previously. The instructions 1428 may also reside, completely or at least partially, within the main memory 1404 and / or within the processing device 1402 during execution by the computer system 1400, and the main memory 1404 and the processing device 1402 also constitute machine-readable storage media. The machine-readable medium 1424, the data storage system 1418, and / or the main memory 1404 may correspond to Figure 1A the memory subsystem 110.

[0112] In one embodiment, the instructions 1426 include instructions for implementing the functionality corresponding to a controller (e.g., Figure 1A the memory subsystem controller 115). Although the machine-readable storage medium 1424 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding an instruction set for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be regarded as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0113] Some parts of the foregoing have been presented in algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts can most effectively convey the substance of their work to others skilled in the art. In this context, and generally, an algorithm is conceived of as a self-consistent sequence of operations that produces a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient, for the common variety of reasons, at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and so forth.

[0114] However, it should be borne in mind that all such and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memory or registers of the computer system or other such information storage systems.

[0115] The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0116] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of various of these systems will be presented as will be set forth in the description below. In addition, the present disclosure has not been described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0117] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, and the like.

[0118] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A device, comprising: An array of memory cells, including a first word line coupled to at least one subset of the array of memory cells; A queue implemented within the array of memory cells; And Control logic coupled to the first word line and the queue, the control logic performing operations including: Detecting a first read command to read first data from a first page of the subset of the array; Accessing a second read command in the queue, the second read command being to read second data from a second page of the subset of the array; Causing a voltage applied to the first word line to ramp up to an initial value; Causing the voltage applied to the first word line to move to a target value to set up a read operation; Guiding a page buffer to sense the first data from a first bit line coupled to the first page of the subset of the array; Guiding the page buffer to sense the second data from a second bit line coupled to the second page of the subset of the array; And Causing the first word line to discharge.

2. The device according to claim 1, wherein the second read command is chained in the queue with the first read command, and wherein guiding the page buffer further includes guiding the page buffer to precharge the first bit line and the second bit line.

3. The device according to claim 1, wherein the operations of causing the voltage applied to the first word line to ramp up to the initial value, causing the voltage applied to the first word line to move to the target value, and causing the first word line to discharge are guided to be performed only once by the control logic.

4. The device according to claim 1, wherein the operations further include: Receiving a first cache release command associated with a latch of the page buffer; And Causing the first data to be stored in the latch of the page buffer.

5. The device according to claim 4, wherein the operations further include: Receiving a second cache release command associated with the latch; And Causing the second data to be stored in the latch of the page buffer.

6. The device according to claim 1, wherein the first word line is a single-level cell word line.

7. The device according to claim 1, wherein the first word line is a three-level cell word line, the first read command is to perform a first read operation on a lower page of a plurality of three-level cells, and the second read command is to perform a second read operation on the lower page.

8. The device according to claim 1, wherein the first word line is a three-level cell word line, the first read command is to perform a first read operation on an additional page of a plurality of three-level cells, and the second read command is to perform a second read operation on the additional page.

9. A method, comprising: Detecting, by control logic coupled to a first word line and a queue within a memory device, a first read command to read first data from a first page of a subset of an array of memory cells; Accessing, by the control logic, a second read command in the queue, the second read command being to read second data from a second page of the subset of the array; Cause the voltage applied to the first word line to ramp up to an initial value via the control logic; Cause the voltage applied to the first word line to move to a target value via the control logic to set up a read operation; Guide, via the control logic, the page buffer to sense the first data from the first bit line of the first page of the subset coupled to the array; Guide, via the control logic, the page buffer to sense the second data from the second bit line of the second page of the subset coupled to the array; and Cause the first word line to discharge via the control logic.

10. The method according to claim 9, wherein the second read command is chained to the first read command in the queue, and wherein guiding the page buffer further comprises guiding the page buffer to precharge the first bit line and the second bit line.

11. The method according to claim 9, wherein the operations of causing the voltage applied to the first word line to ramp up, causing the voltage applied to the first word line to move to the target value, and causing the first word line to discharge are performed only once when processing both the first read command and the second read command.

12. The method according to claim 9, further comprising: Receiving a first cache release command associated with a latch of the page buffer; and Causing the first data to be stored in the latch of the page buffer.

13. The method according to claim 12, further comprising: Receiving a second cache release command associated with the latch; and Causing the second data to be stored in the latch of the page buffer.

14. The method according to claim 9, wherein the first word line is a single-level cell word line.

15. The method according to claim 9, wherein the first word line is a three-level cell word line, the first read command is a first read operation that executes one of a lower page or an upper page of a plurality of three-level cells, and the second read command is a second read operation that executes the one of the lower page or the upper page.

16. A method, comprising: Detecting, via control logic coupled to a three-level cell (TLC) word line and a queue within a memory device, a first set of read commands to read first data from a first lower page of a first TLC of a memory cell array; Accessing, via the control logic, a second set of read commands in the queue to read second data from a second lower page of a second TLC of the memory cell array; Cause the voltage applied to the TLC word line to ramp up to an initial value via the control logic; Cause the voltage applied to the TLC word line to move to a target value via the control logic to set up a read operation; Guide, via the control logic, the page buffer to sense a first portion of the first data from a first bit line of the first lower page of the first TLC coupled to the array; Guide, via the control logic, the page buffer to sense a second portion of the first data from a second bit line of the first lower page of the first TLC; and Cause the voltage applied to the TLC word line to move back to the target value via the control logic to set up the read operation again.

17. The method of claim 16, wherein the second read command set is chained in the queue to the first read command set, and wherein guiding the page buffer further includes guiding the page buffer to precharge the first bit line and the second bit line.

18. The method of claim 16, further comprising: Receiving a first cache release command associated with the latch of the page buffer; Causing the first portion of the first data to be stored in the latch; Receiving a second cache release command associated with the latch of the page buffer; and Causing the second portion of the first data to be stored in the latch.

19. The method of claim 16, further comprising: Guiding the page buffer to precharge the third bit line of the second lower page of the second TLC coupled to the array and sense a first portion of the second data; Guiding the page buffer to precharge the fourth bit line of the second lower page of the second TLC coupled to the array and sense a second portion of the second data; and Causing the TLC word line to discharge.

20. The method of claim 19, further comprising: Receiving a third cache release command associated with the latch of the page buffer; Causing the first portion of the second data to be stored in the latch; Receiving a fourth cache release command associated with the latch of the page buffer; and Causing the second portion of the second data to be stored in the latch.

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