Static random access memory circuit and electronic product

Abstract

The application provides a static random access memory circuit and electronic products, the static random access memory circuit comprises a storage array, a source bias circuit and a control circuit, the control circuit compares a source bias voltage output by the source bias circuit with a reference voltage, and outputs a feedback signal according to a comparison result to control the source bias voltage output by the source bias circuit, so that the source bias voltage provided by the source bias circuit to the storage array is adaptively adjusted, logic is simple, sensitivity is high, and the circuit area increases little.

Description

Technical Field

[0001] The present invention relates to the technical field of low power consumption control, and in particular to a static random access memory circuit and an electronic product. Background Art

[0002] Static power consumption refers to the power consumption when the power supply and ground are turned on. When the circuit is not working, leakage current will flow through the circuit. Therefore, static power consumption can also refer to leakage current power consumption.

[0003] In applications requiring power control, such as wearable devices and automotive chips, the static power consumption of static random-access memory (SRAM) remains a significant component. Due to the unique nature of SRAM storage, static power consumption cannot be reduced by simply cutting off the power supply. Therefore, low-power SRAM designs often incorporate sleep modes and source bias mechanisms, and reduce static power consumption by partially reducing the voltage of the memory array.

[0004] However, currently, within the operating voltage range of SRAM (1V to 2V), there is no good adaptive source bias solution for reducing the static power consumption of SRAM. Summary of the Invention

[0005] The object of the present invention is to provide a static random access memory circuit and an electronic product, which have simple circuits, can realize adaptive adjustment, and have high sensitivity.

[0006] To achieve the above object, the present invention provides a static random access memory circuit, comprising:

[0007] a storage array for storing data;

[0008] a source bias circuit, coupled to the memory array, for providing a source bias voltage to the memory array;

[0009] The control circuit is coupled to the source bias circuit and is used to compare the source bias voltage output by the source bias circuit with a reference voltage and output a feedback signal according to the comparison result to control the source bias voltage output by the source bias circuit.

[0010] Optionally, the control circuit includes a sensitive amplifier.

[0011] Optionally, the sensitive amplifier includes:

[0012] A first switch unit, configured to be turned on under the control of a control signal to access the source bias voltage;

[0013] a second switch unit, configured to be turned on under the control of the control signal to access the reference voltage;

[0014] a coupling inverting unit coupled to the first switch unit and the second switch unit, and configured to compare the source bias voltage with the reference voltage;

[0015] An output unit is coupled to the coupling inverting unit and is configured to output the feedback signal according to a comparison result of the coupling inverting unit.

[0016] Optionally, the first switch unit includes a first MOS transistor, and the second switch unit includes a second MOS transistor; the gates of the first MOS transistor and the second MOS transistor are both connected to the control signal, the source of the first MOS transistor is connected to the source bias voltage, and the source of the second MOS transistor is connected to the reference voltage; the drain of the first MOS transistor is coupled to the first port of the coupled inverting unit and one end of the output unit, and the drain of the second MOS transistor is coupled to the second port of the coupled inverting unit and the other end of the output unit.

[0017] Optionally, the coupled inverting unit includes third to sixth MOS tubes, the source of the third MOS tube and the source of the fourth MOS tube are both connected to the first power supply voltage used to power the control circuit, the source of the fifth MOS tube is coupled to the source of the sixth MOS tube, the drain of the third MOS tube and the drain of the fifth MOS tube are coupled and serve as the first port of the coupled inverting unit, the drain of the fourth MOS tube and the drain of the sixth MOS tube are coupled and serve as the second port of the coupled inverting unit, the gate of the third MOS tube and the gate of the fifth MOS tube are coupled and coupled to the second port, and the gate of the fourth MOS tube and the gate of the sixth MOS tube are coupled and coupled to the first port.

[0018] Optionally, the output unit includes: a first NAND logic circuit, a second NAND logic circuit, and a first inverting logic circuit; the first input end of the first NAND logic circuit is coupled to the second port of the coupled inverting unit, the second input end of the first NAND logic circuit is coupled to the output end of the second NAND logic circuit and the input end of the first inverting logic circuit; the first input end of the second NAND logic circuit is coupled to the output end of the first NAND logic circuit, the second input end of the second NAND logic circuit is coupled to the first port of the coupled inverting unit; the output end of the first inverting logic circuit is coupled to the source bias circuit.

[0019] Optionally, the sense amplifier further includes a pull-down switch unit coupled to the coupling inverting unit, configured to be turned on under the control of the control signal to provide a second power supply voltage to the coupling inverting unit.

[0020] Optionally, the source bias circuit includes:

[0021] a second inverting logic circuit, coupled to the output terminal of the control circuit, configured to receive the feedback signal and output an inverted signal that is inverted to the feedback signal;

[0022] at least two voltage drop branches with different voltage drop levels, at least one of the voltage drop branches being coupled to an output terminal of the control circuit and configured to provide a corresponding voltage drop under control of the feedback signal, and at least another of the voltage drop branches being coupled to an output terminal of the second inverting logic circuit and configured to provide a corresponding voltage drop under control of the inverting signal;

[0023] The sum of the voltage drops provided by all the voltage drop branches at the same time is the source bias voltage provided by the source bias circuit.

[0024] Optionally, the voltage drop branch includes at least two cascaded MOS transistors, and the number of cascaded MOS transistors in the voltage drop branches with different voltage drop degrees is different.

[0025] Based on the same inventive concept, the present invention further provides an electronic product comprising the static random access memory circuit according to the present invention.

[0026] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0027] 1. Under the feedback of the control circuit, the source bias circuit can achieve adaptive adjustment;

[0028] 2. Simple logic, high sensitivity, strong versatility, and small increase in circuit area. For example, the circuit area can be controlled to increase by only about 0.5%;

[0029] 3. Additional power consumption is only generated when the control circuit performs voltage comparison, and the power supply to the control circuit can be cut off after the system enters sleep mode, thereby not increasing static power consumption in sleep mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of a circuit architecture of an existing SRAM that uses a source bias mechanism to reduce power consumption.

[0031] Figure 2 This is a schematic diagram of a circuit architecture that uses a voltage-following analog circuit in an existing SRAM to reduce power consumption.

[0032] Figure 3 FIG. 4 is a schematic diagram of a system architecture of a static random access memory circuit according to a specific embodiment of the present invention.

[0033] Figure 4 FIG. 1 is a schematic diagram of a specific circuit structure example of a control module in a static random access memory circuit according to a specific embodiment of the present invention.

[0034] Figure 5 The figure is a schematic diagram of a specific circuit example structure of a source bias module in a static random access memory circuit according to a specific embodiment of the present invention.

[0035] Figure 6 It is a timing diagram of corresponding signals in a static random access memory circuit according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0036] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] Please refer to Figure 1In the prior art, in order to achieve a balance between data security and low power consumption of SRAM, one solution is to introduce a source bias circuit 20 and control the output of the source bias circuit 20 by applying external control signals B0 and B1 to provide different levels of voltage drop (i.e., source bias voltage) VDDC to the storage array 10 of the SRAM. In this case, a programmable control structure (such as a decoding circuit) can be used to generate a combination of control signals B0 and B1 that meet different working modes to select the corresponding source bias voltage VDDC gear setting. This method has a simple circuit structure, is flexible to use, and does not introduce additional power consumption. However, it has the following disadvantages: (1) To ensure data security, this solution requires a conservative design, and the power consumption reduction effect is not obvious; (2) adaptive adjustment cannot be achieved; (3) under changing external environmental conditions, the voltage reduction effect of the SRAM storage array is uncontrollable, especially when the voltage drop of the storage array 10 exceeds the data retention voltage (DRV), it will cause data damage. Therefore, the voltage reduction effect of the SRAM is usually selected to be conservative. The data retention voltage DRV refers to the minimum voltage at which the SRAM retains data in the idle state.

[0038] Please refer to Figure 2 In the prior art, in order to achieve the effect of adaptive adjustment, a voltage follower analog circuit 30 is usually introduced to provide a corresponding source bias voltage VDDC to the storage array 10. The voltage follower analog circuit 30 can be connected to the voltage before and after the voltage division of resistors R1 and R2, and then adaptively adjust the source bias voltage VDDC output according to the obtained voltage division result, thereby achieving adaptive adjustment with high sensitivity. However, this method has the following disadvantages: (1) The structure of the voltage follower analog circuit 30 is complex, and it usually includes a current source, a reference voltage generator, a voltage follower, etc., which significantly increases the circuit area, and the added modules (such as current source, reference voltage generator, voltage follower, etc.) themselves will bring additional power consumption and cannot be turned off in sleep mode; (2) The versatility is poor. For SRAM memories of different specifications, the voltage follower analog circuit 30 needs to be re-adjusted and designed.

[0039] The technical solutions proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0040] Please refer to Figure 3One embodiment of the present invention provides a static random access memory circuit, which includes a memory array 10, a source bias circuit 20, and a control circuit 40. The memory array 10 is used to store data and can implement data reading, writing, erasing, and other operations under the control of word line signals WL, bit line signals BL and BLB, a source bias voltage VDDC, and a second power supply voltage VSS. The source bias circuit 20 is coupled to the memory array 10 and is used to provide the source bias voltage VDDC to the memory array 10. The control circuit 40 is coupled to the source bias circuit 20 and is used to compare the source bias voltage VDDC output by the source bias circuit 20 with a reference voltage VREF, and output a feedback signal AUTO_SB based on the comparison result to control (i.e., adjust) the magnitude of the source bias voltage VDDC output by the source bias circuit 20.

[0041] Optionally, the control circuit 40 includes a sense amplifier.

[0042] Please refer to Figure 4 Further optionally, the sense amplifier includes a first switch unit 401 , a second switch unit 402 , a coupling inverting unit 403 , a pull-down switch unit 404 , and an output unit 405 .

[0043] The first switch unit 401 is configured to be turned on under the control of a control signal ABS_ON to connect to the source bias voltage VDDC, and the second switch unit 402 is configured to be turned on under the control of the control signal ABS_ON to connect to the reference voltage VREF.

[0044] As an example, see Figure 4 The first switch unit 401 includes a first MOS transistor P1, and the second switch unit includes a second MOS transistor P2. The gates of the first MOS transistor P1 and the second MOS transistor P2 are both connected to the control signal ABS_ON. The source of the first MOS transistor P1 is connected to the source bias voltage VDDC, and the source of the second MOS transistor P2 is connected to the reference voltage VREF. The drain of the first MOS transistor P1 is coupled to the first port D of the coupled inverting unit 403 and one end of the output unit 405. The drain of the second MOS transistor P2 is coupled to the second port DX of the coupled inverting unit 403 and the other end of the output unit 405. The first MOS transistor P1 and the second MOS transistor P2 can be common-gate PMOS transistors.

[0045] The first MOS transistor P1 and the second MOS transistor P2 can be turned on simultaneously under the control of the control signal ABS_ON. After the first MOS transistor P1 and the second MOS transistor P2 are turned on simultaneously, the coupled inverting unit 403 is used to compare the source bias voltage VDDC with the reference voltage VREF.

[0046] As an example, see Figure 4The coupled inverting unit 403 includes a third MOS transistor P3, a fourth MOS transistor P4, a fifth MOS transistor N1, and a sixth MOS transistor N2. The third MOS transistor P3 and the fourth MOS transistor P4 may both be PMOS transistors, and the fifth MOS transistor N1 and the sixth MOS transistor N2 may both be NMOS transistors. The source of the third MOS transistor P3 and the source of the fourth MOS transistor P4 are both connected to the first power supply voltage VDD (VDD is the overall power supply voltage of the static random access memory circuit after power-on) for powering the control circuit 40 and the source bias circuit 20. The source of the fifth MOS transistor N1 is coupled to the source of the sixth MOS transistor N2. The drain of the third MOS transistor P3 is coupled to the drain of the fifth MOS transistor N1 and serves as the first port D of the coupled inverting unit 403. The drain of the fourth MOS transistor P4 is coupled to the drain of the sixth MOS transistor N2 and serves as the second port DX of the coupled inverting unit 403. The gate of the third MOS transistor P3 is coupled to the gate of the fifth MOS transistor N1 and is coupled to the second port DX. The gate of the fourth MOS transistor P4 is coupled to the gate of the sixth MOS transistor N2 and is coupled to the first port D.

[0047] Please refer to Figure 4 The pull-down switch unit 404 is coupled to the source of the fifth MOS transistor N1 and the source of the sixth MOS transistor N2 of the coupled inverting unit 403, and is configured to be turned on under the control of the control signal ABS_ON to provide the second power supply voltage VSS to the coupled inverting unit 403. The pull-down switch unit 404 may include a seventh MOS transistor N3, the gate of which is connected to the control signal ABS_ON, the drain of which is coupled to the source of the fifth MOS transistor N1 and the source of the sixth MOS transistor N2, and the source of which is connected to the second power supply voltage VSS. The second power supply voltage VSS is different from the first power supply voltage VDD and is generally used to achieve grounding of the static random access memory circuit.

[0048] Optionally, when the fifth MOS transistor N1 and the sixth MOS transistor N2 are NMOS transistors, the seventh MOS transistor N3 is also an NMOS transistor, and the second power supply voltage VSS is the ground voltage 0V, that is, the source of the seventh MOS transistor N3 is grounded.

[0049] Please refer to Figure 4 The output unit 405 is coupled to the first port D and the second port DX of the coupled inverting unit 403 , and is configured to output a feedback signal AUTO_SB according to a comparison result of the coupled inverting unit 403 .

[0050] Optional, please continue to refer to Figure 4The output unit 405 includes a first NAND logic circuit nand1, a second NAND logic circuit nand2, and a first inverting logic circuit inv1. A first input terminal (unlabeled) of the first NAND logic circuit nand1 is coupled to the second port DX of the inverting unit 403. A second input terminal (unlabeled) of the first NAND logic circuit nand1 is coupled to the output terminal of the second NAND logic circuit nand2 and the input terminal of the first inverting logic circuit inv1. A first input terminal of the second NAND logic circuit nand2 is coupled to the output terminal of the first NAND logic circuit nand1. A second input terminal of the second NAND logic circuit nand2 is coupled to the first port D of the inverting unit 403. The output terminal of the first inverting logic circuit inv1 is coupled to the source bias circuit 20 to provide a feedback signal AUTO_SB to the source bias circuit 20.

[0051] Among them, the first NAND logic circuit nand1 and the second NAND logic circuit nand2 can be implemented by using NAND gates, or by using any suitable circuit that can implement "NAND" logic. The first inversion logic circuit inv1 can be implemented by using an inverter, or by using any suitable circuit that can implement "inversion" logic. The present invention does not make specific limitations on this.

[0052] Please combine Figure 6 The operating principle of the sense amplifier of this embodiment is as follows: when the control signal ASB_ON is at a low level "0", the first MOS transistor P1 and the second MOS transistor P2 are turned on, transmitting the source bias voltage VDDC and the reference voltage VREF to the first port D and the second port DX of the coupled inverting unit 403. When the control signal ASB_ON is at a high level "1", the first MOS transistor P1 and the second MOS transistor P2 are turned off to prevent noise from affecting the voltage difference change and thus affecting the output result. When VDDC>VREF, the level of the second port DX becomes a low level "0", the level of the first port D becomes a high level "1", and the output feedback signal AUTO_SB becomes a high level "1". Conversely, when VDDC>VREF, the level of the second port DX becomes a low level "0", the level of the first port D becomes a high level "1", and the output feedback signal AUTO_SB becomes a high level "1". <VREF时,第二端口DX的电平变为高电平“1”,第一端口D的电平变为低电平“0”,输出的反馈信号AUTO_SB变为低电平“0”。

[0053] Optional, please refer to Figure 5The source bias circuit 20 includes a second inverting logic circuit inv2 and at least two voltage drop branches with different voltage drop levels. The second inverting logic circuit inv2 is coupled to the output of the control circuit 40, receives the feedback signal AUTO_SB, and outputs an inverted signal AUTO_SBX that is inversely proportional to the feedback signal AUTO_SB. Of all the voltage drop branches, at least one voltage drop branch 201 is coupled to the output of the control circuit 40 and receives the first power supply voltage VDD. Under the control of the feedback signal AUTO_SB, it provides a corresponding voltage drop (i.e., converts the first power supply voltage VDD into a source bias voltage VDDC of a corresponding level before outputting it). At least one other voltage drop branch 202 is coupled to the output of the second inverting logic circuit inv2 and receives the first power supply voltage VDD. Under the control of the inverted signal AUTO_SBX, it provides a corresponding voltage drop (i.e., converts the first power supply voltage VDD into a source bias voltage VDDC of another corresponding level before outputting it).

[0054] The second inverting logic circuit inv2 may be implemented by an inverter, or by any suitable circuit capable of implementing “inverting” logic, and the present invention does not impose any specific limitation on this.

[0055] It should be understood that the magnitude (i.e., the level) of the source bias voltage VDDC ultimately output by the source bias circuit 20 is related to the level of the feedback signal AUTO_SB and the number of voltage drop branches that are turned on under the control of the feedback signal AUTO_SB and the inverted signal AUTO_SBX. The sum of the voltage drops provided by all of the voltage drop branches simultaneously is the source bias voltage VDDC output by the source bias circuit 20. Therefore, the magnitude (i.e., the level) of the source bias voltage VDDC output by the source bias circuit 20 can be adaptively adjusted based on the level of the feedback signal AUTO_SB.

[0056] Optionally, each voltage drop branch in the source bias circuit 20 includes at least two cascaded MOS transistors, and the number of cascaded MOS transistors in the voltage drop branches with different voltage drop degrees is different.

[0057] Taking the source bias circuit 20 as an example, which has two voltage drop branches 201 and 202 with different voltage drops, the voltage drop branch 201 includes two cascaded MOS transistors P11 and P12. The gate of the MOS transistor P11 is connected to the feedback signal AUTO_SB, the source of the MOS transistor P11 is connected to the first power supply voltage VDD, the drain of the MOS transistor P11 is connected to the source of the MOS transistor P12, and the gate and drain of the MOS transistor P12 are connected and connected to the output terminal A of the source bias circuit 20. The voltage drop branch 201 includes three cascaded MOS transistors: P21, P22, and P23. The gate of MOS transistor P21 is connected to the inverted signal AUTO_SBX, the source of MOS transistor P21 is connected to the first power supply voltage VDD, the drain of MOS transistor P21 is connected to the source of MOS transistor P22, the gate and drain of MOS transistor P22 are connected and connected to the source of MOS transistor P23, and the gate and drain of MOS transistor P23 are connected and connected to the output terminal A of the source bias circuit 20. MOS transistors P11, P12, P21, P22, and P23 are all of the same conductivity type, for example, all PMOS transistors. Therefore, the voltage drop branches 201 and 202 are not turned on simultaneously under the control of the mutually inverted signals AUTO_SB and AUTO_SBX.

[0058] Specifically, when the feedback signal AUTO_SB is at a low level "0", the inverting signal AUTO_SBX is at a high level "1", the MOS transistor P11 is turned on, the MOS transistor P21 is turned off (i.e., cut-off), the voltage drop branch 201 is opened, and the voltage drop branch 202 is closed. At this time, the source bias voltage VDDC output by the source bias circuit 20 is the voltage drop provided by the voltage drop branch 201, which is a lower level. When the feedback signal AUTO_SB is at a high level "1", the inverting signal AUTO_SBX is at a low level "0", the MOS transistor P11 is turned off (i.e., cut-off), the MOS transistor P21 is turned on, the voltage drop branch 201 is closed, and the voltage drop branch 202 is opened. At this time, the source bias voltage VDDC output by the source bias circuit 20 is the voltage drop provided by the voltage drop branch 202, which is a higher level.

[0059] It should be noted that after the system enters the sleep mode, the control circuit 40 may be powered off or stop working because the control signal ABS_ON is at a low level, so as to reduce the static power consumption of the system.

[0060] In summary, the static random access memory circuit of this embodiment has a simple structure, requires little additional area, and is easily modularized and standardized. Furthermore, by adding a control circuit to the existing circuit, the control circuit compares the source bias voltage VDDC output by the source bias circuit with the reference voltage VREF under the control of the control signal ABS_ON, and then adaptively adjusts the source bias voltage VDDC output by the source bias circuit based on the comparison result. This dynamically reduces the static power consumption of the SRAM system and ensures data security in the SRAM system. Furthermore, the source bias voltage VDDC can be detected only once each time the SRAM system enters sleep mode, and the power supply to the control circuit 40 can be cut off after entering sleep mode, thereby avoiding unnecessary static power consumption.

[0061] Based on the same inventive concept, an embodiment of the present invention further provides an electronic product comprising the static random access memory circuit of the present invention. Due to the use of the static random access memory circuit of the present invention, the electronic product has low static power consumption.

[0062] It should be noted that in the above-described embodiments, the reference voltage VREF can be provided by any suitable circuit, such as a bandgap reference circuit. Furthermore, the control circuit 40 can also be implemented using other sense amplifier circuits or any other suitable comparison circuit other than a sense amplifier. The source bias circuit 20 can also be implemented using any suitable circuit. The specific structures of the control circuit 40 and the source bias circuit 20 are not limited to those exemplified in the above-described embodiments.

[0063] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of the technical solution of the present invention.

Claims

1. A static random access memory circuit, characterized in that: include: a storage array for storing data; a source bias circuit, coupled to the memory array, for providing a source bias voltage to the memory array; a control circuit coupled to the source bias circuit, configured to compare a source bias voltage output by the source bias circuit with a reference voltage, and output a feedback signal according to a comparison result to control the source bias voltage output by the source bias circuit; The source bias circuit includes at least two voltage drop branches with different voltage drop levels. The sum of the voltage drops provided by all the voltage drop branches at the same time is the source bias voltage provided by the source bias circuit. The source bias circuit adaptively adjusts the number of the voltage drop branches that are turned on within the circuit according to the feedback signal to adaptively adjust the level of the source bias voltage.

2. The static random access memory circuit according to claim 1, wherein: The control circuit includes a sense amplifier.

3. The static random access memory circuit according to claim 2, wherein: The sense amplifier comprises: A first switch unit, configured to be turned on under the control of a control signal to access the source bias voltage; a second switch unit, configured to be turned on under the control of the control signal to access the reference voltage; a coupling inverting unit coupled to the first switch unit and the second switch unit, and configured to compare the source bias voltage with the reference voltage; An output unit is coupled to the coupling inverting unit and is configured to output the feedback signal according to a comparison result of the coupling inverting unit.

4. The static random access memory circuit according to claim 3, wherein: The first switch unit includes a first MOS transistor, and the second switch unit includes a second MOS transistor; the gates of the first MOS transistor and the second MOS transistor are both connected to the control signal, the source of the first MOS transistor is connected to the source bias voltage, and the source of the second MOS transistor is connected to the reference voltage; the drain of the first MOS transistor is coupled to the first port of the coupled inverting unit and one end of the output unit, and the drain of the second MOS transistor is coupled to the second port of the coupled inverting unit and the other end of the output unit.

5. The static random access memory circuit according to claim 3, wherein: The coupled inverting unit includes third to sixth MOS transistors, the source of the third MOS transistor and the source of the fourth MOS transistor are both connected to the first power supply voltage for powering the control circuit, the source of the fifth MOS transistor is coupled to the source of the sixth MOS transistor, the drain of the third MOS transistor is coupled to the drain of the fifth MOS transistor and serves as the first port of the coupled inverting unit, the drain of the fourth MOS transistor is coupled to the drain of the sixth MOS transistor and serves as the second port of the coupled inverting unit, the gate of the third MOS transistor and the gate of the fifth MOS transistor are coupled and coupled to the second port, and the gate of the fourth MOS transistor and the gate of the sixth MOS transistor are coupled and coupled to the first port.

6. The static random access memory circuit according to claim 3, wherein: The output unit includes: a first NAND logic circuit, a second NAND logic circuit, and a first inverting logic circuit; the first input end of the first NAND logic circuit is coupled to the second port of the coupled inverting unit, the second input end of the first NAND logic circuit is coupled to the output end of the second NAND logic circuit and the input end of the first inverting logic circuit; the first input end of the second NAND logic circuit is coupled to the output end of the first NAND logic circuit, the second input end of the second NAND logic circuit is coupled to the first port of the coupled inverting unit; the output end of the first inverting logic circuit is coupled to the source bias circuit.

7. The static random access memory circuit according to any one of claims 3 to 6, wherein: The sense amplifier further includes a pull-down switch unit coupled to the coupling inverting unit and configured to be turned on under the control of the control signal to provide a second power supply voltage to the coupling inverting unit.

8. The static random access memory circuit according to claim 1, wherein: The source bias circuit comprises: a second inverting logic circuit, coupled to the output terminal of the control circuit, configured to receive the feedback signal and output an inverted signal that is inverted to the feedback signal; At least one of the voltage drop branches is coupled to the output end of the control circuit and is used to provide a corresponding degree of voltage drop under the control of the feedback signal. At least another of the voltage drop branches is coupled to the output end of the second inverting logic circuit and is used to provide a corresponding degree of voltage drop under the control of the inverting signal.

9. The static random access memory circuit according to claim 8, wherein: The voltage drop branch includes at least two cascaded MOS transistors, and the number of cascaded MOS transistors in the voltage drop branches with different voltage drop degrees is different.

10. An electronic product, characterized in that: A static random access memory circuit comprising any one of claims 1 to 9.

Images