A power analysis attack resistant unit

Abstract

This invention discloses a power analysis attack resistant unit, which is composed of a first type of MOSFET, a second type of MOSFET, a third type of MOSFET, a fourth type of MOSFET, a fifth type of MOSFET, a second type of first MOSFET, a second type of second MOSFET, a second type of third MOSFET, and a second type of fourth MOSFET. The power analysis attack resistant unit of this invention makes the unit power consumption independent of the read data, inheriting the natural advantage of traditional units in resisting power analysis attacks during read operations. It maintains a low correlation between power consumption and read data, and achieves power consumption balance during data flipping and data retention. Furthermore, because the storage point data is refreshed at the beginning of the write operation, regardless of the initial data stored in the first storage point, power consumption consistency can be guaranteed. In summary, reading and writing any data at the storage point only consumes the energy of a single bit line, thus the overall power consumption of the storage point is also low.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a power consumption analysis attack resistant unit. Background Technology

[0002] Many hardware and software security vulnerabilities often focus on directly stealing confidential information. Side-channel attacks, a type of hardware security attack, primarily involve indirectly stealing information by exploiting unintended information leaks.

[0003] As the name suggests, side-channel attacks do not obtain information by directly stealing it. Instead, they steal information through "backdoor" methods. These side-channel attacks typically include power supply, electromagnetic radiation, and timing attacks. Regarding power supply, all electronic devices are powered via power rails. In power-based side-channel attacks, attackers monitor the device's power rails during operation to obtain current consumption or voltage fluctuations to steal information.

[0004] Most current anti-power analysis attack units employ a method of shielding the power supply and internal storage nodes before a write operation. They then reduce the correlation between stored data and power consumption by shorting the internal storage nodes to balance the voltage at those nodes to VDD / 2. However, this presents a problem: balancing the voltage at the internal storage nodes typically involves shielding the storage nodes from the power supply. This means that when the internal storage nodes are shorted, their voltage may deviate from VDD / 2, thus compromising the unit's anti-power analysis attack capabilities and creating a potential information leakage risk. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a power analysis attack resistant unit to solve the problem that the prior art's method of shielding the connection between the storage node and the power supply to resist power analysis attacks is prone to causing the balanced voltage of the storage node inside the unit to deviate from VDD / 2 when short-circuited, which will destroy the unit's power analysis attack resistant function.

[0006] To achieve the above and other related objectives, the present invention provides a power consumption analysis attack resistant unit, comprising:

[0007] Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class II MOSFET; Class II MOSFET; Class II MOSFET; Class II MOSFET; Class II MOSFET; Class II MOSFET;

[0008] The source of the first type of MOS transistor is connected to the first bit line, the gate of the first type of MOS transistor is connected to the write word line signal, the drain of the first type of MOS transistor is connected to the gate of the second type of MOS transistor, the gate of the third type of MOS transistor, and the drain of the second type of MOS transistor, the source of the second type of MOS transistor is connected to the source of the second type of MOS transistor and connected to the power supply terminal, the gate of the second type of MOS transistor is connected to the write control signal, the source of the second type of MOS transistor is connected to the gate of the second type of MOS transistor, the drain of the second type of MOS transistor and the source of the third type of MOS transistor form a second memory node, the drain of the second type of MOS transistor is connected to the gate of the third type of MOS transistor, the drain of the second type of MOS transistor and the drain of the second type of MOS transistor form a first memory point, and the drain of the third type of MOS transistor is connected to the ground terminal.

[0009] The source of the second type third MOS transistor is connected to the second bit line. The gate of the second type third MOS transistor is connected to the drain of the second type first MOS transistor, the source of the first type third MOS transistor, and the second storage point. The drain of the second type third MOS transistor is connected to the source of the first type fourth MOS transistor. The gate of the first type fourth MOS transistor is connected to the read word line signal. The drain of the first type fourth MOS transistor is connected to the drain of the second type fourth MOS transistor and connected to the ground terminal. The gate of the second type fourth MOS transistor is connected to the second storage point. The source of the second type fourth MOS transistor is connected to the drain of the first type fifth MOS transistor. The gate of the first type fifth MOS transistor is connected to the read control signal. The source of the first type fifth MOS transistor is connected to the first bit line.

[0010] In an optional embodiment, when entering a read operation, both the first bit line and the second bit line are charged to a high level, and the read word line and the read control signal are enabled.

[0011] In one optional embodiment, during the read operation, one of the first bit line and the second bit line is always pulled down to a low level, while the other bit line remains at a high level.

[0012] In an optional embodiment, when the write operation section is initially powered on, the data in the first storage point is pulled high to "1", and the data in the second storage point is pulled down to "0".

[0013] In one alternative embodiment, when a write operation is initiated, the written data is synchronized to the first bit line, and the second bit line is always pulled high.

[0014] In one alternative embodiment, at the start of the write operation, a write control signal is enabled, and the write word line is kept low.

[0015] In one alternative embodiment, after the write operation begins, the write control signal remains low, the write word line signal is enabled, and the read word line signal is enabled after the write word line signal is enabled.

[0016] In an optional embodiment, the first type of MOS transistor, the second type of MOS transistor, the third type of MOS transistor, the fourth type of MOS transistor, the fifth type of MOS transistor, and the sixth type of MOS transistor are all NMOS transistors.

[0017] In an optional embodiment, the second type of first MOS transistor, the second type of second MOS transistor, and the third type of second MOS transistor are all PMOS transistors.

[0018] The anti-power analysis attack unit of this invention is composed of a first type of MOSFET, a second type of MOSFET, a third type of MOSFET, a fourth type of MOSFET, a fifth type of MOSFET, a second type of first MOSFET, a second type of second MOSFET, a third type of second MOSFET, and a fourth type of fourth MOSFET. In the read operation state, when reading different data, it can ensure that one bit line is pulled down to ground while the other bit line remains at a high level. This makes the power consumption of the storage point independent of the read data, inheriting the natural advantage of traditional units in resisting power attacks during read operations and maintaining a low correlation between power consumption and read data. In the write operation state, it can achieve power consumption balance during data flipping and data retention. Furthermore, since the storage point data is refreshed at the beginning of the write operation, regardless of the initial data stored in the first storage point, the consistency of power consumption can be guaranteed. In addition, when reading or writing any data, the storage point only consumes the energy of a single bit line, so the overall power consumption of the storage point is also low. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the anti-power analysis attack unit provided in an embodiment of the present invention.

[0020] Figure 2 This is a timing diagram of the write operation of the anti-power analysis attack unit provided in an embodiment of the present invention;

[0021] Figure 3 The above is a simulation waveform diagram of the write operation of the anti-power analysis attack unit provided in the embodiment of the present invention. Detailed Implementation

[0022] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] Please see Figure 1-3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] like Figure 1 As shown, this embodiment provides a power analysis attack resistant unit, specifically a unit circuit structure that improves the unit's resistance to power analysis attacks. This power analysis attack resistant unit includes: a first type of MOSFET; a second type of MOSFET; a third type of MOSFET; a fourth type of MOSFET; a fifth type of MOSFET; a second type of first MOSFET; a second type of second MOSFET; a second type of third MOSFET; and a second type of fourth MOSFET.

[0025] The source of a first-class MOSFET is connected to the first bit line, the gate of a first-class MOSFET is connected to the write word line signal, the drain of a first-class MOSFET is connected to the gate of a second-class MOSFET, the gate of a third-class MOSFET, and the drain of a second-class MOSFET, the source of a first-class MOSFET is connected to the source of a second-class MOSFET and connected to the power supply terminal, the gate of a second-class MOSFET is connected to the write control signal, the source of a second-class MOSFET is connected to the gate of a second-class MOSFET, the drain of a first-class MOSFET and the source of a third-class MOSFET form a second memory node, the drain of a second-class MOSFET is connected to the gate of a third-class MOSFET, the drain of a second-class MOSFET and the drain of a second-class MOSFET form a first memory point, and the drain of a third-class MOSFET is connected to the ground terminal.

[0026] The source of the Class II third MOSFET is connected to the second bit line. The gate of the Class II third MOSFET is connected to the drain of the Class II first MOSFET, the source of the Class I third MOSFET, and the second memory point. The drain of the Class II third MOSFET is connected to the source of the Class I fourth MOSFET. The gate of the Class I fourth MOSFET is connected to the read word line signal. The drain of the Class I fourth MOSFET is connected to the drain of the Class II fourth MOSFET and connected to the ground terminal. The gate of the Class II fourth MOSFET is connected to the second memory point. The source of the Class II fourth MOSFET is connected to the drain of the Class I fifth MOSFET. The gate of the Class I fifth MOSFET is connected to the read control signal. The source of the Class I fifth MOSFET is connected to the first bit line.

[0027] In an optional embodiment, the first type of MOS transistor, the second type of MOS transistor, the third type of MOS transistor, the fourth type of MOS transistor, and the fifth type of MOS transistor are all NMOS transistors, that is, the first type of MOS transistor is the first NMOS transistor, the second type of MOS transistor is the second NMOS transistor, the third type of MOS transistor is the third NMOS transistor, the fourth type of MOS transistor is the fourth NMOS transistor, and the fifth type of MOS transistor is the fifth NMOS transistor.

[0028] In an optional embodiment, the second type of first MOS transistor, the second type of second MOS transistor, the third type of second MOS transistor, and the fourth type of second MOS transistor are all PMOS transistors, that is, the second type of first MOS transistor is a first PMOS transistor, the second type of second MOS transistor is a second PMOS transistor, the third type of second MOS transistor is a third PMOS transistor, and the fourth type of second MOS transistor is a fourth PMOS transistor.

[0029] Specific examples Figure 1 The image shows an SRAM cell resistant to power consumption analysis attacks, where the write word line signal is denoted as WWL, the read word line signal as RWL, the first bit line as BL, and the second bit line as... The first storage point is denoted as Q, and the second storage point is denoted as... The first NMOS transistor is designated M1, the second NMOS transistor is designated M2, the third NMOS transistor is designated M4, the fourth NMOS transistor is designated M7, the fifth NMOS transistor is designated M9, the first PMOS transistor is designated M3, the second PMOS transistor is designated M5, the third PMOS transistor is designated M6, the fourth PMOS transistor is designated M8, the power supply terminal is designated VDD, and the ground terminal is designated GND.

[0030] The SRAM cell includes: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M4, a fourth NMOS transistor M7, a fifth NMOS transistor M9, a first PMOS transistor M3, a second PMOS transistor M5, a third PMOS transistor M6, and a fourth PMOS transistor M8, wherein the first NMOS transistor M1 is a transmission transistor.

[0031] The source of the first NMOS transistor M1 is connected to the first bit line BL, and the gate of the first NMOS transistor M1 is connected to the write word line signal WWL. The drain of the first NMOS transistor M1 is connected to the gate of the first PMOS transistor M3, the gate of the third NMOS transistor M4, and the drain of the second PMOS transistor M5. The source of the first PMOS transistor M3 is connected to the source of the second PMOS transistor and connected to the power supply terminal VDD. The gate of the second NMOS transistor M2 is connected to the WRITE signal. The source of the second NMOS transistor M2, together with the gate of the second PMOS transistor M5, the drain of the first PMOS transistor M3, and the source of the third NMOS transistor M4, forms the second memory point. The drain of the second NMOS transistor M2 is connected to the gate of the third NMOS transistor M4. The drain of the second NMOS transistor M2 and the drain of the second PMOS transistor M5 form the first storage point Q. The drain of the third NMOS transistor M4 is connected to the ground terminal GND.

[0032] The source of the third PMOS transistor M6 is connected to the second bit line. The gate of the third PMOS transistor M6 is connected to the drain of the first PMOS transistor M3, the source of the third NMOS transistor M4, and the second storage point. The drain of the third PMOS transistor M6 is connected to the source of the fourth NMOS transistor M7. The gate of the fourth NMOS transistor M7 is connected to the read word line RWL signal. The drain of the fourth NMOS transistor M7 is connected to the drain of the fourth PMOS transistor M8 and connected to the ground terminal GND. The gate of the fourth PMOS transistor M8 is connected to the second storage point. The source of the fourth PMOS transistor M8 is connected to the drain of the fifth NMOS transistor M9. The gate of the fifth NMOS transistor M9 is connected to the READ signal, and the source of the fifth NMOS transistor M9 is connected to the first bit line BL.

[0033] The specific principle of the SRAM cell resisting power consumption analysis attacks provided by this invention is as follows:

[0034] Read operation:

[0035] When entering a read operation: the first bit line BL and the second bit line Both are charged to a high level, enabling the read word line RWL and the READ signal.

[0036] When the data stored at the first storage point Q is '1', the third PMOS transistor M6 is turned on, the fourth PMOS transistor M8 is turned off, and the second bit line... The first bit line BL is pulled down to ground through the third PMOS transistor M6 and the fourth NMOS transistor M7, keeping it high and thus reading the data '1'. When the data stored at the first storage point Q is '0', the third PMOS transistor M6 is turned off, the fourth PMOS transistor M8 is turned on, and the first bit line BL is pulled down to ground through the fourth PMOS transistor M8 and the fifth NMOS transistor M9. Keep it high to read the data '0'.

[0037] Write operation:

[0038] Due to the asymmetry of memory cells, each memory cell has a fixed internal voltage level when powered on. Specifically, initially, the first memory point Q is pulled high to '1', and the second memory point... It will simultaneously drop down to '0'.

[0039] When entering a write operation: the data to be written is synchronized to the first bit line (BL), while the second bit line... The WRITE signal is always pulled high. At the start of a write operation, the WRITE signal is briefly enabled while the write word line WWL remains low, causing the data inside the first storage point Q to be refreshed.

[0040] During the remaining stages of the write operation: the WRITE signal remains low, turning on the second NMOS transistor M2. At this time, the write word line WWL signal is enabled, and the read word line RWL signal is enabled slightly later, that is, the read word line RWL is enabled after the write word line WWL is enabled, and the data is written to the first storage point Q.

[0041] If the data to be written is '0', the first bit line BL is pulled low, and the second bit line... When charged to a high level, the first storage point Q discharges through the first bit line BL, causing the potential of the first storage point Q to go high, resulting in a data flip and rewriting the data to '0'. Meanwhile, the second storage point... At this time, it is '1', the third PMOS transistor M6 is turned off, and the second bit line... The energy on it is not consumed.

[0042] If the data to be written is '1', the first bit line BL and the second bit line... Both are pulled high. At this time, since the first storage point Q and the first bit line BL are both at a high potential, the data is retained and no charge transfer occurs. At the same time, the second storage point... Setting it to '0' turns on the third PMOS transistor M6, thus enabling the second bit line... By discharging the third PMOS transistor M6 and the fourth NMOS transistor M7, data flipping is simulated, thereby achieving a power consumption balance between data flipping and data holding.

[0043] Most current anti-power analysis attack units employ the method of connecting the power supply to the first storage point Q and the second storage point within the unit before the write operation. Shield it, and then short-circuit the first storage point Q and the second storage point. By balancing internal storage nodes to VDD / 2, the correlation between cell storage data and cell power consumption is reduced. This is achieved by balancing the first storage point Q and the second storage point within the cell. In this case, the first storage point Q and the second storage point are usually disabled. This method, related to the power supply, will cause a short circuit between the first storage point Q and the second storage point. At that time, the first storage point Q and the second storage point The balance voltage is likely to deviate from VDD / 2 (usually less than VDD / 2), which undermines the cell's ability to resist power consumption analysis attacks, thus creating a potential information leakage risk.

[0044] In this embodiment, during the read operation phase, one bit line is always pulled down to ground while the other bit line remains at a high level. During operation, the unit power consumption is independent of the read data, avoiding the direct acquisition of information from power consumption changes. This inherits the natural advantage of traditional units in resisting power analysis attacks during read operations and maintains a low correlation between power consumption and read data.

[0045] Furthermore, this embodiment can simulate data flipping during the write operation phase, thereby achieving a power consumption balance between data flipping and data retention. Also, since the data at the storage point is refreshed at the beginning of the write operation, the consistency of power consumption can be guaranteed regardless of what the initial data stored at the first storage point Q is.

[0046] Furthermore, considering both the first storage point Q and the second storage point... Reading or writing any data consumes the energy of only a single bit line, resulting in low overall power consumption for the cell.

[0047] Figure 3 This is a simulation waveform diagram of the write operation of the anti-power analysis attack unit provided in this embodiment. Figure 2 This is a timing diagram of the anti-power analysis attack unit provided in this embodiment, while Table 1 shows the power consumption changes of conventional SRAM and anti-power analysis attack SRAM in data flip-flop and data hold states:

[0048] Traditional SRAM SRAM resistant to power analysis attacks Data flip state power consumption / pw 78.9 35.7 Data retention power consumption / pw 6.4 34.3

[0049] Table 1. Power consumption comparison between traditional SRAM and SRAM resistant to power analysis attacks.

[0050] As can be seen from the table, compared to the huge power consumption difference between data flip and data hold states when writing data in traditional SRAM, the power consumption difference between the two states in the SRAM resistant to power analysis attacks is very small. That is, the power consumption balance of the SRAM resistant to power analysis attacks during data flip and data hold can effectively ensure the consistency of power consumption during write operations and reduce the correlation between power consumption changes and write data operations.

[0051] The formula for calculating power consumption and potential energy in this embodiment is: (Where U and I represent the voltage and current at the power supply terminal VDD, respectively)

[0052] Throughout this description, numerous specific details, such as examples of components and / or methods, are provided to provide a complete understanding of embodiments of the invention. However, those skilled in the art will recognize that embodiments of the invention may be practiced without one or more of these specific details or by other devices, systems, components, methods, parts, materials, components, etc. In other instances, well-known structures, materials, or operations have not been specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

[0053] It should also be understood that one or more of the elements shown in the figures may be implemented in a more separate or more integrated manner, or may even be removed because they are inoperable in certain circumstances or provided because they may be useful for a particular application.

[0054] Furthermore, unless otherwise expressly stated, any arrows in the accompanying drawings should be considered illustrative only and not limiting. Additionally, unless otherwise stated, the term "or" as used herein is generally intended to mean "and / or". Where a term is anticipated to provide a separation or combination capability that is unclear, a combination of components or steps will also be considered as indicated.

[0055] The above description of the embodiments shown in this invention (including the content set forth in the abstract of the specification) is not intended to be an exhaustive enumeration or to limit the invention to the precise forms disclosed herein. Although specific embodiments and examples of the invention have been described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the invention, as will be recognized and understood by those skilled in the art. As indicated, these modifications can be made to the invention in accordance with the above description of the embodiments described herein, and such modifications will be within the spirit and scope of the invention.

[0056] This document has generally described the systems and methods in detail to aid in understanding the invention. Furthermore, various specific details have been set forth to provide a general understanding of embodiments of the invention. However, those skilled in the art will recognize that embodiments of the invention can be practiced without one or more specific details, or using other means, systems, accessories, methods, components, materials, parts, etc. In other instances, well-known structures, materials, and / or operations have not been specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

[0057] Therefore, although the invention has been described herein with reference to specific embodiments thereof, freedom of modification, various changes and substitutions are also within the scope of the foregoing disclosure, and it should be understood that in some cases, certain features of the invention may be adopted without departing from the scope and spirit of the invention and without corresponding use of other features. Thus, many modifications can be made to adapt a particular environment or material to the essential scope and spirit of the invention. The invention is not intended to be limited to the specific terminology used in the following claims and / or the specific embodiments disclosed as the best mode for carrying out the invention, but the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Therefore, the scope of the invention will be defined only by the appended claims.

Claims

1. A power consumption analysis attack resistant unit, characterized in that, include: Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class I MOSFET; Class II MOSFET; Class II MOSFET; Class II MOSFET; Class II MOSFET; Class II MOSFET; Class II MOSFET; The source of the first type of MOS transistor is connected to the first bit line, the gate of the first type of MOS transistor is connected to the write word line signal, the drain of the first type of MOS transistor is connected to the gate of the second type of MOS transistor, the gate of the third type of MOS transistor, and the drain of the second type of MOS transistor, the source of the second type of MOS transistor is connected to the source of the second type of MOS transistor and connected to the power supply terminal, the gate of the second type of MOS transistor is connected to the write control signal, the source of the second type of MOS transistor is connected to the gate of the second type of MOS transistor, the drain of the second type of MOS transistor and the source of the third type of MOS transistor form a second memory node, the drain of the second type of MOS transistor is connected to the gate of the third type of MOS transistor, the drain of the second type of MOS transistor and the drain of the second type of MOS transistor form a first memory point, and the drain of the third type of MOS transistor is connected to the ground terminal. The source of the second type third MOS transistor is connected to the second bit line. The gate of the second type third MOS transistor is connected to the drain of the second type first MOS transistor, the source of the first type third MOS transistor, and the second storage point. The drain of the second type third MOS transistor is connected to the source of the first type fourth MOS transistor. The gate of the first type fourth MOS transistor is connected to the read word line signal. The drain of the first type fourth MOS transistor is connected to the drain of the second type fourth MOS transistor and connected to the ground terminal. The gate of the second type fourth MOS transistor is connected to the second storage point. The source of the second type fourth MOS transistor is connected to the drain of the first type fifth MOS transistor. The gate of the first type fifth MOS transistor is connected to the read control signal. The source of the first type fifth MOS transistor is connected to the first bit line.

2. The anti-power analysis attack unit according to claim 1, characterized in that, The first type of MOS transistor is a transmission transistor.

3. The anti-power analysis attack unit according to claim 1, characterized in that, When entering a read operation, both the first bit line and the second bit line are charged to a high level, and the read word line and the read control signal are enabled.

4. The anti-power analysis attack unit according to claim 3, characterized in that, During the read operation, one of the first and second bit lines is always pulled down to a low level, while the other bit line remains at a high level.

5. The anti-power analysis attack unit according to claim 1, characterized in that, When the write operation section is initially powered on, the data in the first storage point is pulled high to "1", and the data in the second storage point is pulled down to "0".

6. The anti-power analysis attack unit according to claim 5, characterized in that, When entering a write operation, the written data is synchronized to the first bit line, and the second bit line is always pulled high.

7. The anti-power analysis attack unit according to claim 6, characterized in that, At the start of the write operation, the write control signal is enabled, and the write word line is kept low.

8. The anti-power analysis attack unit according to claim 7, characterized in that, After the write operation begins, the write control signal remains low, the write word line signal is enabled, and the read word line signal is enabled after the write word line signal is enabled.

9. The anti-power analysis attack unit according to claim 1, characterized in that, The first type of MOS transistor, the second type of MOS transistor, the third type of MOS transistor, the fourth type of MOS transistor, and the fifth type of MOS transistor are all NMOS transistors.

10. The anti-power analysis attack unit according to claim 1, characterized in that, The first type of MOS transistor, the second type of MOS transistor, the third type of MOS transistor, and the fourth type of MOS transistor are all PMOS transistors.

Images