Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes providing a substrate, forming an opening in the substrate, performing a plasma treatment on sidewall surfaces and bottom surfaces of the opening, and forming a fill layer filling the opening after the plasma treatment on the sidewall surfaces and the bottom surfaces of the opening. The semiconductor structure formed by the method has improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] The market demands increasingly higher resolution from image sensors, making high-resolution pixel patterning a crucial technology for them.

[0003] In the image sensor manufacturing process, a pixel definition layer (PDL, or Bank) needs to be prepared. The commonly used Bank preparation process uses photolithography, which uses exposure and development processes to form pixel grooves with uniform depth and basically fixed shape, which are used as "containers" to hold pixel materials.

[0004] However, as resolution increases, the size of each pixel decreases accordingly. To meet the requirements of high-resolution image sensors, the pixel structure still needs improvement and development. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of pixel structures.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an opening in the substrate; performing plasma treatment on the sidewall surface and bottom surface of the opening; and after performing plasma treatment on the sidewall surface and bottom surface of the opening, forming a filling layer that fills the opening.

[0007] Optionally, the plasma treatment method includes: repeating a first-stage treatment and a second-stage treatment after the first-stage treatment several times, wherein the first-stage treatment has a first bias voltage, the second-stage treatment has a second bias voltage, and the first bias voltage and the second bias voltage are opposite.

[0008] Optionally, the first bias voltage is a positive bias voltage, and the second bias voltage is a negative bias voltage; the ratio of the processing time of the first stage to the processing time of the second stage is in the range of 1:0.1 to 1:10.

[0009] Optionally, the absolute value of the first bias voltage ranges from 200V to 2000V; the absolute value of the second bias voltage ranges from 200V to 2000V.

[0010] Optionally, the process parameters for plasma treatment include: a gas source comprising a mixture of hydrogen and chlorine, hydrogen bromide, or hydrogen chloride; a gas flow rate ranging from 10 standard milliliters per minute to 1000 standard milliliters per minute; a pressure range of less than 300 millitors; and a power range of 100 watts to 3000 watts.

[0011] Optionally, the aspect ratio of the opening is greater than 5:1.

[0012] Optionally, the aspect ratio of the opening is in the range of 30:1 to 40:1.

[0013] Optionally, the range of the opening spacing is: greater than 0 and less than or equal to 2 micrometers.

[0014] Optionally, the method of forming an opening in a substrate includes: forming a patterned mask structure on the substrate, the patterned mask structure exposing a portion of the substrate surface; and etching the substrate using the patterned mask structure as a mask to form the opening.

[0015] Optionally, the patterned mask structure includes a hard mask layer and a photoresist layer located on the hard mask layer.

[0016] Optionally, the etching process for the substrate includes a dry etching process, wherein the etching gas in the dry etching process includes a fluorocarbon gas.

[0017] Optionally, when etching the substrate with the patterned mask structure to form the opening, reaction byproducts are also formed on the sidewall surface and bottom surface of the opening.

[0018] Optionally, the materials of the reaction byproducts include carbon-containing polymers.

[0019] Optionally, after the opening is formed, before plasma treatment of the sidewall and bottom surfaces of the opening, the process further includes removing the photoresist layer.

[0020] Optionally, the process for removing the photoresist layer includes a wet etching process; the etching solution in the wet etching process includes an acidic solution.

[0021] Optionally, the filling layer is formed by a deposition process.

[0022] Optionally, the deposition process includes repeating a deposition stage several times and an etching stage following the deposition stage.

[0023] Optionally, the material of the filling layer includes: phosphosilicate or borosilicate.

[0024] Optionally, the deposition stage is a selective epitaxial deposition process; the process parameters of the deposition stage include: the gas includes hydrogen, hydrogen chloride and dichlorosilane, and one of borane and phosphine; the pressure range is less than 30 Torr; and the temperature range is 750 degrees Celsius to 900 degrees Celsius.

[0025] Optionally, the process parameters for the etching stage include: the etching gas is hydrogen chloride.

[0026] Optionally, the material of the filling layer includes: dielectric material or metal.

[0027] Optionally, after forming the filler layer, the method further includes forming a lens on the filler layer.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] The technical solution of this invention involves plasma treatment of the sidewall and bottom surfaces of the opening. This plasma treatment, when the opening has a large depth-to-width ratio, allows the plasma to more easily penetrate to the bottom of the opening, thereby facilitating the removal of reaction byproducts adhering to the inner wall surface of the opening. Thorough removal of reaction byproducts from the inner wall surface ensures a tight bond between the filling layer and the sidewall and bottom surfaces of the opening when a filling layer is formed inside the opening. This results in a dense filling layer material with fewer defects, thus improving the quality of the filling layer.

[0030] Furthermore, the gas source for the plasma treatment process includes a mixture of hydrogen and chlorine, hydrogen bromide, or hydrogen chloride. The hydrogen ions remove the native oxide layer from the surface of the opening sidewalls and the bottom surface, while the chloride or bromide ions remove reaction byproducts from the surface of the opening sidewalls and the bottom surface. The plasma treatment process simultaneously incorporates hydrogen and chloride ions, or simultaneously incorporates hydrogen and bromide ions, thus enabling the removal of both the native oxide layer and reaction byproducts in a single process, thereby improving production efficiency.

[0031] Furthermore, the plasma treatment method includes: repeating a first-stage treatment and a second-stage treatment several times, wherein the first-stage treatment has a first bias voltage, the second-stage treatment has a second bias voltage, and the first and second bias voltages are opposite. Thus, the positive bias voltage in the first and second bias voltages can attract chloride and bromide ions to the bottom of the opening, and the negative bias voltage in the first and second bias voltages can attract hydrogen ions to the bottom of the opening. The alternation of positive and negative bias voltages can attract both positive and negative ions of the reaction to the bottom of the opening, allowing the hydrogen ions to remove the native oxide layer at the bottom of the opening, and the chloride and bromide ions to remove reaction byproducts at the bottom of the opening, thereby achieving a cleaning effect and solving the problem that the reaction gas has difficulty reaching the bottom of the opening due to its large depth-to-width ratio. Attached Figure Description

[0032] Figure 1 and Figure 2 One is a cross-sectional structural schematic diagram of the semiconductor structure formation process in the embodiment;

[0033] Figures 3 to 11 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0034] As described in the background section, existing pixel structures still require improvement and development. This will now be analyzed and explained in conjunction with specific embodiments.

[0035] Figure 1 and Figure 2 One is a cross-sectional structural schematic diagram of the semiconductor structure formation process in the embodiment.

[0036] Please refer to Figure 1 This includes: providing a substrate 100; and forming a plurality of openings 101 within the substrate 100.

[0037] Please refer to Figure 2 A pixel structure 103 is formed by epitaxial growth inside and outside the opening 101.

[0038] During the formation of the semiconductor structure, after the opening 101 is formed, a cleaning process is used to remove the reaction byproduct 102 and the native oxide layer on the sidewall surface of the opening 101. Typically, the native oxide layer on the sidewall surface of the opening 101 is removed using the SICONI process, and the reaction byproduct 102 is removed using a dry etching process containing hydrogen chloride gas.

[0039] However, as semiconductor structure dimensions become smaller, the aspect ratio of the opening 101 becomes larger. Due to the depth of the opening 101, the SICONI process and the hydrogen chloride-containing dry etching process have difficulty penetrating to the bottom of the opening 101. Therefore, the removal effect on the natural oxide layer and reaction byproducts 102 on the sidewall surface of the opening 101 is poor, resulting in byproducts 102 remaining on the inner wall of the opening 101. This subsequently affects the pixel structure 103 formed within the opening 101, causing the pixel structure 103 to have internal holes 104 and poor quality.

[0040] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure by performing plasma treatment on the sidewall and bottom surfaces of the opening. This plasma treatment, even with a large depth-to-width ratio, allows plasma to more easily penetrate the bottom of the opening, thereby facilitating the removal of reaction byproducts adhering to the inner wall surface of the opening. Thorough removal of reaction byproducts from the inner wall surface ensures a tight bond between the filling layer and the sidewall and bottom surfaces of the opening when a filling layer is formed within the opening. This results in a dense filling layer material with fewer defects, thus improving the quality of the filling layer.

[0041] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] Figures 3 to 11 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0043] Please refer to Figure 3 Substrate 200 is provided.

[0044] In this embodiment, the substrate 200 is made of silicon.

[0045] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0046] Please refer to Figure 4 An opening 203 is formed within the substrate 200.

[0047] The method of forming an opening 203 in a substrate 200 includes: forming a patterned mask structure on the substrate 200, the patterned mask structure exposing a portion of the surface of the substrate 200; and etching the substrate 200 using the patterned mask structure 200 as a mask to form the opening 203.

[0048] The patterned mask structure includes a hard mask layer 201 and a photoresist layer 202 located on the hard mask layer 201.

[0049] The hard mask layer 201 serves as a backing for the photoresist layer 202, preventing the morphology and dimensional accuracy of the formed opening 203 from being affected when the photoresist layer 202 is consumed too quickly during the etching process and the etching is not yet complete.

[0050] The method for forming the mask structure includes: forming a hard mask material layer (not shown) on a substrate 200; forming a patterned photoresist layer 202 on the hard mask material layer; etching the hard mask material layer using the patterned photoresist layer 202 as a mask until the surface of the substrate 200 is exposed to form a hard mask layer 201, wherein the hard mask layer 201 and the photoresist layer 202 constitute the mask structure.

[0051] The material of the hard mask layer 201 includes a dielectric material, which includes silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0052] The process for forming the hard mask material layer includes chemical vapor deposition or atomic layer deposition; the process for forming the photoresist layer 202 includes spin coating, exposure and development.

[0053] In this embodiment, the etching process of the substrate 200 includes a dry etching process, and the etching gas in the dry etching process includes a fluorocarbon gas. The dry etching process can obtain an opening 203 with good dimensional accuracy and a smooth sidewall surface.

[0054] The aspect ratio of the opening 203 is greater than 5:1. The large aspect ratio of the opening 203 makes it difficult to remove reaction byproducts within the opening 203.

[0055] In this embodiment, the aspect ratio of the opening 203 is in the range of 30:1 to 40:1. The spacing between the openings 203 is greater than 0 and less than or equal to 2 micrometers, to meet the requirements of smaller-sized devices.

[0056] Please continue to refer to this. Figure 4 When the substrate 200 is etched with the patterned mask structure to form the opening 203, reaction byproducts 204 are also formed on the sidewall surface and bottom surface of the opening 203.

[0057] The reaction byproduct 204 comprises a carbon-containing polymer. The carbon-containing polymer comprises a mixture of photoresist and substrate 200 material, as well as a reaction mixture of fluorocarbon gas and substrate 200 material.

[0058] The reaction byproduct 204 inside the opening 203 needs to be removed to avoid affecting the quality of the filling layer subsequently formed inside the opening 203, which in turn affects the performance of the device.

[0059] Please refer to Figure 5 Remove the photoresist layer 202.

[0060] In this embodiment, the process for removing the photoresist layer 202 includes a wet etching process; the etching solution in the wet etching process includes an acidic solution, which includes a sulfuric acid solution or a hydrogen peroxide solution.

[0061] After removing the photoresist layer 202, and before performing plasma treatment on the sidewall and bottom surfaces of the opening 203, the semiconductor structure needs to be transferred to a cavity, which inevitably exposes the semiconductor structure to air. The substrate 200 is made of silicon, and thus a natural oxide layer (not shown) is formed on the sidewall and bottom surfaces of the opening 203.

[0062] Please refer to Figure 6 The sidewall and bottom surfaces of the opening 203 are subjected to plasma treatment.

[0063] The gas source for the plasma treatment process includes a mixture of hydrogen and chlorine, hydrogen bromide, or hydrogen chloride. The plasma ionizes the gas source into hydrogen and chloride ions, or hydrogen and bromide ions. The hydrogen ions remove the natural oxide layer from the sidewall and bottom surfaces of the opening 203, while the chloride or bromide ions remove the reaction byproduct 204 from the sidewall and bottom surfaces of the opening 203. The plasma treatment process simultaneously incorporates hydrogen and chloride ions, or simultaneously incorporates hydrogen and bromide ions, thus enabling the simultaneous removal of both the natural oxide layer and the reaction byproduct 204 in a single process, thereby improving production efficiency.

[0064] In this embodiment, the gas source for the plasma processing technology includes hydrogen chloride gas.

[0065] In this embodiment, the plasma treatment method includes: repeating a first-stage treatment and a second-stage treatment after the first-stage treatment several times, wherein the first-stage treatment has a first bias voltage, the second-stage treatment has a second bias voltage, and the first bias voltage and the second bias voltage are opposite.

[0066] Therefore, the positive bias in the first and second bias voltages can attract chloride or bromide ions to the bottom of opening 203, and the negative bias in the first and second bias voltages can attract hydrogen ions to the bottom of opening 203. The alternation of positive and negative bias voltages attracts both positive and negative ions to the bottom of opening 203, allowing the hydrogen ions to remove the native oxide layer at the bottom of opening 203, and the chloride or bromide ions to remove the reaction byproduct 204 at the bottom of opening 203, thus achieving a cleaning effect and solving the problem that the reaction gas has difficulty reaching the bottom of opening 203 due to its large depth-to-width ratio. Therefore, the plasma treatment has a better cleaning effect on the inner wall of opening 203, and is less likely to result in difficulty cleaning the bottom of opening 203 due to its large depth-to-width ratio.

[0067] In this embodiment, the first bias voltage is a positive bias voltage, and the second bias voltage is a negative bias voltage; the ratio of the processing time in the first stage to the processing time in the second stage is between 1:0.1 and 1:10. Therefore, the first and second bias voltages in the plasma treatment have a good alternation, which can efficiently and quickly remove the natural oxide layer and reaction byproducts 204 at the bottom of the opening 203, achieving a better cleaning effect.

[0068] In this embodiment, the absolute value of the first bias voltage ranges from 200V to 2000V; the absolute value of the second bias voltage ranges from 200V to 2000V.

[0069] In this embodiment, the process parameters for plasma treatment include: a gas source comprising a mixture of hydrogen and chlorine, hydrogen bromide, or hydrogen chloride; a gas flow rate ranging from 10 standard milliliters per minute to 1000 standard milliliters per minute; a pressure range of less than 300 millitors; and a power range of 100 watts to 3000 watts. The plasma treatment process under these parameters exhibits excellent cleaning performance, efficiently and rapidly removing the natural oxide layer and reaction byproducts 204 from the bottom of the high aspect ratio opening 203.

[0070] Next, a filling layer 208 is formed within the opening 203 to completely fill it. The formation process of the filling layer 208 is described in [reference needed]. Figures 7 to 10 .

[0071] In this embodiment, the material of the filling layer 208 includes: silicon phosphide or silicon borosilicate.

[0072] The filling layer 208 is formed by a deposition process.

[0073] The deposition process includes repeating a deposition stage several times and an etching stage following the deposition stage.

[0074] In other embodiments, the material of the filling layer includes a dielectric material or a metal.

[0075] Please refer to Figure 7 , Figure 7 During the deposition stage, a first initial material layer 205 is formed on the sidewall surface, bottom surface, and hard mask layer 201 of the opening 203.

[0076] The deposition stage is a selective epitaxial deposition process.

[0077] When the material of the filler layer 208 includes silicon phosphide, the process parameters of the deposition stage include: the gas includes hydrogen, hydrogen chloride, silicon dichlorosilane, and phosphine; the pressure range is less than 30 Torr; and the temperature range is 750 degrees Celsius to 900 degrees Celsius.

[0078] When the material of the filler layer 208 includes borosilicate, the process parameters of the deposition stage include: the gas includes hydrogen, hydrogen chloride, dichlorosilane and borane; the pressure range is less than 30 Torr; and the temperature range is 750 degrees Celsius to 900 degrees Celsius.

[0079] Since the reactive gas reaches the top of the opening 203 first, it preferentially deposits on the top surface of the opening 203, resulting in the first initial material layer 205 having a greater thickness on the top surface of the opening 203 than on the bottom surface of the opening 203.

[0080] Please refer to Figure 8 , Figure 8 During the etching stage, a back-etching process is used to remove the thicker first initial material layer 205 on the surface of the hard mask layer 201 and the top surface of the opening 203, forming the first material layer 206.

[0081] After the etching stage, the thickness of the first material layer 206 at the top of the opening 203 is less than or flush with the thickness of the first material layer 206 at the bottom of the opening 203. This is beneficial for subsequent deposition and avoids the first material layer 206 at the top of the opening 203 being too thick, thus sealing the opening and causing the formed filling layer structure to have holes.

[0082] In this embodiment, the process parameters for the etching stage include: the etching gas is hydrogen chloride.

[0083] Please refer to Figure 9 After many times Figure 7 and Figure 8 After the process, a filling material layer 207 is formed, which fills the opening 203 and is partially located on the surface of the hard mask layer 201.

[0084] The filling material layer 207 formed in the opening 203 after multiple deposition and etching stages has a dense structure and few defects, thus exhibiting good performance.

[0085] Please refer to Figure 10 The filler material layer 207 and hard mask layer 201 are planarized until the surface of the substrate 200 is exposed, and the filler layer 208 is formed in the opening 203.

[0086] The process of planarizing the filler material layer 207 and the hard mask layer 201 includes a chemical mechanical polishing process.

[0087] Thus, plasma treatment is applied to the sidewall and bottom surfaces of the opening 203. This plasma treatment allows the plasma to more easily penetrate the bottom of the opening 203, which has a large depth-to-width ratio, thereby facilitating the removal of reaction byproducts adhering to the inner wall surface of the opening 203. The thorough removal of reaction byproducts from the inner wall surface of the opening 203 ensures a tight bond between the filling layer 208 and the sidewall and bottom surfaces of the opening 203. This results in a dense structure and fewer defects in the filling layer 208, improving its quality.

[0088] Please refer to Figure 11 In this embodiment, the method further includes forming a lens 209 on the filling layer 208.

[0089] The lens 209 is used to change the optical path so that light enters the corresponding filling layer 208 along a specific optical path.

[0090] The lens 209 is made of organic materials or glass.

[0091] In other embodiments, the filler layer is made of a dielectric material or a metal. This allows other semiconductor structures to be formed on the filler layer without forming a lens.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; An opening is formed within the substrate; The sidewall surface and bottom surface of the opening are subjected to plasma treatment. The plasma treatment method includes repeating a first stage treatment and a second stage treatment after the first stage treatment several times. The first stage treatment has a first bias voltage, the second stage treatment has a second bias voltage, and the first bias voltage and the second bias voltage are opposite. After plasma treatment of the sidewall and bottom surfaces of the opening, a filling layer is formed inside the opening to completely fill it.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first bias voltage is a positive bias voltage, and the second bias voltage is a negative bias voltage; the ratio of the processing time of the first stage to the processing time of the second stage is 1:0.1 to 1:

10.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The absolute value of the first bias voltage ranges from 200V to 2000V; the absolute value of the second bias voltage ranges from 200V to 2000V.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for plasma treatment include: a gas source consisting of a mixture of hydrogen and chlorine, hydrogen bromide, or hydrogen chloride; a gas flow rate ranging from 10 standard milliliters per minute to 1000 standard milliliters per minute; a pressure range of less than 300 millitors; and a power range of 100 watts to 3000 watts.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The aspect ratio of the opening is greater than 5:

1.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The aspect ratio of the opening is in the range of 30:1 to 40:

1.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The range of the opening spacing is: greater than 0 and less than or equal to 2 micrometers.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming an opening in a substrate includes: forming a patterned mask structure on the substrate, the patterned mask structure exposing a portion of the substrate surface; and etching the substrate using the patterned mask structure as a mask to form the opening.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The patterned mask structure includes a hard mask layer and a photoresist layer on the hard mask layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The etching process for the substrate includes a dry etching process, wherein the etching gas in the dry etching process includes a fluorocarbon gas.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, When the substrate is etched with the patterned mask structure to form the opening, reaction byproducts are also formed on the sidewall surface and bottom surface of the opening.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The materials of the reaction byproducts include carbon-containing polymers.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, After the opening is formed, before plasma treatment of the sidewall and bottom surfaces of the opening, the process further includes removing the photoresist layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process for removing the photoresist layer includes a wet etching process; the etching solution for the wet etching process includes an acidic solution.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The filling layer is formed by a deposition process.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The deposition process includes repeating a deposition stage several times and an etching stage following the deposition stage.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The filling layer is made of materials including phosphosilicate or borosilicate.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The deposition stage is a selective epitaxial deposition process; the process parameters of the deposition stage include: the gas includes hydrogen, hydrogen chloride and dichlorosilane, and one of borane and phosphine; the pressure range is less than 30 Torr; and the temperature range is 750 degrees Celsius to 900 degrees Celsius.

19. The method for forming a semiconductor structure as described in claim 17, characterized in that, The process parameters for the etching stage include: the etching gas is hydrogen chloride.

20. The method for forming a semiconductor structure as described in claim 16, characterized in that, The filling layer is made of dielectric materials or metals.

21. The method for forming a semiconductor structure as described in claim 17, characterized in that, After forming the filling layer, the process also includes forming a lens on the filling layer.

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