Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises an SO I substrate, the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprises a strip-shaped waveguide area and a ridge-shaped waveguide area, and a hard mask layer is formed on the surface of the SO I substrate; a strip-shaped waveguide is formed in the top silicon layer of the strip-shaped waveguide area, and a ridge-shaped waveguide is formed in the top silicon layer of the ridge-shaped waveguide area. According to the semiconductor structure and the forming method thereof, the influence of the etching load effect can be optimized, the etching depth accuracy of the ridge waveguide region and the grating region is improved, and the device performance is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Silicon-based optoelectronic passive device integration technology can realize the fabrication of silicon photonic passive devices, including strip waveguides, ridge waveguides, edge couplers, vertical coupling gratings, directional couplers, micro-ring resonators, star couplers, arrayed waveguide gratings, polarization beam splitters, and more.

[0003] However, current silicon-based optoelectronic passive device fabrication processes still have shortcomings. In current silicon-based optoelectronic passive devices, the etching rate of strip waveguides accounts for approximately 70%-80%, while the etching rate of ridge waveguides and grating structures accounts for approximately 10%-20%. Due to the etching loading effect (the effect of localized etch gas consumption exceeding supply causing a decrease in etching rate or uneven distribution), the etching rate in the ridge waveguide and grating structure regions is too fast, affecting the accuracy of etching depth control and consequently impacting device performance.

[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to optimize the influence of etching load effect, improve the etching depth accuracy of the ridge waveguide region and grating region, and improve device performance. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for forming the same, which can optimize the effect of etching load, improve the etching depth accuracy of the ridge waveguide region and the grating region, and improve device performance.

[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing an SOI substrate, the SOI substrate including a bottom silicon layer, an insulating layer, and a top silicon layer, the SOI substrate including a strip waveguide region and a ridge waveguide region; forming a hard mask layer on the surface of the SOI substrate; performing a first etching process to etch the hard mask layer and the top silicon layer in the strip waveguide region and the ridge waveguide region, forming a pre-ridge waveguide in the top silicon layer of the strip waveguide region and the ridge waveguide region; performing a second etching process to etch the pre-ridge waveguide, converting the pre-ridge waveguide in the strip waveguide region into a strip waveguide and converting the pre-ridge waveguide in the ridge waveguide region into a ridge waveguide.

[0007] In some embodiments of this application, the pre-ridge waveguide includes a main body and extensions extending from the bottom of the main body to both sides. The second etching process etches a portion of the main body and all of the extensions of the pre-ridge waveguide in the strip waveguide region, thereby transforming the pre-ridge waveguide into a strip waveguide.

[0008] In some embodiments of this application, the SO I substrate further includes a grating region.

[0009] In some embodiments of this application, the method for forming the semiconductor structure further includes: performing a third etching process to etch the hard mask layer and the top silicon layer of the grating region, thereby forming a grating structure in the top silicon layer of the grating region.

[0010] In some embodiments of this application, the third etching process is performed after the first etching process and before the second etching process, and the third etching process also etches a portion of the main body of the pre-ridge waveguide in the strip waveguide region.

[0011] In some embodiments of this application, the third etching process is performed before the first etching process, and the third etching process also etches a portion of the top silicon layer of the strip waveguide region and the ridge waveguide region.

[0012] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a dielectric layer covering the SO I substrate on the surface of the SO I substrate, wherein the top surface of the dielectric layer is flush with the top surface of the hard mask layer.

[0013] Another aspect of this application provides a semiconductor structure formed by the semiconductor structure formation method described above, comprising: an SO I substrate, the SO I substrate including a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate including a strip waveguide region and a ridge waveguide region, and a hard mask layer formed on the surface of the SO I substrate; a strip waveguide is formed in the top silicon layer of the strip waveguide region, and a ridge waveguide is formed in the top silicon layer of the ridge waveguide region.

[0014] In some embodiments of this application, the SO I substrate further includes a grating region, wherein a grating structure is formed in the top silicon layer of the grating region.

[0015] In some embodiments of this application, the semiconductor structure further includes: a dielectric layer located on the surface of the SO I substrate covering the SO I substrate, wherein the top surface of the dielectric layer is flush with the top surface of the hard mask layer.

[0016] This application provides a semiconductor structure and a method for forming the same, which can optimize the effect of etching load, improve the etching depth accuracy of the ridge waveguide region and the grating region, and improve device performance. Attached Figure Description

[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0018] in:

[0019] Figures 1 to 5 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to some embodiments of this application;

[0020] Figures 6 to 11 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to other embodiments of this application;

[0021] Figures 12 to 17 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to some embodiments of this application. Detailed Implementation

[0022] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0023] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0024] Based on silicon-on-insulator (SOI) substrates, the fabrication of silicon-based optoelectronic passive devices is mainly achieved through waveguide forming and grating forming processes, including: 1) strip waveguide process, with an etching depth typically ranging from 150 nm to 220 nm, which fully etches the top silicon layer of SOI; 2) deep ridge waveguide process, with an etching depth typically ranging from 70 nm to 150 nm, which partially etches the top silicon and can also be used for modulator fabrication; 3) shallow ridge waveguide process, with an etching depth typically ranging from 0 nm to 70 nm, which typically involves simultaneous etching of silicon gratings for vertical coupling testing; 4) silicon grating process, with an etching depth typically ranging from 0 nm to 70 nm, which is generally etched simultaneously with the shallow ridge waveguide process.

[0025] However, because the etching ratio of the strip waveguide process is much larger than that of the other processes, the etching depth accuracy of the other processes cannot be well controlled, which affects the device performance.

[0026] To address the aforementioned issues, this application provides a semiconductor structure and its formation method. When etching the ridge waveguide and grating structure, the strip waveguide region is also partially etched, thereby increasing the etching ratio of the ridge waveguide and grating structure. This helps to optimize the influence of etching load effect, improve the etching depth accuracy of the ridge waveguide region and grating region, and improve device performance.

[0027] Figures 1 to 5 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to some embodiments of this application. The method for forming a semiconductor structure according to some embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0028] refer to Figure 1 As shown, an SO I substrate 100 is provided. The SO I (silicon-on-insulator) substrate 100 includes a bottom silicon layer 101, an insulating layer 102 located on the surface of the bottom silicon layer 101, and a top silicon layer 103 located on the surface of the insulating layer 102. The SO I substrate 100 includes a strip waveguide region 111 and a ridge waveguide region 112.

[0029] In some embodiments of this application, the semiconductor structure of this application is, for example, a silicon-based optoelectronic passive device based on an SO I substrate.

[0030] In some embodiments of this application, the bottom silicon layer 101 is made of silicon, the insulating layer 102 is made of silicon dioxide, and the top silicon layer 103 is made of silicon. Silicon-on-insulator (SOI) substrates are common substrate structures in semiconductor structures; therefore, the formation process and detailed structure of the SOI substrate 100 will not be described here.

[0031] In some embodiments of this application, the thickness of the insulating layer 102 is about 2 micrometers, and the thickness of the top silicon layer 103 is about 215 nanometers.

[0032] In some embodiments of this application, the strip waveguide region 111 is used to form a strip waveguide, and the ridge waveguide region 112 is used to form a ridge waveguide. The strip waveguide region 111 and the ridge waveguide region 112 may be adjacent or not adjacent.

[0033] refer to Figure 2 As shown, a hard mask layer 110 is formed on the surface of the SO I substrate 100.

[0034] In some embodiments of the present application, the hard mask layer 110 may be a single-layer structure or a multi-layer composite structure. The material of the hard mask layer 110 includes silicon oxide, silicon nitride, etc. For example, the hard mask layer 110 may include a silicon oxide layer and a silicon nitride layer stacked in sequence, etc.

[0035] Refer to Figure 3 As shown, a first etching process is performed to etch the hard mask layer 110 and the top silicon layer 103 in the strip waveguide region 111 and the ridge waveguide region 112, and a preliminary ridge waveguide 110a is formed in the top silicon layer 103 of the strip waveguide region 111 and the ridge waveguide region 112.

[0036] In some embodiments of the present application, the first etching process includes: forming a patterned first photoresist layer on the surface of the hard mask layer 110, and the patterned first photoresist layer defines the position of the preliminary ridge waveguide 110a; etching the hard mask layer 110 and the top silicon layer 103 with the patterned first photoresist layer as a mask to form the preliminary ridge waveguide 110a; removing the patterned first photoresist layer.

[0037] In some embodiments of the present application, the preliminary ridge waveguide 110a refers to: the structural shape of the ridge waveguide has been formed, however, this ridge waveguide is still connected to other structures and not independent, and subsequent etching is needed to make the preliminary ridge waveguide 110a independent from other structures and transform it into a true ridge waveguide or into other structures.

[0038] In some embodiments of the present application, the preliminary ridge waveguide 110a includes a main body portion and extension portions extending from both sides of the bottom end of the main body portion. The preliminary ridge waveguide 110a is in a "convex" shape, the main body portion is the middle part of the "convex" shape, and the extension portions are the two sides of the "convex" shape.

[0039] In some embodiments of the present application, the number of the preliminary ridge waveguides 110a in the strip waveguide region 111 and the ridge waveguide region 112 can be arbitrary. The sizes (widths in the horizontal direction) of multiple preliminary ridge waveguides 110a can be different from each other.

[0040] In the conventional process, the strip waveguide region 111 and the ridge waveguide region 112 are etched separately. Due to the large etching proportion of the strip waveguide region 111, it is difficult to precisely control the etching depth of the ridge waveguide region 112 due to the etching load effect. In the technical solution of the present application, the ridge waveguide is etched first and then the strip waveguide, and both the strip waveguide region 111 and the ridge waveguide region 112 are etched when etching the ridge waveguide, reducing the etching proportion gap between the strip waveguide region 111 and the ridge waveguide region 112, and improving the etching depth accuracy of the ridge waveguide region 112.

[0041] refer to Figure 4 As shown, a second etching process is performed to etch the pre-ridge waveguide 110a, so that the pre-ridge waveguide 110a in the strip waveguide region 111 is transformed into a strip waveguide 120 and the pre-ridge waveguide 110a in the ridge waveguide region 112 is transformed into a ridge waveguide 130.

[0042] In some embodiments of this application, the second etching process etches a portion of the main body (10 nanometers to 3 micrometers in width) and all of the extension of the pre-ridge waveguide 110a in the strip waveguide region 111, thereby transforming the pre-ridge waveguide 110a into a strip waveguide 120. (Comparison) Figure 3 and Figure 4 , Figure 4 The main body of the pre-ridge waveguide 110a in the strip waveguide region 111 is also partially etched, slightly reducing its horizontal width (10 nanometers to 3 micrometers). This is equivalent to increasing the etching of the strip waveguide region 111 during the second etching process, increasing the tolerance between the photolithographic alignment of the second and first etching processes, and increasing the etching process window of the strip waveguide 120. Furthermore, since the main body of the pre-ridge waveguide 110a in the strip waveguide region 111 is also partially etched, the insulating layer 102 below this etched portion suffers less etching loss, and this portion of the insulating layer 102 is slightly higher than the adjacent portion.

[0043] In some embodiments of this application, the second etching process includes: forming an anti-reflection layer covering the SO I substrate 100 on the SO I substrate 100 and forming a patterned second photoresist layer on the surface of the anti-reflection layer, the patterned second photoresist layer defining the positions of the strip waveguide 120 and the ridge waveguide 130; etching the anti-reflection layer and the top silicon layer 103 using the patterned second photoresist layer as a mask to form the ridge waveguide 130 and the strip waveguide 120; and removing the patterned second photoresist layer and the anti-reflection layer.

[0044] In some embodiments of this application, multiple strip waveguides 120 may be formed in the strip waveguide region 111, and the widths of the multiple strip waveguides 120 may be different. The number and size of the strip waveguides 120 are set according to actual needs.

[0045] refer to Figure 5 As shown, in some embodiments of this application, the method for forming the semiconductor structure further includes: forming a dielectric layer 140 covering the SO I substrate 100 on the surface of the SO I substrate 100, wherein the top surface of the dielectric layer 140 is flush with the top surface of the hard mask layer 110.

[0046] In some embodiments of this application, the material of the dielectric layer 140 includes silicon oxide.

[0047] Some embodiments of this application also provide a semiconductor structure formed by the semiconductor structure formation method described above, see reference. Figure 5 As shown, it includes: an SO I substrate 100, the SO I substrate 100 including a bottom silicon layer 101, an insulating layer 102 and a top silicon layer 103, the SO I substrate 100 including a strip waveguide region 111 and a ridge waveguide region 112, and a hard mask layer 110 formed on the surface of the SO I substrate 100; a strip waveguide 120 is formed in the top silicon layer 103 of the strip waveguide region 111, and a ridge waveguide 130 is formed in the top silicon layer 103 of the ridge waveguide region 112.

[0048] In some embodiments of this application, the semiconductor structure of this application is, for example, a silicon-based optoelectronic passive device based on an SO I substrate.

[0049] In some embodiments of this application, the bottom silicon layer 101 is made of silicon, the insulating layer 102 is made of silicon dioxide, and the top silicon layer 103 is made of silicon.

[0050] In some embodiments of this application, the thickness of the insulating layer 102 is about 2 micrometers, and the thickness of the top silicon layer 103 is about 215 nanometers.

[0051] In some embodiments of this application, the strip waveguide region 111 is used to form a strip waveguide, and the ridge waveguide region 112 is used to form a ridge waveguide. The strip waveguide region 111 and the ridge waveguide region 112 may be adjacent or not adjacent.

[0052] In some embodiments of this application, the hard mask layer 110 may be a single-layer structure or a multi-layer composite structure. The material of the hard mask layer 110 includes silicon oxide or silicon nitride, etc. For example, the hard mask layer 110 may include silicon oxide layers and silicon nitride layers stacked sequentially.

[0053] In some embodiments of this application, multiple strip waveguides 120 may be formed in the strip waveguide region 111, and the widths of the multiple strip waveguides 120 may be different. The number and size of the strip waveguides 120 are set according to actual needs.

[0054] In some embodiments of this application, the semiconductor structure further includes a dielectric layer 140 located on the surface of the SO I substrate 100 and covering the SO I substrate 100, wherein the top surface of the dielectric layer 140 is flush with the top surface of the hard mask layer 110.

[0055] In some embodiments of this application, the material of the dielectric layer 140 includes silicon oxide.

[0056] Some embodiments of this application provide a semiconductor structure and a method for forming the same, which can optimize the effect of etching load, improve the accuracy of etching depth in the ridge waveguide region, and improve device performance.

[0057] Figures 6 to 11 The accompanying drawings are schematic diagrams illustrating the steps in the method for forming a semiconductor structure according to other embodiments of this application. The method for forming a semiconductor structure according to other embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0058] refer to Figure 6 As shown, an SO I substrate 200 is provided. The SO I substrate 200 includes a bottom silicon layer 201, an insulating layer 202 located on the surface of the bottom silicon layer 201, and a top silicon layer 203 located on the surface of the insulating layer 202. The SO I substrate 200 includes a strip waveguide region 211, a ridge waveguide region 212, and a grating region 213.

[0059] In some embodiments of this application, the semiconductor structure of this application is, for example, a silicon-based optoelectronic passive device based on an SOI substrate.

[0060] In some embodiments of this application, the bottom silicon layer 201 is made of silicon, the insulating layer 202 is made of silicon dioxide, and the top silicon layer 203 is made of silicon.

[0061] In some embodiments of this application, the thickness of the insulating layer 202 is about 2 micrometers, and the thickness of the top silicon layer 203 is about 215 nanometers.

[0062] In some embodiments of this application, the strip waveguide region 211 is used to form a strip waveguide, the ridge waveguide region 212 is used to form a ridge waveguide, and the grating region 213 is used to form a grating structure. The strip waveguide region 211, the ridge waveguide region 212, and the grating region 213 may be adjacent or not adjacent.

[0063] refer to Figure 7 As shown, a hard mask layer 210 is formed on the surface of the SOI substrate 200.

[0064] In some embodiments of this application, the hard mask layer 210 may be a single-layer structure or a multi-layer composite structure. The material of the hard mask layer 210 includes silicon oxide or silicon nitride, etc. For example, the hard mask layer 210 may include silicon oxide layers and silicon nitride layers stacked sequentially.

[0065] refer to Figure 8As shown, a first etching process is performed to etch the hard mask layer 210 and the top silicon layer 203 in the strip waveguide region 211 and the ridge waveguide region 212, and a preliminary ridge waveguide 210a is formed in the top silicon layer 203 of the strip waveguide region 211 and the ridge waveguide region 212.

[0066] In some embodiments of the present application, the preliminary ridge waveguide 210a includes a main body portion and extending portions extending from both sides of the bottom end of the main body portion. The preliminary ridge waveguide 210a is in a "convex" shape, the main body portion is the middle part of the "convex" shape, and the extending portions are the two sides of the "convex" shape.

[0067] In some embodiments of the present application, the number of the preliminary ridge waveguides 210a in the strip waveguide region 211 and the ridge waveguide region 212 can be arbitrary. The sizes (widths in the horizontal direction) of the multiple preliminary ridge waveguides 210a can be different from each other.

[0068] In the conventional process, the strip waveguide region 211 and the ridge waveguide region 212 are etched separately. Since the etching proportion of the strip waveguide region 211 is relatively large, it is difficult to precisely control the etching depth of the ridge waveguide region 212 due to the etching load effect. In the technical solution of the present application, the ridge waveguide is etched first and then the strip waveguide, and when etching the ridge waveguide, both the strip waveguide region 211 and the ridge waveguide region 212 are etched, reducing the difference in the etching proportion between the strip waveguide region 211 and the ridge waveguide region 212, and improving the accuracy of the etching depth of the ridge waveguide region 212.

[0069] Reference Figure 9 As shown, a third etching process is performed to etch the hard mask layer 210 and the top silicon layer 203 in the grating region 213, and a grating structure 250 is formed in the top silicon layer 203 of the grating region 213. The etching depth of the third etching process is less than the etching depth of the first etching process. And because the etching depth of the third etching process is less than the etching depth of the first etching process, a first step is formed in the top silicon layer 203 at the adjacent position of the grating region 213 and the ridge waveguide region 212 (reference Figure 9 , and the first step is specifically located at the left position in the figure of the grating structure 250).

[0070] In some embodiments of the present application, the third etching process also etches the main body portion (with a width of 5 nm to 1.5 μm) of some preliminary ridge waveguides 210a in the strip waveguide region 211. Compare Figure 8 and Figure 9 , Figure 9The main body of the pre-ridge waveguide 210a in the strip waveguide region 211 is also partially etched, slightly reducing its horizontal width (from 5 nanometers to 1.5 micrometers). This is equivalent to adding etching of the strip waveguide region 211 in the third etching process, further improving etching accuracy and increasing the etching process window of the strip waveguide.

[0071] In some embodiments of this application, the third etching process includes: forming an anti-reflection layer covering the SO I substrate 200 on the SO I substrate 200 and forming a patterned third photoresist layer on the surface of the anti-reflection layer, the patterned third photoresist layer defining the grating structure 250; etching the anti-reflection layer and the top silicon layer 203 using the patterned third photoresist layer as a mask to form the grating structure 250; and removing the patterned third photoresist layer and the anti-reflection layer.

[0072] In conventional processes, the strip waveguide region 211, the ridge waveguide region 212, and the grating region 213 are etched separately. Because the strip waveguide region 211 has a larger etching ratio, the etching depth of the ridge waveguide region 212 and the grating region 213 is difficult to control precisely due to the etching load effect. In the technical solution of this application, the ridge waveguide and the grating structure are etched separately first, followed by the strip waveguide. Furthermore, the strip waveguide region 211 is etched simultaneously during the etching of both the ridge waveguide and the grating structure. This reduces the difference in etching ratio between the strip waveguide region 211 and the ridge waveguide region 212 and the grating region 213, thereby improving the etching depth accuracy of the ridge waveguide region 212 and the grating region 213.

[0073] refer to Figure 10 As shown, a second etching process is performed to etch the pre-ridge waveguide 210a, transforming the pre-ridge waveguide 210a in the strip waveguide region 211 into a strip waveguide 220 and the pre-ridge waveguide 210a in the ridge waveguide region 212 into a ridge waveguide 230. The first step is also partially etched to transform it into a second step 251. The second step 251 is located on the left side of the grating structure and can serve as a detection mark for the semiconductor structure of this application (the semiconductor structure fabricated using the process of this embodiment has this second step detection mark) without affecting the function of the grating structure.

[0074] In some embodiments of this application, the second etching process etches a portion of the main body (5 nanometers to 1.5 micrometers in width) and all of the extension of the pre-ridge waveguide 210a in the strip waveguide region 211, thereby transforming the pre-ridge waveguide 210a into a strip waveguide 220. (Comparison) Figure 9 and Figure 10 , Figure 10The main body of the pre-ridge waveguide 210a in the strip waveguide region 211 is also partially etched, slightly reducing its horizontal width (from 5 nanometers to 1.5 micrometers). This is equivalent to increasing the etching of the strip waveguide region 211 during the second etching process, further improving etching accuracy and increasing the etching process window of the strip waveguide 220. Furthermore, since the main body of the pre-ridge waveguide 210a in the strip waveguide region 211 is also partially etched, the insulating layer 202 below this etched portion suffers less etching loss, and this portion of the insulating layer 202 is slightly higher than the adjacent portion.

[0075] In some embodiments of this application, multiple strip waveguides 220 may be formed in the strip waveguide region 211, and the widths of the multiple strip waveguides 220 may be different. The number and size of the strip waveguides 220 are set according to actual needs.

[0076] refer to Figure 11 As shown, a dielectric layer 240 covering the SO I substrate 200 is formed on the surface of the SO I substrate 200, and the top surface of the dielectric layer 240 is flush with the top surface of the hard mask layer 210.

[0077] In some embodiments of this application, the material of the dielectric layer 240 includes silicon oxide.

[0078] Some embodiments of this application also provide a semiconductor structure formed by the semiconductor structure formation method described above, see reference. Figure 11 As shown, it includes: an SO I substrate 200, the SO I substrate 200 including a bottom silicon layer 201, an insulating layer 202 and a top silicon layer 203, the SO I substrate 200 including a strip waveguide region 211, a ridge waveguide region 212 and a grating region 213, and a hard mask layer 210 formed on the surface of the SO I substrate 200; a strip waveguide 220 is formed in the top silicon layer 203 of the strip waveguide region 211, a ridge waveguide 230 is formed in the top silicon layer 203 of the ridge waveguide region 212, and a grating structure 250 is formed in the top silicon layer 203 of the grating region 213.

[0079] In some embodiments of this application, the semiconductor structure of this application is, for example, a silicon-based optoelectronic passive device based on an SO I substrate.

[0080] In some embodiments of this application, the bottom silicon layer 201 is made of silicon, the insulating layer 202 is made of silicon dioxide, and the top silicon layer 203 is made of silicon.

[0081] In some embodiments of this application, the thickness of the insulating layer 202 is about 2 micrometers, and the thickness of the top silicon layer 203 is about 215 nanometers.

[0082] In some embodiments of this application, the strip waveguide region 211 is used to form a strip waveguide, the ridge waveguide region 212 is used to form a ridge waveguide, and the grating region 213 is used to form a grating structure. The strip waveguide region 211, the ridge waveguide region 212, and the grating region 213 may be adjacent or not adjacent.

[0083] In some embodiments of this application, the hard mask layer 210 may be a single-layer structure or a multi-layer composite structure. The material of the hard mask layer 210 includes silicon oxide or silicon nitride, etc. For example, the hard mask layer 210 may include silicon oxide layers and silicon nitride layers stacked sequentially.

[0084] In some embodiments of this application, multiple strip waveguides 220 may be formed in the strip waveguide region 211, and the widths of the multiple strip waveguides 220 may be different. The number and size of the strip waveguides 220 are set according to actual needs.

[0085] In some embodiments of this application, the semiconductor structure further includes a dielectric layer 240 located on the surface of the SO I substrate 200 and covering the SO I substrate 200, wherein the top surface of the dielectric layer 240 is flush with the top surface of the hard mask layer 210.

[0086] In some embodiments of this application, the material of the dielectric layer 240 includes silicon oxide.

[0087] Other embodiments of this application provide a semiconductor structure and a method for forming the same, which can optimize the effect of etching load, improve the etching depth accuracy of the ridge waveguide region and the grating region, and improve device performance.

[0088] Figures 12 to 17 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to some embodiments of this application. The method for forming a semiconductor structure according to some embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0089] refer to Figure 12 As shown, an SO I substrate 300 is provided. The SO I substrate 300 includes a bottom silicon layer 301, an insulating layer 302 located on the surface of the bottom silicon layer 301, and a top silicon layer 303 located on the surface of the insulating layer 302. The SO I substrate 300 includes a strip waveguide region 311, a ridge waveguide region 312, and a grating region 313.

[0090] In some embodiments of this application, the semiconductor structure of this application is, for example, a silicon-based optoelectronic passive device based on an SO I substrate.

[0091] In some embodiments of this application, the bottom silicon layer 301 is made of silicon, the insulating layer 302 is made of silicon dioxide, and the top silicon layer 303 is made of silicon.

[0092] In some embodiments of this application, the thickness of the insulating layer 302 is about 2 micrometers, and the thickness of the top silicon layer 303 is about 215 nanometers.

[0093] In some embodiments of this application, the strip waveguide region 311 is used to form a strip waveguide, the ridge waveguide region 312 is used to form a ridge waveguide, and the grating region 313 is used to form a grating structure. The strip waveguide region 311, the ridge waveguide region 312, and the grating region 313 may be adjacent or not adjacent.

[0094] refer to Figure 13 As shown, a hard mask layer 310 is formed on the surface of the SO I substrate 300.

[0095] In some embodiments of this application, the hard mask layer 310 may be a single-layer structure or a multi-layer composite structure. The material of the hard mask layer 310 includes silicon oxide or silicon nitride, etc. For example, the hard mask layer 310 may include silicon oxide layers and silicon nitride layers stacked sequentially.

[0096] refer to Figure 14 As shown, a third etching process is performed to etch the hard mask layer 310 and the top silicon layer 303 of the grating region 313, forming a grating structure 350 in the top silicon layer 303 of the grating region 313.

[0097] In some embodiments of this application, the third etching process also etches a portion of the top silicon layer 303 of the strip waveguide region 311 and the ridge waveguide region 312. This is equivalent to adding etching of the strip waveguide region 311 during the third etching process, further improving etching accuracy and increasing the etching process window of the strip waveguide.

[0098] In conventional processes, the strip waveguide region 311 and the grating region 313 are etched separately. Because the strip waveguide region 311 has a larger etching proportion, the etching depth of the grating region 313 is difficult to control precisely due to the etching load effect. In the technical solution of this application, the grating structure is etched first, followed by the strip waveguide. Furthermore, the strip waveguide region 311 is etched simultaneously with the grating structure, reducing the difference in etching proportion between the strip waveguide region 311 and the grating region 313, thereby improving the etching depth accuracy of the grating region 313.

[0099] refer to Figure 15As shown, a first etching process is performed to etch the hard mask layer 310 and the top silicon layer 303 in the strip waveguide region 311 and the ridge waveguide region 312, forming a pre-formed ridge waveguide 310a in the top silicon layer 303 of the strip waveguide region 311 and the ridge waveguide region 312. Since the main body of the pre-formed ridge waveguide 310a in the strip waveguide region 311 and the ridge waveguide region 312 has been partially etched in the third etching process, this pre-etched portion of the top silicon layer 303 is slightly lower than the adjacent portion of the top silicon layer 303.

[0100] In some embodiments of this application, the number of pre-ridge waveguides 310a in the strip waveguide region 311 and the ridge waveguide region 312 can be arbitrary. The dimensions (width in the horizontal direction) of the plurality of pre-ridge waveguides 310a can be different.

[0101] refer to Figure 16 As shown, a second etching process is performed to etch the pre-ridge waveguide 310a, so that the pre-ridge waveguide 310a in the strip waveguide region 311 is transformed into a strip waveguide 320 and the pre-ridge waveguide 310a in the ridge waveguide region 312 is transformed into a ridge waveguide 330.

[0102] In some embodiments of this application, the second etching process etches a portion of the main body and all of the extension portion of the pre-ridge waveguide 310a in the strip waveguide region 311, thereby transforming the pre-ridge waveguide 310a into a strip waveguide 320. (Comparison) Figure 15 and Figure 16 , Figure 16 The main body of the pre-ridge waveguide 310a in the strip waveguide region 311 is also partially etched, slightly reducing its horizontal width. This is equivalent to increasing the etching of the strip waveguide region 311 during the second etching process, further improving etching accuracy and increasing the etching process window of the strip waveguide 320. Since the main body of the pre-ridge waveguide 310a in the strip waveguide region 311 is also partially etched, the insulating layer 302 below this etched part of the main body suffers less etching loss. This part of the insulating layer 302 is slightly higher than the adjacent part of the insulating layer 302 (this morphology can serve as a probe mark for the semiconductor structure of this application (the semiconductor structure fabricated using the process of the embodiment of this application has this probe mark)).

[0103] In some embodiments of this application, multiple strip waveguides 320 may be formed in the strip waveguide region 311, and the widths of the multiple strip waveguides 320 may be different. The number and size of the strip waveguides 320 are set according to actual needs.

[0104] refer to Figure 17As shown, a dielectric layer 340 covering the SO I substrate 300 is formed on the surface of the SO I substrate 300, and the top surface of the dielectric layer 340 is flush with the top surface of the hard mask layer 310.

[0105] In some embodiments of this application, the material of the dielectric layer 340 includes silicon oxide.

[0106] Further embodiments of this application also provide a semiconductor structure formed by the semiconductor structure formation method described above, see reference. Figure 17 As shown, it includes: an SO I substrate 300, the SO I substrate 300 including a bottom silicon layer 301, an insulating layer 302 and a top silicon layer 303, the SO I substrate 300 including a strip waveguide region 311, a ridge waveguide region 312 and a grating region 313, and a hard mask layer 310 formed on the surface of the SO I substrate 300; a strip waveguide 320 is formed in the top silicon layer 303 of the strip waveguide region 311, a ridge waveguide 330 is formed in the top silicon layer 303 of the ridge waveguide region 312, and a grating structure 350 is formed in the top silicon layer 303 of the grating region 313.

[0107] In some embodiments of this application, the semiconductor structure of this application is, for example, a silicon-based optoelectronic passive device based on an SO I substrate.

[0108] In some embodiments of this application, the bottom silicon layer 301 is made of silicon, the insulating layer 302 is made of silicon dioxide, and the top silicon layer 303 is made of silicon.

[0109] In some embodiments of this application, the thickness of the insulating layer 302 is about 2 micrometers, and the thickness of the top silicon layer 303 is about 315 nanometers.

[0110] In some embodiments of this application, the strip waveguide region 311 is used to form a strip waveguide, the ridge waveguide region 312 is used to form a ridge waveguide, and the grating region 313 is used to form a grating structure. The strip waveguide region 311, the ridge waveguide region 312, and the grating region 313 may be adjacent or not adjacent.

[0111] In some embodiments of this application, the hard mask layer 310 may be a single-layer structure or a multi-layer composite structure. The material of the hard mask layer 310 includes silicon oxide or silicon nitride, etc. For example, the hard mask layer 310 may include silicon oxide layers and silicon nitride layers stacked sequentially.

[0112] In some embodiments of this application, multiple strip waveguides 320 may be formed in the strip waveguide region 311, and the widths of the multiple strip waveguides 320 may be different. The number and size of the strip waveguides 320 are set according to actual needs.

[0113] In some embodiments of this application, the semiconductor structure further includes a dielectric layer 340 located on the surface of the SO I substrate 300 and covering the SO I substrate 300, wherein the top surface of the dielectric layer 340 is flush with the top surface of the hard mask layer 310.

[0114] In some embodiments of this application, the material of the dielectric layer 340 includes silicon oxide.

[0115] This application provides a semiconductor structure and a method for forming the same, which can optimize the effect of etching load, improve the etching depth accuracy of the ridge waveguide region and the grating region, and improve device performance.

[0116] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0117] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "comprise," or "including" as used in this application specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0118] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0119] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: An SO I substrate is provided, the SO I substrate comprising a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprising a strip waveguide region and a ridge waveguide region; A hard mask layer is formed on the surface of the SO I substrate; Perform a first etching process to etch the hard mask layer and top silicon layer in the strip waveguide region and the ridge waveguide region, and form a pre-ridge waveguide in the top silicon layer of the strip waveguide region and the ridge waveguide region; A second etching process is performed to etch the pre-ridge waveguide, thereby transforming the pre-ridge waveguide in the strip waveguide region into a strip waveguide and the pre-ridge waveguide in the ridge waveguide region into a ridge waveguide.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The pre-ridge waveguide includes a main body and extensions extending from the bottom of the main body to both sides. The second etching process etches a portion of the main body and all of the extensions of the pre-ridge waveguide in the strip waveguide region, thereby transforming the pre-ridge waveguide into a strip waveguide.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The SO I substrate also includes a grating region.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, Also includes: A third etching process is performed to etch the hard mask layer and top silicon layer of the grating region, forming a grating structure in the top silicon layer of the grating region.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The third etching process is performed after the first etching process and before the second etching process. The third etching process also etches part of the main body of the pre-ridge waveguide in the strip waveguide region.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The third etching process is performed before the first etching process, and the third etching process also etches part of the top silicon layer of the strip waveguide region and the ridge waveguide region.

7. The method for forming a semiconductor structure as described in claim 4, characterized in that, Also includes: A dielectric layer is formed on the surface of the SO I substrate to cover the SO I substrate, and the top surface of the dielectric layer is flush with the top surface of the hard mask layer.

8. A semiconductor structure formed by the method of forming a semiconductor structure according to any one of claims 1-7, characterized in that, include: SO I substrate, the SO I substrate includes a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate includes a strip waveguide region and a ridge waveguide region, and a hard mask layer is formed on the surface of the SO I substrate; A strip waveguide is formed in the top silicon layer of the strip waveguide region, and a ridge waveguide is formed in the top silicon layer of the ridge waveguide region.

9. The semiconductor structure as described in claim 8, characterized in that, The SO I substrate also includes a grating region, in which a grating structure is formed in the top silicon layer of the grating region.

10. The semiconductor structure as described in claim 8, characterized in that, Also includes: A dielectric layer is located on the surface of the SO I substrate, covering the SO I substrate, and the top surface of the dielectric layer is flush with the top surface of the hard mask layer.

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