Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application relates to a semiconductor device manufacturing method and a semiconductor device. The method comprises the following steps: forming a first groove in a first semiconductor material layer; forming an oxide layer, the oxide layer covering the sidewall and the bottom wall of the first groove and not filling the first groove; the oxide layer comprises a first part on the sidewall of the first groove and a second part on the bottom wall of the first groove; the thickness of the first part is greater than the thickness of the second part; etching with the oxide layer as a mask, removing part of the first part, all of the second part, and part of the first semiconductor material layer exposed by the second part, so as to form a second groove extending downward from the bottom of the first groove, and the line width of the second groove is smaller than that of the first groove; and doping a preset thickness of conductive material into the interior of the first semiconductor material layer at the bottom of the first groove and the second groove, so as to form a conductive region. The semiconductor device manufacturing method and the semiconductor device provided by the application can reduce the production cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a preparation method of semiconductor device and semiconductor device. BACKGROUND

[0002] In the preparation process of a junction barrier schottky (JBS) semiconductor device, such as a schottky diode, a groove with stepped side wall needs to be formed. A conductive region is arranged at the bottom of the groove with stepped side wall, so that the conductive region has a larger conductive contact area. Since the etching depth is different at different positions of the stepped side wall, the line width of the etching process is also different, so that two photoetching processes are generally required to achieve the groove with stepped side wall, and a hard mask (HM) needs to be deposited in each photoetching process, which leads to a complex process flow, a long process time and a high cost. SUMMARY

[0003] In view of the above, the embodiments of the present application provide a preparation method of semiconductor device and semiconductor device to solve at least one problem in the background art.

[0004] To achieve the above object, the technical scheme of the present application is as follows:

[0005] In a first aspect, the present application provides a preparation method of semiconductor device, which comprises the following steps:

[0006] forming a first groove in a first semiconductor material layer;

[0007] forming an oxide layer, the oxide layer covering the side wall and the bottom wall of the first groove and not filling the first groove; the oxide layer comprises a first part located at the side wall of the first groove and a second part located at the bottom wall of the first groove; the thickness of the first part is greater than the thickness of the second part;

[0008] performing etching with the oxide layer as a mask layer to remove part of the first part, all of the second part and part of the first semiconductor material layer exposed through the second part, so as to form a second groove extending downward from the bottom surface of the first groove, and the line width of the second groove is smaller than the line width of the first groove;

[0009] doping a conductive material with a preset thickness into the interior of the first semiconductor material layer at the bottom of the first groove and the second groove to form a conductive region.

[0010] Optionally, the step of forming a first groove in a first semiconductor material layer comprises:

[0011] forming a polysilicon layer on the first semiconductor material layer;

[0012] forming an opening in a position of the polysilicon layer corresponding to a preset forming position of the first trench;

[0013] etching the first semiconductor material layer to form the first trench in the first semiconductor material layer, with the polysilicon layer with the opening formed serving as a mask.

[0014] Optionally, the forming the oxide layer comprises:

[0015] performing an oxidation process to oxidize exposed surfaces of the polysilicon layer and the first semiconductor material layer to form the oxide layer; wherein the material of the first semiconductor material layer is silicon carbide, and the thickness of the part of the oxide layer located on the sidewall of the first trench is less than the thickness of the oxide layer located on the sidewall and top surface of the polysilicon layer.

[0016] Optionally, the method further comprises:

[0017] performing dry etching with the polysilicon layer and the oxide layer serving as mask layers to form the second trench.

[0018] Optionally, the doping a preset thickness of conductive material into the interior of the first semiconductor material layer at the bottom of the first trench and the second trench to form a conductive region comprises:

[0019] removing the remaining oxide layer;

[0020] doping at the bottom of the first trench and the second trench to form the conductive region, with a doping thickness of 0.3-1.5 microns.

[0021] Optionally, the oxidation process is a furnace tube thermal oxidation process, and the process parameters of the furnace tube thermal oxidation process comprise: oxidation temperature: 1000-1200 degrees Celsius, oxidation time: 3-10H, and oxidation atmosphere: dry oxygen and / or wet oxygen.

[0022] Optionally, during the furnace tube thermal oxidation process, the ratio of the oxidation rates of the sidewall and top surface of the polysilicon layer, the sidewall of the first trench, and the bottom wall of the first trench is (12-8):(6-3):1.

[0023] In a second aspect, the embodiments of the present application further provide a semiconductor device, which comprises:

[0024] a first semiconductor material layer;

[0025] a first trench extending from the top surface of the first semiconductor material layer to the interior of the first semiconductor material layer;

[0026] a second trench extending from a bottom surface of the first trench to an interior of the first semiconductor material layer, the second trench having a line width less than a line width of the first trench, the second trench having a line width at an upper end of the second trench greater than a line width at a lower end of the second trench;

[0027] a conductive region formed by doping a conductive material of a predetermined thickness from a bottom of the first trench and the second trench to the interior of the first semiconductor material layer.

[0028] Optionally, a sidewall of the second trench is a curved surface that is arc-shaped in any one cross section in a longitudinal direction.

[0029] Optionally, a thickness of the conductive region in the longitudinal direction is 0.3 microns to 1.5 microns.

[0030] A method for manufacturing a semiconductor device and the semiconductor device are provided in the embodiments of the present application, and the method comprises: forming a first trench in a first semiconductor material layer; forming an oxide layer, the oxide layer covering sidewalls and a bottom wall of the first trench and not filling the first trench; the oxide layer comprises a first part on the sidewalls of the first trench and a second part on the bottom wall of the first trench; the first part has a thickness greater than that of the second part; performing etching with the oxide layer as a mask layer to remove part of the first part, all of the second part, and part of the first semiconductor material layer exposed through the second part, so as to form a second trench in the first trench, the second trench having a depth greater than that of the first trench and a line width less than that of the first trench; and performing doping at the bottom of the first trench and the second trench to form a conductive region. The second trench can be obtained by etching with the formed oxide layer as a mask layer, without the need to grow or deposit a hard mask again and perform a photolithography process again. The first trench and the second trench formed can also enable the conductive region to have a larger conductive contact area. The process flow is simplified, the manufacturing process is reduced, and the cost is lowered. Thus, the method for manufacturing a semiconductor device and the semiconductor device provided in the embodiments of the present application can reduce the production cost.

[0031] Additional aspects and advantages of the present application will be made apparent by the following description. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0033] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided in the embodiments of the present application;

[0034] Figure 2 A sectional view of a semiconductor device provided by the embodiment of the present application after forming the first trench in the preparation method of the semiconductor device;

[0035] Figure 3 A sectional view of a semiconductor device provided by the embodiment of the present application after forming the oxide layer in the preparation method of the semiconductor device;

[0036] Figure 4 A sectional view of a semiconductor device provided by the embodiment of the present application after forming the second trench in the preparation method of the semiconductor device;

[0037] Figure 5 A sectional view of a semiconductor device provided by the embodiment of the present application after forming the second trench and removing the oxide layer in the preparation method of the semiconductor device;

[0038] Figure 6 A sectional view of a semiconductor device provided by the embodiment of the present application after forming the conductive region in the preparation method of the semiconductor device.

[0039] Explanation of reference numerals:

[0040] 20, first semiconductor material layer; 30, first trench; 40, oxide layer; 50, second trench; 60, conductive region; 70, photoresist; 80, polysilicon layer. DETAILED DESCRIPTION

[0041] Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present application are illustrated, it should be understood that the present application can be embodied in many forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will convey the scope of the present application to those skilled in the art.

[0042] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate the present application. As used herein, the term "including" means including without limitation.

[0043] In the drawings, the size of layers, regions, elements and the relative sizes among them can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0044] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0045] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] For a thorough understanding of the application, detailed steps and detailed structures will be presented in the following description, in order to explain the technical solutions of the application. The preferred embodiments of the application are described in detail as follows, however, in addition to these detailed descriptions, the application can also have other implementation manners.

[0048] To solve the technical problems in the prior art, the application provides a preparation method of a semiconductor device, as shown in Figure 1 The method comprises the following steps:

[0049] Step 101: forming a first trench 30 in a first semiconductor material layer 20;

[0050] Step 102: forming an oxide layer 40, the oxide layer 40 covering the side wall and bottom wall of the first trench 30 and not filling the first trench 30; the oxide layer 40 comprises a first part located on the side wall of the first trench 30 and a second part located on the bottom wall of the first trench 30; the thickness of the first part is greater than the thickness of the second part;

[0051] Step 103: etching with the oxide layer as a mask layer, removing part of the first part, all of the second part, and part of the first semiconductor material layer 20 exposed through the second part, to form a second trench 50 extending downward from the bottom surface of the first trench 30, the line width of the second trench 50 being smaller than the line width of the first trench 30;

[0052] Step 104: doping a predetermined thickness of conductive material into the inside of the first semiconductor material layer 20 at the bottom of the first trench 30 and the second trench 50, to form a conductive region 60.

[0053] The preparation method of the semiconductor device provided by the application can be used for the preparation of a JBS semiconductor device, and the following mainly takes the JBS semiconductor device as an example for introduction. It can be understood that the preparation method of the semiconductor device of the application can also be used for the preparation of other semiconductor devices.

[0054] As shown in Figure 2 In step 101, the first semiconductor material layer 20 can be an epitaxial layer (EPI) formed by epitaxial growth on a substrate (not shown in the figure). The first semiconductor material layer 20 can be a doped semiconductor material layer, for example, P-type doped or N-type doped.

[0055] For example, in step 101, forming the first trench 30 within the first semiconductor material layer 20 can be achieved through photolithography. Specifically, a mask material is first deposited on the first semiconductor material layer 20 to form a mask layer. Then, through photolithography and etching processes, a preset formation position of the first trench 30 is defined in the mask material, thereby forming a patterned mask layer. The preset formation position can be the designed position of the first trench 30 or a position specified according to semiconductor device standards. The photolithography process requires forming photoresist 70 on the mask material, patterning the photoresist 70 using a mask and a light source, and then etching the patterned mask layer using the patterned photoresist 70. This process is well known to those skilled in the art and will not be described in detail here. Next, using the patterned mask layer as a mask, the first semiconductor material layer 20 is etched until a first trench 30 meeting a preset depth requirement is formed. The depth of the first trench 30 is preset and does not penetrate the first semiconductor material layer 20. The preset depth can be the designed depth of the first trench 30 or a depth specified according to semiconductor device standards. The etching process for forming the first trench 30 can employ a dry etching process. In some embodiments, the mask layer can be a hard mask, and the material of the mask layer can be an inorganic thin film material such as silicon nitride, silicon oxide, or silicon oxynitride. In some embodiments, the first trench 30 can be a trench with a rectangular cross-section (generally referred to as a strip trench in the industry), and the sidewalls of the first trench 30 are perpendicular to the bottom wall, penetrating the first semiconductor material layer 20 in the front-back direction (into-out of the paper direction) in the figures. It is understood that the shape of the cross-section of the first trench 30 is not limited to a rectangle, but can also be other shapes, such as a circle, hexagon, or a square (generally referred to as a rectangular trench in the industry). It is understood that the first trench 30 may not penetrate the first semiconductor material layer 20 in the front-back direction (into-out of the paper direction) in the figures. In this embodiment, the cross-section can be a cross-section parallel to the substrate plane.

[0056] For example, such as Figure 3 As shown, in step 102, due to process limitations, the oxide layer 40 only covers the sidewalls and bottom wall of the first trench 30 and does not fill the first trench 30 completely. For example, due to process and material characteristics, the thickness of the oxide layer 40 located on the sidewall of the first trench 30 is greater than the thickness of the portion located on the bottom wall of the first trench 30; that is, the thickness of the first portion is greater than the thickness of the second portion.

[0057] For example, such as Figure 3 and Figure 4As shown, step 103 includes: etching the sidewall of the first trench 30 to thin it, i.e. to remove part of the first portion; etching the bottom wall of the first trench 30, and after the bottom wall is etched completely, etching the first semiconductor material layer 20 below the bottom wall, i.e. to remove the second portion completely and part of the first semiconductor material layer 20 exposed through the second portion. Exemplarily, the etching of the sidewall and the bottom wall is performed simultaneously, i.e. etching from top to bottom with the oxide layer 40 as a mask. Since the oxide layer 40 of the sidewall of the first trench 30 is not removed completely, the line width of the second trench 50 formed is smaller than that of the first trench 30. Here, the line width can be the width of the first trench or the second trench in the left-right direction in the drawing, and if the cross section of the trench is rectangular, the line width refers to the width of one direction of the rectangle, and for a circular cross section of the trench, the line width is the diameter.

[0058] In some embodiments, the second trench 50 can be formed by etching downward at the bottom of the first trench 30, i.e. etching the first semiconductor material layer 20 below the first trench 30 until the second trench 50 with a preset depth is formed. The depth of the second trench 50 is preset and does not penetrate the first semiconductor material layer 20, and the preset depth is the design depth of the second trench 50 or the depth specified according to the standard of the semiconductor device. The second trench 50 can be a slot with a rectangular cross section (generally referred to as a strip slot in the industry, and the name will not be repeated below for the convenience of readers), which penetrates the first semiconductor material layer 20 in the front-back direction (the direction of going into and out of the paper) in the drawing. It can be understood that the cross-sectional shape of the second trench 50 is not limited to rectangular, but can also be other shapes, such as circular, hexagonal or back-shaped (generally referred to as a rectangular slot in the industry). It can be understood that the second trench 50 can also not penetrate the first semiconductor material layer 20 in the front-back direction (the direction of going into and out of the paper) in the drawing.

[0059] In some embodiments, the forming of the first trench 30 in the first semiconductor material layer 20 can include:

[0060] forming a polysilicon layer 80 on the first semiconductor material layer 20;

[0061] forming an opening on the polysilicon layer 80 at a position corresponding to the preset forming position of the first trench 30;

[0062] using the polysilicon layer 80 with the opening as a mask to etch the first semiconductor material layer 20 to form the first trench 30 in the first semiconductor material layer 20.

[0063] For example, the openings formed on the polysilicon layer 80 are etched using photoresist 70 as a mask. In some embodiments, the polysilicon layer 80 can be formed by chemical vapor deposition (CVD). For example, the thickness of the polysilicon layer 80 can be greater than 1000 angstroms. For example, the material of the polysilicon layer 80 can be doped polysilicon, and the doped impurities can be boron and / or phosphorus. Thus, in step 102, the oxide layer 40 formed on the sidewalls and topwalls of the polysilicon layer 80 can achieve a greater thickness, with a larger difference compared to the thickness of the oxide layer 40 in other parts, making it easier to form a stepped shape in the vertical direction or to make the steps of the stepped shape in the vertical direction larger. This, in turn, makes the shape of the formed second trench more conducive to reducing the probability of leakage in the conductive region 60 (see the description below).

[0064] In some embodiments, forming the oxide layer 40 may include:

[0065] An oxidation process is performed to oxidize the exposed surfaces of the polysilicon layer 80 and the first semiconductor material layer 20 to form the oxide layer 40; wherein the material of the first semiconductor material layer 20 is silicon carbide, and the thickness of the portion of the oxide layer 40 located on the sidewall of the first trench 30 is less than the thickness of the oxide layer 40 located on the sidewall and top surface of the polysilicon layer 80.

[0066] For example, since the first semiconductor material layer 20 is made of silicon carbide, during the oxidation process, the differences in the film structure and atomic density of silicon carbide and polycrystalline silicon lead to inconsistent oxidation rates. This results in the thickness of the oxide layer 40 located on the sidewall of the first trench 30 being less than the thickness of the oxide layer 40 located on the sidewall and top surface of the polycrystalline silicon layer 80. Furthermore, as mentioned above, the thickness of the oxide layer 40 located on the sidewall of the first trench 30 is greater than the thickness located on the bottom wall of the first trench 30. Therefore, the thicknesses of the oxide layer 40 are ordered as follows:

[0067] The portion of oxide layer 40 located on the sidewall and top surface of the polycrystalline silicon layer 80 > the portion of oxide layer 40 located on the sidewall of the first trench 30 > the portion of oxide layer 40 located on the bottom wall of the first trench 30.

[0068] Therefore, as Figure 3 As shown, the portion of oxide layer 40 located on the sidewall of the polysilicon layer 80 and the portion of oxide layer 40 located on the sidewall of the first trench 30 form steps in the vertical direction. This will restrict the shape of the second trench 50 in step 103, as detailed below.

[0069] In some embodiments, the oxidation process is a furnace tube thermal oxidation process, and the process parameters of the furnace tube thermal oxidation process can include: oxidation temperature: 1000-1200 degrees Celsius, such as 1000 degrees Celsius, 1050 degrees Celsius, 1100 degrees Celsius, 1150 degrees Celsius, 1200 degrees Celsius, etc.; oxidation time: 3H-10H, such as 3H, 4H, 5H, 6H, 7H, 8H, 9H, 10H, etc.; oxidation atmosphere: dry oxygen, and / or wet oxygen.

[0070] Exemplarily, the process parameters of the above oxidation process can have better oxidation quality and faster oxidation rate.

[0071] In some embodiments, in the furnace tube thermal oxidation process, the oxidation rate ratio of the side wall and top surface of the polysilicon layer, the side wall of the first trench 30, and the bottom wall of the first trench 30 is (12-8):(6-3):1.

[0072] Exemplarily, the above difference in oxidation rate can make the thickness of the oxide layer 40 different on the side wall and top surface of the first mask layer, the side wall of the first trench 30, and the bottom wall of the first trench 30, respectively, which can limit the formation shape of the second trench 50 in the subsequent step 103. The oxidation rate is related to the film structure of the material to be oxidized, the atomic density of the film surface, the temperature, the humidity, the gas type, and the gas pressure. The oxidation process time can be adjusted by adjusting the film structure of the material to be oxidized and the parameters of the thermal oxidation process. Exemplarily, the film structure of the material to be oxidized and the atomic density of the film surface can be related to the doping concentration of the material to be oxidized. Therefore, the oxidation rate ratio can be adjusted by adjusting the doping concentration of each material to be oxidized.

[0073] In some embodiments, the method further comprises:

[0074] Dry etching is performed on the polysilicon layer 80 and the oxide layer 40 as mask layers to form the second trench 50.

[0075] As shown in Figure 3 The dry etching process is to bombard the oxide layer 40 and the first semiconductor material exposed after the oxide layer 40 is removed from top to bottom by ion beam to form the second trench 50, as shown in Figure 4A portion of the ions hit the top surface of the oxide layer 40, and another portion of the ions hit the sidewall of the polysilicon layer 80 and the sidewall of the first trench 30. Because of the high energy and high speed of the ions, the oxide layer 40 and the first semiconductor material layer 20 at the bottom of the first trench 30 will bounce in other directions after being hit. Because the sidewall of the polysilicon layer 80 and the sidewall of the first trench 30 form a step in the vertical direction, the bouncing provides space. The sidewall of the second trench 50 will not be perpendicular to the bottom of the second trench 50, but will form an arc in the vertical direction. The width of the second trench at the top will be larger than the width of the second trench at the bottom. In other words, the bottom of the arc will bend towards the center of the second trench. Figure 3 The arrowed straight line indicates the direction of the ion beam. The vertical direction is the thickness direction of the semiconductor device. The arc-shaped sidewall of the second trench 50 in the vertical direction in this embodiment can be all the sidewalls of the second trench 50 in the circumferential direction. For example, when the cross section of the second trench is circular, hexagonal, or U-shaped, the sidewalls can be all the sidewalls in the circumferential direction. It can be understood that all the sidewalls of the second trench 50 in the circumferential direction in this embodiment are arc-shaped, and it can also be considered that the shape of the sidewall in any cross section in the vertical direction is arc-shaped. It can be understood that in some cases, the two sidewalls in the left-right direction shown in the figure can be arc-shaped, for example, when the cross section of the second trench is rectangular. In some embodiments, the dry etching process can be reactive ion etching (RIE).

[0076] In some embodiments, the step of doping the first semiconductor material layer 20 in the first trench 30 and the second trench 50 to form a conductive region 60 includes:

[0077] removing the remaining oxide layer 40;

[0078] The doping thickness at the bottom of the first trench 30 and the second trench 50 is 0.3 microns to 1.5 microns to form the conductive region 60.

[0079] For example, the remaining oxide layer 40 refers to the remaining oxide layer after part of the oxide layer is etched away during the formation of the second trench by dry etching in step 103. The semiconductor device after the removal of the remaining oxide layer 40 is shown in FIG. 4. Figure 5 The semiconductor device after the formation of the conductive region 60 is shown in FIG. 5.Figure 6 Exemplarily, since the conductive region 60 is formed by doping a preset thickness of conductive material into the bottom of the first trench 30 and the second trench 50 to the inside of the first semiconductor material layer 20, generally, the upper end of the conductive region 60 abuts against the bottom of the first trench 30, the sidewall of the second trench 50 and the bottom of the second trench 50, and the boundary shape of the conductive region 60 is the same as the shape of the first trench 30 and the second trench 50. Exemplarily, the doping thickness of 0.3-1.5 microns is set according to the performance requirements of the semiconductor device, and too thin or too thick will affect the performance. Among them, the doping thickness of 0.3-1.5 microns, for example, can be 0.3 microns, 0.4 microns, 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, 1.0 microns, 1.1 microns, 1.2 microns, 1.3 microns, 1.4 microns, 1.5 microns, etc. In some embodiments, the doping thickness can also be 0.3-0.7 microns, so that in the application of lower application voltage, not only can the semiconductor device obtain the preset performance, but also can reduce the execution energy of the doping process, reduce energy loss and reduce production cost.

[0080] Specifically, the conductive region 60 can include:

[0081] The first region is a region surrounded between the bottom wall of the first trench 30 and the bottom wall translated downward by a preset distance;

[0082] The second region is a region surrounded between the bottom wall and the sidewall of the second trench 50 and the bottom wall and the sidewall translated downward by a preset distance; the outside of the second region is connected to the inside of the first region.

[0083] The bottom wall of the first trench 30 mentioned above is the remaining bottom wall after the second trench 50 is formed, and the value of the preset distance is the value of the thickness of the doped conductive material. Exemplarily, the conductive region 60 abuts against the first trench 30 and the second trench 50 through the first region and the second region, respectively. Among them, as Figure 6As shown, the shape of the first region is the same as the shape of the first trench 30, and the shape of the second region is the same as the shape of the second trench 50. Since the sidewall of the second trench 50 is arc-shaped in the longitudinal direction, and the arc-shaped sidewall is closer to the central region of the second trench 50 at the lower end in the longitudinal direction. Therefore, the upper end of the second region of the conductive region 60 also has a groove with an arc-shaped sidewall, and the arc-shaped sidewall is closer to the central region of the second trench 50 at the lower end in the longitudinal direction. Compared with the groove in the upper end of the conductive region in the related art: the sidewall is perpendicular to the bottom wall, and the intersection of the sidewall and the bottom wall is a right angle. The conductive region 60 of the embodiment of the present application can increase the thickness of the upper end and the bottom end of the conductive region 60 closest to each other under the condition that the doping thickness is limited, that is, the thickness of the thinnest part of the conductive region 60 can be increased, and the possibility of leakage can be reduced. Since all the sidewalls of the second trench in the circumferential direction are arc-shaped surfaces in the longitudinal direction, the sidewalls of the groove of the conductive region 60 in the entire circumferential direction are also arc-shaped surfaces in the longitudinal direction. Therefore, the conductive region 60 has a structure of increasing the thickness of the thinnest part in the entire circumferential direction, further reducing the possibility of leakage.

[0084] For example, the doping can be performed by an ion implantation process. In the embodiment, the implanted ions can be at least one P-type ion such as boron, indium, gallium, etc., to form a P+ region. In other embodiments of the present application, the implanted ions can be at least one N-type ion such as phosphorus, arsenic, etc., to form an N+ region. Thus, a semiconductor device with the same structure but different types as the embodiment is formed.

[0085] The embodiment of the present application also provides a semiconductor device, as shown in the accompanying drawings, Figure 6 As shown, the semiconductor device comprises:

[0086] a first semiconductor material layer 20;

[0087] a first trench 30 extending from the top surface of the first semiconductor material layer 20 to the inside of the first semiconductor material layer 20;

[0088] a second trench 50 extending from the bottom surface of the first trench 30 to the inside of the first semiconductor material layer 20; the line width of the second trench is smaller than the line width of the first trench; the line width of the upper end of the second trench is greater than the line width of the lower end of the second trench;

[0089] a conductive region 60 formed by doping a predetermined thickness of conductive material from the bottom of the first trench 30 and the second trench 50 to the inside of the first semiconductor material layer 20.

[0090] For example, the first semiconductor material layer 20 may be an epitaxial layer (EPI) formed by epitaxial growth on a substrate (not shown in the figure). The first semiconductor material layer 20 may be a doped semiconductor material layer, such as a P-type doped or N-type doped layer.

[0091] Exemplarily, the depth of the first trench 30 is preset and does not penetrate the first semiconductor material layer 20. Exemplarily, the first trench 30 can be a groove with a rectangular cross-section (generally referred to as a strip groove in the industry), and the sidewalls of the first trench 30 are perpendicular to the bottom wall, penetrating the first semiconductor material layer 20 in the front-back direction (into-out of the paper direction) in the figures. It is understood that the shape of the cross-section of the first trench 30 is not limited to rectangle, but can also be other shapes, such as circular, hexagonal, or U-shaped (generally referred to as a rectangular groove in the industry). It is understood that the first trench 30 may not penetrate the first semiconductor material layer 20 in the front-back direction (into-out of the paper direction) in the figures. In this embodiment, the cross-section can be a cross-section parallel to the substrate plane.

[0092] For example, the second trench 50 extends from the bottom of the first trench 30 into the interior of the first semiconductor material layer 20, extending to a preset depth, and does not penetrate the first semiconductor material layer 20. For example, the linewidth of the second trench 50 is smaller than the linewidth of the first trench 30. Therefore, the first trench 30 and the second trench 50 form a stepped hole with a larger linewidth at the upper end and a smaller linewidth at the lower end. Here, the linewidth can be the width of the first or second trench in the left-right direction in the drawing. For example, for a trench with a rectangular cross-section, it refers to the width dimension in the left-right direction in the drawing; for a trench with a circular cross-section, it refers to the diameter dimension. For example, the second trench 50 can be a groove with a rectangular cross-section (generally referred to as a strip groove in the industry), penetrating the first semiconductor material layer 20 in the front-back direction (the direction in and out of the paper) in the drawing. It is understood that the shape of the cross-section of the second trench 50 is not limited to rectangle; it can also be other shapes, such as circle, hexagon, or U-shape (generally referred to as a rectangular groove in the industry). It is understandable that the second trench 50 may not penetrate the first semiconductor material layer 20 in the front-back direction (in and out of the paper) in the attached figure.

[0093] For example, since the conductive region 60 is formed by doping a predetermined thickness of conductive material into the interior of the first semiconductor material layer 20 from the bottom of the first trench 30 and the second trench 50, generally, the upper end of the conductive region 60 abuts against the bottom of the first trench 30, the sidewall of the second trench 50, and the bottom of the second trench 50, and the boundary shape of the conductive region 60 is the same as the shape of the first trench 30 and the second trench 50.

[0094] For example, the lower end of the second trench 50 is closer to the center region of the second trench 50 than the upper end of the second trench 50, and the shape of the upper end of the conductive region 60 is the same. Compared to the related art where the upper and lower ends of the sidewalls of the second trench 50 are longitudinally aligned (i.e., the sidewalls of the second trench 50 are perpendicular to the bottom wall, and the intersection of the sidewalls and the bottom wall is at a right angle), the shape of the second trench in this embodiment, when the doping thickness is limited, can increase the thickness at the point where the upper and lower ends of the conductive region 60 are closest, i.e., increase the thickness at the thinnest point of the conductive region 60, reducing the possibility of leakage.

[0095] In some embodiments, such as Figure 6 As shown, the sidewalls of the second trench 50 are curved surfaces that are arc-shaped in any longitudinal section. That is, all the sidewalls of the second trench 50 in the circumferential direction are arc-shaped surfaces in the longitudinal direction. For example, if the cross-section of the second trench is circular, hexagonal, or U-shaped, then all the sidewalls in the circumferential direction are arc-shaped surfaces in the longitudinal direction. The arc shape makes the structure of the second trench 50 and the conductive area 60 below it more stable and easier to implement in the manufacturing process. It is understood that in some cases, the two sidewalls in the left and right directions, as shown in the attached figure, can also be arc-shaped surfaces, for example, if the cross-sectional shape of the second trench is rectangular.

[0096] In some embodiments, such as Figure 6 As shown, the conductive region 60 includes:

[0097] The first region is the area enclosed between the bottom wall of the first trench 30 and the bottom wall shifted downward by a predetermined distance;

[0098] The second region is the area enclosed by the bottom wall and sidewalls of the second trench 50 and the area between the bottom wall and sidewalls and a predetermined downward translation distance; the outer side of the second region is connected to the inner side of the first region. The bottom wall of the first trench 30 is the remaining bottom wall after the second trench 50 is formed, and the predetermined distance is the value of the thickness of the doped conductive material. For example, the conductive region 60 abuts against the first trench 30 and the second trench 50 through the first region and the second region, respectively. Wherein, as... Figure 6As shown, the shape of the first region is the same as the shape of the first trench 30, and the shape of the second region is the same as the shape of the second trench 50. Since the sidewall of the second trench 50 is arc-shaped in the longitudinal direction, and the arc-shaped sidewall is closer to the central region of the second trench 50 at the lower end in the longitudinal direction. Therefore, the upper end of the second region of the conductive region 60 also has a groove with an arc-shaped sidewall, and the arc-shaped sidewall is closer to the central region of the second trench 50 at the lower end in the longitudinal direction. Compared with the groove in the upper end of the conductive region in the related art: the sidewall is perpendicular to the bottom wall, and the intersection of the sidewall and the bottom wall is a right angle. The conductive region 60 of the embodiment of the present application can increase the thickness of the upper end and the bottom end of the conductive region 60 closest to each other under the condition that the doping thickness is limited, that is, the thickness of the thinnest part of the conductive region 60 can be increased, and the possibility of leakage can be reduced. Since all the sidewalls of the second trench in the circumferential direction are arc-shaped in the longitudinal direction, the sidewalls of the groove of the conductive region 60 in the entire circumferential direction are also arc-shaped in the longitudinal direction. Therefore, the conductive region 60 has a structure that increases the thickness of the thinnest part in the entire circumferential direction, further reducing the possibility of leakage. In some embodiments, the thickness of the conductive region in the longitudinal direction is 0.3-1.5 microns. Among them, the doping thickness of 0.3-1.5 microns is set according to the performance requirements of the semiconductor device. Too thin or too thick will affect the performance. Among them, the doping thickness of 0.3-1.5 microns, for example, can be 0.3 microns, 0.4 microns, 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, 1.0 microns, 1.1 microns, 1.2 microns, 1.3 microns, 1.4 microns, 1.5 microns, etc. In some embodiments, the doping thickness can also be 0.3-0.7 microns. In this way, in the application of low-voltage application occasions, not only can the semiconductor device obtain the preset performance, but also can reduce the execution energy of the doping process, reduce energy consumption, and reduce production cost.

[0099] For example, the conductive region 60 can be doped to form by ion implantation process; in the embodiment, the implanted ions can be at least one P-type ion such as boron, indium, gallium, etc. to form a P+ region. In other embodiments of the present application, the implanted ions can also be at least one N-type ion such as phosphorus, arsenic, etc. to form an N+ region. To form a semiconductor device with the same structure as the embodiment but different types.

[0100] It should be noted that the semiconductor device embodiments provided in the present application and the semiconductor device manufacturing method embodiments belong to the same concept. The technical features of the technical solutions recorded in each embodiment can be combined arbitrarily without conflict. However, it should be further pointed out that the combination of technical features of the semiconductor device provided in the embodiments of the present application can already solve the technical problems to be solved by the present application. Therefore, the semiconductor device provided in the embodiments of the present application can not be limited by the semiconductor device manufacturing method provided in the embodiments of the present application. Any semiconductor device manufactured by a manufacturing method that can form the semiconductor device structure provided in the embodiments of the present application is within the scope of protection of the present application.

[0101] It should be understood that the above embodiments are exemplary and are not intended to include all possible embodiments encompassed by the claims. Various modifications and changes can also be made to the above embodiments without departing from the scope of the present disclosure. Similarly, any combination of the technical features of the above embodiments can be made to form additional embodiments of the present application that can not have been explicitly described. Therefore, the above embodiments only express several embodiments of the present application and do not limit the scope of protection of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: forming a first trench in a first semiconductor material layer; forming an oxide layer covering sidewalls and bottom wall of the first trench and not filling the first trench; the oxide layer comprises a first part on the sidewalls of the first trench and a second part on the bottom wall of the first trench; the thickness of the first part is greater than the thickness of the second part; performing etching with the oxide layer as a mask layer to remove part of the first part, all of the second part and part of the first semiconductor material layer exposed through the second part to form a second trench extending downward from the bottom surface of the first trench, the line width of the second trench being smaller than that of the first trench; doping a predetermined thickness of conductive material into the first semiconductor material layer at the bottom of the first trench and the second trench to form a conductive region.

2. The method of producing a semiconductor device according to claim 1, wherein The forming of the first trench in the first semiconductor material layer comprises: forming a polysilicon layer on the first semiconductor material layer; forming an opening on the polysilicon layer at a position corresponding to a predetermined forming position of the first trench; performing etching on the first semiconductor material layer with the polysilicon layer with the opening as a mask to form the first trench in the first semiconductor material layer.

3. The method of producing a semiconductor device according to claim 2, wherein The forming of the oxide layer comprises: performing an oxidation process to oxidize the exposed surface layer of the polysilicon layer and the first semiconductor material layer to form the oxide layer; wherein the material of the first semiconductor material layer is silicon carbide, and the thickness of the part of the oxide layer on the sidewalls of the first trench is smaller than the thickness of the oxide layer on the sidewalls and top surface of the polysilicon layer.

4. The method of producing a semiconductor device according to claim 3, wherein The method further comprises: performing dry etching with the polysilicon layer and the oxide layer as mask layers to form the second trench.

5. The method of producing a semiconductor device according to claim 3, wherein The doping of the predetermined thickness of conductive material into the first semiconductor material layer at the bottom of the first trench and the second trench to form the conductive region comprises: removing the remaining oxide layer; performing doping at the bottom of the first trench and the second trench with a doping thickness of 0.3-1.5 microns to form the conductive region.

6. The method of producing a semiconductor device according to claim 3, wherein The oxidation process is a furnace tube thermal oxidation process, and the process parameters of the furnace tube thermal oxidation process comprise: oxidation temperature: 1000-1200 degrees Celsius, oxidation time: 3-10H, and oxidation atmosphere: dry oxygen and / or wet oxygen.

7. The method of producing a semiconductor device according to claim 6, wherein During the furnace tube thermal oxidation process, the ratio of the oxidation rates of the sidewalls and top surface of the polysilicon layer, the sidewalls of the first trench and the bottom wall of the first trench is (12-8):(6-3):

1.

8. A semiconductor device formed by the method of any one of claims 1 to 7, characterized in that The semiconductor device comprises: a first semiconductor material layer; a first trench extending from the top surface of the first semiconductor material layer to the interior of the first semiconductor material layer; a second trench extending from the bottom surface of the first trench to the interior of the first semiconductor material layer; the line width of the second trench is smaller than that of the first trench; and the line width of the upper end of the second trench is greater than that of the lower end of the second trench. The conductive region is formed by doping a preset thickness of conductive material from the bottom of the first and second trenches to the interior of the first semiconductor material layer.

9. The semiconductor device of claim 8, wherein, The sidewall of the second trench is a curved surface with an arc shape in any one cross section in the longitudinal direction.

10. The semiconductor device according to claim 8 or 9, characterized by The thickness of the conductive region in the longitudinal direction is 0.3-1.5 microns.

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