Method for manufacturing semiconductor device, semiconductor device, and electronic apparatus
By uniformly doping metals on the first and second surfaces of the epitaxial substrate, the problem of transistor leakage risk is solved, and the reliability of the device is improved.
Patent Information
- Application Number
- CN202211012757.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-23
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2042-08-23
AI Technical Summary
In existing technologies, transistors have long switching times, and high metal doping concentrations increase the risk of leakage current, affecting device reliability.
First metal doping is performed on both the first and second surfaces of the epitaxial substrate to form doped openings that expose the base region. The metal is then uniformly distributed through sputtering and annealing to reduce defects caused by metal doping.
This achieves a uniform distribution of metal atoms on both sides of the PN junction, reducing the risk of leakage current and improving the reliability of the device.
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Figure CN115346871B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, and an electronic device. Background Technology
[0002] Switching transistors are characterized by long lifespan, safety, reliability, and fast switching speed. They can control the switching of large currents with very small currents and are widely used in various switching circuits, such as commonly used switching power supply circuits, driver circuits, high-frequency oscillation circuits, analog-to-digital converter circuits, pulse circuits, and output circuits. The switching time of a transistor is one of the most important performance metrics. To reduce switching time, some designs often diffuse metals such as gold or platinum onto the back of the device. These designs typically have high gold and platinum doping concentrations. If a faster switching time is required, it may increase the risk of leakage current and even lead to device failure, affecting product reliability. Summary of the Invention
[0003] To overcome the aforementioned shortcomings in the prior art, the purpose of this application is to provide a method for manufacturing a semiconductor device, the method comprising:
[0004] An epitaxial substrate is provided, the epitaxial substrate including opposing first and second surfaces;
[0005] A base region and an emitter region are formed on the first surface of the epitaxial substrate, and a dielectric layer is covered on the base region and the emitter region.
[0006] The dielectric layer is etched to form a doped opening that exposes at least a portion of the base region;
[0007] A first metal is sputtered from one side of the first surface and one side of the second surface, thereby doping the first metal into the base region and the second surface of the epitaxial substrate;
[0008] A base and an emitter are formed on the first surface, and a collector is formed on the second surface.
[0009] In one possible implementation, the step of sputtering the first metal from one side of the first surface and one side of the second surface includes:
[0010] Platinum of 10nm-30nm was sputtered on the first and second surfaces at a sputtering power of 500W-1000W.
[0011] In one possible implementation, after the step of sputtering the first metal from one side of the first surface and one side of the second surface, the method further includes:
[0012] Platinum was removed from the first and second surfaces using aqua regia;
[0013] Platinum is annealed using a high-temperature furnace tube.
[0014] In one possible implementation, the step of annealing platinum through a high-temperature furnace tube includes:
[0015] Platinum is annealed for 15 to 60 minutes in a high-temperature furnace at an environment of 900 to 1000 degrees Celsius.
[0016] In one possible implementation, the doped opening includes annular or grid-shaped openings.
[0017] In one possible implementation, the step of forming a base region and an emitter region on a first surface of the epitaxial substrate, wherein the base region and the emitter region are covered by a dielectric layer, includes:
[0018] A dielectric layer is formed on the epitaxial substrate;
[0019] A base region window is formed on the dielectric layer to expose the epitaxial substrate;
[0020] Boron doping is performed on the epitaxial substrate through the base region window to form a base region and a dielectric layer covering the base region;
[0021] An emitter window is formed on the dielectric layer to expose the epitaxial substrate;
[0022] The epitaxial substrate is phosphorus-doped through the emitter region window to form an emitter region and a dielectric layer covering the emitter region.
[0023] In one possible implementation, the step of forming a base and an emitter on the first surface and a collector on the second surface includes:
[0024] Lead holes exposing the base region and emitter region are formed through photolithography and etching processes;
[0025] A second metal is deposited on the first surface and the second surface;
[0026] The base, the emitter, and the collector are formed by etching the second metal on the first and second surfaces.
[0027] In one possible implementation, the step of providing an epitaxial substrate includes:
[0028] Provide an N-type semiconductor epitaxial substrate.
[0029] Another object of this application is to provide a semiconductor device manufactured by the manufacturing method of the semiconductor device provided in this application.
[0030] Another object of this application is to provide an electronic device, which includes the semiconductor device provided in this application.
[0031] Compared with the prior art, this application has the following beneficial effects:
[0032] The semiconductor device manufacturing method, semiconductor device, and electronic device provided in this application involve forming a doping opening to expose the base region after forming the base region and emitter region, and then performing first metal doping on both the first and second surfaces of the semiconductor device. This ensures that the atoms of the first metal are uniformly distributed on both sides of the PN junction, reducing defects caused by the first metal doping and its impact on the terminal. Attached Figure Description
[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of the manufacturing process of semiconductor devices in the prior art;
[0035] Figure 2 A flowchart illustrating the steps of a method for manufacturing a semiconductor device according to an embodiment of this application;
[0036] Figure 3 One of the schematic diagrams illustrating the manufacturing process of a semiconductor device provided in the embodiments of this application;
[0037] Figure 4 A second schematic diagram illustrating the manufacturing process of a semiconductor device provided in an embodiment of this application;
[0038] Figure 5 This is a schematic diagram of the sub-steps of step S120;
[0039] Figure 6 The third schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this application;
[0040] Figure 7 Fourth schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this application;
[0041] Figure 8Fifth schematic diagram of the manufacturing process of a semiconductor device provided in the embodiments of this application;
[0042] Figure 9 Sixth schematic diagram of the manufacturing process of a semiconductor device provided in the embodiments of this application;
[0043] Figure 10 This is a schematic diagram of the sub-steps of step 150;
[0044] Figure 11 Seventh schematic diagram of the manufacturing process of a semiconductor device provided in the embodiments of this application;
[0045] Figure 12 This is the eighth schematic diagram of the manufacturing process of the semiconductor device provided in the embodiments of this application. Detailed Implementation
[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0047] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0048] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0049] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0050] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0051] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0052] Please refer to Figure 1 In some existing fast-switching transistor manufacturing methods, after forming the base region 130 and emitter region 140 on the front side of the epitaxial substrate 110 through doping, gold or platinum diffusion is only carried out from the back side of the epitaxial substrate 110. This will lead to a severe imbalance in the distribution of metal atoms on both sides of the PN junction, increasing the risk of device leakage.
[0053] In view of this, this embodiment provides a solution that can reduce the risk of device leakage and improve device reliability. The solution will be described in detail below.
[0054] Please see Figure 2 , Figure 2 This is a schematic diagram of the semiconductor device manufacturing method provided in this embodiment. The steps of the method are described in detail below.
[0055] Step S110: Provide an epitaxial substrate 110, the epitaxial substrate 110 including opposing first and second surfaces.
[0056] In this embodiment, an N-type semiconductor epitaxial substrate 110 may be provided.
[0057] In step S120, a base region 130 and an emitter region 140 are formed on the first surface of the epitaxial substrate 110, and a dielectric layer 120 is covered on the base region 130 and the emitter region 140.
[0058] Please refer to Figure 3 In this embodiment, a base region 130 and an emitter region 140 embedded in the epitaxial substrate 110 can be formed on the epitaxial substrate 110 by a doping process. During this process, a dielectric layer 120 covering the base region 130, the emitter region 140 and the first surface will be formed.
[0059] Step S130: Etch the dielectric layer 120 to form a doped opening that exposes at least a portion of the base region 130.
[0060] Optionally, in this embodiment, depending on the specific shape of the base region 130, the doped opening includes annular or grid-shaped openings.
[0061] Please refer to Figure 4 In this embodiment, after forming the base region 130 and the emitter region 140, a mask can be formed on the dielectric layer 120 by photolithography, exposing the dielectric layer 120 corresponding to the base region 130. Then, the dielectric layer 120 is etched to form doped openings exposing at least a portion of the base region 130. The mask is then removed to form... Figure 4 The structure shown.
[0062] Step S140: Sputter a first metal from one side of the first surface and one side of the second surface to dope the first metal onto the base region 130 and the second surface of the epitaxial substrate 110.
[0063] In this embodiment, after the doping opening is formed, a first metal doping can be performed on both the first and second surfaces of the epitaxial substrate 110. The first metal can be gold or platinum. This allows the concentration of the first metal doped in the base region 130 and the concentration of the first metal doped from the second surface of the epitaxial substrate 110 to be more similar.
[0064] In step S150, a base 203 and an emitter 204 are formed on the first surface, and a collector 201 is formed on the second surface.
[0065] In this embodiment, after the doping of the first metal is completed, a base electrode 203 can be formed in the base region 130, an emitter electrode 204 can be formed in the emitter region 140, and a collector electrode 201 can be formed on the second surface.
[0066] Based on the above design, the semiconductor device manufacturing method provided in this application involves forming a doping opening that exposes the base region 130 after forming the base region 130 and the emitter region 140, and then performing first metal doping on both the first and second surfaces of the semiconductor device. This ensures that the atoms of the first metal are uniformly distributed on both sides of the PN junction, reducing defects caused by the first metal doping and its impact on the terminal.
[0067] In one possible implementation, in step S140, 10nm-30nm of platinum can be sputtered on the first and second surfaces at a sputtering power of 500W-1000W.
[0068] Furthermore, after sputtering the first metal from one side of the first surface and one side of the second surface, the platinum on the first surface and the second surface is removed by aqua regia, and then the platinum is annealed by a high-temperature furnace tube.
[0069] Specifically, the device after sputtering the first metal can be subjected to high-temperature boiling with aqua regia for 10 to 30 minutes to remove platinum from the first and second surfaces that has not diffused into the epitaxial substrate 110. Then, the platinum is annealed for 15 to 60 minutes in a high-temperature furnace at an environment of 900 to 1000 degrees Celsius.
[0070] In one possible implementation, please refer to Figure 5 Step S120 may include the following sub-steps.
[0071] Step S121: A dielectric layer 120 is formed on the epitaxial substrate 110.
[0072] Please refer to Figure 6 In this embodiment, after the epitaxial substrate 110 is provided, an oxide layer can be formed on the first surface of the epitaxial substrate 110 as the dielectric layer 120 by a thermal oxidation process.
[0073] Step S122: A base region window 123 is formed on the dielectric layer 120 to expose the epitaxial substrate 110.
[0074] Please refer to Figure 7 In this embodiment, a base region window 123 exposing the epitaxial substrate 110 can be formed by removing part of the dielectric layer 120 through photolithography and etching processes.
[0075] In step S123, the epitaxial substrate 110 is boron doped through the base region window 123 to form a base region 130 and a dielectric layer 120 covering the base region 130.
[0076] Please refer to Figure 8 In this embodiment, boron can be doped into the base region window 123 using implantation and diffusion techniques to form the base region 130. Simultaneously, this process also forms a dielectric layer 120 covering the base region 130.
[0077] Step S124: Form an emitter window 124 on the dielectric layer 120 to expose the epitaxial substrate 110.
[0078] Please refer to Figure 9In this embodiment, a portion of the dielectric layer 120 can be removed using photolithography and etching processes to form an emitter window 124 exposing the epitaxial substrate 110. The emitter window 124 does not coincide with the base region 130.
[0079] In step S125, phosphorus doping is performed on the epitaxial substrate 110 through the emitter window 124 to form an emitter region 140 and a dielectric layer 120 covering the emitter region 140.
[0080] In this embodiment, phosphorus ions can be doped into the emitter window 124 using phosphorus pre-diffusion and diffusion techniques to form the emitter region 140. Simultaneously, this process also forms a dielectric layer 120 covering the emitter region 140, ultimately forming a structure as shown below. Figure 3 The structure shown.
[0081] In one possible implementation, please refer to Figure 10 Step S150 may include the following sub-steps.
[0082] Step S151: A lead hole is formed to expose the base region 130 and the emitter region 140 through photolithography and etching processes.
[0083] In this embodiment, please refer to Figure 11 ,exist Figure 4 After the first metal is doped, the dielectric layer 120 can be further etched to form a lead hole that exposes the base region 130 and the emitter region 140.
[0084] Step S152: Deposit a second metal on the first surface and the second surface.
[0085] Step S153: Etch the second metal on the first surface and the second surface to form the base 203, the emitter 204 and the collector 201.
[0086] In this embodiment, please refer to Figure 12 In this embodiment, a second metal can be deposited on the first surface and the second surface, and then the second metal can be etched to form a base 203 in the base region 130, an emitter 204 in the emitter region 140, and a collector 201 in the second surface.
[0087] Based on the same inventive concept, this embodiment also provides a semiconductor device, which is manufactured by the manufacturing method of the semiconductor device provided in this embodiment.
[0088] This embodiment also provides an electronic device, which includes the semiconductor device provided in this embodiment.
[0089] In summary, the semiconductor device manufacturing method, semiconductor device, and electronic device provided in this application involve forming a doping opening to expose the base region after forming the base region and emitter region, and then performing first metal doping on both the first and second surfaces of the semiconductor device. This ensures that the atoms of the first metal are uniformly distributed on both sides of the PN junction, reducing defects caused by the first metal doping and its impact on the terminal.
[0090] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0091] The above descriptions are merely various embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The method includes: An epitaxial substrate is provided, the epitaxial substrate including opposing first and second surfaces; A base region and an emitter region are formed on the first surface of the epitaxial substrate, and a dielectric layer is covered on the base region and the emitter region. The dielectric layer is etched to form a doped opening that exposes at least a portion of the base region; A first metal is sputtered from one side of the first surface and one side of the second surface, causing the first metal to be doped into the base region and into the second surface of the epitaxial substrate to form a collector region. The first metal atoms are uniformly distributed on both sides of the PN junction formed by the base region and the collector region. A base and an emitter are formed on the first surface, and a collector is formed on the second surface.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The step of sputtering the first metal from one side of the first surface and one side of the second surface includes: Platinum of 10nm-30nm was sputtered on the first and second surfaces at a sputtering power of 500W-1000W.
3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, After the step of sputtering the first metal from one side of the first surface and one side of the second surface, the method further includes: Platinum was removed from the first and second surfaces using aqua regia; Platinum is annealed using a high-temperature furnace tube.
4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The step of annealing platinum in a high-temperature furnace tube includes: Platinum is annealed for 15 to 60 minutes in a high-temperature furnace at an environment of 900 to 1000 degrees Celsius.
5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The doped openings include annular or grid-shaped openings.
6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The step of forming a base region and an emitter region on a first surface of the epitaxial substrate, wherein the base region and the emitter region are covered with a dielectric layer, includes: A dielectric layer is formed on the epitaxial substrate; A base region window is formed on the dielectric layer to expose the epitaxial substrate; Boron doping is performed on the epitaxial substrate through the base region window to form a base region and a dielectric layer covering the base region; An emitter window is formed on the dielectric layer to expose the epitaxial substrate; The epitaxial substrate is phosphorus-doped through the emitter region window to form an emitter region and a dielectric layer covering the emitter region.
7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The step of forming a base and an emitter on the first surface and a collector on the second surface includes: Lead holes exposing the base region and emitter region are formed through photolithography and etching processes; A second metal is deposited on the first surface and the second surface; The base, the emitter, and the collector are formed by etching the second metal on the first and second surfaces.
8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The epitaxial substrate is an N-type semiconductor epitaxial substrate.
9. A semiconductor device, characterized in that, The semiconductor device is manufactured by the semiconductor device manufacturing method according to any one of claims 1-8.
10. An electronic device, characterized in that, The electronic device includes the semiconductor device of claim 9.
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