Method for manufacturing an integrated circuit structure and integrated circuit structure

Abstract

The present disclosure relates to a method for fabricating an integrated circuit structure and an integrated circuit structure. A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top end of the first semiconductor strip and a second width at about 60 nm below the top end of the first semiconductor strip. The first width is less than about 5 nm and the second width is less than about 14.5 nm. The trench is filled with a dielectric material to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes above the isolation region to form a protruding fin. The protruding fin has a height that is less than the depth. A gate stack is formed to extend over sidewalls and a top surface of the protruding fin.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductors, and in particular, to a method for fabricating an integrated circuit structure and an integrated circuit structure. BACKGROUND

[0002] Technological advances in integrated circuit (IC) materials and design have resulted in several generations of ICs, with each generation having features that are significantly smaller and more complex than the last. As ICs evolve, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometry size (e.g., the size of the features that can be created using a process) has decreased.

[0003] This shrinking process has also increased the complexity of processing and manufacturing ICs, and to achieve these advances, similar developments in IC processing and manufacturing have been needed. For example, fin-type field effect transistors (FinFETs) have been introduced to replace planar transistors. The structure of FinFETs and methods of fabricating FinFETs are under development.

[0004] Formation of FinFETs generally includes forming a semiconductor fin, forming a dummy gate electrode on the semiconductor fin, etching certain portions of the semiconductor fin to form a recess, performing epitaxy to regrow source / drain regions from the recess, and replacing the dummy gate electrode with a replacement gate. SUMMARY

[0005] According to one embodiment of the present disclosure, a method for fabricating an integrated circuit structure is provided, comprising: etching a semiconductor substrate to form a first trench between a first semiconductor strip and a second semiconductor strip, and a second trench between the second semiconductor strip and a third semiconductor strip, wherein the second trench is deeper than the first trench; filling the first trench and the second trench to form a first isolation region between the first semiconductor strip and the second semiconductor strip, and a second isolation region between the second semiconductor strip and the third semiconductor strip; recessing the first isolation region and the second isolation region, wherein a top of the first semiconductor strip forms a first protruding fin, a top of the second semiconductor strip forms a second protruding fin, and a top of the third semiconductor strip forms a third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch, the second protruding fin is spaced apart from the third protruding fin by a second pitch, the second pitch is substantially equal to the first pitch, wherein a bending value of the first protruding fin, the second protruding fin, and the third protruding fin is less than about 4 nm; forming a gate stack on the second protruding fin; and forming a source region and a drain region based on the second protruding fin, wherein the gate stack is between the source region and the drain region.

[0006] According to another embodiment of the disclosure, an integrated circuit structure is provided, comprising: a first protruding fin having a first width at about 5 nm below a first top end of the first protruding fin and a second width at about 60 nm below the first top end of the first protruding fin, wherein the first width is less than about 5 nm and the second width is less than about 14.5 nm; a second protruding fin having a third width at about 5 nm below a second top end of the second protruding fin and a fourth width at about 60 nm below the second top end of the second protruding fin, wherein the third width is less than about 5 nm and the fourth width is less than about 14.5 nm; and a first shallow trench isolation region between the first protruding fin and the second protruding fin, wherein the first shallow trench isolation region has a depth, wherein a first fin height of the first protruding fin is less than the depth and a bending value of the first protruding fin and the second protruding fin is less than 4 nm.

[0007] According to another embodiment of the disclosure, an integrated circuit structure is provided, comprising: a bulk semiconductor substrate; a first protruding fin, a second protruding fin, and a third protruding fin adjacent to each other, the second protruding fin being between the first protruding fin and the third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch and the second protruding fin is spaced apart from the third protruding fin by a second pitch, wherein a difference between the first pitch and the second pitch is less than about 4 nm; a first isolation region above the bulk semiconductor substrate and between the first protruding fin and the second protruding fin; and a second isolation region above the bulk semiconductor substrate and between the second protruding fin and the third protruding fin, wherein a bending value of the second protruding fin and the third protruding fin is less than about 4 nm. BRIEF DESCRIPTION OF DRAWINGS

[0008] When read in conjunction with the accompanying Figure One Aspects of the disclosure can best be understood from the following detailed description when read with the accompanying drawings. It is emphasized that various features are not to scale. In fact, the dimensions of various features can be arbitrarily increased or decreased for the sake of discussion.

[0009] Figures 1-4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figures 7-19 and Figures 22-26 FIGS. 1-3 show perspective views of intermediate stages of forming a fin field effect transistor (FinFET) according to some embodiments.

[0010] Figure 20A , Figure 20B and Figure 20CA top view and a cross-sectional view of a curved protruding semiconductor fin are shown, in accordance with some embodiments.

[0011] Figure 21A 、 Figure 21B and Figure 21C A top view and a cross-sectional view of a vertical protruding semiconductor fin are shown, in accordance with some embodiments.

[0012] Figure 27 A determination of a curvature of an adjacent semiconductor fin is shown, in accordance with some embodiments.

[0013] Figures 28-30 Embodiments to reduce fin curvature are shown, in accordance with some embodiments.

[0014] Figure 31 A process flow for forming semiconductor fins and FinFETs is shown, in accordance with some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments where the first feature and the second feature are formed directly contacting one another, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not directly contact one another. Furthermore, the present disclosure can refer to a number of examples using a corresponding reference numeral and / or letter. Such repetition is for simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] A method and corresponding structure to reduce fin bending is provided. According to some embodiments of the present disclosure, a semiconductor strip is formed by etching a semiconductor substrate. Shallow trench isolation (STI) regions are formed between the semiconductor strips. The STI regions are recessed, with portions of the top surface of the remaining STI regions forming protruding semiconductor fins. The fin height of the protruding semiconductor fins is kept less than the height of the STI regions. By keeping the fin height less than the height of the STI regions, the fin bending can be less than a critical value, such that dummy gate stacks and remnants of replacement gate stacks left over in a corresponding patterning process can be eliminated. Embodiments discussed herein are to provide examples to enable or use the subject matter of the present disclosure, and modifications that are within the intended scope of the different embodiments will be readily apparent to those of ordinary skill in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments can be discussed as being performed in a particular order, other method embodiments can be performed in any logical order.

[0018] Figures 1-4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figures 7-19 and Figures 22-26 shows a cross-sectional view of an intermediate stage of forming a fin field effect transistor (FinFET) according to some embodiments of the present disclosure. The corresponding process is also reflected in the process flow shown in Figure 31 .

[0019] In Figure 1 , a substrate 20 is provided. The substrate 20 can be a semiconductor substrate, e.g., a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc. The semiconductor substrate 20 can be a portion of a wafer 10, e.g., a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer can be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates can also be used, e.g., a multilayer or graded substrate. In some embodiments, the semiconductor material of the semiconductor substrate 20 can include silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0020] According to some embodiments, the substrate 20 is a silicon substrate. A germanium-containing semiconductor region 22B is formed as a surface region of the substrate 20 and can be used to form a p-type transistor. According to some embodiments, the germanium-containing semiconductor region 22B includes silicon germanium (SiGe), SiGeSn, GeSn, etc., and the germanium percentage can be in a range between about 10% and about 40%. A semiconductor region 22A is formed at the same level as the semiconductor region 22B and can be formed of or include silicon. The semiconductor region 22A can be free of germanium.

[0021] A pad oxide layer 24 and a hard mask layer 26 are formed on the semiconductor substrate 20. The pad oxide layer 24 can be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 24 is formed by a deposition process. The pad oxide layer 24 acts as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 26. The pad oxide layer 24 can also act as an etch stop layer for etching the hard mask layer 26. According to some embodiments of the present disclosure, the hard mask layer 26 is formed of silicon nitride, e.g., using atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), etc. A patterned photoresist 28 is formed on the hard mask layer 26. The corresponding process is shown as process 202 in the process flow 200 shown in Figure 31

[0022] Next, the hard mask layer 26 is patterned with an etching process using the patterned photoresist 28 as an etching mask, thereby forming a hard mask 26', as shown in Figure 2 The corresponding process is shown as process 204 in the process flow 200 shown in Figure 31 The pad oxide layer 24 is then etched, and the remaining portion of the pad oxide layer is denoted as pad oxide layer 24'. The semiconductor substrate 20 is thus exposed. The photoresist 28 is removed before or after the patterning of the pad oxide layer 24. The resulting structure is shown in Figure 2

[0023] Referring to Figure 3 , the exposed semiconductor substrate 20 is etched with an anisotropic etching process, forming a trench 32. The corresponding process is shown as process 206 in the process flow 200 shown in Figure 31 ​​The process flow 200 shown is illustrated as process 206. The portion between adjacent trenches 32 of the semiconductor substrate 20 is hereinafter referred to as semiconductor strips 30 (including 30A and 30B). The trenches 32 may have stripe shapes parallel to each other (when viewed in a top view of the wafer 10), and the trenches 32 are positioned close to each other. According to some embodiments of this disclosure, the aspect ratio (depth to width ratio) of the trenches 32 is greater than about 7 and may be greater than about 10. The semiconductor strips 30 include semiconductor strip 30A, which may include a silicon region 22A. The semiconductor strips 30 also include semiconductor strip 30B, which may include a silicon strip as a lower portion and a germanium-containing region strip 22B as an upper portion (which is the remaining portion of the germanium-containing region 22B). After forming the trenches 32, the hard mask 26′ may be removed, as... Figure 3 As shown, or some parts of the hard mask 26′ can be preserved.

[0024] Figure 4 and Figure 5A The patterning (cutting) of the semiconductor strip 30 is shown. (Reference) Figure 4 This can form a three-layer etch mask 34. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 208. The etching mask 34 may include a bottom layer (sometimes also called a lower layer) 34BL, an intermediate layer 34ML above the bottom layer 34BL, and a top layer (sometimes also called an upper layer) 34TL above the intermediate layer 34ML. According to some embodiments, the bottom layer 34BL and the top layer 34TL are formed of photoresist, and the bottom layer 34BL is cross-linked. The intermediate layer 34ML may be formed of an inorganic material, which may be a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), etc. The intermediate layer 34ML has high etch selectivity relative to the top layer 34TL and the bottom layer 34BL, therefore the top layer 34TL can be used as an etching mask for patterning the intermediate layer 34ML, and the intermediate layer 34ML can be used as an etching mask for patterning the bottom layer 34BL. The top layer 34TL is patterned to form openings 37.

[0025] like Figure 4 The etch mask 34 shown is used to cut the semiconductor strip 30, wherein an anisotropic etching process is performed to etch the intermediate layer 34ML, the bottom layer 34BL, the hard mask 26′ (if any remains), and the pad oxide layer 24′, as well as the semiconductor strip 30. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 210. An example of a diced semiconductor strip 30B is shown in... Figure 5A As shown in the image. Figure 5B It shows Figure 5AThe cross-section 5B-5B of the structure shown illustrates a semiconductor strip 30A. The cross-sectional view of semiconductor strip 30B is similar to that of semiconductor strip 30A, except that the top of semiconductor strip 30B may be a germanium-containing region.

[0026] Figure 6A , Figure 6B , Figure 7 and Figure 8 The formation of the STI region according to some embodiments is illustrated. Reference Figure 6A The liner dielectric 36 is formed at the bottom of the trench 32 and extends along the sidewalls of the semiconductor strip 30. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 212. The liner dielectric 36 may be a conformal layer, with the thicknesses of its horizontal and vertical portions being approximately equal, for example, with a thickness variation of less than 20% or 10%. According to some embodiments of this disclosure, the liner dielectric 36 is formed using deposition methods such as chemical vapor deposition (CVD), subatmospheric pressure chemical vapor deposition (SACVD), atomic layer deposition (ALD), etc. The liner dielectric 36 may be formed of, or comprise, silicon oxide, silicon nitride, or a composite layer thereof. Figure 6B It shows Figure 6A The structure shown is section 6B-6B.

[0027] Then, dielectric material 38 is deposited to fill the remaining portion of trench 32, thereby obtaining Figure 7 The structure is shown in the figure. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 214. The deposition method for the dielectric material 38 can be selected from flowable chemical vapor deposition (FCVD), spin coating, CVD, ALD, high-density plasma chemical vapor deposition (HDPCVD), LPCVD, etc. According to some embodiments using FCVD, a silicon- and nitrogen-containing precursor (e.g., trimethylsilylamine (TSA) or dimethylsilylamine (DSA)) is used, thus the resulting dielectric material 38 is flowable. According to alternative embodiments of this disclosure, the flowable dielectric material 38 is formed using an alkylaminosilane-based precursor. The deposition temperature can be in the range of about 300°C to about 1100°C. The precursor pressure can be in the range of about 0.01 Torr to about 760 Torr. The deposition time can be less than 10 hours.

[0028] After deposition of the dielectric material 38, an anneal / cure process is performed which converts the flowable dielectric material 38 into a solid dielectric material. The cured dielectric material 38 is also referred to as the dielectric material 38. According to some embodiments of the present disclosure, the anneal process is performed in an oxygen-containing environment. The anneal temperature can be above about 200 °C, for example, in a range between about 200 °C and about 700 °C. During annealing, an oxygen-containing process gas is introduced into the process chamber in which the wafer 10 is placed. The oxygen-containing process gas can include oxygen (O2), ozone (O3), or a combination thereof. Steam (H2O) can also be used, and can be used with or without oxygen (O2) or ozone. As a result of the anneal process, the dielectric layer 38 is solidified and cured.

[0029] A planarization process, for example, a chemical mechanical polishing (CMP) process or a mechanical grinding process, is then performed, as shown in Figure 8 . The corresponding process is shown as process 216 in the process flow 200 shown in Figure 31 . The STI region 40 is thus formed including the remaining portion of the liner dielectric 36 and the dielectric material 38. The hard mask 26' (if remaining) or the liner oxide layer 24' can be used as a CMP stop layer, and thus the top surface of the STI region 40 is flush with the top surface of the hard mask 26' or the liner oxide layer 24'.

[0030] Figure 9 Recessing of the STI region 40 is shown, the recessing process being performed, for example, by an isotropic etch process. The corresponding process is shown as process 218 in the process flow 200 shown in Figure 31 . The height of the remaining STI region 40 can be in a range between about 10 nm and about 80 nm. The etch process can be a dry etch process, which can be performed using a mixture of NF3and NH3or a mixture of HF and NH3. Alternatively, the etch process can be a wet etch process, which can be performed using a dilute HF solution as an etchant.

[0031] Figure 10 Formation and planarization of a liner layer 42 is shown. The corresponding process is shown as process 220 in the process flow 200 shown in Figure 31 . According to some embodiments, the liner layer 42 includes an oxide layer (e.g., a silicon oxide layer), a nitride layer (e.g., a silicon nitride layer), or a composite layer including an oxide layer and a nitride layer overlying or underlying the oxide layer. The liner layer 42 fills the recess formed as a result of recessing the STI region 40. Next, a planarization process is performed. The planarization process can be performed using the semiconductor strip 30 as a CMP stop layer. Thus, after the planarization process, the semiconductor strip 30 is exposed, and the top surface of the semiconductor strip 30 is flush with the top surface of the liner layer 42.

[0032] Then remove the liner layer 42. Next, refer to... Figure 11 This causes the STI region 40 to be recessed, forming groove 44. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 222. Therefore, the top of the semiconductor strip 30 protrudes above the top surface of the remainder of the STI region 40 to form protruding fins 48 (including 48A and 48B). Etching can be performed using a dry etching process, where, for example, HF and NH3 are used as etching gases. Plasma may be generated during the etching process. Argon gas may also be included. According to an alternative embodiment of this disclosure, the recess in the STI region 40 is performed using a wet etching process. For example, the etching chemicals may include HF. The protruding fins 48 include protruding fins 48A and 48B, where protruding fin 48A is a silicon fin and protruding fin 48B is a silicon-germanium fin or includes silicon-germanium fins.

[0033] The protruding fin 48 may be subject to bending. According to some embodiments, a process is selected to reduce bending of the protruding fin 48. The process can also be controlled to make certain portions of the protruding fin 48 (e.g.) Figure 28 The portion 48′ is extended laterally and positioned at a selected location to reinforce the protruding fin 48 and reduce the curvature of the protruding fin 48. (Then refer to...) Figures 27 to 30 Discuss the details of reducing bending.

[0034] Figure 27 The bending amplitude of the protruding fin 48 is shown. The bending amplitude is also referred to as the bending value of the protruding fin 48. Two semiconductor strips 30 are adjacent to each other. The protruding fin 48 is the top of the semiconductor strip 30, which is higher than the top surface of the STI region 40. The left and right semiconductor strips 30 have center lines 102A and 102B, respectively. When the protruding fin 48 bends, the spacing between the center lines 102A and 102B at the higher horizontal plane is different from the spacing between the center lines 102A and 102B at the lower horizontal plane. Since the top of the protruding fin 48 is rounded, the top pitch P of the protruding fin 48 is measured at a horizontal plane 5 nm below the top of the protruding fin 48. T The top pitch is the distance between the median lines 102A and 102B. The bottom pitch P of the protruding fin 48 is measured at the bottom of the protruding fin 48. B Alternatively, the bottom pitch P can be measured at the top of STI zone 40. B Difference | (P) T –P B | That is, pitch P T and P B The absolute value of the difference between them is called the curvature (value) B of the protruding fin 48. The curvature value B can also be calculated as |[(W TL +W TR) / 2 + S TLR ]-[(W BL +W BR ) / 2 + S BLR ]|, where width W TL and W TR is the top width of the protruding fin 48 (measured 5 nm below the top end), width W BL and W BR is the bottom width of the protruding fin 48. Spacing S TLR is the top spacing between the left and right protruding fins 48. Spacing S BLR is the bottom spacing between the left and right protruding fins 48.

[0035] It has been found that a bend value B equal to 4 nm is a critical value that has a significant impact on the resulting device. For example, as will be discussed with reference to Figure 20A , Figure 20B and Figure 20C , when the bend value B is greater than 4 nm, residue 54”( Figure 20B ) can be left behind when the dummy gate electrode layer is patterned to form the dummy gate, which cannot be removed. In addition, residue of the replacement gate stack can also be left behind when the bend value B is greater than 4 nm in the subsequent etching of the replacement gate stack. These residues can electrically short the features on the opposite side of the residue. On the other hand, when the bend value B is less than 4 nm, no residue is found. Therefore, the bend value B is to be kept below 4 nm. Furthermore, when the ratio B / H Figure 27 ) is the height of the protruding fin 48. Throughout the description, the bend value B that does not cause residue is referred to as the in-spec bend value B, which is less than 4 nm, and the in-spec bend value B satisfies the requirement (B / H < 0.1).

[0036] Figure 28 A schematic of a structure is shown, which includes the semiconductor strip 30, the STI region 40, and the gate dielectric 52’ / 80, which can be either the dummy gate dielectric 52’ or the replacement gate dielectric 80( Figure 26It was also found that the degree to which the semiconductor strip 30 is embedded in the STI region 40 (and the degree to which the semiconductor strip 30 protrudes above the STI region 40) affects the bending value B of the protruding fin 48. When more of the semiconductor strip 30 is embedded in the STI region 40 rather than protruding from it, the bending value B will be less than the specification bending value B. Or, when the ratio H / D is less than 1, the bending value B will be less than the specification bending value B. Throughout the specification, when the bending value B is described as less than 4 nm, the bending value B can be 0 nm, or it can be a non-zero value, for example, greater than about 0.5 nm or greater than about 1 nm. Therefore, the bending value B can be about 0 nm, or in the range between about 1 nm and about 4 nm. Conversely, when the height H of the protruding fin 48 is equal to or greater than the depth D of the adjacent STI region 40 (making H / D equal to or greater than 1), the bending value B is greater than the specification bending value B.

[0037] The ratio H / D can also be in the range of about 0.2 to about 0.9 to keep the bend value B within specifications with sufficient process margin. The ratio H / D can also be in the range of about 0.2 to about 0.5 to further reduce bend, for example, when the semiconductor strip 30 is very narrow. According to some embodiments of this disclosure, when the ratio H / D is less than 1.0 (e.g., when the depth D is in the range of about 55 nm to about 80 nm, and when the height H is in the range of about 10 nm to about 33 nm), the bend value B is within specifications. The ratio B / H can be less than about 0.1. Reducing the ratio H / D can also effectively reduce the bend value B of very fine and tall fins. For example, a fine and tall fin according to an embodiment of this disclosure may have a width W of less than 5 nm. a,5 Width W less than 6.5nm a,20 Width W less than 8.3nm a,40 and a width W less than 14.5nm a,60 Width W a,5 W a,20 W a,40 and W a,60 Measurements were taken at horizontal planes 5 nm, 20 nm, 40 nm, and 60 nm below the tip of the protruding fin 48. According to some embodiments, the fin height H can be in the range of approximately 40 nm to approximately 80 nm.

[0038] like Figure 28 , Figure 29 and Figure 30 As shown, according to some embodiments, the protruding fin 48 may have a portion 48' that extends laterally and is wider than the upper and lower portions of the protruding fin 48. The formation of the wider portion 48' can be achieved by adjusting process conditions, for example by adjusting... Figure 5ABias power in the illustrated process to achieve. For example, a lower bias power can be used when etching portions of the semiconductor substrate on opposite sides of the lateral extension portion 48', while a larger bias power can be used before and after forming the lateral extension portion 48'. The lateral extension portion 48' can strengthen the protruding fin 48 to reduce the bowing. In addition, the position of the lateral extension portion 48' also affects the bowing. According to some embodiments, the lateral extension portion 48' includes some portions that are higher than the top point 40 T ( Figure 28 ) of the STI region 40. The bottom of the lateral extension portion 48' can be flush with the top point 40 T , or slightly lower than the top point 40 T .

[0039] Figure 29 An embodiment is shown in which two STI regions 40 are adjacent to each other, and the semiconductor strip 30 and the protruding fin 48 are located on opposite sides of the STI regions 40. According to some embodiments, to ensure that the bowing values B of the three illustrated protruding fins 48 are all within the specification, the ratios H1 / D1 and H2 / D2 are both less than 1. Otherwise, assuming that H1 / D1 is greater than 1 (e.g., when D1 is in a range between about 10 nm and about 30 nm) and H2 / D2 is less than 1 (e.g., when D2 is in a range between about 55 nm and about 80 nm), the bowing value B measured between the left protruding fin 48 and the middle protruding fin 48 can be greater than 4 nm (out of specification), and the bowing value B measured between the middle protruding fin 48 and the right protruding fin 48 can be less than 4 nm (within specification). Again, the bowing value B can or can not be a non-zero value, e.g., the bowing value B is in a range between about 1 nm and about 4 nm. Therefore, to have the bowing values B of the protruding fins 48 have in-spec bowing values B, both H1 / D1 and H2 / D2 are designed to be less than 1, and can be in a range between about 0.2 and about 0.9. In addition, the width W2 can be greater than the width W1, e.g., the ratio W2 / W1 is greater than 2 or 3. This can further exacerbate the bowing of the middle protruding fin 48. Having both H1 / D1 and H2 / D2 less than 1 can reduce the bowing. In Figure 30 , the ratios D3 / D1, D3 / D2, D4 / D1, and D4 / D2 can be greater than about 1.2, greater than about 1.5, or greater than about 2, without affecting the bowing value B to be out of specification.

[0040] Figure 30 An embodiment is shown in which two STI regions 40 are adjacent to each other, and the semiconductor strip 30 and the protruding fin 48 are located on opposite sides of the STI regions. It is also found that when more than two protruding fins 48 are formed adjacent to each other, the spacing of one fin from its adjacent fins can be designed to be uniform and have values close to each other to reduce the fin bowing. For example, in Figure 30 , the spacings S a and Sb When the spacing S a and S b are substantially equal to each other, e.g., when the spacing difference |(S a -S b | is less than 4 nm, the bending value B of the protruding fin is within specification regardless of whether the ratio H1 / D1 and / or H2 / D2 is greater than 1 or less than 1, and B / H1 and B / H2 can remain less than 0.1. Or stated differently, when one or both of the requirements (H / D < 1) and (|(S a -S b | < 4 nm) are met, the corresponding protruding fin 48 will have a bending value B that is within specification.

[0041] Further, the depth D2 can be greater than the depth D1, e.g., the ratio D2 / D1 is greater than about 1.2, greater than about 1.5, or greater than about 2, or greater than about 5. Further, the ratio (H2+D2) / (H1+D1) can also be greater than about 1.2, greater than about 1.5, or greater than about 2, where the values (H2+D2) and (H1+D1) are the corresponding depths of the trench 32 Figure 5A ) in which the STI region 40 is formed. This can further exacerbate the bending of the protruding fin 48 in the middle, as the STI region 40 exerts different stresses from opposite sides. Where both of the requirements (H / D < 1) and (|(S a -S b | < 4 nm) are met, the bending can be reduced.

[0042] According to some embodiments, to ensure that all protruding fins in the entire die and wafer have a bending value within specification, all fins in the entire die and wafer meet at least one or both of the requirements (H / D < 1) and (|(S a -S b | < 4 nm) in any combination. For example, in a device die, a first plurality of protruding fins can have a bending value within specification because they meet the requirement (H / D < 1); a second plurality of fins can have a bending value within specification because they meet the requirement (|(S a -S b | < 4 nm); a third plurality of fins have a bending value within specification because they meet both of the requirements (H / D < 1) and (|(S a -S b | < 4 nm). No protruding fin in the die and wafer will simultaneously fail both of the requirements (H / D < 1) and (|(S a -S b | < 4 nm). Likewise, the bending value B can or can not be a non-zero value, e.g., the bending value is in a range between about 1 nm and about 4 nm.

[0043] Figure 12The deposition of the silicon capping layer 50 and the dummy gate dielectric layer 52 above the silicon capping layer 50 is shown. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 224. According to some embodiments, the silicon capping layer 50 is formed by deposition. According to some embodiments, the silicon capping layer 50 is deposited using a silicon-containing precursor comprising silane, disilane, dichlorosilane (DCS), trichlorosilane (SiHCl3), chlorosilane (SiH3Cl), etc. Deposition can be performed using a conformal deposition process such as CVD or ALD. When using ALD, the aforementioned precursor can be pulsed and purged, followed by pulsed and purged another process gas, such as H2. Alternating pulsed and purged gas types are used to increase the thickness of the silicon capping layer 50 to the desired thickness. The ALD process can be a thermal ALD process, for example, performed at a temperature in the range of about 350°C to about 500°C. When using CVD, precursors such as silane, disilane, HMDS, DCS, H2, and / or those described above can be used.

[0044] The dummy gate dielectric layer 52 is formed concurrently with the gate dielectric of the input / output (IO) device, and is therefore alternatively referred to as the IO dielectric. According to some embodiments, the dummy gate dielectric layer 52 comprises silicon oxide.

[0045] Figure 13 The formation of the dummy gate electrode layer 54 is shown. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 226. According to some embodiments, the dummy gate electrode layer 54 comprises polycrystalline silicon or amorphous silicon. This formation can be performed using precursors including: silane, silane, dichlorosilane (DCS), trisilane (Si3H8), and advanced silanes (Si...). n H 2n+2The precursors can be silanes such as dimethylaminosilane (SiH3[N(CH3)2], DMAS), ethylmethylaminosilane (SiH3[N(CH3C2H5)], EMAS), diethylaminosilane (SiH3[N(C2H5)2], DEAS), ethylisopropylaminosilane (SiH3[N(C2H5C3H7)], EIPAS), diisopropylaminosilane (SiH3[N(C3H7)2], DIPAS), dipropylaminosilane (SiH3[N(C3H7)2], DPAS), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and chlorosilane (SiH3Cl). The pressure of the precursor can be between approximately 0.1 Torr and approximately 5 Torr. The temperature for growing the dummy gate electrode layer 54 can be between approximately 100°C and approximately 750°C. Depending on the temperature, growth rate of the dummy gate electrode layer 54, and other process conditions, the dummy gate electrode layer 54 can be an amorphous silicon layer, a polycrystalline silicon layer, or a mixture thereof. CVD, ALD, or other deposition processes can also be used. The top surface of the deposited dummy gate electrode layer 54 is higher than the top surface of the protruding fin 48. A planarization process can then be performed to flatten the top surface of the dummy gate electrode layer 54.

[0046] According to some embodiments, a pad layer 56, which may be formed of silicon nitride, silicon oxide, etc., may be deposited on the top surface of the dummy gate electrode layer 54. The pad layer 56 is used to perform other processes, which will not be discussed here. For example, a polysilicon layer 57 may be deposited on the pad layer 56. Next, the polysilicon layer 57 and the pad layer 56 are removed. Then, according to some embodiments, the dummy gate electrode layer 54 may be recessed (thinned) to a desired thickness. The resulting structure is as follows: Figure 14 As shown. According to an alternative embodiment, the pad layer 56 is not deposited, and the dummy gate electrode layer 54 is polished to the desired thickness.

[0047] Figures 15 to 19 The diagram illustrates the formation of a dummy gate stack using a dual-patterning process. It can be understood that a single-patterning or quad-patterning process may also be used, depending on the device requirements.

[0048] refer to Figure 15 A hard mask layer is formed. The hard mask layer may include an oxide layer, a nitride layer, or a composite layer thereof. According to some embodiments, the hard mask layer includes layers 58 and 60, which may include a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.

[0049] A core layer 62 is deposited over hard mask layers 58 and 60. Core layer 62 may be formed of or include amorphous silicon, amorphous carbon, tin oxide, etc. An etch mask 64 is formed over core layer 62 and may be a three-layer etch mask 64. The etch mask 64 may include a bottom layer 64BL, an intermediate layer 64ML above the bottom layer 64BL, and a top layer 64TL above the intermediate layer 64ML. According to some embodiments, the bottom layer 64BL and the top layer 64TL are formed of photoresist, and the bottom layer 64BL is cross-linked. The intermediate layer 64ML may be formed of an inorganic material, such as a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), or an oxide (e.g., silicon oxide). The top layer 64TL is patterned.

[0050] Then, multiple etching processes are performed using an etching mask 64 to define a pattern, thereby etching the mandrel layer 62 to form the mandrel 62'. The corresponding processes are as follows: Figure 31 The process flow 200 shown is illustrated as process 228. After the patterning process, the remaining portion of the etched mask 64 is removed. The resulting structure is as follows: Figure 16 As shown.

[0051] refer to Figure 17 A spacer layer 66 is deposited. According to some embodiments, the spacer layer 66 is formed of or includes a metal-containing material, such as a metal oxide or metal nitride, for example, titanium oxide, titanium nitride, etc. The spacer layer 66 is formed as a conformal spacer, which includes a vertical portion located on the sidewall of the mandrel 62', a top horizontal portion located on the top of the mandrel 62', and a bottom horizontal portion located on the top of the hard mask 60.

[0052] Then an anisotropic etching process is performed to remove the top and bottom horizontal portions, leaving the vertical portion as spacer 66′, as shown. Figure 18 As shown. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 230. According to some embodiments, an anisotropic etching process is performed using an etching gas such as Cl2, HBr, CH4, or combinations thereof. A carrier gas such as N2 or argon may also be added to the etching gas. After the etching process, the mandrel 62′ is removed by the etching process.

[0053] In subsequent processes, hard masks 60 and 58 are patterned in anisotropic etching, and mandrel 62' is used as an etching mask. The remaining hard masks 60' and 58' are as follows... Figure 19 As shown. Hard masks 60′ and 58′ are then used as etching masks to etch the dummy gate electrode layer 54 and form the dummy gate electrode 54′. The corresponding process is as follows: Figure 31The process flow 200 shown is illustrated as process 232. The gate dielectric layer 52 is also etched to form a dummy gate dielectric 52'. Etching of the silicon in the dummy gate electrode layer can be performed at a temperature ranging from about 100°C to about 700°C. The etching gas can include fluorine (F2), chlorine (Cl2), hydrogen chloride (HCl), hydrogen bromide (HBr), bromine (Br2), SiH2Cl2, or combinations thereof. The pressure of the etching gas can range from about 0.1 Torr to about 200 Torr. The carrier gas can include H2 and / or N2, which can have a flow rate of less than about 20 slm.

[0054] This forms a dummy gate stack 68. The dummy gate stack 68 includes a dummy gate electrode 54' and a dummy gate dielectric 52', which are the remainders of the dummy gate electrode layer 54 and the dummy gate dielectric 52, respectively. The dummy gate stack 68 may also include hard masks 58' and 60', which are the remainders of patterned hard mask layers 58 and 60.

[0055] Figure 20A , 20B And 20C shows Figure 19 The diagram shows a top view and two cross-sectional views of the structure, where the protruding fin 48 is curved and the curvature value B exceeds the specification (greater than 4 nm). Figure 20A A top view of the three protruding fins 48 is shown. Figure 20B and 20C They are shown respectively Figure 20A Reference sections 20B-20B and 20C-20C are shown. The silicon cap layer 50 is not shown separately because it can be incorporated with the protruding fins 48 and the bulk portion of the semiconductor substrate 20. See also Figure 20B The left and middle fins curve outwards relative to each other, while the middle and right fins curve inwards relative to each other. (The sentence is incomplete and lacks context.) Figure 20B In the cross-section shown, most of the dummy gate electrode layer 54 has been removed. However, due to the bending of the protruding fins 48, some portions of the dummy gate electrode layer 54 are obscured by the bent protruding fins 48 and have not been removed; these are shown as dummy gate residue 54.

[0056] Figure 21A , 21B 21C illustrates embodiments according to this disclosure. Figure 19 The diagram shows a top view and two cross-sectional views of the structure, where the protruding fin 48 has a nominal bend value B. Alternatively, the protruding fin 48 is vertical or substantially vertical, with a bend value B less than 4 nm. Figure 21A A top view of the three protruding fins 48 is shown. Figure 21B and Figure 21C They are shown respectively Figure 21A Reference sections 21B-21B and 21C-21C are shown in the figure. In, for example...Figure 21B In the cross-section shown, the entire dummy gate electrode layer 54 has been removed, leaving no residue.

[0057] refer to Figure 22 Gate spacers 70 are formed on the sidewalls of the dummy gate stack 68. According to some embodiments of the present disclosure, gate spacers 70 are formed of a dielectric material, such as silicon nitride, oxygen-carbon-silicon nitride, etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers.

[0058] Next, an etching process is used to make... Figure 19 Some portions of the protruding fin 48 shown (these portions are not covered by the dummy gate stack 68 and the gate spacer 70) are recessed, thereby obtaining Figure 22 The structure is shown in the figure. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 234. The recess can be anisotropic, thus protecting the portion of the protruding fin 48 located directly beneath the dummy gate stack 68 and the gate spacer 70 from etching. According to some embodiments, the top surface of the recessed semiconductor strip 30 can be lower than the top surface 40A of the STI region 40. A recess 72 is formed accordingly. The recess 72 includes portions located on the opposite side of the dummy gate stack 68 and portions between the remaining portions of the protruding fin 48.

[0059] Next, an epitaxial region (source / drain region) 74 is formed by selectively growing (by epitaxy) semiconductor material in the recess 72, resulting in... Figure 23 The structure within. The corresponding processes are as follows: Figure 31 The process flow 200 shown is illustrated as process 236. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be doped in situ as epitaxy progresses. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boride (SiGeB), silicon boride (SiB), GeB, etc., can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbide phosphide (SiCP), etc., can be grown. According to an alternative embodiment of this disclosure, the epitaxial region 74 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the trench 72 is filled with the epitaxial region 74, further epitaxial growth of the epitaxial region 74 results in the horizontal expansion of the epitaxial region 74. Further growth of the epitaxial region 74 may also cause adjacent epitaxial regions 74 to merge with each other.

[0060] Figure 24A perspective view of the structure after the formation of the contact etch stop layer (CESL) 76 and the interlayer dielectric (ILD) 78 is shown. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 238. CESL 76 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 78 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. ILD 78 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based material, such as tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process, such as CMP or mechanical polishing, can be performed to make the top surfaces of ILD 78, dummy gate stack 68, and gate spacer 70 flush with each other.

[0061] Then, hard masks 58′ and 60′, dummy gate electrode 54′, and dummy gate dielectric layer 52′ are removed, trenches are formed between gate spacers 70, and then replacement gate stack 84 is formed. The corresponding process is as follows: Figure 31 The process flow 200 shown is illustrated as process 240. The gate stack 84 includes a gate dielectric 80 and a gate electrode 82. The gate dielectric 80 may include an interface layer (IL, not shown separately) and a high-k dielectric layer (not shown). The IL is formed on the exposed surface of the protruding fin 48 and may include an oxide layer, such as a silicon oxide layer, formed by a thermal oxidation, chemical oxidation, or deposition process of the protruding fin 48. The high-k dielectric layer includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0. According to some embodiments of this disclosure, the high-k dielectric layer is formed using ALD, CVD, etc.

[0062] According to some embodiments, the gate electrode 82 includes a stacked layer that may include a diffusion barrier layer (cap layer) and one or more work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride, which may (or may not) be doped with silicon. The work function layers determine the work function of the gate electrode and include at least one layer, or multiple layers formed of different materials. The specific material of the work function layers may be selected depending on whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. A metal fill region is then formed on the stacked layer, completely filling the trench left by the removed dummy gate stack. The metal fill region may be formed of cobalt, tungsten, alloys thereof, or other metals or metal alloys, or may include cobalt, tungsten, alloys thereof, or other metals or metal alloys.

[0063] Next, as Figure 25As shown in FIG. 1, a planarization process, such as a CMP process or a mechanical polishing process, is performed to make the top surface of the gate stack 84 coplanar with the top surface of the ILD 78. In a subsequent process, the gate stack 84 is etched deeply so that recesses are formed between the opposing gate spacers 70. Next, as shown in FIG. 2, a hard mask 86 is formed over the replacement gate stack 84. According to some embodiments of the disclosure, forming the hard mask 86 includes a deposition process for forming a blanket dielectric material and a planarization process for removing excess dielectric material over the gate spacers 70 and the ILD 78. For example, the hard mask 86 can be formed of silicon nitride or other similar dielectric material. Figure 26

[0064] According to some embodiments, a gate isolation region 85 can be formed to cut the gate stack 84 into discrete portions. The formation of the gate isolation region 85 can include etching the gate stack 84 to form openings that separate the longer gate stack 84 in the uncut state into smaller portions. The openings are filled with a dielectric material to electrically isolate the gate stacks. In the etching of the gate stack 84, if the protruding fin 48 is curved beyond the specified curvature value B, then the etched gate stack 84 can also have a residue that can electrically couple the portions of the gate stack 84 that are intended to be electrically isolated from each other. Thus, embodiments of the disclosure also address this issue.

[0065] Figure 26 Some features formed in subsequent processes are also shown, which can include source / drain silicide regions 88, source / drain contact plugs 90. Thus, the FinFET 94 is formed.

[0066] Embodiments of the disclosure have some advantageous features. By controlling the ratio of the height of the protruding fin to the depth of the STI region, and / or controlling the uniformity of the spacing between adjacent protruding fins, the curvature of the protruding fin is controlled. Thus, the issues caused by the curved protruding fin are addressed.

[0067] ​According to some embodiments of the present disclosure, a method includes: etching a semiconductor substrate to form a first trench between a first semiconductor strip and a second semiconductor strip, and a second trench between the second semiconductor strip and a third semiconductor strip, wherein the second trench is deeper than the first trench; filling the first trench and the second trench to form a first isolation region between the first semiconductor strip and the second semiconductor strip, and a second isolation region between the second semiconductor strip and the third semiconductor strip; recessing the first isolation region and the second isolation region, wherein a top of the first semiconductor strip forms a first protruding fin, a top of the second semiconductor strip forms a second protruding fin, and a top of the third semiconductor strip forms a third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch, the second protruding fin is spaced apart from the third protruding fin by a second pitch, the second pitch is substantially equal to the first pitch, wherein a curvature value of the first protruding fin, the second protruding fin, and the third protruding fin is less than about 4 nm; forming a gate stack on the second protruding fin; forming a source region and a drain region based on the second protruding fin, wherein the gate stack is between the source region and the drain region. In one embodiment, after the recessing, a height of the second protruding fin is less than both a first depth of the first isolation region and a second depth of the second isolation region. In one embodiment, a difference between the first pitch and the second pitch is less than about 4 nm. In one embodiment, the first semiconductor strip is a thin and tall fin having a first width at about 5 nm below a top end of the first semiconductor strip, and a second width at about 60 nm below the top end of the first semiconductor strip, wherein the first width is less than about 5 nm, and the second width is less than about 14.5 nm. In one embodiment, the second semiconductor strip is also an additional thin and tall fin. In one embodiment, the first isolation region is included in a device die, the device die includes a plurality of FinFETs, and each of the plurality of FinFETs includes an additional protruding fin and an additional isolation region proximate to the additional protruding fin, wherein a height of all the additional protruding fins is less than a depth of the corresponding additional isolation region throughout the device die. In one embodiment, forming the gate stack includes: forming a dummy gate stack on the first protruding fin; replacing the dummy gate stack with a replacement gate stack. In one embodiment, forming the dummy gate stack includes: depositing a dummy gate electrode layer on the first protruding fin; forming a mandrel above the dummy gate electrode layer; forming spacers on opposite sidewalls of the mandrel; removing the mandrel; etching the dummy gate electrode layer using the spacers as an etching mask, wherein a remaining portion of the dummy gate electrode layer forms a portion of the gate stack.In one embodiment, filling the first trench and the second trench is filled using trisilylamine as a precursor. In one embodiment, recessing the first isolation region is such that a top surface of the first isolation region is curved, with a middle portion of the top surface being lower than edge portions of the top surface, wherein a depth of the first isolation region is measured from the middle portion of the top surface.

[0068] According to some embodiments of the present disclosure, a method includes: etching a semiconductor substrate to form a first trench between a first semiconductor strip and a second semiconductor strip, wherein the first semiconductor strip has a first width at about 5 nm below a top end of the first semiconductor strip and a second width at about 60 nm below the top end of the first semiconductor strip, wherein the first width is less than about 5 nm and the second width is less than about 14.5 nm; filling the first trench with a dielectric material to form a first isolation region; recessing the first isolation region, after which the first isolation region has a first depth, wherein a first top portion of the first semiconductor strip protrudes above the first isolation region to form a first protruding fin, the first protruding fin having a first height that is less than the first depth; forming a gate stack that extends over sidewalls and a top surface of the first protruding fin. In one embodiment, recessing the first isolation region causes a top portion of the second semiconductor strip to protrude above the first isolation region and form a second protruding fin, the second protruding fin having a second height that is less than the first depth. In one embodiment, after recessing, a second top portion of the second semiconductor strip protrudes above the first isolation region to form a second protruding fin, wherein a bending value of the first protruding fin and the second protruding fin is less than about 4 nm after the gate stack is formed. In one embodiment, the method further includes forming a second isolation region between and in contact with the second semiconductor strip and a third semiconductor strip, a top portion of the third semiconductor strip protruding above the second isolation region to form a third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch, the second protruding fin is spaced apart from the third protruding fin by a second pitch, and wherein a difference between the first pitch and the second pitch is less than about 4 nm, wherein an additional bending value of the second protruding fin and the third protruding fin is less than 4 nm. In one embodiment, the second isolation region has a second depth, the third protruding fin has a third height that is less than the second depth. In one embodiment, the first isolation region is included in a device die, the device die including a plurality of FinFETs, each of the plurality of FinFETs including an additional protruding fin and an additional isolation region proximate to the additional protruding fin, wherein a height of all the additional protruding fins is less than a depth of the corresponding additional isolation regions throughout the device die. In one embodiment, forming the gate stack includes forming a dummy gate stack on the first protruding fin; replacing the dummy gate stack with a replacement gate stack.In one embodiment, forming the dummy gate stack includes depositing a dummy gate electrode layer on the first protruding fin, forming a mandrel over the dummy gate electrode layer, forming spacers on opposite sidewalls of the mandrel, removing the mandrel, etching the dummy gate electrode layer using the spacers as etch masks, wherein a remaining portion of the dummy gate electrode layer forms a portion of the gate stack. In one embodiment, filling the first trench with a dielectric material is performed using trimethylsilylamine as a precursor. In one embodiment, recessing the isolation region is such that a top surface of the first isolation region is curved, with a middle portion of the top surface being lower than edge portions of the top surface, wherein the first depth is measured from the middle portion of the top surface.

[0069] According to some embodiments of the present disclosure, an integrated circuit structure includes: a first protruding fin having a first width at about 5 nm below a first top end of the first protruding fin and a second width at about 60 nm below the first top end of the first protruding fin, wherein the first width is less than about 5 nm and the second width is less than about 14.5 nm; a second protruding fin having a third width at about 5 nm below a second top end of the second protruding fin and a fourth width at about 60 nm below the second top end of the second protruding fin, wherein the third width is less than about 5 nm and the fourth width is less than about 14.5 nm; a first shallow trench isolation region between the first protruding fin and the second protruding fin, wherein the first shallow trench isolation region has a depth, wherein a first fin height of the first protruding fin is less than the depth and a bending value of the first protruding fin and the second protruding fin is less than 4 nm. In one embodiment, the first fin height is measured from the first top end of the first protruding fin to a lowest end of a top surface of the first shallow trench isolation region. In one embodiment, the first protruding fin is included in a device die that includes a plurality of FinFETs, each of the plurality of FinFETs including an additional protruding fin and an additional isolation region immediately adjacent to the additional protruding fin, wherein, throughout the device die, a height of all the additional protruding fins is less than a depth of the corresponding additional isolation regions. In one embodiment, the first protruding fin is a silicon fin. In one embodiment, the first protruding fin includes silicon germanium. In one embodiment, the integrated circuit structure further includes: a third protruding fin; a second isolation region between the second protruding fin and the third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch and the second protruding fin is spaced apart from the third protruding fin by a second pitch, wherein a difference between the first pitch and the second pitch is less than about 4 nm, wherein an additional bending value of the second protruding fin and the third protruding fin is less than about 4 nm. In one embodiment, a top surface of the first shallow trench isolation region is curved, with a middle portion of the top surface being lower than edge portions of the top surface, wherein the depth is measured at the middle portion.

[0070] According to some embodiments of the present disclosure, an integrated circuit structure includes: a bulk semiconductor substrate; a first protruding fin, a second protruding fin, and a third protruding fin adjacent to each other, the second protruding fin being between the first protruding fin and the third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch, the second protruding fin is spaced apart from the third protruding fin by a second pitch, wherein a difference between the first pitch and the second pitch is less than about 4 nm; a first isolation region above the bulk semiconductor substrate and between the first protruding fin and the second protruding fin; a second isolation region above the bulk semiconductor substrate and between the second protruding fin and the third protruding fin, wherein a bowing value of the second protruding fin and the third protruding fin is less than about 4 nm. In one embodiment, a first height of the first isolation region is greater than a depth of the first isolation region. In one embodiment, the first height of the first isolation region is less than the depth of the first isolation region.

[0071] The foregoing summary has outlined features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the present disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure.

[0072] Example 1 is a method for fabricating an integrated circuit structure, comprising: etching a semiconductor substrate to form a first trench between a first semiconductor strip and a second semiconductor strip, and a second trench between the second semiconductor strip and a third semiconductor strip, wherein the second trench is deeper than the first trench; filling the first trench and the second trench to form a first isolation region between the first semiconductor strip and the second semiconductor strip, and a second isolation region between the second semiconductor strip and the third semiconductor strip; recessing the first isolation region and the second isolation region, wherein a top of the first semiconductor strip forms a first protruding fin, a top of the second semiconductor strip forms a second protruding fin, and a top of the third semiconductor strip forms a third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch, the second protruding fin is spaced apart from the third protruding fin by a second pitch, the second pitch is substantially equal to the first pitch, wherein a bowing value of the first protruding fin, the second protruding fin, and the third protruding fin is less than about 4 nm; forming a gate stack on the second protruding fin; and forming a source region and a drain region based on the second protruding fin, wherein the gate stack is between the source region and the drain region.

[0073] Example 2 is the method of example 1, wherein, after the recessing, the second protruding fin has a height that is less than both a first depth of the first isolation region and a second depth of the second isolation region.

[0074] Example 3 is the method of example 1, wherein a difference between the first pitch and the second pitch is less than about 4 nm.

[0075] Example 4 is the method of example 1, wherein the first semiconductor strip is a thin and tall fin having a first width at about 5 nm below a top end of the first semiconductor strip and a second width at about 60 nm below the top end of the first semiconductor strip, wherein the first width is less than about 5 nm and the second width is less than about 14.5 nm.

[0076] Example 5 is the method of example 4, wherein the second semiconductor strip is also an additional thin and tall fin.

[0077] Example 6 is the method of example 1, wherein the first isolation region is included in a device die that includes a plurality of fin field effect transistors (FinFETs), each of the plurality of fin field effect transistors including an additional protruding fin and an additional isolation region proximate to the additional protruding fin, wherein, throughout the device die, a height of all the additional protruding fins is less than a depth of the corresponding additional isolation regions.

[0078] Example 7 is the method of example 1, wherein forming a gate stack includes forming a dummy gate stack on the first protruding fin and replacing the dummy gate stack with a replacement gate stack.

[0079] Example 8 is the method of example 7, wherein forming a dummy gate stack includes depositing a dummy gate electrode layer on the first protruding fin, forming a mandrel over the dummy gate electrode layer, forming spacers on opposite sidewalls of the mandrel, removing the mandrel, and etching the dummy gate electrode layer using the spacers as etch masks, wherein a remaining portion of the dummy gate electrode layer forms part of the gate stack.

[0080] Example 9 is the method of example 1, wherein filling the first trench and the second trench is filled using trimethylsilylamine as a precursor.

[0081] Example 10 is the method of example 1, wherein recessing the first isolation region is such that a top surface of the first isolation region is curved, with a middle portion of the top surface being lower than edge portions of the top surface, wherein a depth of the first isolation region is measured from the middle portion of the top surface.

[0082] Example 11 is an integrated circuit structure comprising: a first protruding fin having a first width at about 5 nm below a first top end of the first protruding fin and a second width at about 60 nm below the first top end of the first protruding fin, wherein the first width is less than about 5 nm, and the second width is less than about 14.5 nm; a second protruding fin having a third width at about 5 nm below a second top end of the second protruding fin and a fourth width at about 60 nm below the second top end of the second protruding fin, wherein the third width is less than about 5 nm, and the fourth width is less than about 14.5 nm; and a first shallow trench isolation region between the first protruding fin and the second protruding fin, wherein the first shallow trench isolation region has a depth, wherein a first fin height of the first protruding fin is less than the depth, and a bending value of the first protruding fin and the second protruding fin is less than 4 nm.

[0083] Example 12 is the integrated circuit structure of example 11, wherein the first fin height is measured from the first top end of the first protruding fin to a lowest end of a top surface of the first shallow trench isolation region.

[0084] Example 13 is the integrated circuit structure of example 11, wherein the first protruding fin is included in a device die that includes a plurality of fin field effect transistors (FinFETs), each of the plurality of fin field effect transistors including an additional protruding fin and an additional isolation region immediately adjacent to the additional protruding fin, wherein throughout the device die, a height of all the additional protruding fins is less than a depth of the corresponding additional isolation regions.

[0085] Example 14 is the integrated circuit structure of example 11, wherein the first protruding fin is a silicon fin.

[0086] Example 15 is the integrated circuit structure of example 11, wherein the first protruding fin includes silicon germanium.

[0087] Example 16 is the integrated circuit structure of Example 11, further comprising: a third protruding fin; and a second isolation region located between the second protruding fin and the third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch, the second protruding fin is spaced apart from the third protruding fin by a second pitch, wherein a difference between the first pitch and the second pitch is less than about 4 nm, wherein an additional curvature value of the second protruding fin and the third protruding fin is less than about 4 nm.

[0088] Example 17 is the integrated circuit structure of Example 11, wherein a top surface of the first shallow trench isolation region is curved, a middle portion of the top surface is lower than an edge portion of the top surface, wherein the depth is measured at the middle portion.

[0089] Example 18 is an integrated circuit structure comprising: a bulk semiconductor substrate; a first protruding fin, a second protruding fin, and a third protruding fin adjacent to each other, the second protruding fin located between the first protruding fin and the third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch, the second protruding fin is spaced apart from the third protruding fin by a second pitch, wherein a difference between the first pitch and the second pitch is less than about 4 nm; a first isolation region located above the bulk semiconductor substrate and between the first protruding fin and the second protruding fin; and a second isolation region located above the bulk semiconductor substrate and between the second protruding fin and the third protruding fin, wherein a curvature value of the second protruding fin and the third protruding fin is less than about 4 nm.

[0090] Example 19 is the integrated circuit structure of Example 18, wherein a first height of the first protruding fin is greater than a depth of the first isolation region.

[0091] Example 20 is the integrated circuit structure of Example 18, wherein a first height of the first protruding fin is less than a depth of the first isolation region.

Claims

1. A method for fabricating an integrated circuit structure, comprising: etching a semiconductor substrate to form a first trench between a first semiconductor strip and a second semiconductor strip, and a second trench between the second semiconductor strip and a third semiconductor strip, wherein the second trench is deeper than the first trench; filling the first trench and the second trench to form a first isolation region between the first semiconductor strip and the second semiconductor strip, and a second isolation region between the second semiconductor strip and the third semiconductor strip; recessing the first isolation region and the second isolation region, wherein a top of the first semiconductor strip forms a first protruding fin, a top of the second semiconductor strip forms a second protruding fin, and a top of the third semiconductor strip forms a third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch, the second protruding fin is spaced apart from the third protruding fin by a second pitch, the second pitch is substantially equal to the first pitch, wherein a curvature value of the first protruding fin, the second protruding fin, and the third protruding fin is less than 4 nm; forming a gate stack on the second protruding fin; and forming a source region and a drain region based on the second protruding fin, wherein the gate stack is located between the source region and the drain region.

2. The method of claim 1, wherein, The second protruding fin has a height that is less than both a first depth of the first isolation region and a second depth of the second isolation region after the recessing.

3. The method of claim 1, wherein, A difference between the first pitch and the second pitch is less than 4 nm.

4. The method of claim 1, wherein, The first semiconductor strip is a thin and tall fin having a first width at 5 nm below a top end of the first semiconductor strip and a second width at 60 nm below the top end of the first semiconductor strip, wherein the first width is less than 5 nm, and the second width is less than 14.5 nm.

5. The method of claim 4, wherein, The second semiconductor strip is an additional thin and tall fin.

6. The method of claim 1, wherein, The first isolation region is included in a device die that includes a plurality of fin field effect transistors (FinFETs), each of the plurality of fin field effect transistors including an additional protruding fin and an additional isolation region proximate to the additional protruding fin, wherein a height of all the additional protruding fins is less than a depth of the corresponding additional isolation regions throughout the device die.

7. The method of claim 1, wherein, Forming the gate stack includes: forming a dummy gate stack on the first protruding fin; and replacing the dummy gate stack with a replacement gate stack.

8. The method of claim 7, wherein, Forming the dummy gate stack includes: depositing a dummy gate electrode layer on the first protruding fin; forming a mandrel over the dummy gate electrode layer; forming spacers on opposite sidewalls of the mandrel; removing the mandrel; and etching the dummy gate electrode layer using the spacers as etch masks, wherein a remaining portion of the dummy gate electrode layer forms a portion of the gate stack.

9. The method of claim 1, wherein, Filling the first trench and the second trench is performed using trimethylsilyl amine as a precursor.

10. The method of claim 1, wherein, recessing the first isolation region such that a top surface of the first isolation region is curved, a middle portion of the top surface being lower than an edge portion of the top surface, wherein a depth of the first isolation region is measured from the middle portion of the top surface.

11. An integrated circuit structure, comprising: a first protruding fin having a first width at 5 nm below a first top end of the first protruding fin and a second width at 60 nm below the first top end of the first protruding fin, wherein the first width is less than 5 nm and the second width is less than 14.5 nm; a second protruding fin having a third width at 5 nm below a second top end of the second protruding fin and a fourth width at 60 nm below the second top end of the second protruding fin, wherein the third width is less than 5 nm and the fourth width is less than 14.5 nm; and a first shallow trench isolation region between the first protruding fin and the second protruding fin, wherein the first shallow trench isolation region has a depth, wherein a first fin height of the first protruding fin is less than the depth and a bending value of the first protruding fin and the second protruding fin is less than 4 nm.

12. The integrated circuit structure of claim 11, wherein, the first fin height is measured from the first top end of the first protruding fin to a lowest end of a top surface of the first shallow trench isolation region.

13. The integrated circuit structure of claim 11, wherein, the first protruding fin is included in a device die that includes a plurality of fin field effect transistors (FinFETs), each of the plurality of fin field effect transistors including an additional protruding fin and an additional isolation region proximate to the additional protruding fin, wherein, throughout the device die, a height of all the additional protruding fins is less than a depth of the corresponding additional isolation regions.

14. The integrated circuit structure of claim 11, wherein, the first protruding fin is a silicon fin.

15. The integrated circuit structure of claim 11, wherein, the first protruding fin includes silicon germanium.

16. The integrated circuit structure of claim 11, further comprising: a third protruding fin; and a second isolation region between the second protruding fin and the third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch and the second protruding fin is spaced apart from the third protruding fin by a second pitch, wherein a difference between the first pitch and the second pitch is less than 4 nm, wherein an additional bending value of the second protruding fin and the third protruding fin is less than 4 nm. a top surface of the first shallow trench isolation region is curved, a middle portion of the top surface being lower than an edge portion of the top surface, wherein the depth is measured at the middle portion.

17. The integrated circuit structure of claim 11, wherein, 18. An integrated circuit structure, comprising: a bulk semiconductor substrate; first, second, and third protruding fins adjacent to each other, the second protruding fin between the first protruding fin and the third protruding fin, wherein the first protruding fin is spaced apart from the second protruding fin by a first pitch and the second protruding fin is spaced apart from the third protruding fin by a second pitch, wherein a difference between the first pitch and the second pitch is less than 4 nm; a first isolation region above the bulk semiconductor substrate and between the first protruding fin and the second protruding fin; and a second isolation region above the bulk semiconductor substrate and between the second protruding fin and the third protruding fin. A second isolation region is located above the body semiconductor substrate and between the second protruding fin and the third protruding fin, wherein a bending value of the second protruding fin and the third protruding fin is less than 4 nm.

19. The integrated circuit structure of claim 18, wherein, A first height of the first protruding fin is greater than a depth of the first isolation region.

20. The integrated circuit structure of claim 18, wherein, A first height of the first protruding fin is less than a depth of the first isolation region.

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