Semiconductor device

Abstract

The present invention provides a semiconductor device, comprising a semiconductor substrate, a first well, a second well, a field oxide layer, and a polysilicon layer. The semiconductor substrate has a first conductivity type. The first well is formed in the semiconductor substrate and has a second conductivity type. The second well is formed in the first well and has the first conductivity type. The field oxide layer is formed over the second well. The polysilicon layer is formed over the field oxide layer and forms a resistance element.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device for increasing the breakdown voltage of a resistive element and providing electrostatic discharge protection. Background Art

[0002] With the development of high-voltage integrated circuits, especially for some AC-DC circuits used for high-voltage alternating current, some resistive elements need to withstand high voltages of several hundred volts. However, before such high voltages of several hundred volts, traditional high-voltage resistive elements may encounter problems of element breakdown first, making traditional resistors unable to meet the requirements.

[0003] By fabricating polysilicon resistors on a field oxide layer, the breakdown voltage can be greatly improved, and the breakdown voltage mainly depends on the thickness of the field oxide layer. The breakdown voltage of the field oxide layer in general processes can reach 300 - 400V. However, for AC-DC circuits of high-voltage alternating current, the highest peak voltage received by the resistive elements may be as high as 500 - 650V, making polysilicon resistors unable to meet the requirements. Therefore, it is necessary to improve the breakdown voltage of the resistive elements. Summary of the Invention

[0004] The semiconductor device proposed by the present invention can not only increase the breakdown voltage of the resistive element, but also provide a path for discharging electrostatic charges, so that in addition to meeting the requirements of high-voltage applications, the polysilicon resistor can also provide the required protection function when there is a need for electrostatic discharge protection at one end of the polysilicon resistor.

[0005] In view of this, the present invention proposes a semiconductor device, including a semiconductor substrate, a first well, a second well, a field oxide layer, and a polysilicon layer. The above semiconductor substrate has a first conductivity type. The above first well is formed in the above semiconductor substrate and has a second conductivity type. The above second well is formed in the above first well and has the above first conductivity type. The above field oxide layer is formed on the above second well. The above polysilicon layer is formed on the above field oxide layer and forms a resistive element.

[0006] According to an embodiment of the present invention, the above semiconductor device further includes a first top doped layer and a second top doped layer. The above first top doped layer is formed in the above first well and has the above first conductivity type. The above second top doped layer is formed in the above first well and has the above first conductivity type, wherein the above first top doped layer and the above second top doped layer are located on both sides of the above second well and are separated from the above second well respectively.

[0007] According to an embodiment of the present invention, the semiconductor device further includes a third well and a doped region. The third well is formed in the semiconductor substrate and has the first conductivity type. The doped region is formed in the third well and has the first conductivity type, wherein the doped region is coupled to a ground terminal.

[0008] The present invention further provides a semiconductor device, including a semiconductor substrate, a first well, a second well, a first doped region, a field oxide layer, and a polysilicon layer. The semiconductor substrate has the first conductivity type. The first well is formed in the semiconductor substrate and has the second conductivity type. The second well is formed in the first well and has the second conductivity type. The first doped region is formed in the second well and has the second conductivity type. The field oxide layer is formed on the first well and surrounds the first doped region. The polysilicon layer is formed on the field oxide layer and forms a resistor element.

[0009] According to an embodiment of the present invention, the semiconductor device further includes a first top doped layer and a second top doped layer. The first top doped layer is formed in the first well and has the first conductivity type. The second top doped layer is formed in the first well and has the first conductivity type, wherein the first top doped layer and the second top doped layer are located on both sides of the second well, and wherein the resistor element is further formed on the first top doped layer and the second top doped layer.

[0010] According to an embodiment of the present invention, the semiconductor device further includes a third well and a second doped region. The third well is formed in the semiconductor substrate and has the first conductivity type. The second doped region is formed in the third well and has the first conductivity type.

[0011] According to an embodiment of the present invention, the resistor element has a first end coupled to a high voltage level and a second end coupled to a low voltage level, wherein the first doped region is coupled to the high voltage level, and the second doped region is coupled to a ground terminal.

[0012] According to another embodiment of the present invention, the semiconductor device further includes a third doped region. The third doped region is formed in the third well, adjacent to the second doped region, and has the second conductivity type, wherein the third doped region is coupled to the ground terminal, and wherein the first doped region, the second doped region, and the third doped region form a parasitic bipolar transistor.

[0013] According to another embodiment of the present invention, the semiconductor device further includes a fourth doped region and a fifth doped region. The fourth doped region is formed in the second well, adjacent to the first doped region and has the first conductivity type. The fifth doped region is formed in the semiconductor substrate and has the second conductivity type.

[0014] According to an embodiment of the present invention, the fourth doped region is coupled to the high voltage level, the fifth doped region is coupled to the ground terminal, wherein the fifth doped region is separated from the third well, and wherein the first doped region, the fourth doped region, the second doped region, and the fifth doped region form a parasitic silicon controlled rectifier. Description of the Drawings

[0015] Figure 1 A cross-sectional view showing a semiconductor device according to an embodiment of the present invention;

[0016] Figure 2 Showing according to the present invention Figure 1 A top view of the polysilicon layer described above;

[0017] Figure 3 A cross-sectional view showing a semiconductor device according to another embodiment of the present invention;

[0018] Figure 4 Showing according to the present invention Figure 3 A top view of the polysilicon layer described above;

[0019] Figure 5 A cross-sectional view showing a semiconductor device according to another embodiment of the present invention; and

[0020] Figure 6 A cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0021] Reference Numerals in the Drawings

[0022] 100, 300, 500, 600: Semiconductor device

[0023] 200, 400: Resistance element

[0024] SUB: Semiconductor substrate

[0025] W1: First well

[0026] W2: Second well

[0027] W3: Third well

[0028] TOP1: First top doped layer

[0029] TOP2: Second top doped layer

[0030] FOX: Field oxide layer

[0031] PLY: Polysilicon layer

[0032] R: Resistance element

[0033] G: Distribution width

[0034] H: Well width

[0035] PAD: Bonding pad

[0036] N1: First node

[0037] N2: Second node

[0038] VH: High voltage level

[0039] VL: Low voltage level

[0040] GND: Ground terminal

[0041] D: Doped region

[0042] DP1: First parasitic diode

[0043] DP2: Second parasitic diode

[0044] DP3: Third parasitic diode

[0045] D1: First doped region

[0046] D2: Second doped region

[0047] D3: Third doped region

[0048] D4: Fourth doped region

[0049] D5: Fifth doped region

[0050] X1: First width

[0051] X2: Second width

[0052] NPN: Parasitic bipolar transistor Detailed implementation manners

[0053] The following provides a detailed description of a semiconductor substrate, a semiconductor device, and a method for manufacturing a semiconductor device according to some embodiments of the present invention. It should be understood that the following description provides many different embodiments or examples for implementing different aspects of some embodiments of the present invention. The specific elements and arrangements described below are only for simply and clearly describing some embodiments of the present invention. Of course, these are only for illustration and not limitations of the present invention. In addition, repeated reference numerals or labels may be used in different embodiments. These repetitions are only for simply and clearly describing some embodiments of the present invention and do not represent any correlation between the different embodiments and / or structures discussed. Furthermore, when it is stated that a first material layer is on or above a second material layer, it includes the case where the first material layer is in direct contact with the second material layer. Or, there may also be a case where one or more other material layers are interposed, in which case the first material layer and the second material layer may not be in direct contact.

[0054] In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of a figure to another element. It can be understood that if the device of the figure is flipped so that it is upside down, the element described on the "lower" side will become the element on the "higher" side.

[0055] Here, the terms "about", "approximately", "substantially" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3%, or 2%, or 1%, or 0.5%. The given quantity is an approximate quantity, that is, the meaning of "about", "approximately", "substantially" can still be implied even without specifically stating "about", "approximately", "substantially".

[0056] It can be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present invention.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention belongs. It can be understood that these terms, such as those defined in a commonly used dictionary, should be interpreted to have a meaning consistent with the relevant technology and the background or context of the present invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present invention.

[0058] Some embodiments of the present invention can be understood in conjunction with the drawings, and the drawings of the embodiments of the present invention are also regarded as part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn to the scale of actual devices and components. In the drawings, the shapes and thicknesses of the embodiments may be exaggerated to clearly show the features of the embodiments of the present invention. In addition, the structures and devices in the drawings are shown in a schematic manner to clearly show the features of the embodiments of the present invention.

[0059] In some embodiments of the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in this section and the related drawings. Such relative terms are only for convenience of description and do not represent that the devices described need to be manufactured or operated in a specific orientation. Regarding terms related to joining and connecting, such as "connected", "interconnected", etc., unless otherwise defined, they may refer to two structures in direct contact, or they may also refer to two structures not in direct contact, with other structures disposed between these two structures. And such terms related to joining and connecting may also include the cases where both structures are movable, or both structures are fixed.

[0060] Embodiments of the present invention relate to embodiments of semiconductor devices, and the above embodiments can be included in an integrated circuit (IC) such as a microprocessor, a storage element, and / or other components. The above integrated circuit may also include different passive and active microelectronic components, such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAPs), inductors, diodes, Metal-Oxide-Semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors, high-power MOS transistors, or other types of transistors. Those skilled in the art can understand that semiconductor devices can also be used in integrated circuits containing other types of semiconductor components.

[0061] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. As Figure 1As shown, the semiconductor device 100 includes a semiconductor substrate SUB, a first well W1, a second well W2, a field oxide layer FOX, and a polysilicon layer PLY. The semiconductor substrate SUB has a first conductivity type. According to an embodiment of the present invention, the semiconductor substrate SUB is a silicon substrate. According to other embodiments of the present invention, the semiconductor substrate SUB may also be a lightly doped semiconductor substrate having a first conductivity type.

[0062] The first well W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type. According to an embodiment of the present invention, the first well W1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted into a predetermined region of the first well W1 to form the first well W1.

[0063] The second well W2 is formed in the first well W1 and has a first conductivity type. According to an embodiment of the present invention, the second well W2 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted into a predetermined region where the second well W2 is to be formed to form the second well W2. In this embodiment, the doping concentration of the second well W2 is higher than that of the semiconductor substrate SUB.

[0064] The field oxide layer FOX is formed above the first well W1 and the second well W2, and the polysilicon layer PLY is formed above the field oxide layer FOX and the second well W2 and is used to form a resistance element R. According to an embodiment of the present invention, the resistance element R is formed above the field oxide layer FOX and the second well W2. According to another embodiment of the present invention, the resistance element R can be formed above the field oxide layer FOX, the first well W1, and the second well W2, where the widths distributed on both sides of the resistance element R do not exceed the width of the first well W1. As Figure 1 shown, the distribution width G of the resistance element R is less than or equal to the well width H of the first well W1.

[0065] Figure 2 shows a top view of the polysilicon layer according to the present invention Figure 1 as described. As Figure 2 shown, the resistance element 200 is a ring structure and includes a pad PAD, a first node N1, and a second node N2, where Figure 2 the first node N1 corresponds to Figure 1 the first node N1 of Figure 2 and the second node N2 corresponds to Figure 1 the second node N2 of Figure 1As shown, the first node N1 and the pad PAD are coupled to a high voltage level VH, and the second node N2 is coupled to a low voltage level VL. According to some embodiments of the present invention, the low voltage level VL is a lower voltage level relative to the high voltage level VH. Therefore, the low voltage level VL can be the ground terminal GND or a voltage between the high voltage level VH and the ground terminal GND.

[0066] Returning to Figure 1 , the semiconductor device 100 further includes a third well W3 and a doped region D. The third well W3 is formed in the semiconductor substrate SUB and has a first conductivity type. According to an embodiment of the present invention, the third well W3 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted into a region where the third well W3 is to be formed to form the third well W3. In this embodiment, the doping concentration of the third well W3 is higher than that of the semiconductor substrate SUB.

[0067] The doped region D is formed in the third well W3 and has a first conductivity type. According to an embodiment of the present invention, the doping concentration of the doped region D is higher than that of the third well W3. As Figure 1 shown, the doped region D is coupled to the ground terminal GND.

[0068] As Figure 1 shown, the semiconductor device 100 further includes a first top doped layer TOP1 and a second top doped layer TOP2. The first top doped layer TOP1 is formed in the first well W1 and has a first conductivity type, and the second top doped layer TOP2 is formed in the first well W1 and has a first conductivity type, where the first top doped layer TOP1 and the second top doped layer TOP2 are located on both sides of the second well W2 and are separated from the second well W2 respectively. According to an embodiment of the present invention, the doping concentrations of the first top doped layer TOP1 and the second top doped layer TOP2 are lower than that of the second well W2.

[0069] According to an embodiment of the present invention, since the second well W2 and the first well W1 form a first parasitic diode DP1, and the first well W1 and the semiconductor substrate SUB form a second parasitic diode DP2, the breakdown voltage from the high voltage level VH to the ground terminal GND is shared by the field oxide layer FOX, the first parasitic diode DP1, and the second parasitic diode DP2, thereby improving the breakdown voltage withstand of the resistance element R of the semiconductor device 100. According to an embodiment of the present invention, the first top doped layer TOP1 and the second top doped layer TOP2 are used to increase the tolerance of the lateral electric field of the semiconductor device 100.

[0070] Figure 3 Showing a cross-sectional view of a semiconductor device according to another embodiment of the present invention. As Figure 3As shown, the semiconductor device 300 includes a semiconductor substrate SUB, a first well W1, a second well W2, a first doped region D1, a field oxide layer FOX, and a polysilicon layer PLY. The semiconductor substrate SUB has a first conductivity type. According to an embodiment of the present invention, the semiconductor substrate SUB is a silicon substrate. According to other embodiments of the present invention, the semiconductor substrate SUB may also be a lightly doped semiconductor substrate having a first conductivity type.

[0071] The first well W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type. According to an embodiment of the present invention, the first well W1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted into a predetermined region of the first well W1 to form the first well W1.

[0072] The second well W2 is formed in the first well W1 and has a second conductivity type. According to an embodiment of the present invention, the second well W2 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted into a predetermined region of the first well W1 to form the second well W2. In this embodiment, the doping concentration of the second well W2 is higher than that of the first well W1.

[0073] The first doped region D1 is formed in the second well W2 and has a second conductivity type. According to an embodiment of the present invention, the first doped region D1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted into a predetermined region of the first doped region D1 to form the first doped region D1. In this embodiment, the doping concentration of the first doped region D1 is higher than that of the second well W2.

[0074] The field oxide layer FOX is formed above the first well W1 and the second well W2 and surrounds the first doped region D1. The polysilicon layer PLY is formed on the field oxide layer FOX and is used to form a resistor element R.

[0075] Figure 4 Showing according to the present invention Figure 3 The top view of the polysilicon layer described above. As Figure 4 shown, the resistor element 400 is a ring structure and includes a first node N1 and a second node N2, where Figure 4 The first node N1 corresponds to Figure 3 The first node N1 of Figure 4 The second node N2 corresponds to Figure 3 The second node N2 of Figure 4 shown, the first doped region D1 is located at the central position of the resistor element 400. Comparing Figure 4 The resistor element 400 of Figure 2 with the resistor element 200 of Figure 4 The first doped region D1 of Figure 2The position of the pad PAD. As Figure 3 shown, the first node N1 and the first doped region D1 of the resistive element R are coupled to the high voltage level VH, and the second node N2 of the resistive element R is coupled to the low voltage level VL.

[0076] Returning to Figure 3 , the semiconductor device 300 further includes a third well W3 and a second doped region D2. The third well W3 is formed in the semiconductor substrate SUB and has a first conductivity type. According to an embodiment of the present invention, the third well W3 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted into a region where the third well W3 is to be formed to form the third well W3. In this embodiment, the doping concentration of the third well W3 is higher than that of the semiconductor substrate SUB.

[0077] The second doped region D2 is formed in the third well W3 and has a first conductivity type. According to an embodiment of the present invention, the doping concentration of the second doped region D2 is higher than that of the third well W3. As Figure 3 shown, the second doped region D2 is coupled to the ground terminal GND.

[0078] As Figure 3 shown, the semiconductor device 300 further includes a first top doped layer TOP1 and a second top doped layer TOP2. The first top doped layer TOP1 is formed in the first well W1 and has a first conductivity type, and the second top doped layer TOP2 is formed in the first well W1 and has a first conductivity type, where the first top doped layer TOP1 and the second top doped layer TOP2 are located on both sides of the second well W2 and are separated from the second well W2 respectively. According to an embodiment of the present invention, the doping concentrations of the first top doped layer TOP1 and the second top doped layer TOP2 are lower than that of the third well W3 and higher than that of the semiconductor substrate SUB.

[0079] As Figure 3 shown, the width of the resistive element R distributed on the field oxide layer FOX is a first width X1, and the width of the first top doped region TOP1 or the second doped region TOP2 is a second width X2, and the second width X2 is not less than the first width X1.

[0080] According to an embodiment of the present invention, the voltage drop from the high voltage level to the ground terminal GND is jointly borne by the field oxide layer FOX, the first top doped region TOP1 (or the second top doped region TOP2), the first well W1, and the semiconductor substrate SUB, thereby improving the breakdown voltage of the semiconductor device 500. According to an embodiment of the present invention, since a third parasitic diode DP3 is formed between the first well W1 and the semiconductor substrate SUB, the third parasitic diode DP3 provides an exclusion path for an electrostatic charge at the first node N1 coupled to the high voltage level VH.

[0081] In other words, when the first node N1 of the resistive element R is subjected to electrostatic discharge, since the first node N1 is coupled to the first doped region D1, the electrostatic charge will pass through the third parasitic diode DP3 formed by the first well W1 and the semiconductor substrate SUB, and discharge the electrostatic charge to the ground terminal GND through the second doped region D2. According to an embodiment of the present invention, the first top doped layer TOP1 and the second top doped layer TOP2 are not only used to increase the withstand ability of the vertical electric field of the semiconductor device 300, but also used to increase the withstand ability of the lateral electric field of the semiconductor device 300.

[0082] Figure 5 Shows a cross-sectional view of a semiconductor device according to another embodiment of the present invention. The Figure 5 semiconductor device 500 is compared with the Figure 3 semiconductor device 300, and the semiconductor device 500 further includes a third doped region D3.

[0083] The third doped region D3 is formed in the third well W3, located between the first doped region D1 and the second doped region D2 and adjacent to the second doped region D2, and has a second conductivity type. According to an embodiment of the present invention, the third doped region D3 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted into the region of the predetermined third doped region D3 to form the third doped region D3. In this embodiment, the doping concentration of the third doped region D3 is higher than the doping concentration of the second well W2. As Figure 5 shown, the third doped region D3 is further coupled to the ground terminal GND.

[0084] According to an embodiment of the present invention, the voltage drop from the high voltage level to the ground terminal GND is jointly borne by the field oxide layer FOX, the first top doped region TOP1 (or the second top doped region TOP2), the first well W1, and the semiconductor substrate SUB, thereby improving the breakdown voltage of the semiconductor device 500. According to an embodiment of the present invention, since the first doped region D1, the second doped region D2, and the third doped region D3 form a parasitic bipolar transistor NPN and the first node N1 is coupled to the first doped region D1, when the first node N1 of the resistive element R is subjected to electrostatic discharge, the parasitic bipolar transistor NPN is immediately turned on and discharges the electrostatic charge to the ground terminal GND quickly. According to an embodiment of the present invention, the first top doped layer TOP1 and the second top doped layer TOP2 are not only used to increase the withstand ability of the vertical electric field of the semiconductor device 500, but also used to increase the withstand ability of the lateral electric field of the semiconductor device 500.

[0085] Figure 6 Shows a cross-sectional view of a semiconductor device according to another embodiment of the present invention. The Figure 6 semiconductor device 600 is compared with the Figure 3Compared with the semiconductor device 300 , the semiconductor device 600 further includes a fourth doping region D4 and a fifth doping region D5 .

[0086] The fourth doping region D4 is formed in the second well W2, adjacent to the first doping region D1 and has the first conductivity type. According to one embodiment of the present invention, the fourth doping region D4 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the region where the fourth doping region D4 is to be formed to form the fourth doping region D4.

[0087] The fifth doping region D5 is formed in the semiconductor substrate SUB and has the second conductivity type. According to one embodiment of the present invention, the fifth doping region D5 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the fifth doping region D5 is to be formed to form the fifth doping region D5. Figure 6 As shown, the fifth doped region D5 is coupled to the ground terminal GND and is separated from the third well W3 .

[0088] According to one embodiment of the present invention, since the first doping region D1, the fourth doping region D4, the second doping region D2 and the fifth doping region D5 form a parasitic silicon controlled rectifier (SCR) and the first node N1 is coupled with the first doping region D1 and the fourth doping region, when the first node N1 of the resistor R is subjected to electrostatic discharge, the parasitic silicon controlled rectifier is immediately turned on and discharges the electrostatic charge received by the first node N1 to the ground terminal GND.

[0089] The semiconductor device proposed in the present invention can not only increase the voltage resistance of the resistor element, but also provide a path for eliminating electrostatic charges, so that the polysilicon resistor can not only meet the needs of high-voltage applications, but also provide electrostatic discharge protection at one end of the polysilicon resistor, providing the required protection function.

[0090] Although the embodiments of the present invention and their advantages are described above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present invention. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim scope constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each patent application scope and embodiment.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor substrate having a first conductivity type; A first well formed in the semiconductor substrate and having a second conductivity type; A second well formed in the first well and having the second conductivity type; A first doped region formed in the second well and having the second conductivity type; A field oxide layer formed over the first well and surrounding the first doped region; and A polysilicon layer formed over the field oxide layer and forming a resistor element; A third well formed in the semiconductor substrate and having the first conductivity type; and A second doped region formed in the third well and having the first conductivity type; Wherein the resistor element has a first end coupled to a high voltage level and a second end coupled to a low voltage level, wherein the first doped region is coupled to the high voltage level, and the second doped region is coupled to a ground terminal.

2. The semiconductor device according to claim 1, wherein Further comprising: A first top doped layer formed in the first well and having the first conductivity type; and A second top doped layer formed in the first well and having the first conductivity type, wherein the first top doped layer and the second top doped layer are located on both sides of the second well, and wherein the resistor element is further formed over the first top doped layer and the second top doped layer.

3. The semiconductor device according to claim 1, wherein Further comprising: A third doped region formed in the third well, adjacent to the second doped region and having the second conductivity type, wherein the third doped region is coupled to the ground terminal, and wherein the first doped region, the second doped region, and the third doped region form a parasitic bipolar transistor.

4. The semiconductor device according to claim 1, wherein Further comprising: A fourth doped region formed in the second well, adjacent to the first doped region and having the first conductivity type; and A fifth doped region formed in the semiconductor substrate and having the second conductivity type.

5. The semiconductor device according to claim 4, wherein, The fourth doped region is coupled to the high voltage level, the fifth doped region is coupled to the ground terminal, wherein the fifth doped region is separated from the third well, and wherein the first doped region, the fourth doped region, the second doped region, and the fifth doped region form a parasitic silicon controlled rectifier.

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