Semiconductor integrated circuit device and method for manufacturing the same

Abstract

A semiconductor integrated circuit device includes a channel layer, a barrier layer, a first p-type semiconductor layer and a second p-type semiconductor layer spaced apart from each other on the barrier layer, and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer can partially deactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor integrated circuit device and / or a method of manufacturing the same. BACKGROUND

[0002] Various power conversion systems can require a device for controlling current flow via on / off switching, such as a switching device. In a power conversion system, the efficiency of a switching device can determine the efficiency of the entire system.

[0003] Due to limitations of characteristics of silicon and characteristics of a manufacturing process, it is becoming increasingly difficult to improve the efficiency of a silicon (Si)-based power device. In order to overcome these limitations, research and development to improve conversion efficiency by applying a III-V compound semiconductor such as GaN to a power device is in progress. Recently, a high electron mobility transistor (HEMT) using a heterojunction structure of a compound semiconductor has been researched. SUMMARY

[0004] A semiconductor integrated circuit device having a plurality of devices having two or more threshold voltages and / or a method of manufacturing the same is provided.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the description and / or the presentation of the presented embodiments of the disclosure.

[0006] According to an embodiment, a semiconductor integrated circuit device includes a channel layer, a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer, a first p-type semiconductor layer and a second p-type semiconductor layer spaced apart from each other on the barrier layer, and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer partially deactivates at least one of a dopant of the first p-type semiconductor layer and a dopant of the second p-type semiconductor layer.

[0007] In some embodiments, the passivation layer can include a first portion on the first p-type semiconductor layer and a second portion on the second p-type semiconductor layer. A thickness or a material composition of the first portion can be different from a thickness or a material composition of the second portion. In some embodiments, the thickness and the material composition of the first portion can each be different from the thickness and the material composition of the second portion.

[0008] In some embodiments, the passivation layer can include a first passivation layer on the first p-type semiconductor layer and a second passivation layer on the second p-type semiconductor layer and the first passivation layer, and at least one of the first passivation layer and the second passivation layer can partially deactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

[0009] In some embodiments, the first passivation layer and the second passivation layer can partially deactivate the dopants of the first p-type semiconductor layer and the dopants of the second p-type semiconductor layer.

[0010] In some embodiments, the second passivation layer can partially deactivate the dopants of the second p-type semiconductor layer, and the first passivation layer can limit and / or prevent deactivation of the dopants of the first p-type semiconductor layer.

[0011] In some embodiments, the thickness of the first p-type semiconductor layer and the thickness of the second p-type semiconductor layer can be equal.

[0012] In some embodiments, the first p-type semiconductor layer and the second p-type semiconductor layer can have different thicknesses from each other.

[0013] In some embodiments, the semiconductor integrated circuit device can further include a first gate contacting the first p-type semiconductor layer and a second gate contacting the second p-type semiconductor layer. The first gate can be partially inserted into the first p-type semiconductor layer, or the second gate can be partially inserted into the second p-type semiconductor layer. In some embodiments, the first gate can be partially inserted into the first p-type semiconductor layer, and the second gate can be partially inserted into the second p-type semiconductor layer.

[0014] According to another embodiment, a semiconductor integrated circuit device includes a channel layer, a barrier layer on the channel layer and configured to induce a 2DEG in the channel layer, and a first p-type semiconductor layer and a second p-type semiconductor layer spaced apart from each other on the barrier layer. The first p-type semiconductor layer and the second p-type semiconductor layer can have different active dopant concentrations from each other.

[0015] In some embodiments, the thickness of the first p-type semiconductor layer and the thickness of the second p-type semiconductor layer can be equal.

[0016] In some embodiments, the first p-type semiconductor layer and the second p-type semiconductor layer can have different thicknesses from each other.

[0017] In some embodiments, the semiconductor integrated circuit device can further include a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer can partially deactivate at least one of the dopants of the first p-type semiconductor layer and the dopants of the second p-type semiconductor layer.

[0018] In some embodiments, the semiconductor integrated circuit device can further include a first gate in contact with the first p-type semiconductor layer and a second gate in contact with the second p-type semiconductor layer. The first gate can be partially inserted into the first p-type semiconductor layer, or the second gate can be partially inserted into the second p-type semiconductor layer. In some embodiments, the first gate can be partially inserted into the first p-type semiconductor layer and the second gate can be partially inserted into the second p-type semiconductor layer.

[0019] According to an embodiment, a method of manufacturing a semiconductor integrated circuit device can include sequentially forming a channel layer, a barrier layer configured to induce a 2DEG in the channel layer, and a p-type semiconductor layer, and partially deactivating dopants of a partial region of the p-type semiconductor layer.

[0020] In some embodiments, the partially deactivating can include dividing the p-type semiconductor layer into a first p-type semiconductor layer and a second p-type semiconductor layer separated from each other, forming a first passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer, exposing the second p-type semiconductor layer by etching the first passivation layer, and forming a second passivation layer on the first passivation layer and the second p-type semiconductor layer. In the forming process, the first passivation layer can provide a deactivation ion that deactivates the dopants of the first p-type semiconductor layer, or the second passivation layer can provide a deactivation ion that deactivates the dopants of the second p-type semiconductor layer. In some embodiments, in the forming process, the first passivation layer can provide a deactivation ion that deactivates the dopants of the first p-type semiconductor layer, and the second passivation layer can provide a deactivation ion that deactivates the dopants of the second p-type semiconductor layer.

[0021] In some embodiments, in the forming process, the first passivation layer can partially deactivate the dopants of the first p-type semiconductor layer, and the second passivation layer can partially deactivate the dopants of the second p-type semiconductor layer.

[0022] In some embodiments, the method can further include partially deactivating the dopants of the second p-type semiconductor layer before forming the second passivation layer.

[0023] In some embodiments, the method can further include forming a first gate in contact with the first p-type semiconductor layer and a second gate in contact with the second p-type semiconductor layer. The first gate can be partially inserted into the first p-type semiconductor layer, or the second gate can be partially inserted into the second p-type semiconductor layer. In some embodiments, the first gate can be partially inserted into the first p-type semiconductor layer and the second gate can be partially inserted into the second p-type semiconductor layer.

[0024] In some embodiments, the inactivation can include forming a first protective layer on the p-type semiconductor layer, dividing the p-type semiconductor layer into a first region covered by the first protective layer and a second region not covered by the first protective layer by etching the first protective layer, and partially inactivating dopants of the second region of the p-type semiconductor layer by forming a passivation layer including a nitride on the first protective layer and in the second region.

[0025] In some embodiments, the inactivation can include forming a first protective layer on the p-type semiconductor layer, dividing the p-type semiconductor layer into a first region covered by the first protective layer and a second region not covered by the first protective layer by etching the first protective layer, and supplying hydrogen ions to the p-type semiconductor layer in the second region.

[0026] According to an embodiment, a semiconductor integrated circuit device can include a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a first p-type semiconductor layer and a second p-type semiconductor layer spaced apart from each other on the barrier layer; a first passivation layer on the first p-type semiconductor layer and not on the second p-type semiconductor layer; and a second passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer, the second passivation layer partially inactivating dopants of the second p-type semiconductor layer.

[0027] In some embodiments, the first passivation layer can be configured to prevent the second passivation layer from inactivating dopants of the first p-type semiconductor layer.

[0028] In some embodiments, a thickness of the first p-type semiconductor layer can be different from a thickness of the second p-type semiconductor layer.

[0029] In some embodiments, a thickness of the first p-type semiconductor layer can be equal to a thickness of the second p-type semiconductor layer.

[0030] In some embodiments, the semiconductor integrated circuit device can further include a first gate contacting the first p-type semiconductor layer; and a second gate contacting the second p-type semiconductor layer. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a schematic cross-sectional view of a semiconductor integrated circuit device according to an embodiment;

[0033] Figure 2 is a schematic cross-sectional view of an embodiment of a semiconductor integrated circuit device;

[0034] Figure 3is a schematic cross-sectional view of an embodiment of a semiconductor integrated circuit device;

[0035] Figure 4 is a schematic cross-sectional view of an embodiment of a semiconductor integrated circuit device;

[0036] Figure 5 is a schematic cross-sectional view of an embodiment of a semiconductor integrated circuit device;

[0037] Figure 6 is a schematic cross-sectional view of an embodiment of a semiconductor integrated circuit device;

[0038] Figures 7A to 7F is a diagram showing an embodiment of a method of manufacturing a semiconductor integrated circuit device;

[0039] Figure 8A and Figure 8B is a diagram showing an embodiment of a method of manufacturing a semiconductor integrated circuit device;

[0040] Figure 8C and Figure 8D is a diagram showing an embodiment of a method of manufacturing a semiconductor integrated circuit device;

[0041] Figure 8E and Figure 8F is a diagram showing an embodiment of a method of manufacturing a semiconductor integrated circuit device;

[0042] Figure 9 is a diagram showing an embodiment of an operation of deactivating a second p-type semiconductor layer;

[0043] Figures 10A to 10E is a diagram showing an embodiment of a method of manufacturing a semiconductor integrated circuit device;

[0044] Figures 11A to 11F is a diagram showing an embodiment of a method of manufacturing a semiconductor integrated circuit device;

[0045] Figure 12A and Figure 12B is a cross-sectional view showing an embodiment of a method of manufacturing a semiconductor integrated circuit device;

[0046] Figure 13A and Figure 13B is a cross-sectional view showing an embodiment of a method of manufacturing a semiconductor integrated circuit device; and

[0047] Figure 14 is a schematic view of an electronic device according to an embodiment. DETAILED DESCRIPTION

[0048] Reference will now be made in detail embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the drawings, to explain aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding the list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0049] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same elements are designated by the same reference numerals, and the dimensions of elements can be exaggerated for clarity and convenience. The embodiments described below are only examples, and various modifications can be made to the embodiments.

[0050] Herein, a component referred to as "above" or "on" another component can be directly on, or below, or left or right of the other component, or an intervening component can be present such that the component can be on the intervening component and non-contacting on the other component. An expression used in the singular encompasses the expression in the plural, unless it has a clearly different meaning in the context. When a part "includes" a component, it means that the part can include only the component or can include other components, unless it is specifically stated to the contrary.

[0051] The use of the term "the" and similar referents is to be interpreted as encompassing singular and plural. The steps of all methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context.

[0052] In addition, terms such as "…unit", "…module", etc. refer to a unit that performs at least one function or operation, and the unit can be implemented as hardware or software or a combination of hardware and software.

[0053] In addition, the connection lines or connectors shown in the various figures presented herein are intended to represent example functional relationships and / or physical or logical couplings between the various elements. It is to be noted that many alternatives or substitutions can be made to the functional relationships, physical connections or logical connections in actual devices.

[0054] The use of any and all examples, or exemplary language provided herein, is intended merely to better illuminate the present inventive concepts and does not pose a limitation on the scope of the disclosure unless otherwise claimed.

[0055] Figure 1is a schematic cross-sectional view of a semiconductor integrated circuit device according to an embodiment. The semiconductor integrated circuit device includes two or more devices. In the present embodiment, a semiconductor integrated circuit device including two or more high electron mobility transistors (HEMTs) will be described as an example, but the present disclosure is not limited thereto. The HEMT can include semiconductor layers having different electrode polarization properties. In the HEMT, a semiconductor layer having a relatively high polarization rate can introduce a two-dimensional electron gas (2DEG) to another semiconductor layer combined therewith, and the 2DEG can have a very high electron mobility. When a normally-on state in which a current flows at 0 V gate voltage due to a relatively low resistance between a drain electrode and a source electrode is reached in the HEMT, current and power can be consumed, and in order to change the current between the drain electrode and the source electrode to an off state, a negative voltage is to be applied to the gate electrode. To address these issues, a depletion formation layer can be included to achieve a normally-off characteristic in which the current between the drain electrode and the source electrode is in an off state when the gate voltage is 0 V.

[0056] Referring to Figure 1 , the semiconductor integrated circuit device can include a channel layer 20, a barrier layer 30 provided on the channel layer 20 and inducing a 2DEG in the channel layer 20, and a first p-type semiconductor layer 41 and a second p-type semiconductor layer 42 spaced apart from each other on the barrier layer 30. The first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can have different active dopant concentrations from each other. In Figure 1 , the above-described material layers can be formed on a substrate (not shown), and Figure 1 shows a state in which the substrate is removed after the semiconductor integrated circuit device including two or more HEMTs is formed.

[0057] The channel layer 20 can include a material in which a 2DEG can be formed inside thereof. The barrier layer 30 can include a material having a larger band gap than the channel layer 20. The first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 are formed on the barrier layer 30. The first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can have different band gaps from the barrier layer 30. The channel layer 20, the barrier layer 30, and the first and second p-type semiconductor layers 41 and 42 can include the same material and can be distinguished from each other by their relative positions and / or different material compositions. For example, the channel layer 20, the barrier layer 30, and the first and second p-type semiconductor layers 41 and 42 can have a single-layer or multi-layer structure including at least one material selected from among nitrides including Group III-V materials (e.g., at least one of Al, Ga, and In). For example, the channel layer 20, the barrier layer 30, and the first and second p-type semiconductor layers 41 and 42 can include Al x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layer 20, the barrier layer 30, and the first and second p-type semiconductor layers 41 and 42 can include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, and AlInGaN.

[0058] For example, the channel layer 20 can include GaN, and can be an undoped layer or a layer doped with impurities. The channel layer 20 can have a thickness of approximately several hundred nm or less. For example, the barrier layer 30 can include AlGaN. For example, the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can include GaN. The first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can be p-type semiconductor layers doped with a p-type impurity such as magnesium (Mg).

[0059] The first and second gates 51 and 52 contact the first and second p-type semiconductor layers 41 and 42, respectively. The first source 61 and the first drain 71 are located on both sides of the first p-type semiconductor layer 41 and electrically contact the channel layer 20. The second source 62 and the second drain 72 are located on both sides of the second p-type semiconductor layer 42 and electrically contact the channel layer 20. The first and second gates 51 and 52, the first and second sources 61 and 62, and the first and second drains 71 and 72 can include conductive materials.

[0060] The first HEMT 11 can be implemented by the channel layer 20, the barrier layer 30, the first p-type semiconductor layer 41, the first gate 51, the first source 61, and the first drain 71. Also, the second HEMT 12 can be implemented by the channel layer 20, the barrier layer 30, the second p-type semiconductor layer 42, the second gate 52, the second source 62, and the second drain 72. Although a semiconductor integrated circuit device including two HEMTs is shown as an example in Figure 1 However, the semiconductor integrated circuit device can include three or more HEMTs.

[0061] The first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 serve as depletion formation layers. Since the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can increase the band gap of the portion of the barrier layer 30 that corresponds to the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42, a depletion region of the 2DEG can be formed in the portion of the channel layer 20 that corresponds to the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42. Thus, the portion of the 2DEG that corresponds to the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can be cut or have different characteristics (e.g., different electron concentration) from other portions thereof. The region in which the 2DEG is cut can be referred to as a "break region", and due to the break region, the first and second HEMTs 11 and 12 can have normally-off characteristics, i.e., no current flows between the drain and the source at a gate voltage of 0 V.

[0062] In a semiconductor integrated circuit device including a plurality of HEMTs, at least one of the plurality of HEMTs can have a threshold voltage different from those of the other HEMTs. The threshold voltage of a HEMT can be adjusted by adjusting the thickness, composition, or the like of a semiconductor layer (e.g., the barrier layer 30). However, a method of adjusting the threshold voltage of each HEMT by changing the thickness or composition of the semiconductor layer of each HEMT in an integrated circuit device can not be practical in terms of process complexity or performance stability. As another method, the threshold voltage of the first HEMT 11 and the threshold voltage of the second HEMT 12 can be made different from each other by adjusting the doping concentration of the first and second p-type semiconductor layers 41 and 42. In this case, since the first and second p-type semiconductor layers 41 and 42 are to be grown under different process conditions, the manufacturing process of the semiconductor integrated circuit device can be complex. As another method, a method of adjusting the threshold voltage of a HEMT by implanting a negatively charged ion such as a F ion into the barrier layer 30 can be considered. However, it can be difficult to change the amount of ion to be implanted differently depending on the position in the barrier layer 30, and it can be difficult to adjust the projection range Rp when a negative ion is implanted into a relatively thin barrier layer 30.

[0063] The semiconductor integrated circuit device according to the present embodiment can have a structure in which the dopants of the relatively thick first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 are selectively and partially deactivated. Thus, the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 have different active dopant concentrations from each other, and the first HEMT 11 and the second HEMT 12 have different threshold voltages from each other. The active dopant concentration refers to the concentration of dopants that are not deactivated.

[0064] Reference Signs List Figure 1The semiconductor integrated circuit device can include a passivation layer 80 formed on the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42. The passivation layer 80 can partially deactivate at least one of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 in a process of forming the passivation layer 80. The passivation layer 80 can provide a deactivating ion to at least one of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 in a process of forming the passivation layer 80. The deactivating ion combines with a portion of a dopant of at least one of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 to deactivate the portion of the dopant, thereby changing an active dopant concentration of at least one of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42. The deactivating ion can be, for example, a hydrogen ion.

[0065] The passivation layer 80 can include a first portion 80a on the first p-type semiconductor layer 41 and a second portion 80b on the semiconductor layer 42, and at least one of a thickness and a material composition of the first portion 80a can be different from the second portion 80b. For example, the passivation layer 80 can include a first passivation layer 81 on the first p-type semiconductor layer 41 and a second passivation layer 82 on the first passivation layer 81 and the second p-type semiconductor layer 42. In this case, the first portion 80a includes the first and second passivation layers 81 and 82 stacked in order, and the second portion 80b includes the second passivation layer 82. Accordingly, the passivation layer 80 having the first portion 80a and the second portion 80a with different thicknesses can be implemented. The first passivation layer 81 and the second passivation layer 82 can include different materials from each other. For example, at least one of the first passivation layer 81 and the second passivation layer 82 can include a material through which a dopant of at least one of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can be partially deactivated. At least one of the first passivation layer 81 and the second passivation layer 82 can provide a hydrogen ion as a deactivating ion to at least one of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42.

[0066] For example, the first passivation layer 81 can partially deactivate the first p-type semiconductor layer 41, and the second passivation layer 82 can partially deactivate the second p-type semiconductor layer 42. The first passivation layer 81 is formed on the entire barrier layer 30 including the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42, and then the first passivation layer 81 on the second p-type semiconductor layer 42 is removed by an etching process to expose the second p-type semiconductor layer 42. In this case, the first passivation layer 81 can partially deactivate the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42. For example, the first passivation layer 81 and the second passivation layer 82 can provide deactivating ions to the first and second p-type semiconductor layers 41 and 42 in a forming process of the first passivation layer 81 and the second passivation layer 82. The deactivating ions can include, for example, hydrogen ions. The first passivation layer 81 and the second passivation layer 82 can include a material that can provide hydrogen ions. For example, the first passivation layer 81 and the second passivation layer 82 can include nitride. The nitride can include, for example, SiN or SiO x N y .

[0067] The SiN first passivation layer 81 and the SiN second passivation layer 82 can be formed by providing process gases such as NH3 and SiH4, and hydrogen ions are generated in this process. First, in a process of forming the SiN first passivation layer 81, hydrogen ions are implanted into the first and second p-type semiconductor layers 41 and 42 whose upper surfaces are exposed. The hydrogen ions react with dopants (for example, with Mg) in the first and second p-type semiconductor layers 41 and 42 to form MgH2 and deactivate Mg, and thus the active dopant concentration of the first and second p-type semiconductor layers 41 and 42 is reduced. Next, in a process of forming the SiN second passivation layer 82, hydrogen ions are implanted into the second p-type semiconductor layer 42 whose upper surface is exposed. The hydrogen ions react with dopants (for example, with Mg) in the second p-type semiconductor layer 42 to form MgH2 and deactivate Mg, and thus the active dopant concentration in the second p-type semiconductor layer 42 is further reduced. According to this configuration, since the active dopant concentrations of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 are made different from each other, it is possible to implement a semiconductor integrated circuit device including the first HEMT 11 and the second HEMT 12 having threshold voltages different from each other.

[0068] For example, the first passivation layer 81 can be formed on the first p-type semiconductor layer 41 and function as a protective layer that limits and / or prevents deactivation of the dopant of the first p-type semiconductor layer 41, and the second passivation layer 82 can function as a passivation layer for partially deactivating the dopant of the second p-type semiconductor layer 42 in a formation process. For example, the second passivation layer 82 can provide hydrogen ions as deactivating ions to the second p-type semiconductor layer 42 in a formation process thereof, and the first passivation layer 81 can limit and / or prevent the hydrogen ions from penetrating into the first p-type semiconductor layer 41. The first passivation layer 81 can include, for example, an oxide. The oxide can include, for example, SiO2, HfOx, Al2O3, or the like. The second passivation layer 82 can include a material that can provide hydrogen ions. For example, the second passivation layer 82 can include a nitride. The nitride can include, for example, SiN or SiO x N y .

[0069] The SiN second passivation layer 82 can be formed by providing process gases such as NH3 and SiH4, and hydrogen ions are generated in this process. The hydrogen ions are implanted into the second p-type semiconductor layer 42 of which the upper surface is exposed. The hydrogen ions react with the dopant (for example, with Mg) in the second p-type semiconductor layer 42 to form MgH2 and deactivate Mg, and thus the active dopant concentration of the second p-type semiconductor layer 42 decreases. The first p-type semiconductor layer 41 is protected by the SiO2 first passivation layer 81. Since the hydrogen ions are blocked by the SiO2 first passivation layer 81 and thus are not implanted into the first p-type semiconductor layer 41, the active dopant concentration of the first p-type semiconductor layer 41 does not change. According to this configuration, since the active dopant concentrations of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 are different from each other, a semiconductor integrated circuit device including the first HEMT 11 and the second HEMT 12 having different threshold voltages from each other can be implemented.

[0070] When the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 have the same initial dopant concentration, the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can be formed at the same process conditions at the same time. Also, by providing the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 with the same thickness, the process of forming the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can be simplified. After forming the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42, by adjusting the active dopant concentration of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 by appropriately selecting the material composition and thickness of the passivation layer on the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 in the process of forming the passivation layer 80, which is an interlayer dielectric layer, the first HEMT 11 and the second HEMT 12 having different threshold voltages from each other can be realized. The active dopant concentration of the second p-type semiconductor layer 42 can be controlled by process conditions such as the thickness of the passivation layer such as the second passivation layer 82, the flow rate of the precursor for forming the passivation layer, and the like. The thicker the deactivation layer such as the second passivation layer 82, the longer the process time for forming the second passivation layer 82, and the higher the flow rate of the precursor material, and therefore, more hydrogen ions can penetrate into the second p-type semiconductor layer 42 to deactivate more dopants. Thus, the active dopant concentration of the second p-type semiconductor layer 42 can be further reduced.

[0071] The composition of the passivation layer on the first p-type semiconductor layer 41 can be different from the composition of the passivation layer on the second p-type semiconductor layer 42. In Figure 1 In the illustrated embodiment, the passivation layer on the first p-type semiconductor layer 41 can have a multi-layer structure including a nitride first passivation layer 81 and a nitride second passivation layer 82, or an oxide first passivation layer 81 and a nitride second passivation layer 82, and the passivation layer on the second p-type semiconductor layer 42 can have a single-layer structure including a nitride second passivation layer 82. By changing the thickness and / or material composition of the passivation layer of the first and second HEMTs 11 and 12, a semiconductor integrated circuit device including the first and second HEMTs 11 and 12 having different threshold voltages from each other can be realized by a simple process. Reference numeral 83 can denote an insulating layer.

[0072] The threshold voltage of a HEMT can be adjusted by the thickness of the p-type semiconductor layer. In an embodiment, the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can have different thicknesses from each other. Figure 2 is a schematic cross-sectional view of an embodiment of a semiconductor integrated circuit device. In Figure 1In the embodiment of the semiconductor integrated circuit device shown, the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 have the same thickness as each other, and the first gate 51 and the second gate 52 are in contact with the upper surfaces of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42, respectively. Referring to Figure 2 , the semiconductor integrated circuit device according to the present embodiment is different from the embodiment of the semiconductor integrated circuit device shown in Figure 1 in that the thicknesses of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 are different from each other. Hereinafter, the description will focus on the difference. For example, the thickness T1 of the first p-type semiconductor layer 41 can be greater than the thickness T2 of the second p-type semiconductor layer 42. According to this configuration, the difference between the active dopant concentrations of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 is further increased, and the difference between the threshold voltages of the first HEMT 11 and the second HEMT 12 can be further increased.

[0073] The actual thickness of the p-type semiconductor layer can be controlled using the gate. Figure 3 is a schematic cross-sectional view of an embodiment of a semiconductor integrated circuit device. In Figure 1 the embodiment of the semiconductor integrated circuit device shown, the first gate 51 and the second gate 52 are in contact with the upper surfaces of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42, respectively. Referring to Figure 3 , the semiconductor integrated circuit device according to the present embodiment is different from the embodiment of the semiconductor integrated circuit device shown in Figure 1 in that the second gate 52 is partially inserted into the second p-type semiconductor layer 42. Hereinafter, the description will focus on the difference. The first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 have the same thickness as each other. The first gate 51 is in contact with the upper surface of the first p-type semiconductor layer 41. The second gate 52 is inserted into the second p-type semiconductor layer 42, beyond the upper surface of the second p-type semiconductor layer 42. The second gate 52 can extend to a certain position between the upper surface and the lower surface of the second p-type semiconductor layer 42. The effect of reducing the thickness of the second p-type semiconductor layer 42 can be obtained by the second gate 52 inserted into the second p-type semiconductor layer 42. According to this configuration, it is possible to make the active dopant concentrations of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 different from each other, and at the same time, it is also possible to make the thicknesses of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 different from each other, thereby making the threshold voltages of the first HEMT 11 and the second HEMT 12 different from each other.

[0074] The shape of the second gate 52 applied to the embodiment of the semiconductor integrated circuit device shown in Figure 3 can also be applied to Figure 2Embodiments of the semiconductor integrated circuit device shown. Figure 4 is a schematic cross-sectional view of an embodiment of the semiconductor integrated circuit device. In Figure 2 Embodiments of the semiconductor integrated circuit device shown differ from the semiconductor integrated circuit device shown in FIG. 1 in that the first and second gates 51 and 52 are formed on the first and second p-type semiconductor layers 41 and 42, respectively, and a passivation layer 80 is formed on the first and second gates 51 and 52. In this case, also, in the process of forming the nitride first passivation layer 81, the dopant of the first p-type semiconductor layer 41 or the dopants of the first and second p-type semiconductor layers 41 and 42 can be partially deactivated, and the dopant of the second p-type semiconductor layer 42 can be partially deactivated by the nitride second passivation layer 82. Referring to Figure 4 , the semiconductor integrated circuit device according to the present embodiment differs from the semiconductor integrated circuit device shown in FIG. 1 in that the first and second gates 51 and 52 are formed on the first and second p-type semiconductor layers 41 and 42, respectively, and a passivation layer 80 is formed on the first and second gates 51 and 52. In this case, also, in the process of forming the nitride first passivation layer 81, the dopant of the first p-type semiconductor layer 41 or the dopants of the first and second p-type semiconductor layers 41 and 42 can be partially deactivated, and the dopant of the second p-type semiconductor layer 42 can be partially deactivated by the nitride second passivation layer 82. Referring to Figure 2 Embodiments of the semiconductor integrated circuit device shown differ from the semiconductor integrated circuit device shown in FIG. 1 in that the first and second gates 51 and 52 are formed on the first and second p-type semiconductor layers 41 and 42, respectively, and a passivation layer 80 is formed on the first and second gates 51 and 52. In this case, also, in the process of forming the nitride first passivation layer 81, the dopant of the first p-type semiconductor layer 41 or the dopants of the first and second p-type semiconductor layers 41 and 42 can be partially deactivated, and the dopant of the second p-type semiconductor layer 42 can be partially deactivated by the nitride second passivation layer 82. Referring to

[0075] Figure 5 and Figure 6 is a schematic cross-sectional view of an embodiment of the semiconductor integrated circuit device. First, referring to Figure 5 , the semiconductor integrated circuit device according to the present embodiment differs from the semiconductor integrated circuit device shown in FIG. 1 in that the first and second gates 51 and 52 are formed on the first and second p-type semiconductor layers 41 and 42, respectively, and a passivation layer 80 is formed on the first and second gates 51 and 52. In this case, also, in the process of forming the nitride first passivation layer 81, the dopant of the first p-type semiconductor layer 41 or the dopants of the first and second p-type semiconductor layers 41 and 42 can be partially deactivated, and the dopant of the second p-type semiconductor layer 42 can be partially deactivated by the nitride second passivation layer 82. Referring to Figure 1 , the semiconductor integrated circuit device according to the present embodiment differs from the semiconductor integrated circuit device shown in FIG. 1 in that the first and second gates 51 and 52 are formed on the first and second p-type semiconductor layers 41 and 42, respectively, and a passivation layer 80 is formed on the first and second gates 51 and 52. In this case, also, in the process of forming the nitride first passivation layer 81, the dopant of the first p-type semiconductor layer 41 or the dopants of the first and second p-type semiconductor layers 41 and 42 can be partially deactivated, and the dopant of the second p-type semiconductor layer 42 can be partially deactivated by the nitride second passivation layer 82. Referring to Figure 6 , the semiconductor integrated circuit device according to the present embodiment differs from the semiconductor integrated circuit device shown in FIG. 1 in that the first and second gates 51 and 52 are formed on the first and second p-type semiconductor layers 41 and 42, respectively, and a passivation layer 80 is formed on the first and second gates 51 and 52. In this case, also, in the process of forming the nitride first passivation layer 81, the dopant of the first p-type semiconductor layer 41 or the dopants of the first and second p-type semiconductor layers 41 and 42 can be partially deactivated, and the dopant of the second p-type semiconductor layer 42 can be partially deactivated by the nitride second passivation layer 82. Referring to Figure 5 , the semiconductor integrated circuit device according to the present embodiment differs from the semiconductor integrated circuit device shown in FIG. 1 in that the first and second gates 51 and 52 are formed on the first and second p-type semiconductor layers 41 and 42, respectively, and a passivation layer 80 is formed on the first and second gates 51 and 52. In this case, also, in the process of forming the nitride first passivation layer 81, the dopant of the first p-type semiconductor layer 41 or the dopants of the first and second p-type semiconductor layers 41 and 42 can be partially deactivated, and the dopant of the second p-type semiconductor layer 42 can be partially deactivated by the nitride second passivation layer 82. Referring to

[0076] Hereinafter, embodiments of a method of manufacturing a semiconductor integrated circuit device will be described. In the method of manufacturing a semiconductor integrated circuit device, a channel layer, a barrier layer that causes 2DEG in the channel layer, and a p-type semiconductor layer are sequentially formed, and a dopant of a partial region of the p-type semiconductor layer can be partially deactivated. Deactivation can be performed using various methods. For example, the p-type semiconductor layer can be divided into a region protected by a protective layer and a region not protected, and the dopant of the region not protected can be partially deactivated.

[0077] An embodiment of a method of manufacturing a semiconductor integrated circuit device can include sequentially forming a channel layer, a barrier layer that causes 2DEG in the channel layer, and a p-type semiconductor layer; dividing the p-type semiconductor layer into a first p-type semiconductor layer and a second p-type semiconductor layer separated from each other; forming a first passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer; exposing the second p-type semiconductor layer by etching the first passivation layer; forming a second passivation layer on the first passivation layer and the second p-type semiconductor layer, wherein at least one of the first passivation layer and the second passivation layer can provide a deactivation ion for deactivating a dopant of a corresponding p-type semiconductor layer in the at least one of the first passivation layer and the second passivation layer in a forming process of the at least one of the first passivation layer and the second passivation layer. The deactivation ion can include a hydrogen ion.

[0078] In the forming process of the first passivation layer and the second passivation layer, the first passivation layer and the second passivation layer can partially deactivate the dopants of the first p-type semiconductor layer and the second p-type semiconductor layer. The first passivation layer and the second passivation layer can include a nitride. The nitride can include at least one of SiN and SiN x O y .

[0079] The second passivation layer can partially deactivate the dopant of the second p-type semiconductor layer, and the first passivation layer can limit and / or prevent deactivation of the first p-type semiconductor layer. The first passivation layer can include an oxide, and the second passivation layer can include a nitride. The oxide can include at least one of SiO2, HfO x , and Al2O3, and the nitride can include at least one of SiN and SiN x O y .

[0080] The method can include partially deactivating the dopant of the second p-type semiconductor layer before forming the second passivation layer. The partial deactivation can include supplying a hydrogen ion to the second p-type semiconductor layer.

[0081] The method includes forming first and second gates in contact with the first and second p-type semiconductor layers, respectively, wherein at least one of the first and second gates can be partially inserted into the p-type semiconductor layer corresponding to at least one of the first and second gates.

[0082] Figures 7A to 7F is a diagram illustrating an embodiment of a method of manufacturing a semiconductor integrated circuit device. Figures 7A to 7F The illustrated embodiment of the method of manufacturing a semiconductor integrated circuit device involves sequentially forming a channel layer, a barrier layer that induces 2DEG in the channel layer, and a p-type semiconductor layer, and partially deactivating a dopant of a partial region of the p-type semiconductor layer. In Figures 7A to 7F The growth substrate is omitted in

[0083] First, referring to Figure 7A A channel layer 20, a barrier layer 30 that induces 2DEG in the channel layer 20, and a p-type semiconductor layer 40 are sequentially formed on a substrate (not shown). The channel layer 20, the barrier layer 30, and the p-type semiconductor layer 40 can have a single layer or a multi-layer structure including at least one material selected from nitrides including III-V group materials (e.g., at least one of Al, Ga, and In). For example, the channel layer 20, the barrier layer 30, and the p-type semiconductor layer 40 can include Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layer 20, the barrier layer 30, and the p-type semiconductor layer 40 can include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, and AlInGaN. The channel layer 20, the barrier layer 30, and the p-type semiconductor layer 40 can include the same material as each other, and can be distinguished from each other by their relative positions and / or different material compositions. For example, the channel layer 20 can include GaN, and can be an undoped layer or a layer doped with an impurity. The channel layer 20 can have a thickness of about several hundred nm or less. For example, the barrier layer 30 can include AlGaN. For example, the p-type semiconductor layer 40 includes GaN. The p-type semiconductor layer 40 can be doped with a p-type impurity such as Mg. As Figure 7A As shown by the dotted line in

[0084] The substrate may include, but is not limited to, sapphire, Si, SiC, or GaN, and may include a variety of other materials. For example, although not shown in the figures, a seed layer and a buffer layer may be sequentially provided on the substrate, and a channel layer 20 may be formed on the buffer layer. The seed layer may be a base layer for growing the buffer layer. The buffer layer mitigates the difference in lattice constant and coefficient of thermal expansion between the substrate and the channel layer 20, thereby limiting and / or preventing a decrease in the crystallinity of the channel layer 20. The buffer layer may include at least one material selected from nitrides comprising group III-V materials (e.g., at least one of Al, Ga, and In).

[0085] Next, as Figure 7A As shown by the solid lines, the p-type semiconductor layer 40 is divided into a first p-type semiconductor layer 41 and a second p-type semiconductor layer 42 that are separated from each other. The partitioning operation can be performed by forming an etch mask on the p-type semiconductor layer 40 and partially etching the p-type semiconductor layer 40. Therefore, the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42, having the same doping concentration and the same thickness, are formed on the barrier layer 30.

[0086] Next, refer to Figure 7B A first passivation layer 81 is formed on the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42. Next, as... Figure 7C As shown, the first passivation layer 81 is partially etched to expose the second p-type semiconductor layer 42. Next, as... Figure 7D As shown, a second passivation layer 82 is formed on the second p-type semiconductor layer 42. The second passivation layer 82 may also be formed on the first passivation layer 81. Therefore, the process for forming the second passivation layer 82 can be simplified. At least one of the first passivation layer 81 and the second passivation layer 82 may provide deactivating ions during its formation process for deactivating the dopant of the p-type semiconductor layer 40. The deactivating ions may include, for example, hydrogen ions.

[0087] For example, the first passivation layer 81 and the second passivation layer 82 can partially deactivate the dopants in the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 during their formation process. For example, the first passivation layer 81 can partially deactivate the first p-type semiconductor layer 41, and the second passivation layer 82 can partially deactivate the second p-type semiconductor layer 42. For example, the first passivation layer 81 and the second passivation layer 82 can include nitrides. Nitrides can include, for example, SiN and SiO. x N y At least one of them.

[0088] For example, the SiN first passivation layer 81 and the SiN second passivation layer 82 can be formed by providing process gases such as NH3 and SiH4, and hydrogen ions are generated in this process. First, as Figure 7BAs shown, in the process of forming the first SiN passivation layer 81, hydrogen ions are implanted into the first and second p-type semiconductor layers 41 and 42, whose upper surfaces are exposed. The hydrogen ions react with dopants (e.g., with Mg) in the first and second p-type semiconductor layers 41 and 42 to form MgH2 and deactivate Mg, thus reducing the concentration of active dopants in the first and second p-type semiconductor layers 41 and 42. Next, as... Figure 7D As shown, in the process of forming the SiN second passivation layer 82, hydrogen ions are implanted into the second p-type semiconductor layer 42, whose upper surface is exposed. The hydrogen ions react with dopants (e.g., with Mg) in the second p-type semiconductor layer 42 to form MgH2, deactivating Mg and further reducing the concentration of active dopants in the second p-type semiconductor layer 42. According to this configuration, since the concentrations of active dopants in the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 are different from each other, a semiconductor integrated circuit device including a first HEMT 11 and a second HEMT 12 having different threshold voltages can be realized.

[0089] For example, the second passivation layer 82 may be a passivation layer that partially deactivates the dopants in the second p-type semiconductor layer 42, and the first passivation layer 81 may be a protective layer for limiting and / or preventing the deactivation of the first p-type semiconductor layer 41. The first passivation layer 81 may include, for example, an oxide. The oxide may include, for example, SiO2, HfO. x Al2O3, etc. The second passivation layer 82 may include nitrides that can provide hydrogen ions, such as SiN and SiN2O3. x O y At least one of them. For example, by providing, for example, NH3 and SiH4 as process gases, a second SiN passivation layer 82 can be formed, such as... Figure 7D As shown, in this process, hydrogen ions are generated and implanted into a second p-type semiconductor layer 42 exposed on its upper surface. The hydrogen ions react with a dopant, such as Mg, in the second p-type semiconductor layer 42 to form MgH2, thereby deactivating Mg. Therefore, the concentration of active dopant in the second p-type semiconductor layer 42 is reduced. The first p-type semiconductor layer 41 is protected by, for example, a SiO2 first passivation layer 81; therefore, hydrogen ions are not implanted into the first p-type semiconductor layer 41. Therefore, the concentration of active dopant in the first p-type semiconductor layer 41 remains unchanged. According to this structure, the concentration of active dopant in the first p-type semiconductor layer 41 differs from the concentration of active dopant in the second p-type semiconductor layer 42.

[0090] Next, as Figure 7EAs shown, a first gate 51 and a second gate 52 are formed to contact the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42, respectively. For example, a via 51a is formed through the second passivation layer 82 and the first passivation layer 81, and a first gate 51 that contacts the upper surface of the first p-type semiconductor layer 41 through the via 51a can be formed on the second passivation layer 82. Furthermore, a via 52a can be formed through the second passivation layer 82, and a second gate 52 that contacts the upper surface of the second p-type semiconductor layer 42 through the via 52a can be formed on the second passivation layer 82. The first gate 51 and the second gate 52 may comprise conductive metals or metal compounds, etc.

[0091] Next, as Figure 7F As shown, an insulating layer 83 is formed on the first and second gates 51 and 52 and the second passivation layer 82. The insulating layer 83 may include, for example, an oxide. Next, first and second source electrodes 61 and 62 and first and second drain electrodes 71 and 72 are formed to contact the channel layer 20. The first source electrode 61 and the first drain electrode 71 are located on both sides of the first p-type semiconductor layer 41 and pass through the insulating layer 83, the second passivation layer 82, and the first passivation layer 81 to contact the channel layer 20. The first source electrode 61 and the first drain electrode 71 may extend beyond the channel layer 20 to partially insert into the channel layer 20. The second source electrode 62 and the second drain electrode 72 are located on both sides of the second p-type semiconductor layer 42 and pass through the insulating layer 83 and the second passivation layer 82 to contact the channel layer 20. The second source electrode 62 and the second drain electrode 72 may extend beyond the channel layer 20 to partially insert into the channel layer 20. The first and second source electrodes 61 and 71 and the first and second drain electrodes 62 and 72 may include a conductive material. The conductive material may include, for example, a conductive metal or a conductive metal oxide.

[0092] According to this configuration, the first HEMT 11 and the second HEMT 12 can have different threshold voltages from each other. According to the manufacturing method of the present embodiment, since the initial dopant concentrations of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can be the same as each other, the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can be formed at the same process conditions at the same time. Also, by providing the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 with the same thickness, the process of forming the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 can be simplified. After forming the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42, by appropriately selecting the types and thicknesses of the first and second passivation layers 81 and 82 on the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 in the process of forming the passivation layer as an interlayer dielectric layer to adjust the active dopant concentrations of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42, the first HEMT 11 and the second HEMT 12 having different threshold voltages from each other can be realized. The active dopant concentration of the second p-type semiconductor layer 42 can be controlled by process conditions such as the thickness of the second passivation layer 82, the flow rate of the precursor, the process temperature, and the like. The thicker the second passivation layer 82, the longer the process time of forming the second passivation layer 82, and the higher the flow rate of the precursor material, the more hydrogen can penetrate into the second p-type semiconductor layer 42 to deactivate more dopants. Thus, the active dopant concentration of the second p-type semiconductor layer 42 can be further reduced.

[0093] At least one of the first gate 51 and the second gate 52 can be partially inserted into the p-type semiconductor layer. The above-described structure can be provided by replacing the operations of Figure 8A and Figure 8B described above with the operations of Figure 7E described below. Figure 8A and Figure 8B are diagrams illustrating an embodiment of a method of manufacturing a semiconductor integrated circuit device. The operations of Figures 7A to 7D described above are performed. Next, as shown in Figure 8A , a via 51a is formed through the second passivation layer 82 and the first passivation layer 81 to expose the upper surface of the first p-type semiconductor layer 41. Also, a via 52a is formed through the second passivation layer 82 to extend beyond the upper surface of the second p-type semiconductor layer 42 and partially into the second p-type semiconductor layer 42. Next, as shown in Figure 8B , a first gate 51 that contacts the upper surface of the first p-type semiconductor layer 41 via the via 51a and a second gate 52 that is partially inserted into the second p-type semiconductor layer 42 via the via 52a can be formed on the second passivation layer 82. According to this configuration, the semiconductor integrated circuit device shown in Figure 3 can be realized.

[0094] In one embodiment, as shown in Figure 8C and Figure 8D , a semiconductor integrated circuit device can be formed in which the first gate 51 is partially inserted into the first p-type semiconductor layer 41 via the via 51a, and the second gate 52 can be partially inserted into the second p-type semiconductor layer 42 via the via 52a. Figure 8C and Figure 8D is different from the embodiment in Figure 8A and Figure 8B in that Figure 8C the via 51a formed in Figure 8D penetrates through the second passivation layer 82 and the first passivation layer 81 to partially penetrate into the first p-type semiconductor layer 41. Although not shown, in Figure 3 an insulating layer 83 can be formed over the second passivation layer 82, the first gate 51, and the second gate 52. Then, the first and second source 61 and 62 and the first and second drain 71 and 72 connecting the channel layer 20 can be formed as shown in

[0095] In one embodiment, as shown in Figure 8E and Figure 8F , a semiconductor integrated circuit device can be formed in which the first gate 51 is partially inserted into the first p-type semiconductor layer 41 via the via 51a, and the second gate 52 contacts the upper surface of the second p-type semiconductor layer 42 via the via 52a. Figure 8E and Figure 8F is different from the embodiment in Figure 8A and Figure 8B in that Figure 8E the via 51a formed in Figure 8E penetrates through the second passivation layer 82 and the first passivation layer 81 to partially penetrate into the first p-type semiconductor layer 41. In addition, in Figure 8E the via 52a penetrates the second passivation layer 82 to contact the upper surface of the second p-type semiconductor layer 42, but does not penetrate into the second p-type semiconductor layer 42. Although not shown, in Figure 3 an insulating layer 83 can be formed over the second passivation layer 82, the first gate 51, and the second gate 52. Then, the first and second source 61 and 62 and the first and second drain 71 and 72 connecting the channel layer 20 can be formed as shown in Figure 9 is a diagram showing one embodiment of the operation of deactivating the second p-type semiconductor layer 42. Referring to Figure 9 , the above-mentioned Figures 7A to 7CAfter the operation of the first p-type semiconductor layer 41 is covered and protected by the first passivation layer 81, and the second p-type semiconductor layer 42 is exposed. In this state, the second p-type semiconductor layer 42 can be partially deactivated. The partial deactivation can include supplying hydrogen ions to the second p-type semiconductor layer 42. For example, in a high voltage state, a source gas such as NH3 gas can be supplied into the reaction chamber. The NH3 gas can then be dissolved to generate hydrogen ions, and the hydrogen ions are injected into the exposed second p-type semiconductor layer 42. The hydrogen ions react with the dopant such as Mg in the second p-type semiconductor layer 42 to form MgH2, thereby deactivating the Mg. Thus, the active dopant concentration in the second p-type semiconductor layer 42 can be reduced. In this operation, hydrogen gas can also be used instead of NH3 gas as the process gas. Next, the operation of forming the second passivation layer 82 can be performed. Figures 7D to 7F According to this configuration, the control range of the active dopant concentration of the second p-type semiconductor layer 42 can be increased without excessively increasing the process time for forming the second passivation layer 82, i.e., without excessively increasing the thickness of the second p-type passivation layer 82.

[0096] In the above-described embodiment of the method of manufacturing a semiconductor integrated circuit device, the gate is formed first, and then the source and the drain are formed, but the source and the drain can be formed first, and then the gate is formed.

[0097] The gate can also be formed on the p-type semiconductor layer before the passivation layer is formed on the p-type semiconductor layer. In this case, Figures 7A to 7E the operation of forming the second passivation layer 82 can be replaced by the operation shown in Figures 10A to 10E . Figures 10A to 10E is a diagram illustrating an embodiment of a method of manufacturing a semiconductor integrated circuit device. First, as shown in Figure 10A , a channel layer 20, a barrier layer 30 that induces 2DEG in the channel layer 20, and a p-type semiconductor layer 40 are sequentially formed on a substrate (not shown). Next, a gate layer 50 is formed on the p-type semiconductor layer 40. The gate layer 50 can include a layer of conductive material. Next, as shown in Figure 10B , the p-type semiconductor layer 40 and the gate layer 50 are etched to divide them into a first stack including a first p-type semiconductor layer 41 and a first gate 51, and a second stack including a second p-type semiconductor layer 42 and a second gate 52 that are spaced apart from each other.

[0098] Next, as shown in Figure 10C , a first passivation layer 81 is formed on the first stack including the first p-type semiconductor layer 41 and the first gate 51, and the second stack including the second p-type semiconductor layer 42 and the second gate 52. Next, as shown in Figure 10D , the first passivation layer 81 is partially etched to expose the second stack including the second p-type semiconductor layer 42 and the second gate 52. Next, as shown in Figure 10EAs shown, a second passivation layer 82 is formed on a second stack including a second p-type semiconductor layer 42 and a second gate 52. The second passivation layer 82 may also be formed on the first passivation layer 81. As described above, the material composition of the first and second passivation layers 81 and 82 may be a combination of nitride-nitride layers or a combination of oxide-nitride layers. For example, when the material composition of the first passivation layer 81 and the second passivation layer 82 is a nitride-nitride layer, in the process of forming the first passivation layer 81, the dopants of the first p-type semiconductor layer 41 and the second p-type semiconductor layer 42 are partially deactivated, and in the process of forming the second passivation layer 82, the dopants of the second p-type semiconductor layer 42 are additionally partially deactivated. For example, when the material composition of the first passivation layer 81 and the second passivation layer 82 is an oxide-nitride layer, in the process of forming the second passivation layer 82, the dopants of the second p-type semiconductor layer 42 are partially deactivated. Furthermore, during the execution... Figure 10D The operation shown is followed by execution. Figure 10E Before the operation shown, you can perform... Figure 9 The operation shown partially deactivates the dopant in the second p-type semiconductor layer 42. Next, the following can be performed: Figure 7F The operation shown forms the first and second source electrodes 61 and 62 and the first and second drain electrodes 71 and 72.

[0099] One embodiment of a method for manufacturing a semiconductor integrated circuit device may include: sequentially forming a channel layer, a barrier layer that induces 2DEG in the channel layer, and a p-type semiconductor layer; forming a first protective layer on the p-type semiconductor layer; dividing the p-type semiconductor layer into a first region covered by the first protective layer and a second region not covered by the first protective layer by etching the first protective layer; and deactivating a portion of the dopant in the second region of the p-type semiconductor layer.

[0100] Deactivation can include deactivating the portion of the dopant in the second region by forming a deactivation layer comprising a nitride layer on the first protective layer and in the second region. The nitride can include SiN and SiN2. x O y At least one of the following. The first protective layer may include SiO2, HfO x The method may include removing a first protective layer and a deactivating layer; dividing the p-type semiconductor layers of the first region and the second region into a first p-type semiconductor layer and a second p-type semiconductor layer spaced apart from each other. During the removal of the first protective layer and the deactivating layer, the thicknesses of the p-type semiconductor layers of the first region and the second region may be different from each other.

[0101] The deactivation can include supplying hydrogen ions to the second p-type semiconductor layer of the second region. The method can include removing the first protective layer and the deactivation layer; and dividing the p-type semiconductor layers of the first region and the second region into the first p-type semiconductor layer and the second p-type semiconductor layer spaced apart from each other. Upon removing the first protective layer and the deactivation layer, the thicknesses of the p-type semiconductor layers of the first region and the second region can be made different from each other.

[0102] Figures 11A to 11F FIG. 1 is a diagram illustrating an embodiment of a method of manufacturing a semiconductor integrated circuit device. Figures 11A to 11F Embodiments of the method of manufacturing a semiconductor integrated circuit device disclosed in the specification relate to dividing a p-type semiconductor layer into a region protected by a protective layer and a region not protected, and then partially deactivating a dopant of the unprotected region. Figures 11A to 11F The growth substrate is omitted in

[0103] First, referring to Figure 11A A channel layer 20, a barrier layer 30 inducing a 2DEG in the channel layer 20, and a p-type semiconductor layer 40 are sequentially formed on a substrate (not shown). The channel layer 20, the barrier layer 30, and the p-type semiconductor layer 40 can have a single layer or a multi-layer structure including at least one material selected from nitrides including III-V group materials (e.g., at least one of Al, Ga, and In). For example, the channel layer 20, the barrier layer 30, and the p-type semiconductor layer 40 can include Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1, x+y≤1). For example, the channel layer 20, the barrier layer 30, and the p-type semiconductor layer 40 can include at least one of AlN, GaN, InN, InGaN, AlGaN, AlInN, and AlInGaN. The channel layer 20, the barrier layer 30, and the p-type semiconductor layer 40 can include the same material as each other, and can be distinguished from each other by their relative positions and / or different material compositions. For example, the channel layer 20 can include GaN, and can be an undoped layer or a layer doped with an impurity. The channel layer 20 can have a thickness of about several hundred nm or less. For example, the barrier layer 30 can include AlGaN. For example, the p-type semiconductor layer 40 includes GaN. The p-type semiconductor layer 40 can be doped with a p-type impurity such as Mg. The p-type semiconductor layer 40 is formed on the barrier layer 30 with a uniform thickness, and its dopant concentration is also uniform.

[0104] The substrate may include, but is not limited to, sapphire, Si, SiC, or GaN, and may include a variety of other materials. For example, although not shown in the figures, a seed layer and a buffer layer may be sequentially provided on the substrate, and a channel layer 20 may be formed on the buffer layer. The seed layer may be a base layer for the growth of the buffer layer. The buffer layer mitigates the difference in lattice constant and coefficient of thermal expansion between the substrate and the channel layer 20, thereby limiting and / or preventing a decrease in the crystallinity of the channel layer 20. The buffer layer may include at least one material selected from nitrides comprising group III-V materials (e.g., at least one of Al, Ga, and In).

[0105] Next, as Figure 11B As shown, a first protective layer 91-1 is formed on the p-type semiconductor layer 40. The first protective layer 91-1 may include oxides, such as SiO2 or HfO. x At least one of Al2O3. Next, the first protective layer 91-1 can be etched to remove a portion of the first protective layer 91-1 (the portion indicated by the dashed line). Thus, the p-type semiconductor layer 40 can be divided into a first region 40-1 covered by the first protective layer 91-1 and a second region 40-2 not covered by the first protective layer 91-1. The first protective layer 91-1 covers the first region 40-1 of the p-type semiconductor layer 40 to limit and / or prevent the deactivation of the first region 40-1 of the p-type semiconductor layer 40. The upper surface of the p-type semiconductor layer 40 is exposed in the second region 40-2.

[0106] Next, an operation is performed to partially deactivate the dopant in the second region 40-2 by deactivating the second region 40-2 of the p-type semiconductor layer 40. In one embodiment, deactivation can be performed by forming a deactivation layer comprising a nitride. (See also...) Figure 11C A first deactivation layer 92-1 comprising a nitride is formed on the first protective layer 91-1 and in the second region 40-2 of the p-type semiconductor layer 40. The first deactivation layer 92-1 provides deactivating ions to the second region 40-2 of the p-type semiconductor layer 40. The deactivating ions may include, for example, hydrogen ions. The first deactivation layer 92-1 may include a nitride, such as SiN or SiN2, that can provide hydrogen ions. x O yAt least one of the following. For example, by providing NH3 and SiH4 as process gases, a first deactivation layer 92-1 of SiN can be formed. Hydrogen ions are generated in this process and implanted into a second region 40-2 of the p-type semiconductor layer 40 whose upper surface is exposed. The hydrogen ions react with dopants, such as Mg, in the p-type semiconductor layer 40 of the second region 40-2 to form MgH2, thereby deactivating Mg. Therefore, the concentration of active dopants in the p-type semiconductor layer 40 of the second region 40-2 can be reduced. In the first region 40-1, the p-type semiconductor layer 40 is protected by, for example, a first protective layer 91-1 of SiO2, so hydrogen ions are not implanted into the p-type semiconductor layer 40. Therefore, the concentration of active dopants in the p-type semiconductor layer 40 does not change in the first region 40-1. According to this configuration, the concentration of active dopants in the p-type semiconductor layer 40 becomes different between the first region 40-1 and the second region 40-2.

[0107] Next, as Figure 11E As shown, the first protective layer 91-1 and the first deactivation layer 92-1 are removed. For example, a wet etching process can be used to remove the first protective layer 91-1 and the first deactivation layer 92-1. In this case, the thickness of the p-type semiconductor layer 40 can be generally uniform. A p-type semiconductor layer 40 with a first region 40-1 and a second region 40-2 having different active dopant concentrations is formed on the barrier layer 30. Next, as... Figure 11F As shown, the p-type semiconductor layers 40 of the second region 40-1 and the second region 40-2 are divided into first and second p-type semiconductor layers 41 and 42 spaced apart from each other. The partitioning process can be performed by an etching process using an etching mask. Therefore, the first and second p-type semiconductor layers 41 and 42 with different concentrations of active dopant can be formed.

[0108] According to one embodiment, the first deactivation layer 92-1 can be etched to divide the second region 40-2 of the p-type semiconductor layer 40 into a third region 40-3 covered by the first deactivation layer 92-1 and a fourth region 40-4 not covered by the first deactivation layer 92-1, such as... Figure 11D As shown. Next, the operation of partially deactivating a portion of the dopant in the fourth region 40-4 of the p-type semiconductor layer 40 by partially deactivating the fourth region 40-4 of the p-type semiconductor layer 40 can be further performed. A second deactivation layer 92-2 comprising a nitride can be formed on the first deactivation layer 92-1 and in the fourth region 40-4 of the p-type semiconductor layer 40. The second deactivation layer 92-2 provides deactivating ions to the fourth region 40-4 of the p-type semiconductor layer 40. The deactivating ions can include, for example, hydrogen ions. The second deactivation layer 92-2 can include nitrides that can provide hydrogen ions, such as SiN and SiN x O yAt least one of the following. For example, by providing NH3 and SiH4 as process gases, a second deactivation layer 92-2 of SiN can be formed. Hydrogen ions are generated in this process and implanted into a fourth region 40-4 of the p-type semiconductor layer 40, where the upper surface of the p-type semiconductor layer 40 is exposed. The hydrogen ions react with dopants, such as Mg, in the p-type semiconductor layer 40 of the fourth region 40-4 to form MgH2, thereby deactivating Mg. Therefore, the concentration of active dopants in the p-type semiconductor layer 40 can be reduced in the fourth region 40-4. In the first region 40-1 and the third region 40-3, the p-type semiconductor layer 40 is protected by a first SiO2 protective layer 91-1 and a first deactivation layer 92-1; therefore, hydrogen ions are not implanted into the p-type semiconductor layer 40. Therefore, the concentration of active dopants in the p-type semiconductor layer 40 of the first region 40-1 and the third region 40-3 can remain unchanged or its change can be very small. According to this configuration, the concentration of active dopant in the p-type semiconductor layer 40 varies between the first region 40-1, the third region 40-3, and the fourth region 40-4.

[0109] Next, as Figure 11E As shown, the first protective layer 91-1 and the first and second deactivation layers 92-1 and 92-2 are removed by, for example, a wet etching process. Then, a p-type semiconductor layer 40 with a uniform thickness and different active dopant concentrations in the first region 40-1, the third region 40-3, and the fourth region 40-4 is formed on the barrier layer 30. Next, the p-type semiconductor layer 40 in the first region 40-1, the third region 40-3, and the fourth region 40-4 is divided into first, second, and third p-type semiconductor layers 41, 42, and 43 spaced apart from each other, as shown. Figure 11F As shown in the diagram, the partitioning process can be performed using an etching process employing an etching mask. Therefore, first, second, and third p-type semiconductor layers 41, 42, and 43 with different concentrations of active dopant can be formed. By performing subsequent processes to form the gate, source, and drain, a semiconductor integrated circuit device comprising three HEMTs with different threshold voltages can be fabricated.

[0110] Next, by reference Figure 7E and Figure 7F The operation shown involves forming an insulating layer 93 on the first, second, and third p-type semiconductor layers 41, 42, and 43, and forming first and second gates 51 and 52, first and second sources 61 and 62, and first and second drains 71 and 72. This allows the fabrication of semiconductor integrated circuit devices including first and second HEMTs 11 and 12 with different threshold voltages. Furthermore, by referring to… Figure 8A and Figure 8B As shown in the diagram, the second gate 52 can be partially inserted into the second p-type semiconductor layer 42. Furthermore, as... Figure 11FAfter the p-type semiconductor layer 40 is divided into the first and second p-type semiconductor layers 41 and 42 spaced apart from each other, an operation of Figures 7B to 7D or Figure 9 may be performed to further reduce the active dopant concentration of the second p-type semiconductor layer 42.

[0111] Figure 12A and Figure 12B are cross-sectional views illustrating an embodiment of a method of manufacturing a semiconductor integrated circuit device. When the operation of dividing the p-type semiconductor layer 40 into the first, second, and third p-type semiconductor layers 41, 42, and 43 is performed, the thickness of the p-type semiconductor layer 40 in the first region 40-1 and the second region 40-2 can be made different from each other. In this case, Figure 11E and Figure 11F may be replaced with the operations illustrated in Figure 12A and Figure 12B . After the operation of Figure 11D is performed, the operation of removing the first protective layer 91-1 and the first and second inactivation layers 92-1 and 92-2 is performed, as illustrated in Figure 12A . The above operation can be performed by, for example, a dry etching operation. In this case, due to the difference in the thickness of the stacked layers (i.e., the first protective layer 91-1 and the first and second inactivation layers 92-1 and 92-2) covering the first, third, and fourth regions 40-1, 40-3, and 40-4, the etching depth of the p-type semiconductor layer 40 is the smallest in the first region 40-1 and becomes deeper in the order of the third region 40-3 and the fourth region 40-4. Thus, after the first protective layer 91-1 and the first and second inactivation layers 92-1 and 92-2 are removed, the thickness of the p-type semiconductor layer 40 decreases in the order of the first region 40-1, the third region 40-3, and the fourth region 40-4, as illustrated in Figure 12A . Next, the p-type semiconductor layer 40 of the first, second, and third regions 40-1, 40-2, and 40-3 is divided into the first, second, and third p-type semiconductor layers 41, 42, and 43 spaced apart from each other, as illustrated in Figure 12B . The division process can be performed by an etching process using an etching mask. Thus, the first, second, and third p-type semiconductor layers 41, 42, and 43 having different active dopant concentrations and thicknesses from each other can be formed.

[0112] After the operation of Figure 12B is performed, the operations of Figure 7E and Figure 7FThe operations shown in FIGS. 1, 2, and 3 can manufacture a semiconductor integrated circuit device including the first and second HEMTs 11 and 12 having threshold voltages different from each other. Also, by referring to Figure 8A and Figure 8B the operations shown in FIGS. 1, 2, and 3, the second gate 52 can be partially inserted into the second p-type semiconductor layer 42. In addition, as shown in Figure 12B after the p-type semiconductor layer 40 is divided into the first and second p-type semiconductor layers 41 and 42 spaced apart from each other, the operations of Figures 7B to 7D or the operations of Figure 9 may be performed to further reduce the active dopant concentration of the second p-type semiconductor layer 42.

[0113] Figure 13A and Figure 13B are cross-sectional views showing embodiments of a method of manufacturing a semiconductor integrated circuit device. In an embodiment, the deactivation operation can be performed by supplying hydrogen ions to the p-type semiconductor layer. In this case, instead of the operations of Figure 11C and Figure 11D the operations of Figure 13A and Figure 13B are performed. First, referring to Figure 13A the first region 40-1 of the p-type semiconductor layer 40 is covered by the first protective layer 91-1 to be protected, and the second region 40-2 of the p-type semiconductor layer 40 is exposed. In this state, hydrogen ions can be supplied to the second region 40-2 of the p-type semiconductor layer 40. For example, in a high voltage state, NH3 gas can be supplied into a reaction chamber. The NH3 gas can then be dissolved to generate hydrogen ions, and the hydrogen ions are injected into the exposed second region 40-2 of the second p-type semiconductor layer 42. The hydrogen ions react with the dopant, e.g., Mg, in the second region 40-2 of the second p-type semiconductor layer 42 to form MgH2, thereby deactivating the Mg. Thus, the active dopant concentration of the second region 40-2 of the second p-type semiconductor layer 42 can be reduced. As a process gas, hydrogen gas (H2) can be used instead of NH3 gas. Thus, the p-type semiconductor layer 40 having the first region 40-1 and the second region 40-2 having active dopant concentrations different from each other can be realized.

[0114] According to an embodiment, the second region 40-2 of the p-type semiconductor layer 40 can be divided into a third region 40-3 covered by the second protective layer 91-2 and a fourth region 40-4 not covered by the second protective layer 91-2, as shown in Figure 13BThe operation of partially deactivating a part of the dopant of the fourth region 40-4 by hydrogenating the fourth region 40-4 of the p-type semiconductor layer 40 can be further performed next. In the first region 40-1 and the third region 40-3, the p-type semiconductor layer 40 is protected by the first protective layer 91-1 and the second protective layer 91-2, and thus hydrogen ions are not injected into the p-type semiconductor layer 40. Accordingly, the active dopant concentration in the p-type semiconductor layer 40 in the first region 40-1 and the third region 40-3 is not changed. According to this configuration, the p-type semiconductor layer 40 including the first region 40-1, the third region 40-3, and the fourth region 40-4 having different active dopant concentrations from each other can be formed.

[0115] The semiconductor integrated circuit device according to the embodiments can be used for components that can require various types of threshold voltages of transistors, such as a radio frequency integrated circuit (RFIC) and an RF element using a radio frequency (e.g., in mobile communication, satellite communication, and the like), a power management integrated circuit (PMIC), and a power semiconductor device. As another example, the semiconductor integrated circuit device according to an embodiment can be used as a power semiconductor component of a fast charger for a mobile device, a switching converter used in a power supply for a server, an automobile charger, an automobile sensor such as a light detection and ranging (LiDAR), or a robot.

[0116] Figure 14 is a schematic view of an electronic device according to an embodiment.

[0117] Referring to Figure 14 The electronic device 1000 includes one or more electronic device components, including a processing circuit 1020 and a memory 1030 communicatively coupled together by a bus 1010.

[0118] The processing circuit 1020 can be included in, can include and / or can be implemented as one or more instances of a processing circuit, such as hardware including a logic circuit, a hardware / software combination such as a processor executing software, or a combination thereof. For example, the processing circuit 1020 can include, but is not limited to, a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, or an application specific integrated circuit (ASIC), and the like. In some example embodiments, the memory 1030 can include a non-transitory computer-readable storage device storing an instruction program, such as a solid state drive (SSD), and the processing circuit 1020 can be configured to execute the instruction program to implement the functions of the electronic device 1000.

[0119] In some example implementations, the electronic device 1000 can include one or more additional components 1040 coupled to the bus 1010, which can include, for example, a power source, a light sensor, a light emitting device, any combination thereof, and the like. In some example implementations, one or more of the processing circuitry 1020, the memory 1030, or the one or more additional components 1040 can include any power semiconductor device in accordance with any of the semiconductor integrated circuit devices described herein.

[0120] According to the above-described implementations, a semiconductor integrated circuit device having a plurality of devices with two or more threshold voltages can be implemented.

[0121] It should be understood that the implementations described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each implementation should typically be considered as being applicable to other similar features or aspects in other implementations. While one or more implementations have been described with reference to the figures, it will be apparent to those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims.

[0122] This application is based on and claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2021-0061645, filed on May 12, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

Claims

1. A semiconductor integrated circuit device comprising: a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a first p-type semiconductor layer and a second p-type semiconductor layer spaced apart from each other on the barrier layer; and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer, wherein the passivation layer partially deactivates at least one of a dopant of the first p-type semiconductor layer and a dopant of the second p-type semiconductor layer, wherein the passivation layer includes a first passivation layer on the first p-type semiconductor layer and a second passivation layer on the second p-type semiconductor layer and the first passivation layer, and at least one of the first passivation layer and the second passivation layer partially deactivates the dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

2. The semiconductor integrated circuit device of claim 1, wherein the passivation layer includes a first portion on the first p-type semiconductor layer and a second portion on the second p-type semiconductor layer, and a thickness or a material composition of the first portion is different from a thickness or a material composition of the second portion, or both the thickness and the material composition of the first portion are different from the thickness and the material composition of the second portion.

3. The semiconductor integrated circuit device of claim 1, wherein the first passivation layer and the second passivation layer partially deactivate the dopant of the first p-type semiconductor layer and the dopant of the second p-type semiconductor layer.

4. The semiconductor integrated circuit device of claim 1, wherein the second passivation layer partially deactivates the dopant of the second p-type semiconductor layer, and the first passivation layer prevents deactivation of the dopant of the first p-type semiconductor layer.

5. The semiconductor integrated circuit device of claim 1, wherein a thickness of the first p-type semiconductor layer is equal to a thickness of the second p-type semiconductor layer.

6. The semiconductor integrated circuit device of claim 1, wherein a thickness of the first p-type semiconductor layer is different from a thickness of the second p-type semiconductor layer.

7. The semiconductor integrated circuit device of claim 1, further comprising: a first gate contacting the first p-type semiconductor layer; and a second gate contacting the second p-type semiconductor layer, wherein the first gate is partially inserted in the first p-type semiconductor layer, or the second gate is partially inserted in the second p-type semiconductor layer, or the first gate is partially inserted in the first p-type semiconductor layer and the second gate is partially inserted in the second p-type semiconductor layer.

8. A semiconductor integrated circuit device comprising: a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; and a first p-type semiconductor layer and a second p-type semiconductor layer spaced apart from each other on the barrier layer, wherein ​ wherein a first HEMT is formed of the first p-type semiconductor layer, and portions of the channel layer and the barrier layer facing the first p-type semiconductor layer, and a second HEMT is formed of the second p-type semiconductor layer, and portions of the channel layer and the barrier layer facing the second p-type semiconductor layer, wherein the first p-type semiconductor layer and the second p-type semiconductor layer include the same active dopant, an active dopant concentration in the first p-type semiconductor layer is different from an active dopant concentration in the second p-type semiconductor layer, the first HEMT and the second HEMT have different threshold voltages.

9. The semiconductor integrated circuit device according to claim 8, wherein a thickness of the first p-type semiconductor layer is equal to a thickness of the second p-type semiconductor layer.

10. The semiconductor integrated circuit device according to claim 8, wherein a thickness of the first p-type semiconductor layer is different from a thickness of the second p-type semiconductor layer.

11. The semiconductor integrated circuit device according to claim 8, further comprising: a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer, wherein the passivation layer partially deactivates at least one of a dopant of the first p-type semiconductor layer and a dopant of the second p-type semiconductor layer.

12. The semiconductor integrated circuit device according to claim 8, further comprising: a first gate contacting the first p-type semiconductor layer; and a second gate contacting the second p-type semiconductor layer, wherein the first gate is partially inserted into the first p-type semiconductor layer, or the second gate is partially inserted into the second p-type semiconductor layer, or the first gate is partially inserted into the first p-type semiconductor layer and the second gate is partially inserted into the second p-type semiconductor layer.

13. A method of manufacturing a semiconductor integrated circuit device, the method comprising: sequentially forming a channel layer, a barrier layer configured to induce a two-dimensional electron gas (2DEG) in the channel layer, and a p-type semiconductor layer; and partially deactivating a dopant of a partial region of the p-type semiconductor layer, wherein the partially deactivating the dopant includes: dividing the p-type semiconductor layer into a first p-type semiconductor layer and a second p-type semiconductor layer separate from each other; forming a first passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer; exposing the second p-type semiconductor layer by etching the first passivation layer; and forming a second passivation layer on the first passivation layer and the second p-type semiconductor layer, wherein in a forming process, the first passivation layer provides a deactivating ion that deactivates a dopant of the first p-type semiconductor layer, or the second passivation layer provides a deactivating ion that deactivates a dopant of the second p-type semiconductor layer, or in the forming process, the first passivation layer provides a deactivating ion that deactivates the dopant of the first p-type semiconductor layer and the second passivation layer provides a deactivating ion that deactivates the dopant of the second p-type semiconductor layer.

14. The method according to claim 13, ​ wherein, In the forming process, the first passivation layer partially deactivates the dopant of the first p-type semiconductor layer, and the second passivation layer partially deactivates the dopant of the second p-type semiconductor layer.

15. The method of claim 13, further comprising: partially deactivating the dopant of the second p-type semiconductor layer before forming the second passivation layer.

16. The method of claim 13, further comprising: forming first and second gates in contact with the first and second p-type semiconductor layers, wherein the first gate partially penetrates the first p-type semiconductor layer, or the second gate partially penetrates the second p-type semiconductor layer, or the first gate partially penetrates the first p-type semiconductor layer, and the second gate partially penetrates the second p-type semiconductor layer.

17. A method of manufacturing a semiconductor integrated circuit device, the method comprising: sequentially forming a channel layer, a barrier layer configured to induce a two-dimensional electron gas (2DEG) in the channel layer, and a p-type semiconductor layer; and partially deactivating a dopant of a partial region of the p-type semiconductor layer, wherein the deactivation includes: forming a first protective layer on the p-type semiconductor layer; dividing the p-type semiconductor layer into a first region covered by the first protective layer and a second region not covered by the first protective layer by etching the first protective layer; and partially deactivating the dopant of the second region of the p-type semiconductor layer by forming a deactivation layer including a nitride on the first protective layer and in the second region.

18. A method of manufacturing a semiconductor integrated circuit device, the method comprising: sequentially forming a channel layer, a barrier layer configured to induce a two-dimensional electron gas (2DEG) in the channel layer, and a p-type semiconductor layer; and partially deactivating a dopant of a partial region of the p-type semiconductor layer, wherein the deactivation includes: forming a first protective layer on the p-type semiconductor layer; dividing the p-type semiconductor layer into a first region covered by the first protective layer and a second region not covered by the first protective layer by etching the first protective layer; and supplying a hydrogen ion to the p-type semiconductor layer in the second region.

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