Integrated jfet vdmos device and manufacturing method and application thereof
By integrating a JFET structure into a VDMOS device, the high cost of integrating a JFET into an LDMOS device is solved, enabling high-voltage startup and flexible power adjustment in power management products, and reducing manufacturing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN BASIC SEMICON LTD
- Filing Date
- 2022-07-11
- Publication Date
- 2026-07-10
AI Technical Summary
In existing technologies, the high-voltage BCD process that integrates JFETs using LDMOS devices is costly and difficult to achieve high-power integration, resulting in high costs for power management products.
By integrating a JFET structure into a VDMOS device, the channel of the JFET is formed by arranging the P-type and N+ regions on the substrate surface. Combined with standard low-voltage CMOS logic control, high-voltage startup is achieved, and VDMOS devices with different on-resistances can be selected according to power requirements.
It reduces manufacturing costs and allows for flexible adjustment based on power requirements, enabling efficient integration of power management products in high-voltage starting power electronic devices.
Smart Images
Figure CN115347035B_ABST
Abstract
Description
[Technical Field]
[0001] This application relates to the field of power electronic device technology, and in particular to a VDMOS device with integrated JFET, its fabrication method and application. [Background Technology]
[0002] In related technologies, high-voltage direct power supply is the ideal operating state for power management products. The common approach to achieving this ideal state is to integrate a JFET (Junction Field-Effect Transistor) into an LDMOS (laterally-diffused metal-oxide-semiconductor) device using a high-voltage BCD (Bipolar-CMOS-DMOS) process. This means integrating the JFET structure into the fabricated LDMOS device to achieve high-voltage startup. However, due to the high layer count and cost of the high-voltage BCD process, as well as the latch-up effect, it is difficult to achieve high-power integration, ultimately resulting in the high cost of power management products.
[0003] Therefore, it is necessary to improve the structure of the JFET integrated into the aforementioned LDMOS device. [Summary of the Invention]
[0004] This application provides a VDMOS device with integrated JFET, its fabrication method and application, aiming to solve the problem of excessively high fabrication cost when integrating JFET into LDMOS devices in related technologies.
[0005] To address the aforementioned technical problems, a first aspect of this application provides a VDMOS device with integrated JFET, comprising a substrate, the surface of which has a first side and a second side opposite to the first side, and a first direction pointing from the first side to the second side; the surface of the substrate is provided with a plurality of P-type regions spaced apart from each other, wherein two of the P-type regions are first P-type regions, and all the remaining P-type regions are second P-type regions;
[0006] The second P-type region encloses a first P+ region and two first N+ regions. The first P+ region and the two first N+ regions are connected to each other. The two first N+ regions are located on opposite sides of the first P+ region. The first P+ region and the two first N+ regions in each second P-type region are led out through a first metal to serve as the source of the VDMOS.
[0007] The first P-type region near the first side contains a second N+ region and a second P+ region arranged and connected along the first direction. The first P-type region near the second side contains a third P+ region and a third N+ region arranged and connected along the first direction. A fourth N+ region is also provided on the surface of the substrate between the two first P-type regions. The two opposite ends of the fourth N+ region are respectively wrapped in the two first P-type regions. The fourth N+ region is led out through a second metal to serve as the source of the JFET. The side of the substrate away from the P-type region serves as the drain of the VDMOS and the JFET. The two first P-type regions and the area between the two first P-type regions together constitute the channel of the JFET.
[0008] A second aspect of this application provides a method for fabricating a VDMOS device with integrated JFET, comprising:
[0009] Obtain a substrate; wherein the surface of the substrate has a first side and a second side opposite to the first side, and a first direction from the first side to the second side;
[0010] Multiple P-type regions are formed by implantation on the surface of the substrate; wherein the multiple P-type regions are spaced apart from each other, and two of the multiple P-type regions are first P-type regions, and all the remaining P-type regions are second P-type regions;
[0011] A first P+ region and two first N+ regions are implanted and formed in the second P-type region; wherein the two first N+ regions are located on opposite sides of the first P+ region, and the first P+ region and the two first N+ regions in each second P-type region are led out through a first metal to serve as the source of VDMOS.
[0012] A second N+ region and a second P+ region are injected and formed in the first P-type region near the first side, which are arranged in the first direction and interconnected with each other, and a third P+ region and a third N+ region are injected and formed in the first P-type region near the second side, which are arranged in the first direction and interconnected with each other.
[0013] A fourth N+ region is formed by implantation between the two first P-type regions; wherein the two opposite ends of the fourth N+ region are respectively wrapped within the two first P-type regions, the fourth N+ region is led out through a second metal to serve as the source of the JFET, the side of the substrate away from the P-type region serves as the drain of the VDMOS and the JFET, and the two first P-type regions and the region between the two first P-type regions together constitute the channel of the JFET.
[0014] The third aspect of this application provides an application of the VDMOS device with integrated JFET described in the first aspect of this application, or the VDMOS device with integrated JFET fabricated by the fabrication method described in the second aspect of this application, in power electronic devices.
[0015] As can be seen from the above description, compared with related technologies, the beneficial effects of this application are as follows:
[0016] Multiple P-type regions are spaced apart on the surface of a substrate, with two of them designated as first P-type regions (and the remaining P-type regions as second P-type regions). A fourth N+ region, with its two ends enclosed within the two first P-type regions, is positioned on the substrate surface between the two first P-type regions. Each second P-type region encloses an interconnected first P+ region and two first N+ regions. The first P+ region and the two first N+ regions within each second P-type region are led out through a first metal layer to serve as the source of a VDMOS. The fourth N+ region is led out through a second metal layer to serve as the source of a JFET. The side of the substrate away from the P-type regions serves as the drain of both the VDMOS and the JFET. The two first P-type regions and the area between them together form the channel of the JFET. It is understandable that conventional VDMOS devices are all three-terminal devices (three terminals refer to the source, drain, and gate), and they do not integrate JFETs. However, this application integrates JFETs into VDMOS devices (that is, when fabricating VDMOS devices, the fabricated VDMOS devices have the relevant structures of JFETs) to achieve high-voltage startup in power management products. Its logic control can use standard low-voltage CMOS. At the same time, we can also select VDMOS with different on-resistances according to different power requirements. This is a novel implementation method. Compared with the existing implementation method of integrating JFETs into LDMOS devices, it can not only reduce the manufacturing cost, but also flexibly package according to power requirements. [Attached Image Description]
[0017] To more clearly illustrate the related technologies or the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the related technologies or the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application, and not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the structure of a conventional VDMOS device;
[0019] Figure 2 A first structural schematic diagram of a VDMOS device with integrated JFET provided for an embodiment of this application;
[0020] Figure 3 A second structural schematic diagram of a VDMOS device with integrated JFET provided in an embodiment of this application;
[0021] Figure 4 A schematic diagram of the third structure of a VDMOS device with integrated JFET provided for an embodiment of this application;
[0022] Figure 5 A schematic flowchart illustrating the fabrication method of a VDMOS device with integrated JFET provided in an embodiment of this application;
[0023] Figure 6 A schematic diagram of a first structure of a VDMOS device with integrated JFET provided in the embodiment of this application during the fabrication process;
[0024] Figure 7 A second structural schematic diagram of a VDMOS device with integrated JFET provided in the embodiment of this application during the fabrication process;
[0025] Figure 8 This is a schematic diagram of a third structure of the VDMOS device with integrated JFET provided in the embodiments of this application during the fabrication process.
Detailed Implementation Methods
[0026] To make the objectives, technical solutions, and advantages of this application more apparent and understandable, the application will be clearly and completely described below in conjunction with the embodiments and corresponding drawings. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. It should be understood that the various embodiments of this application described below are merely illustrative and not intended to limit the application. That is, all other embodiments obtained by those skilled in the art based on the various embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0027] A FET (Field Effect Transistor) is a semiconductor device that controls the current in the output circuit by controlling the electric field effect of the input circuit. It typically includes two types: MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and JFET (Junction Field-Effect Transistor). MOSFETs also typically include two types: DMOS (Double-Diffused Metal-Oxide-Semiconductor) and CMOS (Complementary Metal-Oxide-Semiconductor). DMOS transistors can be further divided into LDMOS (Laterally-Diffused Metal-Oxide-Semiconductor) and VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor). Because FETs possess excellent characteristics such as high input resistance, low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, and wide safe operating area, they have become a strong competitor to bipolar transistors and power transistors, and are widely used in various power electronic devices that require FETs, such as power management products, mobile phones, laptops, and smart wearable devices.
[0028] In related technologies, high-voltage direct power supply is the ideal operating state for power management products. The common approach to achieve this ideal state is to integrate JFETs (JFET structures within the fabricated LDMOS device) using a high-voltage BCD (Bipolar-CMOS-DMOS) process to achieve high-voltage startup. However, due to the high layer count and cost of the high-voltage BCD process, as well as the latch-up effect, it is difficult to achieve high-power integration, ultimately resulting in high costs for power management products. Therefore, this application provides a VDMOS device with integrated JFETs. This VDMOS device can be applied to various power electronic devices requiring related functions, including but not limited to power management products, mobile phones, laptops, and smart wearable devices.
[0029] Before providing a detailed description of the VDMOS device with integrated JFET provided in the embodiments of this application, a brief description of conventional VDMOS devices will be given first.
[0030] Please see Figure 1 , Figure 1 This is a schematic diagram of a conventional VDMOS device. In the diagram, N-sub represents the N-type substrate, N-epi represents the N-type epitaxial layer, Pbody represents the P-type ion-doped body region, N+ represents the heavily N-type ion-doped region, P+ represents the heavily P-type ion-doped region, poly represents polysilicon, ILD represents the insulating layer, and source metal represents the source metal. In a conventional VDMOS device, the surface of N-epi has multiple spaced-apart Pbody layers. Each Pbody contains one P+ and two N+ ions. The P+ and two N+ ions within each Pbody are connected to the source metal through vias (i.e., the gaps between adjacent ILDs). In other words, the P+ and two N+ ions within each Pbody are led out through the source metal to serve as the source of the conventional VDMOS device. The potentials of the multiple Pbody layers are equal due to the shorting effect of the source metal, and the distance between any N+ ion and the Pbody containing it is the channel length of the conventional VDMOS device. Therefore, it is evident that a conventional VDMOS device does not integrate the structure of a JFET.
[0031] The VDMOS device with integrated JFET provided in this application will be described in detail below with reference to the structure of the conventional VDMOS device described above. In the following text, P-type, P+ and other terms refer to P-type ion doping, such as boron (B) and aluminum (Al); N-type, N+ and other terms refer to N-type ion doping, such as phosphorus (P) and arsenic (As).
[0032] Please see Figure 2 , Figure 2 This is a first structural schematic diagram of a VDMOS device with integrated JFET provided in an embodiment of this application. The VDMOS device with integrated JFET provided in this embodiment includes a substrate 10. The surface of the substrate 10 has a first side U and a second side V opposite to the first side U, and a first direction x from the first side U to the second side V. The surface of the substrate 10 is provided with a plurality of P-type regions 20 spaced apart from each other, two of which are first P-type regions 21, and all the remaining P-type regions 20 are second P-type regions 22.
[0033] Specifically, the second P-shaped region 22 encloses a first P+ region 221 and two first N+ regions 222. The first P+ region 221 and the two first N+ regions 222 are interconnected, and the two first N+ regions 222 are located on opposite sides of the first P+ region 221. The first P-shaped region 21 near the first side U encloses a second N+ region 211 and a second P+ region 212 arranged along the first direction x and interconnected. The first P-shaped region 21 near the second side V encloses a second N+ region 211 and a second P+ region 212 arranged along the first direction x and interconnected. The third P+ region 213 and the third N+ region 214; wherein, the first P+ region 221 and the two first N+ regions 222 in each second P-type region 22 are led out through the first metal 30 to serve as the source of VDMOS, and the second N+ region 211 and the second P+ region 212 in the first P-type region 21 near the first side U, and the third P+ region 213 and the third N+ region 214 in the first P-type region 21 near the second side V are also led out through the first metal 30 to serve as the source of VDMOS.
[0034] Furthermore, a fourth N+ region 40 is provided on the surface of the substrate 10 between the two first P-type regions 21. The opposite ends of the fourth N+ region 40 are respectively enclosed within the two first P-type regions 21. The fourth N+ region 40 is led out through the second metal 50 to serve as the source of the JFET. The two first P-type regions 21 and the region between them together constitute the channel of the JFET. In addition, the side of the substrate 10 facing away from the P-type region 20 serves as the common drain for both the VDMOS and the JFET.
[0035] In this embodiment, the substrate 10 can be configured similarly to a conventional VDMOS device, meaning the substrate 10 may include an N-type substrate 11 and an N-type epitaxial layer 12. The N-type epitaxial layer 12 covers the surface of the N-type substrate 11, and the side of the substrate 10 facing away from the P-type region 20 is the side of the N-type substrate 11 away from the N-type epitaxial layer 12. In other words, the side of the N-type substrate 11 away from the N-type epitaxial layer 12 serves as the common drain for both the VDMOS and JFET. In this document, the substrate 10 can be made of silicon (Si) or silicon carbide (SiC), meaning the N-type substrate 11 and the N-type epitaxial layer 12 can be made of either silicon or silicon carbide.
[0036] Furthermore, as described above, the two first P-type regions 21 are spaced apart, i.e., there is a first distance s between the two first P-type regions 21. This first distance s affects the pinch-off voltage of the JFET. In other words, the first distance s is positively correlated with the pinch-off voltage of the JFET (i.e., the shorter the first distance s, the smaller the pinch-off voltage and the easier it is to pinch off; the longer the first distance s, the larger the pinch-off voltage and the less likely it is to pinch off). Therefore, in this embodiment, the first distance s is taken as 1 to 10 μm. There is a second distance a between the fourth N+ region 40 and the second P+ region 212, and between the fourth N+ region 40 and the third P+ region 213. This second distance a must be at least greater than 1 μm to avoid the phenomenon that the fourth N+ region 40 breaks down prematurely with the second P+ region 212 and / or the third P+ region 213 when a high voltage is applied to it. There is a third distance b between the fourth N+ region 40 near the outer edge of the N-type substrate 11 and the first P-type region 21 near the outer edge of the N-type substrate 11. This third distance b affects the DIBL (Drain Induced Barrier Lowering) effect. In other words, the third distance b is negatively correlated with the DIBL effect (i.e., the shorter the third distance b, the more severe the DIBL effect, but the smaller the channel resistance of the JFET; the longer the third distance b, the milder the DIBL effect, but the larger the channel resistance of the JFET). Therefore, the third distance b in the embodiments of this application is 1 to 8 μm.
[0037] In this embodiment, a plurality of mutually spaced P-type regions 20 are formed on the surface of a substrate 10, with two of the P-type regions 20 designated as first P-type regions 21 and the remaining P-type regions 20 designated as second P-type regions 22. Simultaneously, a fourth N+ region 40 is formed on the surface of the substrate 10 between the two first P-type regions 21, with its two ends respectively enclosed within the two first P-type regions 21. Each second P-type region 22 encloses interconnected first P+ regions 221 and two first N+ regions 222. The first P-type regions 21 near the first side U enclose interconnected second N+ regions 211 and second P+ regions 212 arranged along the first direction x. The first P-type regions 21 near the second side V enclose interconnected second N+ regions 211 and second P+ regions 212 arranged along the first direction x. The third P+ region 213 and the third N+ region 214 are arranged in x direction and connected to each other. The first P+ region 221 and the two first N+ regions 222 in each second P-type region 22, the second N+ region 211 and the second P+ region 212 in the first P-type region 21 near the first side U, and the third P+ region 213 and the third N+ region 214 in the first P-type region 21 near the second side V are all led out through the first metal 30 to serve as the source of VDMOS. The fourth N+ region 40 is led out through the second metal 50 to serve as the source of JFET. The two first P-type regions 21 and the region between the two first P-type regions 21 together form the channel of JFET. The side of the substrate 10 away from the P-type region 20 serves as the common drain of VDMOS and JFET. It is understandable that conventional VDMOS devices are all three-terminal devices (the three terminals refer to the source, drain, and gate), and they do not integrate JFETs. However, the embodiments of this application utilize VDMOS devices to integrate JFETs (that is, when fabricating VDMOS devices, the fabricated VDMOS devices have the relevant structures of JFETs) to achieve high-voltage startup in power management products. Its logic control can use standard low-voltage CMOS. At the same time, we can also select VDMOS with different on-resistances according to different power requirements. This is a novel implementation method. Compared with the existing implementation method of integrating JFETs using LDMOS devices, it can not only reduce manufacturing costs, but also flexibly package according to power requirements.
[0038] As one implementation method, please refer to Figure 2 The substrate 10 also has a second direction y pointing from the N-type epitaxial layer 12 to the N-type substrate 11. Based on this, the two first P-type regions 21 and all the second P-type regions 22 can have the same depth along the second direction y; that is, the two first P-type regions 21 and all the second P-type regions 22 can be embedded into the substrate 10 at the same depth, or the two first P-type regions 21 and all the second P-type regions 22 can be embedded into the N-type epitaxial layer 12 at the same depth. In this embodiment, the two first P-type regions 21 and all the second P-type regions 22 serve as the body regions of the VDMOS.
[0039] As another implementation method, please refer to further information. Figure 3 , Figure 3 This is a schematic diagram of the second structure of a VDMOS device with integrated JFET provided in an embodiment of this application. Unlike the previous embodiment, in this embodiment, all the second P-type regions 22 can have the same depth along the second direction y, and the two first P-type regions 21 can have the same depth along the second direction y, and the depth of the first P-type region 21 along the second direction y is greater than the depth of the second P-type region 22 along the second direction y.
[0040] Understandably, the third distance b mentioned above is limited by the depth of the Pbody (equivalent to the first P-type region 21 in this article) along the second direction y in the standard VDMOS fabrication process. If we want to adjust the electrical parameters of the JFET during high-voltage startup, especially the value of the third distance b, then we need to use two separate first P-type regions 21 to wrap the opposite ends of the fourth N+ region 40 respectively. At this time, the depth of these two separate first P-type regions 21 along the second direction y can be optimized separately to obtain better electrical parameters of the JFET. The "separate" in "two separate first P-type regions 21" means that these two first P-type regions 21 are not formed in the same process step as all the second P-type regions 22. That is, these two first P-type regions 21 are formed separately. The most intuitive manifestation of this is that the depth of the first P-type region 21 along the second direction y is different from that of the second P-type region 22. That is, the depth of the first P-type region 21 along the second direction y is greater than that of the second P-type region 22 along the second direction y.
[0041] It should be noted that the above implementation is only a preferred implementation of the embodiments of this application, and it is not the only limitation on the depth of the first P-type region 21 and the second P-type region 22 along the second direction y; those skilled in the art can make flexible settings based on the embodiments of this application and according to the actual application scenario.
[0042] In some embodiments, please refer to further information. Figure 4 , Figure 4 This is a schematic diagram of the third structure of the VDMOS device with integrated JFET provided in this application embodiment. In addition to the structure shown above, the VDMOS device with integrated JFET provided in this embodiment may also include an N-type region 80, that is, an N-type region 80 may be provided on the surface of the substrate 10 between the two first P-type regions 21. The N-type region 80 is wrapped around the fourth N+ region 40, and the ion doping concentration of the N-type region 80 is lower than that of the fourth N+ region 40. The N-type region 80 being wrapped around the fourth N+ region 40 indicates that the fourth N+ region 40 is wrapped within the N-type region 80. At this time, the two opposite ends of the N-type region 80 are respectively wrapped within the two first P-type regions 21.
[0043] Understandably, the fourth N+ region 40 is led out through the second metal 50 to serve as the source of the JFET, and can subsequently be connected to the logic control IC (Integrated Circuit Chip) via wire bonding. However, when only the fourth N+ region 40 serves as the source of the JFET, the pinch-off voltage of the JFET is usually not higher than 10V (because an excessively high pinch-off voltage will result in an excessively high source voltage). However, the breakdown voltage between the fourth N+ region 40 and the first P-type region 21 is usually lower than 10V. Therefore, using only the fourth N+ region 40 as the source of the JFET does not support applications with high pinch-off voltages. If the external logic control IC requires a startup voltage higher than 10V, then the structure of this embodiment needs to be adopted, that is, a separate N-type region 80 is set to wrap the fourth N+ region 40, and the ion doping concentration of the N-type region 80 is lower than that of the fourth N+ region 40, so as to change the PN junction from a single-sided abrupt junction to a gradually changing junction, thereby improving the breakdown voltage of the JFET source to the first P-type region 21, and thus supporting a higher pinch-off voltage.
[0044] In some embodiments, still refer to Figure 4 In addition to the structure shown above, the VDMOS device with integrated JFET provided in this embodiment may also include a polysilicon layer 60, a first insulating layer 71, and a second insulating layer 72. Specifically, a polysilicon layer 60 may be disposed on the surface of the substrate 10 at positions between adjacent first P-type regions 21 and second P-type regions 22, and at positions between two adjacent second P-type regions 22. A first insulating layer 71 may be wrapped around the polysilicon layer 60. A second insulating layer 72 may be disposed on the surface of the substrate 10 at positions between the fourth N+ region 40 and the second P+ region 212, and at positions between the fourth N+ region 40 and the third P+ region 213. Based on this, a first metal 30 may be disposed on the surface of the substrate 10 at positions between adjacent first insulating layers 71 and second insulating layers 72, and at positions between two adjacent first insulating layers 71; a second metal 50 may be disposed on the surface of the substrate 10 at positions between two second insulating layers 72.
[0045] Please see Figure 5 , Figure 5 This is a flowchart illustrating a method for fabricating a VDMOS device with integrated JFET provided in an embodiment of this application. This application also provides a method for fabricating a VDMOS device with integrated JFET, which includes the following steps 501 to 505.
[0046] Step 501: Obtain the substrate.
[0047] In this embodiment of the application, when fabricating a VDMOS device with integrated JFET, a substrate 10 needs to be obtained first. The surface of the substrate 10 has a first side U and a second side V opposite to the first side U, and a first direction x from the first side U to the second side V. Specifically, the substrate 10 may include an N-type substrate 11 and an N-type epitaxial layer 12. The N-type epitaxial layer 12 covers the surface of the N-type substrate 11.
[0048] Step 502: Multiple P-type regions are implanted on the surface of the substrate.
[0049] In this embodiment of the application, after the substrate 10 is prepared, it is also necessary to implant and form a plurality of P-type regions 20 on the surface of the substrate 10; wherein, the plurality of P-type regions 20 are spaced apart from each other, and two of the plurality of P-type regions 20 are first P-type regions 21, and all the remaining P-type regions 20 are second P-type regions 22.
[0050] Step 503: Inject into the second P-type region to form an interconnected first P+ region and two first N+ regions.
[0051] In this embodiment of the application, after multiple P-type regions 20 are implanted on the surface of the substrate 10, a first P+ region 221 and two first N+ regions 222 that are interconnected are implanted in the second P-type region 22. The two first N+ regions 222 are located on opposite sides of the first P+ region 221, and the first P+ region 221 and the two first N+ regions 222 in each second P-type region 22 are led out through the first metal 30 to serve as the source of the VDMOS.
[0052] Step 504: Injecting and forming a second N+ region and a second P+ region arranged and connected in the first direction in the first P-type region near the first side, and injecting and forming a third P+ region and a third N+ region arranged and connected in the first direction in the first P-type region near the second side.
[0053] In this embodiment, after the first P+ region 221 and two first N+ regions 222 are formed in the second P-type region 22, the second N+ region 211 and the second P+ region 212, which are arranged along the first direction x and are connected to each other, are formed in the first P-type region 21 near the first side U, and the third P+ region 213 and the third N+ region 214, which are arranged along the first direction x and are connected to each other, are formed in the first P-type region 21 near the second side V. The second N+ region 211 and the second P+ region 212 in the first P-type region 21 near the first side U, and the third P+ region 213 and the third N+ region 214 in the first P-type region 21 near the second side V are also led out through the first metal 30 to serve as the source of VDMOS.
[0054] Step 505: Inject between the two first P-type regions to form a fourth N+ region.
[0055] In this embodiment, after forming the second N+ region 211, the second P+ region 212, the third P+ region 213, and the third N+ region 214, a fourth N+ region 40 needs to be formed between the two first P-type regions 21. The two opposite ends of the fourth N+ region 40 are respectively wrapped within the two first P-type regions 21. The fourth N+ region 40 is led out through the second metal 50 to serve as the source of the JFET. The two first P-type regions 21 and the region between the two first P-type regions 21 together constitute the channel of the JFET. The side of the substrate 10 away from the P-type region 20 serves as the common drain of the VDMOS and the JFET, that is, the side of the N-type substrate 11 away from the N-type epitaxial layer 12 serves as the common drain of the VDMOS and the JFET.
[0056] As can be seen from the above, the method for fabricating the VDMOS device with integrated JFET provided in this application embodiment fabricates the VDMOS device with integrated JFET provided in this application embodiment through steps 501 to 505, so that the VDMOS device with integrated JFET has a substrate 10, a P-type region 20 (including two first P-type regions 21 and multiple second P-type regions 22), a first P+ region 221, a first N+ region 222, a second N+ region 211, a second P+ region 212, a third P+ region 213, a third N+ region 214 and a fourth N+ region 40 and other structures. However, as mentioned earlier, the VDMOS device with integrated JFET also has other structures such as a polysilicon layer 60, a first insulating layer 71, a second insulating layer 72, a first metal 30, a second metal 50, and an N-type region 80. That is, the fabrication method of the VDMOS device with integrated JFET provided in this application embodiment can also include steps other than steps 501 to 505, such as fabricating the polysilicon layer 60, the first insulating layer 71, the second insulating layer 72, the first metal 30, the second metal 50, and the N-type region 80. Furthermore, step 503 forms the first P+ region 221 and the first N+ region 222, step 504 forms the second N+ region 211, the second P+ region 212, the third P+ region 213, and the third N+ region 214, and step 505 forms the fourth N+ region 40. In fact, these structures can all be formed in the same process step, and forming them in multiple process steps is not necessary.
[0057] To better understand the fabrication method of the VDMOS device with integrated JFET provided in the embodiments of this application, a specific example is given below to aid in understanding the fabrication method of the VDMOS device with integrated JFET:
[0058] (1) An N-type epitaxial layer 12 is grown on the surface of an N-type substrate 11; wherein, the thickness, resistivity, etc. of the N-type epitaxial layer 12 determine the breakdown voltage and on-resistance of the VDMOS and the integrated JFET.
[0059] (2) A voltage withstand ring region is fabricated on the surface of the N-type epitaxial layer 12. However, since VDMOS and integrated JFET have the same voltage withstand performance, the embodiments of this application do not provide a separate structure for the voltage withstand ring region. The structure of the voltage withstand ring region in conventional VDMOS devices can be directly adopted.
[0060] (3) Gate oxidation and polysilicon deposition are performed on the surface of the N-type epitaxial layer 12, as well as polysilicon photolithography and etching, thereby forming a structure on the surface of the N-type epitaxial layer 12 such as... Figure 6 ( Figure 6 The diagram shows a plurality of polysilicon layers 60 during the fabrication process of the VDMOS device with integrated JFET provided in the embodiments of this application.
[0061] (4) Photolithography, ion implantation, and push-well formation of the P-type region 20 are performed in the reserved area between multiple polysilicon layers 60, thereby forming a structure like the one described above on the surface of the N-type epitaxial layer 12. Figure 7 ( Figure 7 The diagram shows a second structural schematic of a VDMOS device with integrated JFET provided in the embodiment of this application during the fabrication process, which includes multiple P-type regions 20 (including two first P-type regions 21 and multiple second P-type regions 22); wherein, the first distance s between the two first P-type regions 21 is the main factor affecting the pinch-off voltage of the JFET, and in conventional VDMOS devices, after self-aligned ion implantation through polysilicon (similar to polysilicon layer 60), Pbody and corresponding channels are formed by transverse pushing, while the embodiment of this application adds photolithography of P-type regions 20 during the formation of multiple P-type regions 20;
[0062] (5) Perform photolithography and ion implantation of N+ and P+ to form, as shown in the second P-type region 22. Figure 8 ( Figure 8 As shown in the third structural schematic diagram of the VDMOS device with integrated JFET provided in the embodiments of this application, the first P+ region 221 and the first N+ region 222 are formed in the first P-type region 21 near the first side U of the N-type epitaxial layer 12, as shown in the first structural schematic diagram of the fabrication process of the VDMOS device with integrated JFET provided in the embodiments of this application. Figure 8 The second N+ region 211 and the second P+ region 212 shown are formed in the first P-type region 21 near the second side V of the N-type epitaxial layer 12, as shown in the figure. Figure 8 The third P+ region 213, the third N+ region 214 shown, and the formation between the two first P-type regions 21 as shown Figure 8 The fourth N+ region 40 is shown;
[0063] (6) Perform ILD deposition, contact hole photolithography and etching, metal deposition, metal photolithography and etching, etc., to form a layer on the surface of the N-type epitaxial layer 12 such as Figure 2 The structure shown includes a first insulating layer 71, a second insulating layer 72, a first metal 30, and a second metal 50. A contact hole refers to the gap between adjacent first insulating layers 71 and second insulating layers 72, between two adjacent first insulating layers 71, and between two adjacent second insulating layers 72. Metal deposition, photolithography, and etching are used to form the first metal 30 and the second metal 50, and ILD deposition is used to form the first insulating layer 71 and the second insulating layer 72.
[0064] It should be noted that the various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For product-related embodiments, since they are similar to method-related embodiments, the descriptions are relatively simple, and relevant parts can be referred to the descriptions of the method-related embodiments.
[0065] It should also be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0066] The above description of the disclosed embodiments enables those skilled in the art to implement or use the content of this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in this application may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A VDMOS device with integrated JFET, comprising a substrate, the surface of the substrate having a first side and a second side opposite to the first side, and a first direction pointing from the first side to the second side; characterized in that, The surface of the substrate is provided with a plurality of P-type regions spaced apart from each other, two of which are first P-type regions and all the remaining P-type regions are second P-type regions; The second P-type region encloses a first P+ region and two first N+ regions. The first P+ region and the two first N+ regions are connected to each other. The two first N+ regions are located on opposite sides of the first P+ region. The first P+ region and the two first N+ regions in each second P-type region are led out through a first metal to serve as the source of the VDMOS. The first P-type region near the first side encloses a second N+ region and a second P+ region arranged and connected along the first direction. The first P-type region near the second side encloses a third P+ region and a third N+ region arranged and connected along the first direction. A fourth N+ region is also provided on the surface of the substrate between the two first P-type regions. The two opposite ends of the fourth N+ region are respectively enclosed in the two first P-type regions. The fourth N+ region is led out through a second metal to serve as the source of the JFET. The side of the substrate away from the P-type region serves as the drain of the VDMOS and the JFET. The two first P-type regions and the area between the two first P-type regions together constitute the channel of the JFET. There is a first distance between the two first P-type regions, and the first distance is used to adjust the breakdown voltage performance of the JFET; There is a second distance between the fourth N+ region and the second P+ region, and between the fourth N+ region and the third P+ region. The second distance is used to avoid parasitic breakdown of the P+ region during high-voltage operation. The surface of the substrate is further provided with an N-type region located between the two first P-type regions. The N-type region surrounds the fourth N+ region, and the ion doping concentration of the N-type region is lower than that of the fourth N+ region. The substrate includes an N-type substrate and an N-type epitaxial layer covering the surface of the N-type substrate, and the fourth N+ region near the outer edge of the N-type substrate has a third distance from the first P-type region near the outer edge of the N-type substrate.
2. The VDMOS device with integrated JFET as described in claim 1, characterized in that, The first distance is 1~10μm.
3. The VDMOS device with integrated JFET as described in claim 1, characterized in that, The second distance is at least greater than 1 μm.
4. The VDMOS device with integrated JFET as described in claim 1, characterized in that, The side of the substrate away from the P-type region is the side of the N-type substrate away from the N-type epitaxial layer.
5. The VDMOS device with integrated JFET as described in claim 4, characterized in that, The third distance is 1~8μm.
6. The VDMOS device with integrated JFET as described in claim 4, characterized in that, The substrate has a second direction pointing from the N-type epitaxial layer to the N-type substrate; The two first P-type regions and all the second P-type regions have the same depth along the second direction; Alternatively, all the second P-type regions have the same depth along the second direction, the two first P-type regions have the same depth along the second direction, and the depth of the first P-type region along the second direction is greater than the depth of the second P-type region along the second direction.
7. The VDMOS device with integrated JFET as described in claim 1, characterized in that, The substrate surface is provided with polysilicon layers at positions between adjacent first P-type regions and second P-type regions, and at positions between two adjacent second P-type regions. A first insulating layer is wrapped on the polysilicon layers. The substrate surface is provided with second insulating layers at positions between the fourth N+ region and the second P+ region, and at positions between the fourth N+ region and the third P+ region. The substrate surface is provided with the first metal at positions between adjacent first insulating layers and second insulating layers, and at positions between two adjacent first insulating layers. The substrate surface is provided with the second metal at positions between two second insulating layers.
8. A method for fabricating a VDMOS device with integrated JFET as described in any one of claims 1 to 7, characterized in that, include: Obtain a substrate; wherein the surface of the substrate has a first side and a second side opposite to the first side, and a first direction from the first side to the second side; Multiple P-type regions are formed by implantation on the surface of the substrate; wherein the multiple P-type regions are spaced apart from each other, and two of the multiple P-type regions are first P-type regions, and all the remaining P-type regions are second P-type regions; A first P+ region and two first N+ regions are implanted and formed in the second P-type region; wherein the two first N+ regions are located on opposite sides of the first P+ region, and the first P+ region and the two first N+ regions in each second P-type region are led out through a first metal to serve as the source of VDMOS. A second N+ region and a second P+ region are injected and formed in the first P-type region near the first side, which are arranged in the first direction and interconnected with each other, and a third P+ region and a third N+ region are injected and formed in the first P-type region near the second side, which are arranged in the first direction and interconnected with each other. A fourth N+ region is formed by implantation between the two first P-type regions; wherein the two opposite ends of the fourth N+ region are respectively wrapped within the two first P-type regions, the fourth N+ region is led out through a second metal to serve as the source of the JFET, the side of the substrate away from the P-type region serves as the drain of the VDMOS and the JFET, and the two first P-type regions and the region between the two first P-type regions together constitute the channel of the JFET.
9. The application of a VDMOS device with integrated JFET as described in any one of claims 1-7, or a VDMOS device with integrated JFET fabricated by the fabrication method as described in claim 8, in power electronic devices.