Planar gate sic mosfet and method of manufacturing the same

Abstract

This invention belongs to the technical field, specifically relating to a planar gate SiC MOSFET and its fabrication method. The planar gate SiC MOSFET of this invention sets the height of the upper surface of the JFET region to be higher than the upper surface height of the P-well, P+, and N+ regions on both sides. This results in a higher gate oxide layer height in the region above the JFET region compared to the gate oxide layers on both sides. When a voltage is applied to the source and drain, the increased longitudinal distance within the JFET region reduces the gate oxide voltage reaching the gate oxide above the JFET region, thereby reducing the electric field strength on the gate oxide and improving its reliability. This, in turn, improves the performance and stability of the entire planar gate SiC MOSFET device, better meeting the high reliability requirements of high-voltage power devices in fields such as new energy vehicles, power grids, and intelligent transportation. Furthermore, the side region height of the gate oxide layer above the P-well region where the channel is located remains unchanged, maintaining a high channel mobility and effectively reducing on-resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a planar gate SiC MOSFET and its fabrication method. Background Technology

[0002] Compared to Si, SiC (Silicon Carbide) has a critical breakdown electric field 10 times higher. When designing MOSFET devices at the same voltage level, the thickness of the drift region can be significantly reduced, and the doping concentration can be increased. The drift region resistance can be reduced by 1000 times. Therefore, SiC has become a very attractive semiconductor material for developing high-voltage power MOSFET structures. High-voltage SiC MOSFETs are currently widely used in new energy vehicles, power grids, and intelligent transportation, requiring high reliability from these applications. This has been a key focus of the industry.

[0003] Currently, the mainstream commercial SiC MOSFET still uses a planar structure. During operation, the gate oxide is subjected to a high electric field. If the gate oxide thickness is critical, device reliability may be compromised, especially at higher voltages. To ensure high gate oxide reliability, a sufficiently thick gate oxide layer is required. However, if the gate oxide layer is too thick, it leads to a significant decrease in channel mobility, resulting in a significant increase in on-resistance. Therefore, improving gate oxide reliability is of great importance to the device. Summary of the Invention

[0004] The purpose of this invention is to provide a planar gate SiC MOSFET and its fabrication method.

[0005] This application provides a planar gate SiC MOSFET, comprising: The P well regions are spaced apart; a P+ region is provided in the middle of the upper part of the P well region, and N+ regions are provided on both sides of the P+ region. The JFET region is located between adjacent P well regions; The gate oxide layer located above the JFET region and the P well region, and the gate located above the gate oxide layer; wherein The height of the upper surface of the JFET region is higher than the height of the upper surfaces of the other regions located on both sides of the JFET region.

[0006] In one embodiment of this application, the height of the upper surface of the JFET region is 0.5 to 1.5 μm higher than the height of the upper surfaces of other regions located on both sides of the JFET region.

[0007] In one embodiment of this application, the upper surfaces of the P well region, P+ region, and N+ region are flush.

[0008] In one embodiment of this application, the gate oxide layer includes a central region located above the JFET region and side regions extending beyond both sides of the JFET region; The height of the upper surface of the middle region is higher than the height of the upper surface of the side region.

[0009] In one embodiment of this application, the side region covers a portion of the N+ region.

[0010] In one embodiment of this application, the planar gate SiC MOSFET further includes: The drain, substrate, and epitaxial layer are arranged sequentially from bottom to top; the JFET region and P well region are located above the epitaxial layer; and The source is connected to the P+ and N+ regions.

[0011] In one embodiment of this application, the distance from the lower surface of the intermediate region to the drain is greater than the distance from the lower surface of the side region to the drain.

[0012] Accordingly, this application provides a method for fabricating a planar gate SiC MOSFET as described above, comprising: An epitaxial layer is formed on the substrate layer; Formed on the epitaxial layer The barrier layer of the structure; Apply photoresist and remove the corresponding photoresist at the location of the barrier layer that needs to be etched; A barrier layer is etched at the location where ion implantation is required, and a first preset thickness is retained at the location where ion implantation is required. Ion implantation is performed to form P well regions; Remove the first preset thickness ; The SiC of the second predetermined thickness on the upper surface of the P well region is oxidized to... ; Remove all barrier layers and oxidized material. ; This forms P+ and N+ regions; Forming the gate oxide layer and the gate.

[0013] In one embodiment of this application, the second preset thickness ranges from 0.5 to 1.5 μm.

[0014] In one embodiment of this application, the preparation method further includes forming a source and a drain.

[0015] The beneficial effects of this invention are: Unlike existing technologies, this application provides a planar gate SiC MOSFET, comprising: spaced-apart P-well regions; a P+ region disposed in the middle of the upper part of the P-well regions, and N+ regions disposed on both sides of the P+ regions; a JFET region located between adjacent P-well regions; a gate oxide layer located above the JFET region and the P-well regions, and a gate located above the gate oxide layer; wherein the height of the upper surface of the JFET region is higher than the height of the upper surfaces of the other regions located on both sides of the JFET region. By setting the height of the upper surface of the JFET region to be higher than the height of the upper surfaces of the P-well regions, P+ regions, and N+ regions on both sides, the height of the gate oxide layer formed in the region above the JFET region will be higher than the gate oxide layers on both sides. Thus, when a voltage is applied to the source and drain, due to the increased longitudinal distance in the JFET region, the gate oxide voltage reaching the gate oxide above the JFET region is reduced, thereby reducing the electric field strength on the gate oxide, improving the reliability of the gate oxide, and thus improving the performance and stability of the entire planar gate SiC MOSFET device, better meeting the application requirements of high reliability of high-voltage power devices in fields such as new energy vehicles, power grids, and intelligent transportation. Furthermore, the side region height of the gate oxide layer remains unchanged above the P well region where the channel is located, which can maintain a high channel mobility and thus effectively reduce the on-resistance.

[0016] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a planar gate SiC MOSFET according to a preferred embodiment of the present invention; Figure 2 This is an enlarged schematic diagram of the JFET region according to a preferred embodiment of the present invention; Figure 3 This is a schematic diagram of the epitaxial layer formation according to a preferred embodiment of the present invention; Figure 4 This is a schematic diagram of the barrier layer formation according to a preferred embodiment of the present invention; Figure 5 This is a schematic diagram of a preferred embodiment of the present invention after the removal of the corresponding photoresist; Figure 6 This is a schematic diagram of the P well region after formation according to a preferred embodiment of the present invention; Figure 7 This is a preferred embodiment of the present invention for removing the first preset thickness. The following diagram; Figure 8 In a preferred embodiment of the present invention, SiC of a second predetermined thickness on the upper surface of P well region 1 is oxidized to... A schematic diagram; Figure 9 This is a preferred embodiment of the invention, which removes all barrier layers and oxidized layers. The following diagram; Figure 10 This is a schematic diagram of a preferred embodiment of the present invention after the formation of the P+ region, N+ region and the gate oxide layer.

[0020] In the picture: P well region 1, P+ region 2, N+ region 3, JFET region 4, gate oxide layer 5, middle region 51, side region 52, gate 6, drain 7, substrate layer 8, epitaxial layer 9, source 10. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This application provides a planar gate SiC MOSFET and its fabrication method, which are described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0023] See Figure 1 and Figure 2 In one embodiment, the planar gate SiC MOSFET includes: The drain electrode 7, the substrate layer 8, and the epitaxial layer 9 are arranged sequentially from bottom to top; P well regions 1 are spaced apart; P+ region 2 is disposed in the middle of the upper part of P well region 1, and N+ region 3 is disposed on both sides of P+ region 2; JFET region 4 is located between adjacent P well regions 1; JFET region 4 and P well region 1 are located above epitaxial layer 9. Gate oxide layer 5 located above JFET region 4 and P well region 1, and gate 6 located above gate oxide layer 5; Source 10 is connected to P+ region 2 and N+ region 3; where The height of the upper surface of the JFET region 4 is higher than the height of the upper surfaces of the other regions located on both sides of the JFET region 4.

[0024] In this embodiment, by setting the height of the upper surface of JFET region 4 to be higher than the height of the upper surfaces of P well regions 1, P+ regions 2, and N+ regions 3 on both sides, the height of the gate oxide layer 5 formed above JFET region 4 is higher than that of the gate oxide layers 5 on both sides. This structural design brings significant technical advantages: when a voltage is applied to the source and drain, because the longitudinal distance of the JFET region is greater than the distance from the two sides to the drain 7, the gate oxide voltage reaching the gate oxide above the JFET region is reduced, thereby reducing the electric field strength on the gate oxide. This key improvement directly improves the reliability of the gate oxide, thereby enhancing the performance and stability of the entire planar gate SiC MOSFET device, enabling it to better meet the application requirements of high reliability for high-voltage power devices in fields such as new energy vehicles, power grids, and intelligent transportation. At the same time, the height of the gate oxide layer 5 above P well region 1, where the channel is located, remains unchanged, which can maintain a high channel mobility, thereby effectively reducing the on-resistance and avoiding the problem of decreased device conduction performance caused by simply increasing the gate oxide thickness, achieving a good balance between gate oxide reliability and conduction performance.

[0025] Optionally, the height of the upper surface of the JFET region 4 is 0.5 to 1.5 μm higher than the height of the upper surfaces of other regions located on both sides of the JFET region 4.

[0026] Optionally, the regions on both sides of the JFET region 4 include P well region 1, P+ region 2, and N+ region 3, and their upper surfaces can be flush.

[0027] See Figure 2 Optionally, the gate oxide layer 5 includes a central region 51 located above the JFET region 4 and side regions 52 extending beyond both sides of the JFET region 4; the height of the upper surface of the central region 51 is higher than the height of the upper surface of the side regions 52.

[0028] Furthermore, the distance from the lower surface of the intermediate region 51 to the drain electrode 7 is greater than the distance from the lower surface of the side region 52 to the drain electrode 7.

[0029] Furthermore, the side region 52 covers a portion of the N+ region 3.

[0030] Accordingly, one embodiment of this application provides a method for fabricating a planar gate SiC MOSFET as described above, comprising: See Figure 3 An epitaxial layer 9 is formed on the substrate layer 8. This can be achieved using existing methods such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and physical vapor transport (PVT).

[0031] See Figure 4 Furthermore, a layer is formed on the epitaxial layer 9. The barrier layer of the structure. In one embodiment, specifically, a cleaned commercial 1200V SiC wafer can be used to deposit a barrier layer on the surface via CVD. The structures, with thicknesses of 500 Å, 4000 Å, and 15000 Å, serve as injection barrier layers.

[0032] See Figure 5 Furthermore, photoresist is applied and removed from the locations of the barrier layer that need to be etched. Specifically, on the wafer behind the barrier layer, a layer of photoresist, which can be 2µm thick, is spin-coated onto the wafer surface using a photolithography machine. This photoresist serves as an etching mask for the barrier layer, and the photoresist is removed from the locations of the barrier layer that need to be etched.

[0033] See Figure 6 Furthermore, a barrier layer is etched at the locations requiring ion implantation, and a first preset thickness is retained at these locations. Ion implantation is performed to form the P well region 1. Optionally, the first preset thickness can be 200 Å.

[0034] Specifically, the barrier layer can be etched using an ICP etching machine; to prevent damage to SiC, the implantation site should be re-etched after etching. There is a remaining 200 Å, after which Al ions are implanted to form P well region 1.

[0035] See Figure 7 Furthermore, remove the first preset thickness. Specifically, after the injection in P well region 1 is completed, a wet etching process can be used to remove the first preset thickness. HF corrosion can completely remove it in 30 seconds. Furthermore, since the barrier layer is relatively thick, the impact of the barrier layer thickness can be ignored.

[0036] See Figure 8 Furthermore, the SiC layer on the upper surface of P well region 1 with a second predetermined thickness is oxidized into... Specifically, to form a higher JFET region, etched SiC wafers are subjected to etching at 1000℃. In a suitable atmosphere, thermal oxidation is performed. Since all areas except Pwell region 1 are protected by a barrier layer, only the unprotected Pwell region 1 is oxidized during thermal oxidation. For example, to oxidize the 0.5µm thick SiC layer on the upper surface of Pwell region 1... This requires generating a 1.1µm thick layer. Based on the oxidation rate, oxidation needs to be carried out for 60 minutes.

[0037] See Figure 9 Furthermore, remove all barrier layers and oxidized materials. Alternatively, a wet etching process can be used to remove the barrier layer and the oxidized layer. .

[0038] Optionally, subsequent processes can be implemented using existing techniques, such as photolithography, etching, and implantation, to form the P+ region 2 and N+ region 3 functional regions N+ and PP. Then, existing techniques are used to form the gate oxide. See [link to documentation]. Figure 10 After the gate oxide is applied, the top position of the JFET is higher than the top position of the channel region formed by the pwell. Under the same drain-source voltage, the electric field strength of the gate oxide above the JFET region is smaller.

[0039] In summary, the planar gate SiC MOSFET proposed in this application cleverly achieves a higher gate oxide layer height above the JFET region (middle region) than on both sides (side regions) through an innovative JFET region height design. Specifically, the upper surface of the JFET region is higher than the upper surfaces of the P-well, P+, and N+ regions on either side. This structural optimization significantly reduces the electric field strength experienced by the gate oxide above the JFET region during device operation, effectively improving gate oxide reliability. This is crucial for the stable operation of high-voltage power devices in harsh environments such as new energy vehicles and power grids. Simultaneously, since the height of the side region of the gate oxide layer above the P-well region where the channel is located remains unaffected, a high channel mobility is ensured, helping to maintain a low on-resistance and achieving an optimized balance between device reliability and conduction performance. The corresponding fabrication method precisely controls the height difference between the JFET region and other regions through specific oxidation steps and photolithography etching processes. The process steps are reasonable and feasible, providing an effective approach for realizing this novel SiC MOSFET structure. These features and advantages of the present invention collectively enhance the overall performance of planar gate SiCMOSFET devices, making them better able to meet the urgent needs of the modern power electronics field for high-efficiency, high-reliability power devices.

[0040] It should be noted that all the devices (parts whose specific structures are not specified) selected in this application are general standard parts or parts known to those skilled in the art, and their structures and principles can be known to those skilled in the art through technical manuals or conventional experimental methods.

[0041] In the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0042] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0043] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A planar gate SiC MOSFET, characterized in that, include: A P well area (1) is arranged at intervals; a P+ area (2) is arranged in the middle of the upper part of the P well area (1), and N+ areas (3) are arranged on both sides of the P+ area (2); JFET region (4) is located between adjacent P well regions (1); A gate oxide layer (5) located above the JFET region (4) and the P well region (1), and a gate (6) located above the gate oxide layer (5); wherein The height of the upper surface of the JFET region (4) is higher than the height of the upper surfaces of the other regions located on both sides of the JFET region (4).

2. The planar gate SiC MOSFET according to claim 1, characterized in that, The height of the upper surface of the JFET region (4) is 0.5 to 1.5 μm higher than the height of the upper surfaces of other regions located on both sides of the JFET region (4).

3. The planar gate SiC MOSFET according to claim 1, characterized in that, The upper surfaces of the P well region (1), P+ region (2), and N+ region (3) are flush.

4. The planar gate SiC MOSFET according to claim 1, characterized in that, The gate oxide layer (5) includes a central region (51) located above the JFET region (4) and a side region (52) extending beyond both sides of the JFET region (4). The height of the upper surface of the middle region (51) is higher than the height of the upper surface of the side region (52).

5. The planar gate SiC MOSFET according to claim 4, characterized in that, The side region (52) covers part of the N+ region (3).

6. The planar gate SiC MOSFET according to claim 1, characterized in that, The planar gate SiC MOSFET also includes: The drain (7), substrate (8), and epitaxial layer (9) are arranged sequentially from bottom to top; the JFET region (4) and P well region (1) are located above the epitaxial layer (9); and The source (10) is connected to the P+ region (2) and the N+ region (3).

7. The planar gate SiC MOSFET according to claim 6, characterized in that, The distance from the lower surface of the intermediate region (51) to the drain (7) is greater than the distance from the lower surface of the side region (52) to the drain (7).

8. A method for fabricating a planar gate SiC MOSFET as described in any one of claims 1-7, characterized in that, include: An epitaxial layer (9) is formed on the substrate layer (8); Formed on the epitaxial layer (9) The barrier layer of the structure; Apply photoresist and remove the corresponding photoresist at the location of the barrier layer that needs to be etched; A barrier layer is etched at the location where ion implantation is required, and a first preset thickness is retained at the location where ion implantation is required. Ion implantation was performed to form a P well region (1); Remove the first preset thickness ; The SiC layer on the upper surface of the P well region (1) with a second predetermined thickness is oxidized into ; Remove all barrier layers and oxidized material. ; P+ region (2) and N+ region (3) are formed; A gate oxide layer (5) and a gate (6) are formed.

9. The preparation method according to claim 8, characterized in that, The second preset thickness ranges from 0.5 to 1.5 μm.

10. The preparation method according to claim 8, characterized in that, It also includes forming the source (10) and drain (7).

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