Semiconductor structure and method of fabricating the same

Abstract

A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor structure includes a substrate, two shallow trench isolation structures in the substrate, a first region, a second region and a third region defined between the two shallow trench isolation structures, the second region between the first region and the third region, two thick oxide layers in the first region and the third region, respectively, directly contacting the two shallow trench isolation structures, and a thin oxide layer in the second region, wherein the thickness of the thick oxide layer in the first region is greater than the thickness of the thin oxide layer in the second region.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of semiconductor, and more particularly, to a structure and a method of fabricating a double diffusion drain metal oxide semiconductor (DDDMOS) with oxide layers of different thicknesses. BACKGROUND

[0002] Double diffusion drain metal oxide semiconductor transistors (DDDMOS) are often used as a working structure and / or an electrostatic discharge (ESD) structure for high voltage circuits.

[0003] In high voltage integrated circuit fabrication, double diffusion drain metal oxide semiconductor transistor (DDDMOS) arrays are often used to provide large output current. Since DDDMOS is introduced to high voltage, a strong electric field is generated, especially near the gate edge where the electric field is the strongest, which can cause the electric field to penetrate through the gate and cause damage to the device.

[0004] Therefore, there is a need for an improved DDDMOS structure to reduce the probability of the above problems. SUMMARY

[0005] The present invention provides a semiconductor structure, comprising a substrate, two shallow trench isolation structures located in the substrate, wherein a first region, a second region and a third region are defined between the two shallow trench isolation structures, wherein the second region is located between the first region and the third region, two thick oxide layers located in the first region and the third region respectively and directly contacting the two shallow trench isolation structures, and a thin oxide layer located in the second region, wherein the thickness of the thick oxide layer in the first region is greater than the thickness of the thin oxide layer in the second region.

[0006] The present invention further provides a method of fabricating a semiconductor structure, comprising providing a substrate, forming two shallow trench isolation structures located in the substrate, wherein a first region, a second region and a third region are defined between the two shallow trench isolation structures, wherein the second region is located between the first region and the third region, forming an oxide layer located in the first region, the second region and the third region and directly contacting the two shallow trench isolation structures, removing the oxide layer in the second region, leaving the oxide layer in the first region and the third region, and forming another oxide layer in the first region, the second region and the third region, so as to form a thick oxide layer in the first region and the third region respectively and a thin oxide layer in the second region, wherein the thickness of the thick oxide layer in the first region is greater than the thickness of the thin oxide layer in the second region.

[0007] According to the embodiment of the present application, a portion of the buffer oxide layer is left near the shallow trench isolation on both sides of the DDDMOS structure. When another new oxide layer is subsequently reformed, a central thinner oxide layer and thicker oxide layers on both sides will be formed under the gate structure. The thicker oxide layers on both sides can more effectively protect the gate structure from being broken down by a large current, while the central portion still has a thinner oxide layer, which can also avoid the influence of the Kirk effect. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figures 1 to 5 A flow cross-sectional schematic diagram of a double-diffused drain metal oxide semiconductor field effect transistor (DDDMOS) according to a preferred embodiment of the present application.

[0009] Explanation of Main Element Symbols

[0010] 10: substrate

[0011] 12: shallow trench isolation structure

[0012] 14: buffer oxide layer

[0013] 15: doped region

[0014] 16: lightly doped region

[0015] 20: oxide layer (thin oxide layer)

[0016] P1: ion doping step

[0017] P2: patterning step

[0018] P3: heating step

[0019] 22: thick oxide layer

[0020] 24: gate structure

[0021] 26: spacer

[0022] 30: interlayer dielectric layer DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to further understand the present application, the preferred embodiment of the present application is described below, and the configuration content and the desired effects of the present application are explained in detail with reference to the accompanying drawings.

[0024] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0025] Figures 1 to 5 A schematic cross-sectional view illustrating the fabrication process of a dual-drain metal-oxide-semiconductor field-effect transistor (DDDMOS) according to a preferred embodiment of the present invention is shown. Figure 1 As shown, a substrate 10, such as a silicon substrate, is first provided. Then, at least two shallow trench isolation structures 12 are formed in the substrate 10. The shallow trench isolation structures 12 are made of, for example, silicon oxide. A portion of the shallow trench isolation structure 12 is located within the substrate 10 (i.e., extending into the substrate 10), while another portion protrudes from the surface of the substrate 10. In addition, a buffer oxide layer 14 is formed between the two shallow trench isolation structures 12. Preferably, the buffer oxide layer 14 and the shallow trench isolation structures can be formed simultaneously (e.g., the buffer oxide layer 14 can be a pad oxide layer formed before the shallow trench isolation structures 12), but the invention is not limited thereto. The function of the buffer oxide layer 14 is to protect the substrate 10 during subsequent ion doping steps.

[0026] Next, as Figure 2 As shown, an ion doping step P1 is performed to form at least one doped region 15 and a lightly doped region 16 in the substrate, wherein the doped region 15 and the lightly doped region 16 contain suitable ions, such as group III-V ions, etc. The doped region 15 is, for example, a well region, and the lightly doped region 16 can be used as a lightly doped drain (LDD) in a subsequent DDDMOS. Then, a patterning step P2 is performed, for example, using a mask (not shown) in combination with an exposure, development, and etching step to remove a portion of the buffer oxide layer 14. More specifically, the buffer oxide layer 14 can be defined on the substrate 10 as a first region R1, a second region R2, and a third region R3, wherein the second region R2 is located between the first region R1 and the third region R3. After the patterning step P2 is performed, the buffer oxide layer 14 in the second region R2 is removed, but the buffer oxide layer 14 in the first region R1 and the third region R3 is still retained.

[0027] In the above steps, the ion doping step P1 is performed first to form the lightly doped region 16 before the patterning step P2 is performed. However, in other embodiments of the present invention, the patterning step P2 may be performed first before the ion doping step P1, and this process is also within the scope of the present invention.

[0028] It is worth noting that in existing technologies, after the lightly doped region 16 is formed, the patterning step P2 is not performed to partially remove the buffer oxide layer 14 in the second region R2; instead, the entire buffer oxide layer 14 is completely removed, and a new oxide layer is subsequently regenerated. One feature of this invention is that after the patterning step P2, only a portion of the buffer oxide layer 14 (i.e., the buffer oxide layer 14 in the second region R2) is removed, while the buffer oxide layers 14 adjacent to the shallow trench isolation structure 12 (i.e., the buffer oxide layers 14 in the first region R1 and the third region R3) are retained. In this way, the remaining portion of the buffer oxide layer 14 will subsequently form a thick oxide layer below both sides of the gate structure, thus better protecting the gate structure.

[0029] like Figure 3 As shown, for example, a heating step P3 is used to regenerate the oxide layer 20 on the substrate 10. In this embodiment, the heating step is, for example, an in-situ vapor generation technique (ISSG), in which the temperature is raised to approximately 140 degrees Celsius in an environment containing oxygen (e.g., a mixture of hydrogen and oxygen, oxygen, ozone, water vapor, etc.), but is not limited to this. The oxide layer 20 is made of, for example, silicon oxide, and grows along the surface of the substrate 10 and the previously existing buffer oxide layer 14. Therefore, after the heating step P3 is performed, the thickness of the buffer oxide layer 14 in the original first region R1 and the third region R3 increases (because a new oxide layer 20 is generated on its surface), and the oxide layer 20 is also regenerated in the original second region R2.

[0030] In this embodiment, since both the buffer oxide layer 14 and the oxide layer 20 are made of silicon oxide, they are identical in material, and their interface is represented by dashed lines. However, it is understood that the buffer oxide layer 14 and the oxide layer 20 are formed in different steps. Furthermore, since the buffer oxide layer 14 is formed by deposition, its density may be lower than that of the oxide layer 20 formed by the ISSG method. However, during the heating step, the buffer oxide layer 14 may be reheated to increase its density. Additionally, after the oxide layer 20 is formed, the buffer oxide layer 14 and the oxide layer 20 in the first region R1 and the third region R3 can be combined and defined as a thick oxide layer 22, while the oxide layer 20 in the second region R2 is thinner than the thick oxide layer 22, and therefore can also be referred to as a thin oxide layer 20.

[0031] In addition to changing the temperature of the heating step, the thickness of the oxide layer 20 can also be adjusted by changing the oxygen content of the introduced gas in this embodiment. Preferably, the thickness of the thick oxide layer 22 is about 10% to 30% greater than the thickness of the thin oxide layer 20, but it is not limited thereto.

[0032] It is also noted that since the silicon in the substrate reacts with oxygen during the heating step to form silicon oxide (oxide layer 20), a portion of the oxide layer 20 will sink into the surface of the substrate 10. In particular, in the second region R2, the bottom surface of the oxide layer 20 will be lower than the top surface of the substrate 10 in the first region Rl or the third region R3. The formation of the recessed profile of the oxide layer 20 in the second region R2 in the present application helps to provide better field protection for the subsequently formed gate.

[0033] Next, as shown in FIG. 2, a gate structure 24 is formed on the oxide layer 20. The gate structure 24 is primarily located in the second region R2, but a portion of the gate structure 24 is also located in the first region Rl and the third region R3. The gate structure 24 spans a portion of the thick oxide layer 22 and is located on the thin oxide layer 20. The gate structure 24 is, for example, a polysilicon gate. In addition, spacers 26 can be formed on both sides of the gate structure 24. The spacers 26 can serve to protect the gate structure 24. Figure 4 Finally, as shown in FIG. 3, an interlayer dielectric layer 30 is formed over the gate structure 24 and the spacers 26. A planarization step (e.g., chemical mechanical polishing) is then performed to remove a portion of the gate structure 24, the spacers 26 and the interlayer dielectric layer 30. As a result, the gate structure 24, the spacers 26 and the interlayer dielectric layer 30 have a planar top surface after the planarization step is performed. These steps are known in the art and will not be described in further detail.

[0034] Figure 5 In summary, the present application provides a semiconductor structure comprising a substrate 100, two shallow trench isolation structures 12 located in the substrate 12, wherein a first region Rl, a second region R2 and a third region R3 are defined between the two shallow trench isolation structures 12, wherein the second region R2 is located between the first region Rl and the third region R3, two thick oxide layers 22 located in the first region Rl and the third region R3, respectively, and directly contacting the two shallow trench isolation structures 12, a thin oxide layer 20 located in the second region R2, wherein the thickness of the thick oxide layer 22 in the first region Rl is greater than the thickness of the thin oxide layer 20 in the second region R2.

[0035] In some embodiments, the thick oxide layer 22 and the thin oxide layer 20 are formed in different steps.

[0036] In some embodiments, the thick oxide layer 22 and the thin oxide layer 20 comprise the same material.

[0037] In some embodiments, the thickness of the thick oxide layer 22 in the first region Rl is greater than the thickness of the thin oxide layer 20 in the second region R2 by 10% to 30%.

[0038] In some embodiments, the thickness of the thick oxide layer 22 in the first region Rl is greater than the thickness of the thin oxide layer 20 in the second region R2 by 10% to 30%.​

[0039] In some embodiments, the thickness of the thick oxide layer 22 in the third region R3 is equal to the thickness of the thick oxide layer 22 in the first region Rl.

[0040] In some embodiments, a bottom surface of the thin oxide layer 20 in the second region R2 is lower than a bottom surface of the thick oxide layer 22 in the first region Rl.

[0041] In some embodiments, a gate structure 24 is further included on the thin oxide layer 20 and on the thick oxide layer 22, wherein the gate structure 24 is located in the second region R2 and in part of the first region Rl and the third region R3.

[0042] In some embodiments, a doped region (doped region 15 or lightly doped region 16) is further included in the substrate 10.

[0043] The present application further provides a method for fabricating a semiconductor structure, comprising: providing a substrate 10; forming two shallow trench isolation structures 12 in the substrate 10, wherein a first region Rl, a second region R2 and a third region R3 are defined between the two shallow trench isolation structures 12, wherein the second region R2 is located between the first region Rl and the third region R3; forming an oxide layer 14 in the first region Rl, the second region R2 and the third region R3, and the oxide layer 14 directly contacts the two shallow trench isolation structures 12; removing the oxide layer 14 in the second region R2, leaving the oxide layer 14 in the first region Rl and the third region R3; forming another oxide layer 20 in the first region Rl, the second region R2 and the third region R3, so as to form a thick oxide layer 22 in the first region Rl and the third region R3 respectively, and a thin oxide layer 20 in the second region R2, wherein the thickness of the thick oxide layer 22 in the first region Rl is greater than the thickness of the thin oxide layer 20 in the second region R2.

[0044] In some embodiments, the oxide layer 14 and the shallow trench isolation structures 12 are formed simultaneously.

[0045] In some embodiments, the another oxide layer 20 is formed by a high temperature oxidation step.

[0046] In some embodiments, an ion implantation step P1 is further included to form at least one doped region (doped region 15 or lightly doped region 16) in the substrate.

[0047] In some embodiments, the ion implantation step P1 is performed before the removal of the oxide layer 14 in the second region R2.

[0048] Compared with the prior art, the advantages of the present application are shown as follows: since the DDDMOS is connected to high voltage, a large current will also pass through the DDDMOS. The inventor finds that when a large current passes through the gate structure of the DDDMOS, the current is easy to pass through the oxide layer under the gate structure, thereby affecting the gate structure. According to the experimental observation results of the inventor, the electric field and the current are the largest at the two sides of the gate structure (near the spacer). However, if only the thickness of the entire gate dielectric layer (oxide layer) is thickened, the DDDMOS will be easy to be affected by the Kirk effect, that is, when a large current passes, the transistor is not easy to saturate and is resistive, thereby possibly causing leakage. This will also affect the performance of the DDDMOS.

[0049] Therefore, according to the embodiment of the present application, a part of the buffer oxide layer is left at the left and right sides of the DDDMOS structure near the shallow trench isolation, and when another new oxide layer is subsequently reformed, the oxide layer under the gate structure will be formed to be thinner in the center and thicker at the left and right sides. The oxide layer thicker at the left and right sides can more effectively protect the gate structure from being broken down by a large current, and the thinner oxide layer in the center can also avoid the influence of the above-mentioned Kirk effect.

[0050] The above only describes the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall be within the scope of the present application.

Claims

1. A semiconductor structure, characterized by, A semiconductor structure, comprising: a substrate; two shallow trench isolation structures in the substrate, wherein a first region, a second region and a third region are defined between the two shallow trench isolation structures, wherein the second region is between the first region and the third region; two thick oxide layers in the first region and the third region, respectively, and directly contacting the two shallow trench isolation structures; a thin oxide layer in the second region, wherein a thickness of the thick oxide layer in the first region is greater than a thickness of the thin oxide layer in the second region, and a bottom surface of the thin oxide layer is lower than a top surface of the substrate in the first region or the third region to form a concave profile structure, wherein the thickness of the thick oxide layer in the first region is greater than the thickness of the thin oxide layer in the second region by 10-30%; a gate structure on the thin oxide layer and on the thick oxide layer, wherein the gate structure is in the second region and in part of the first region and the third region.

2. The semiconductor structure of claim 1, wherein the thick oxide layer and the thin oxide layer are formed in different steps.

3. The semiconductor structure of claim 1, wherein the thick oxide layer and the thin oxide layer comprise a same material.

4. The semiconductor structure of claim 1, wherein a thickness of the thick oxide layer in the third region is equal to a thickness of the thick oxide layer in the first region.

5. The semiconductor structure of claim 1, wherein a bottommost surface of the thin oxide layer in the second region is lower than a bottommost surface of the thick oxide layer in the first region.

6. The semiconductor structure of claim 1, further comprising a doped region in the substrate.

7. A method for fabricating a semiconductor structure, comprising: providing a substrate; forming two shallow trench isolation structures in the substrate, wherein a first region, a second region and a third region are defined between the two shallow trench isolation structures, wherein the second region is between the first region and the third region; forming a first oxide layer in the first region, the second region and the third region, and the first oxide layer directly contacts the two shallow trench isolation structures; removing the first oxide layer in the second region, leaving the first oxide layer in the first region and the third region; forming a second oxide layer in the first region, the second region and the third region, such that the first oxide layer and the second oxide layer in each of the first region and the third region merge and define a thick oxide layer, and the second oxide layer in the second region defines a thin oxide layer, wherein a thickness of the thick oxide layer in the first region is greater than a thickness of the thin oxide layer in the second region, and a bottom surface of the thin oxide layer is lower than a top surface of the substrate in the first region or the third region to form a concave profile structure, wherein the thickness of the thick oxide layer in the first region is greater than the thickness of the thin oxide layer in the second region by 10-30%; a gate structure on the thin oxide layer and on the thick oxide layer, wherein the gate structure is in the second region and in part of the first region and the third region. ​ ​ ​ 8. The method of claim 7, wherein the first oxide layer is formed simultaneously with the shallow trench isolation structure.

9. The method of claim 7, wherein the thick oxide layer and the thin oxide layer comprise the same material.

10. The method of claim 7, wherein the thickness of the thick oxide layer in the third region is equal to the thickness of the thick oxide layer in the first region.

11. The method of claim 7, wherein the second oxide layer is formed by a high temperature oxidation step.

12. The method of claim 11, wherein the bottom surface of the thin oxide layer in the second region is lower than the bottom surface of the thick oxide layer in the first region.

13. The method of claim 7, further comprising performing an ion implantation step to form at least one doped region in the substrate.

14. The method of claim 13, wherein the ion implantation step is performed prior to removing the oxide layer in the second region.

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