Low leakage ESD protection

Abstract

The present disclosure relates to electrostatic discharge (ESD) protection circuitry for an electronic device that is capable of protecting thin oxide metal oxide semiconductor (MOS) transistors within the electronic device during ESD events and / or power-on transient phases without large current leakage. The disclosed ESD protection circuitry includes at least a protection switch and a switch controller. The protection switch is coupled between an external pin of the electronic device and internal circuitry of the electronic device, and the internal circuitry is composed of thin oxide MOS transistors. The switch controller is configured to control the protection switch to be conductive or non-conductive based on both a state of a first voltage source powering the ESD protection block and a presence of an ESD event at the external pin, the external pin is electrically connected to the internal circuitry or electrically disconnected from the internal circuitry, such that the external pin is electrically connected to or electrically disconnected from the internal circuitry.

Description

[0001] Related applications

[0002] This application claims the benefit of provisional patent application serial number 63 / 693,979 filed on September 12, 2024, and provisional patent application serial number 63 / 745,008 filed on January 14, 2025, the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an electrostatic discharge (ESD) protection circuit system for an electronic device, which is capable of protecting thin oxide metal oxide semiconductor (MOS) transistors within the electronic device during ESD events and / or power-on transient phases without significant current leakage. Background Technology

[0004] With the increasing prevalence of smart devices and portable electronic devices, there is a high demand for high-speed and compact transistors. Compared to conventional metal-oxide-semiconductor (MOS) transistors, thin oxide MOS transistors offer significantly increased switching speeds and higher current densities, and allow for denser integrated circuits, thus improving performance in high-speed applications. However, these advantages of the thin oxide layer are often accompanied by an increased risk of breakdown during electrostatic discharge (ESD) events involving temporary high voltages experienced by the device.

[0005] To prevent the thin-oxide-semiconductor (SMOS) transistors inside a device from breaking down during ESD events, clamping cells made of thin oxide are typically applied between the device's external pins and the internal circuitry consisting of SMOS transistors. These clamping cells limit the voltage to a safe level for all subsequent circuitry. A major challenge with existing SMOS clamping cells is their large leakage current. For applications requiring a large number of SMOS clamping cells, the total leakage current can become quite large, significantly impacting the device's electronic performance.

[0006] Therefore, there is still a need for improved ESD protection circuitry systems that can protect thin oxide MOS transistors within a device during an ESD event without causing excessive current leakage from the device. Summary of the Invention

[0007] This disclosure relates to an electrostatic discharge (ESD) protection circuit system for an electronic device, capable of protecting a thin oxide-metal-oxide-semiconductor (MOS) transistor within the electronic device without significant current leakage during an ESD event and / or a power-on transient phase. The disclosed ESD protection circuit system includes at least a protection switch and a switch controller. The protection switch is coupled between an external pin of the electronic device and the internal circuitry of the electronic device. The switch controller is configured to control the protection switch to be on or off based on both the state of a first voltage source supplying power to the ESD protection block and the presence of an ESD event at the external pin. Herein, the breakdown voltage of the internal circuitry is lower than the breakdown voltage of the protection switch and the switch controller. The switch controller is configured to control the protection switch to be off when the first voltage source is absent, when the first voltage source is in a power-on transient phase, or when an ESD event occurs at the external pin and / or in association with the first voltage source, thereby electrically disconnecting the external pin from the internal circuitry. Additionally, the switch controller is configured to turn on the protection switch when a first voltage source supplying power to the ESD protection block is stably present and no ESD event occurs at the external pin or is not associated with the first voltage source, so that the external pin is electrically connected to the internal circuitry.

[0008] In one embodiment of the ESD protection circuitry system, the internal circuitry includes multiple thin oxide metal-oxide-semiconductor (MOS) transistors. The protection switches and switch controllers are fabricated using thick oxide, rather than the thin oxide used in the thin oxide MOS transistors within the internal circuitry.

[0009] According to one embodiment, the ESD protection circuitry further includes an ESD clamping unit coupled between an external pin and ground, and coupled before the protection switch and the switch controller. Herein, the ESD clamping unit is configured to limit the voltage level at the external pin to below the breakdown voltage of the protection switch and the switch controller. The ESD clamping unit is fabricated using thick oxide, rather than the thin oxide used in the thin oxide MOS transistors within the internal circuitry.

[0010] In one embodiment of the ESD protection circuit system, the protection switch is implemented by a protection transistor that is an N-type MOS transistor. The drain of the protection transistor is coupled to the external pin, the source of the protection transistor is coupled to the internal circuit system, and the gate of the protection transistor is controlled by the switch controller.

[0011] In one embodiment of the ESD protection circuit system, the switching controller includes an inverter, a first capacitor, a control switch, and a second capacitor. The inverter is coupled between a first voltage source supplying power to the ESD protection block and ground, and the first capacitor is coupled between the first voltage source and the input terminal of the inverter. The control switch is coupled between the gate of the protection transistor and ground, the output terminal of the inverter is coupled to the gate of the protection transistor, and the second capacitor is coupled between an external pin and the control terminal of the control switch.

[0012] In one embodiment of the ESD protection circuit system, the inverter is implemented by a first transistor and a second transistor, wherein the first transistor is a P-type MOS transistor and the second transistor is an N-type MOS transistor. The source of the first transistor is coupled to a first voltage source, the gate of the first transistor is coupled to the gate of the second transistor, thereby forming the input terminal of the inverter, the drain of the first transistor is coupled to the drain of the second transistor, thereby forming the output terminal of the inverter, and the source of the second transistor is coupled to ground. The control switch is implemented by a control transistor, which is an N-type MOS transistor, wherein the drain of the control transistor is coupled to the gate of the protection transistor, the source of the control transistor is coupled to ground, and the gate of the control transistor is coupled to an external pin through a second capacitor. The control transistor is larger than the first transistor of the inverter. When the first voltage source is absent, the inverter is inactive, and the voltage level at the output terminal of the inverter is low. In this state, the protection transistor does not conduct regardless of whether an ESD event occurs at the external pin, thereby electrically disconnecting the internal circuit system from the external pin. During the short-circuit transient phase of the first voltage source or when an ESD event occurs in association with the first voltage source, the first capacitor pulls the voltage level at the inverter's input terminals high, resulting in a low voltage level at the inverter's output terminals. In this state, the protection transistor does not conduct regardless of whether the ESD event occurs at an external pin, thereby electrically disconnecting the internal circuitry from the external pin. When the first voltage source is stable and an ESD event occurs at an external pin, the second capacitor pulls the voltage level at the gate of the control transistor high, causing the control transistor to conduct to ground. In this state, the conducting control transistor, larger than the first transistor of the inverter, pulls the inverter's output terminals and the gate of the protection transistor to a low voltage level. When the first voltage source is stable and no ESD event occurs at an external pin or is not associated with the first voltage source, the control transistor does not conduct, and the voltage level at the inverter's output terminals is high, causing the protection transistor to conduct, and the external pin is electrically connected to the internal circuitry.

[0013] In one embodiment of the ESD protection circuit system, the first transistor, the second transistor, the control transistor, and the protection transistor are fabricated using thick oxide, rather than the thin oxide used in thin oxide MOS transistors within the internal circuitry. The first voltage source supplying power to the ESD protection block is greater than the voltage input applied to the internal circuitry.

[0014] In one embodiment of the ESD protection circuit system, the switch controller further includes a first resistor and a second resistor. Herein, the first resistor is coupled between the input terminal of the inverter and ground, and the second resistor is coupled between the gate of the control transistor and ground.

[0015] According to one embodiment, an electronic device includes at least an external pin, an internal circuitry, and an ESD protection block coupled between the external pin and the internal circuitry. Herein, the internal circuitry includes a plurality of thin-film MOS transistors, and the ESD protection block is fabricated with thick oxide instead of the thin oxide used in the thin-film MOS transistors within the internal circuitry, such that the breakdown voltage of the internal circuitry is lower than the breakdown voltage of the ESD protection block. The ESD protection block is configured to connect the external pin to the internal circuitry or disconnect the external pin from the internal circuitry based on both the state of a first voltage source supplying power to the ESD protection block and the presence of an ESD event at the external pin. When the first voltage source is absent, when the first voltage source is in a power-on transient phase, or when an ESD event occurs at the external pin and / or is associated with the first voltage source, the external pin is electrically disconnected from the internal circuitry. Additionally, when the first voltage source supplying power to the ESD protection block is stably present and no ESD event occurs at the external pin or is not associated with the first voltage source, the external pin is electrically connected to the internal circuitry.

[0016] In one embodiment of the electronic device, the ESD protection block includes at least a protection switch coupled between an external pin and an internal circuitry, and a switch controller configured to control the protection switch to be on or off based on both the state of a first voltage source supplying power to the ESD protection block and the presence of an ESD event at the external pin. The switch controller is configured to control the protection switch to be off when the first voltage source is absent, when the first voltage source is in a power-on transient phase, or when an ESD event occurs at the external pin and / or is associated with the first voltage source, thereby electrically disconnecting the external pin from the internal circuitry. Alternatively, the switch controller is configured to control the protection switch to be on when the first voltage source supplying power to the ESD protection block is stably present and no ESD event occurs at the external pin or is not associated with the first voltage source, thereby electrically connecting the external pin to the internal circuitry.

[0017] In one embodiment of the electronic device, the ESD protection block further includes an ESD clamping unit coupled between an external pin and ground and before the protection switch and the switch controller. Herein, the ESD clamping unit is configured to limit the voltage level at the external pin to below the breakdown voltage of the protection switch and the switch controller.

[0018] In one embodiment of the electronic device, an external pin is configured to provide a second voltage source to power the internal circuitry, and the second voltage source is lower than a first voltage source that powers the ESD protection block.

[0019] In one embodiment of the electronic device, an external pin is configured to provide a logic input signal to an internal circuit system, and the logic input signal of the internal circuit system is lower than a first voltage source that powers the ESD protection block.

[0020] According to one embodiment, the electronic device further includes a low-dropout regulator (LDO) coupled between a first voltage source and an internal circuitry. Herein, the internal circuitry is powered by a regulated version of the first voltage source provided via the LDO.

[0021] According to one embodiment, the electronic device further includes a clamping unit coupled between the first voltage source and ground and coupled before the LDO. Herein, the clamping unit is configured to clamp the voltage level applied to the LDO to a value below the breakdown voltage of the LDO during the energizing transient phase of the first voltage source.

[0022] In one embodiment of the electronic device, the LDO and clamping unit are fabricated with thick oxide instead of the thin oxide used in the thin oxide MOS transistors within the internal circuitry, such that the breakdown voltage of the internal circuitry is lower than the breakdown voltage of the LDO and clamping unit.

[0023] According to one embodiment, a method for operating an ESD protection block of an electronic device is described, the method being designed to protect thin oxide MOS transistors within the internal circuitry of the electronic device. The ESD protection block includes a switch controller and a protection switch coupled between an external pin of the electronic device and the internal circuitry. The method of operating the ESD protection block includes: disconnecting the external pin from the internal circuitry by opening the protection switch when a first voltage source supplying power to the ESD protection block is absent; disconnecting the external pin from the internal circuitry by opening the protection switch during a power-on transient phase of the first voltage source supplying power to the ESD protection block; and disconnecting the external pin from the internal circuitry by opening the protection switch when an ESD event occurs at the external pin and / or is associated with the first voltage source. Furthermore, the method of operating the ESD protection block further includes: connecting the external pin to the internal circuitry by closing the protection switch when the first voltage source supplying power to the ESD protection block is stably present and no ESD event occurs at the external pin or is not associated with the first voltage source. In this document, the opening or closing of the protection switch is controlled by the switch controller based on both the state of the first voltage source and the presence of an ESD event at the external pin. The breakdown voltage of the thin oxide MOS transistor within the internal circuit system is lower than the breakdown voltage of the protection switch and the switch controller.

[0024] In another respect, any of the foregoing aspects and / or the various separate aspects and features as described herein may be combined individually or together to obtain additional advantages. Unless otherwise indicated herein, any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements.

[0025] Those skilled in the art will understand the scope of this disclosure and implement its additional aspects after reading the following preferred embodiments associated with the accompanying drawings. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0027] Figure 1 An exemplary schematic diagram of a portion of an electronic device including an electrostatic discharge (ESD) protection block according to some embodiments of the present disclosure is shown.

[0028] Figure 2 An exemplary schematic diagram of an alternative portion of an electronic device including an ESD protection block according to some embodiments of the present disclosure is shown.

[0029] Figure 3An exemplary implementation of a switch controller within an ESD protection block according to some embodiments of this disclosure is shown.

[0030] Figure 4 A flowchart illustrating the operation of an ESD protection block for protecting a thin oxide metal oxide semiconductor (MOS) transistor in an electronic device, according to some embodiments of the present disclosure, is shown.

[0031] It should be understood that, for the sake of clarity, Figures 1 to 4 It is not necessary to draw it to scale. Detailed Implementation

[0032] The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0033] It will be understood that while terms such as first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish different elements. For example, a first element may be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly located on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on another element" or "directly extended to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "on top of another element" or "extending over another element," it may be directly located on top of or directly extended over the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on top of another element" or "extending directly over another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected to or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0035] For example, relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those depicted in the figures.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” are also intended to include the plural forms. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0037] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as in the context of this specification and related art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0038] The embodiments of this disclosure are illustrated herein with reference to schematic diagrams. Therefore, the actual dimensions of layers and elements may differ, and variations from the shapes shown are expected due to (for example) manufacturing techniques and / or tolerances. For instance, areas shown or described as squares or rectangles may have rounded or curved features, and areas shown as straight lines may have some irregularities. Therefore, the areas shown in the figures are schematic, and their shapes are not intended to be the precise shapes of areas of the apparatus, nor are they intended to limit the scope of this disclosure. Additionally, the size of structures or areas may be particularly exaggerated relative to other structures or areas for illustrative purposes, and is therefore provided to illustrate the general structure of the subject matter of this disclosure, and may or may not be drawn to scale. Common elements in the figures may be presented herein using common element reference numerals and will not be described further thereafter.

[0039] This disclosure relates to electrostatic discharge (ESD) protection circuitry systems for electronic devices, designed to protect thin oxide metal-oxide-semiconductor (MOS) transistors within the electronic device during ESD events involving temporary high voltages experienced by the electronic device and / or power-on transient phases of the electronic device. The disclosed ESD protection circuitry system combines the ability to conduct abnormally high currents (e.g., ESD currents or power-on transient currents) while maintaining low leakage currents in the electronic device.

[0040] Figure 1 A simplified schematic diagram of a portion of an electronic device 10 is shown, which includes an ESD protection block 100 electrically coupled between an external pin 102 of the electronic device 10 and an internal circuit system 104. In practical applications, the electronic device 10 may include multiple external pins (similar to external pin 102) and multiple ESD protection blocks (similar to ESD protection block 100), each ESD protection block being coupled between a corresponding external pin and the internal circuit system 104 (not shown). These ESD protection blocks constitute the ESD protection circuit system of the electronic device 10.

[0041] The internal circuitry 104 may consist of thin-film MOS transistors (not shown), which offer excellent fast switching speeds and high current densities, but are accompanied by relatively low breakdown voltages. Typically, the temporary high voltage experienced by the electronic device 10 during an ESD event occurs at an external pin (e.g., external pin 102) of the electronic device 10. If external pin 102 is directly connected to the internal circuitry 104 (without the ESD protection block 100), the internal circuitry 104 will also experience a temporary high voltage during an ESD event, potentially leading to breakdown damage to the thin-film MOS transistors within the internal circuitry 104. The proposed ESD protection block 100 is configured to limit the voltage applied to the internal circuitry 104 to a safe voltage level (e.g., 0.8V) for each thin-film MOS transistor within the internal circuitry 104, while ensuring relatively low leakage current.

[0042] In some applications, external pin 102 can be configured to input voltage V. EX Provided to the internal circuit system 104. Voltage input V EX It can serve as a second voltage source for powering the internal circuitry 104 of the electronic device 10, or as a logic input signal for the internal circuitry 104. The ESD protection block 100 is configured to ensure that only voltage input V can be used. EX Protected / Secure Version V P An application is made to the internal circuit system 104 to prevent electronic damage to the thin oxide MOS transistors within the internal circuit system 104.

[0043] In detail, the ESD protection block 100 includes an ESD clamping unit 106 coupled between the external pin 102 and ground, a protection switch 108 coupled between the external pin 102 and the internal circuitry 104, and a switch controller 110 configured to operate based at least on a voltage input V provided at the external pin 102. EX The protection switch 108 is controlled to be on or off. The ESD protection block 100 is powered by a first voltage source V1, which may be an internal power supply integrated into the electronic device 10 or an external power supply provided from outside the electronic device 10.

[0044] It should be noted that if the voltage input V is provided at external pin 102 EX The second voltage source used to power the internal circuit system 104 provides the voltage input V to the ESD protection block 100. EX This is a different power source from the first voltage source V1. The voltage input V... EX The first voltage source V1 is provided by two different power rails (not shown) within the electronic device 10, one power rail for high-speed thin oxide MOS transistors (e.g., within internal circuit system 104) and the other power rail for low standby power and interfacing circuit systems (e.g., ESD protection block 100 with thick oxide elements).

[0045] The first voltage source V1 can be a battery power source. If the ESD protection block 100 exhibits a relatively large leakage current, the battery may be depleted undesirably and rapidly. To achieve low leakage current, the ESD clamping unit 106, the protection switch 108, and the switch controller 110 are manufactured using thick oxide, rather than the thin oxide used in the thin oxide MOS transistors within the internal circuitry 104. However, due to the thick oxide, the ESD clamping unit 106 cannot ensure that its clamping voltage is as low as the breakdown voltage of the thin oxide MOS transistors within the internal circuitry 104. Therefore, without being combined with the protection switch 108 and the switch controller 110, the ESD clamping unit 106 alone cannot effectively protect the thin oxide MOS transistors within the internal circuitry 104. The clamping voltage of the ESD clamping unit 106 is too high to be safely applied to the thin oxide MOS transistors within the internal circuitry 104. In this document, the ESD clamping unit 106 is actually configured to protect the protection switch 108 and the switch controller 110 during an ESD event, rather than protecting the thin oxide MOS transistors within the internal circuitry 104. The clamping voltage of the ESD clamping unit 106 is sufficiently low (e.g., below the breakdown voltage of the protection switch 108 and the switch controller 110) to be safely applied to the thick oxide protection switch 108 and the thick oxide switch controller 110. During an ESD event, the protection switch 108 and the switch controller 110 are configured to protect the internal circuitry 104 by disconnecting it from the external pin 102, thereby preventing the thin oxide MOS transistors within the internal circuitry 104 from experiencing abnormally high voltages (further details are described in subsequent paragraphs). Additionally, due to the thick oxide layer, the first voltage source V1 supplying power to the ESD protection block 100 is higher than the voltage input V applied to the thin oxide MOS transistors in the internal circuitry 104. EX Protected / Secure Version V P (For example, the first voltage source V1 is about 3V, while the protected / safe voltage V...) P (approximately 0.8V).

[0046] When the first voltage source V1 is absent, the protection switch 108 of the ESD protection block 100 (controlled by the switch controller 110) is de-energized (i.e., the protection switch 108 is open). Therefore, regardless of the voltage level at the external pin 102, the external pin 102 is always electrically disconnected from the internal circuitry 104 and no voltage input is supplied to the internal circuitry 104. During the energizing transient phase of the first voltage source V1, the protection switch 108 of the ESD protection block 100 (controlled by the switch controller 110) is de-energized. Therefore, regardless of the voltage level at the external pin 102, the external pin 102 remains disconnected from the internal circuitry 104 and no voltage input is supplied to the internal circuitry 104. When an ESD event occurs in association with the first voltage source V1, the protection switch 108 of the ESD protection block 100 (controlled by the switch controller 110) is de-energized (i.e., the protection switch 108 is open). Therefore, regardless of the voltage level at external pin 102, external pin 102 is always electrically disconnected from internal circuitry 104 and will not provide voltage input to internal circuitry 104.

[0047] When the first voltage source V1 is stably present and not associated with any ESD event, the protection switch 108 of the ESD protection block 100 is controlled to be on or off based on the transient voltage level presented at external pin 102 (by the switch controller 110). When the first voltage source V1 is stably present and the transient voltage level presented at external pin 102 exceeds the breakdown voltage of the thin oxide MOS transistor (i.e., an ESD event occurs at external pin 102), the switch controller 110 is configured to de-conduct the protection switch 108. Therefore, abnormally high transient voltage levels presented at external pin 102 will not reach the internal circuitry 104. Additionally, in some scenarios where the transient voltage level presented at external pin 102 exceeds the breakdown voltage of the protection switch 108 or the switch controller 110, the ESD clamping unit 106 is configured to clamp the abnormally high transient voltage level presented at external pin 102 to a safe level for both the protection switch 108 and the switch controller 110. Therefore, an ESD event occurring at external pin 102 will not damage the protection switch 108 or the switch controller 110. Furthermore, when the first voltage source V1 is stably present and the voltage input V provided at external pin 102... EX When the voltage is stable and does not exceed the breakdown voltage of the thin oxide MOS transistor (i.e., no ESD event occurs at external power pin 102), the switch controller 110 is configured to turn on the protection switch 108 (i.e., the protection switch 108 is closed). Therefore, external pin 102 is electrically connected to the internal circuitry 104, and the voltage input V provided by external pin 102 and monitored by the switch controller 110 is... EX(For example, about 0.8V) will be applied to the internal circuit system 104.

[0048] In some applications, such as Figure 2 As shown, the internal circuitry 104 can be powered by a regulated version of the first voltage source V1 provided by a low-dropout regulator (LDO) 112, rather than by a separate voltage source provided at external pin 102. Herein, the LDO 112 is coupled between the first voltage source V1 and the internal circuitry 104, and the LDO 112 is configured to regulate the first voltage source V1 to a safe voltage level V suitable for the internal circuitry 104. P (For example, below the breakdown voltage of the thin oxide MOS transistor within the internal circuitry 104). LDO 112 is also made of thick oxide, rather than the thin oxide used in the thin oxide MOS transistor within the internal circuitry 104. Therefore, LDO 112 can withstand voltage levels higher than those in the internal circuitry 104 (e.g., the first voltage source V1). In one embodiment, electrical device 10 may further include another clamping unit 114 coupled between the first voltage source V1 and ground and coupled before LDO 112. Clamping unit 114 is also made of thick oxide and configured to protect LDO 112 during the energizing transient phase of the first voltage source V1 (e.g., clamping unit 114 is configured to clamp the voltage level applied to LDO 112 to below the breakdown voltage of LDO 112 during the energizing transient phase of the first voltage source V1). Clamping unit 114 may be implemented in the same manner as ESD clamping unit 106.

[0049] Typically, LDOs require a capacitor (coupled between the LDO's output and ground) to stabilize their output signal. However, due to the relatively large physical size of stabilizing capacitors, it is not desirable to integrate the stabilizing capacitor with the LDO in the same device. For the purposes of this illustration, the stabilizing capacitor C1 of the LDO 112 is not integrated into the electrical device 10, but is connected to the electrical device 10 at external pin 102. External pin 102 is electrically connected to the output of the LDO 112, allowing the stabilizing capacitor C1 to stabilize the output signal (i.e., stabilize it to the safe voltage source V of the internal circuitry 104). PIn this document, although external pin 102 is not configured to provide any voltage input to internal circuitry 104, external pin 102 may still experience ESD events. If external pin 102 is directly connected to the output of LDO 112, and the output of LDO 112 is directly connected to internal circuitry 104, internal circuitry 104 will experience a temporary high voltage during an ESD event, potentially causing breakdown damage to the thin oxide MOS transistors within internal circuitry 104. Therefore, an ESD protection block 100 is still required between external pin 102 and the output of LDO 112 / internal circuitry 104.

[0050] Similar to the description above, when the first voltage source V1 is absent, the protection switch 108 of the ESD protection block 100 (controlled by the switch controller 110) is de-energized (i.e., the protection switch 108 is open). Therefore, regardless of whether the ESD event occurs at the external pin 102, the external pin 102 is always disconnected from the internal circuitry 104. Additionally, when the first voltage source V1 is absent, the LDO 112 is inactive and will not supply a voltage source to the internal circuitry 104. During the energizing transient phase of the first voltage source V1, the protection switch 108 of the ESD protection block 100 (controlled by the switch controller 110) is de-energized. Therefore, regardless of the voltage level at the external pin 102, the external pin 102 remains disconnected from the internal circuitry 104. Additionally, during the energizing transient phase of the first voltage source V1, the clamping unit 114 is configured to clamp the transient voltage level of the first voltage source V1 to the safe level of the LDO 112, and the LDO 112 is activated and configured to provide a protected / safe voltage V. P The internal circuitry 104 is powered by the LDO 100. When an ESD event occurs in association with the first voltage source V1, the protection switch 108 of the ESD protection block 100 (controlled by the switch controller 110) is deactivated. Therefore, regardless of the voltage level at the external pin 102, the external pin 102 is always electrically disconnected from the internal circuitry 104. Additionally, the clamping unit 114 is configured to clamp abnormally high voltage levels associated with the first voltage source V1 (due to an ESD event) to the safe level of the LDO 112, and the LDO 112 is activated and configured to provide the protected / safe voltage V. P It supplies power to the internal circuit system 104.

[0051] When the first voltage source V1 is stably present and not associated with any ESD event, the protection switch 108 of the ESD protection block 100 is controlled to be on or off based on the transient voltage level presented at external pin 102 (by the switch controller 110). Additionally, when the first voltage source V1 is stably present, the LDO 112 is activated and configured to provide a protected / safe voltage v.P The internal circuitry 104 is powered by the first voltage source V1. When the first voltage source V1 is stably present and an ESD event occurs at external pin 112 (e.g., a transient voltage level presented at external pin 102 exceeds the breakdown voltage of the thin oxide MOS transistor), the switch controller 110 is configured to de-energize the protection switch 108 (i.e., the protection switch 108 is open). Therefore, the abnormally high transient voltage level presented at external pin 102 will not reach the internal circuitry 104. Additionally, in some scenarios where the transient voltage level presented at external pin 102 exceeds the breakdown voltage of the protection switch 108 or the switch controller 110, the ESD clamping unit 106 is configured to clamp the abnormally high transient voltage level presented at external pin 102 to a safe level for both the protection switch 108 and the switch controller 110. Therefore, an ESD event occurring at external pin 102 will not damage the protection switch 108 or the switch controller 110. Furthermore, when the first voltage source V1 is stably present and no ESD event occurs at the external power supply pin 102, the switch controller 110 is configured to turn on the protection switch 108 (i.e., the protection switch 108 is closed). Therefore, the external pin 102 and the stabilizing capacitor C1 are electrically connected to the output of the LDO 112, and a safe voltage source V1 is stably set at the output of the LDO 112 to power the internal circuitry system 104. P .

[0052] In some embodiments, each of the ESD clamping units 106 and 114 may be implemented by a Zener diode or a typical RC-based power rail ESD clamping circuit with multiple MOS transistors, and is made of thick oxide rather than the thin oxide used in the thin oxide MOS transistors within the internal circuitry 104. Figure 3An exemplary embodiment of a switch controller 110 is illustrated. In this document, the switch controller 110 includes an inverter 1102 coupled between a first voltage source V1 and ground, and the input terminal A_1 of the inverter 1102 is coupled to the first voltage source V1 via a first capacitor 1104. For the purposes of this illustration, the inverter 1102 may be implemented by a first transistor 1106 and a second transistor 1108, wherein the first transistor 1106 is a P-type MOS transistor and the second transistor 1108 is an N-type MOS transistor. The source of the first transistor 1106 is coupled to the first voltage source V1, the gate of the first transistor 1106 is coupled to the gate of the second transistor 1108, thereby forming the input terminal A_1 of the inverter 1102, the drain of the first transistor 1106 is coupled to the drain of the second transistor 1108, thereby forming the output terminal A_2 of the inverter 1102, and the source of the second transistor 1108 is coupled to ground. The input terminal A_1 of inverter 1102 can also be coupled to ground via a first resistor 1110 (i.e., the first capacitor 1104 and the first resistor 1110 are coupled in series between the first voltage source V1 and ground, and the input terminal A_1 of inverter 1102 is coupled to the junction of the first capacitor 1104 and the first resistor 1110). In different applications, inverter 1102 can be implemented in other configurations, and the first resistor 1110 can be omitted or replaced by other resistor structures.

[0053] Additionally, the switch controller 110 also includes a control switch 1112 coupled between the protection switch 108 and ground. For the purposes of this illustration, each of the protection switch 108 and the control switch 1112 may be implemented by an N-type MOS transistor (in this document and hereinafter, protection switch 108 and protection transistor 108 refer to the same electronic component, and control switch 1112 and control transistor 1112 refer to the same electronic component). The drain of protection transistor 108 is coupled to an external pin 102, the source of protection transistor 108 is coupled to an internal circuit system 104, and the gate of protection transistor 108 (i.e., the control terminal of protection switch 1108) is coupled to the drain of control transistor 1112 and to the output terminal of inverter 1102. The source of control transistor 1112 is coupled to ground, and the gate of control transistor 1112 (i.e., the control terminal of control switch 1112) is coupled to external pin 102 via a second capacitor 1114. The gate of the control transistor 1112 can also be coupled to ground via a second resistor 1116 (i.e., the second capacitor 1114 and the second resistor 1116 are coupled in series between the external pin 102 and ground, and the gate of the control transistor 1112 is coupled to the junction of the second capacitor 1114 and the second resistor 1116). In different applications, the protection switch 108 and the control switch 1112 can be implemented in other configurations. The second resistor 1116 can be omitted or replaced by other resistor structures.

[0054] The first transistor 1106, the second transistor 1108, and the control transistor 1112 are fabricated using thick oxide, rather than the thin oxide used in the thin oxide MOS transistors within the internal circuit system 104. Therefore, the first voltage source V1 applied to these transistors 1106, 1108, and 1112 can be greater than the voltage input V applied to the internal circuit system 104. P When the first voltage source V1 is absent, inverter 1102 is inactive, and the voltage level at output terminal A_2 of inverter 1102 is low (e.g., grounded). Regardless of whether an ESD event occurs at external pin 102 and / or whether control transistor 1112 is turned on or off, the voltage level applied to the gate of protection transistor 108 is low. Therefore, protection transistor 108 is always off, thereby electrically disconnecting internal circuitry 104 from external pin 102.

[0055] During the short-circuit transient phase of the first voltage source V1, the first capacitor 1104 pulls the voltage level at input terminal A_1 of inverter 1102 high. This is because the voltage across the first capacitor 1104 cannot be changed immediately. There is a time constant for the first capacitor 1104, which indicates the rate at which the first capacitor 1104 charges or discharges to change the voltage across it. The first resistor 1110 can be configured to tune the time constant of the first capacitor 1104. Once the voltage level at input terminal A_1 of inverter 1102 is high, the voltage level at output terminal A_2 of inverter 1102 is low (e.g., grounded). Regardless of whether an ESD event occurs at external pin 102 and / or whether control transistor 1112 is on or off, the voltage level applied to the gate of protection transistor 108 is low. Therefore, protection transistor 108 is always off, thereby electrically disconnecting the internal circuitry 104 from external pin 102. In this document, the first capacitor 1104 ensures that the protective switch 108 is not turned on if a sudden voltage jump occurs on the first voltage source V1.

[0056] When an ESD event occurs in association with the first voltage source V1 (i.e., a sudden voltage jump in the first voltage source), the first capacitor 1104 pulls the voltage level at input terminal A_1 of inverter 1102 high. This is because the voltage across the first capacitor 1104 cannot change immediately. There is a time constant for the first capacitor 1104, which indicates the rate at which the first capacitor 1104 charges or discharges to change the voltage across it. The first resistor 1110 can be configured to tune the time constant of the first capacitor 1104. Once the voltage level at input terminal A_1 of inverter 1102 is high, the voltage level at output terminal A_2 of inverter 1102 is low (e.g., grounded). Regardless of whether the ESD event occurs at external pin 102 and / or whether control transistor 1112 is on or off, the voltage level applied to the gate of protection transistor 108 is low. Therefore, protection transistor 108 is always off, thereby electrically disconnecting the internal circuitry 104 from external pin 102. In this document, the first capacitor 1104 ensures that the protection switch 108 is not turned on if an ESD event occurs in association with the first voltage source V1.

[0057] When the first voltage source V1 is stably present, the voltage level at input terminal A_1 of inverter 1102 is low (because most of the first voltage source V1 crosses the first capacitor 1104), and the voltage level at output terminal A_2 of inverter 1102 will be high. In this document, if an ESD event occurs at external pin 102 (i.e., a sudden high voltage is presented at external pin 102), the second capacitor 1114 will pull the voltage level at the gate of control transistor 1112 high (because the voltage across the second capacitor 1114 cannot be changed immediately as described above). The second resistor 1116 can be configured to tune the time constant of the second capacitor 1114. The high voltage level at the gate of control transistor 1112 turns control transistor 1112 to ground. In this document, control transistor 1112 is larger than the first transistor 1106. Therefore, the control transistor 1112, which is turned to ground, pulls the output terminal A_2 of inverter 1102 and the gate of protection transistor 108 to a low voltage level. When the first voltage source V1 is stably present and no ESD event occurs at external pin 102 (i.e., no sudden high voltage is presented at external pin 102), the voltage level at the gate of control transistor 1112 is low and control transistor 1112 is not turned on. Therefore, a high voltage level at the output terminal of inverter 1102 will be applied to the gate of protection transistor 108, protection transistor 108 will be turned on, and external pin 102 will be electrically connected to internal circuit system 104. For a non-limiting example, internal circuit system 104 may receive a voltage input from external pin 102, or electronic components external to the electrical device 10 coupled to external pin 102 may be stably applied to internal circuit system 104.

[0058] Figure 4 A flowchart illustrating the operation of an ESD protection block 100 for protecting thin oxide MOS transistors within an internal circuit system 104 during ESD events and / or power-on transient phases, according to some embodiments of the present disclosure, is provided. Although the process steps are shown sequentially, they are not necessarily sequentially related. Some steps may be performed in a different order than presented. Furthermore, processes within the scope of this disclosure may include more than […]. Figure 4The process shown has fewer or more steps. When the first voltage source V1 for powering the ESD protection block 100 is absent, the external pin 102 is disconnected from the internal circuit system 104 by disconnecting the protection switch 108 coupled between the external pin 102 and the internal circuit system 104 (step 400). Additionally, during the power-on transient phase of the first voltage source V1 for powering the ESD protection block 100, the external pin 102 is disconnected from the internal circuit system 104 by disconnecting the protection switch 108 coupled between the external pin 102 and the internal circuit system 104 (step 402). When an ESD event occurs at the external pin and / or occurs in association with the first voltage source V1, the external pin 102 is disconnected from the internal circuit system 104 by disconnecting the protection switch 108 coupled between the external pin 102 and the internal circuit system 104 (step 404). When the first voltage source V1, which supplies power to the ESD protection block 100, is stably present and no ESD event occurs at external pin 102 or is not associated with the first voltage source, the external pin 102 is connected to the internal circuitry 104 by closing the protection switch 108 coupled between external pin 102 and internal circuitry 104 (step 406). Herein, the opening or closing of the protection switch 108 is controlled by the switch controller 110 based on both the state of the first voltage source V1 and the presence of an ESD event at external pin 102.

[0059] It is envisioned that any of the foregoing aspects and / or various separate aspects and features described herein may be combined to obtain additional advantages. Unless otherwise indicated herein, any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0060] Those skilled in the art will understand improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. An electrostatic discharge (ESD) protection block for an electronic device, comprising: • A protective switch, coupled between the external pins of the electronic device and the internal circuitry of the electronic device; as well as • A switch controller configured to control the protection switch to be on or off based on both the state of a first voltage source supplying power to the ESD protection block and the presence of an ESD event at the external pin, wherein: • The breakdown voltage of the internal circuit system is lower than the breakdown voltage of the protection switch and the switch controller; The switch controller is configured to de-energize the protection switch when the first voltage source is absent, when the first voltage source is in a power-on transient phase, or when an ESD event occurs at the external pin and / or in association with the first voltage source, thereby electrically disconnecting the external pin from the internal circuitry. The switch controller is configured to turn on the protection switch when the first voltage source supplying power to the ESD protection block is stably present and no ESD event occurs at the external pin or is not associated with the first voltage source, such that the external pin is electrically connected to the internal circuitry.

2. The ESD protection block according to claim 1, wherein: The internal circuitry includes multiple thin-film metal-oxide-semiconductor (MOS) transistors; and The protection switch and the switch controller are made of thick oxide, rather than the thin oxide used in the plurality of thin oxide MOS transistors within the internal circuit system.

3. The ESD protection block of claim 1, further comprising an ESD clamping unit coupled between the external pin and ground and before the protection switch and the switch controller, wherein the ESD clamping unit is configured to limit the voltage level at the external pin to below the breakdown voltage of the protection switch and the switch controller.

4. The ESD protection block according to claim 3, wherein: The internal circuitry system comprises multiple thin oxide MOS transistors; and The ESD clamping unit, the protection switch, and the switch controller are manufactured using thick oxide, rather than the thin oxide used in the plurality of thin oxide MOS transistors within the internal circuitry.

5. The ESD protection block according to claim 4, wherein: The protection switch is implemented by a protection transistor that is an N-type MOS transistor; and The drain of the protection transistor is coupled to the external pin, the source of the protection transistor is coupled to the internal circuit system, and the gate of the protection transistor is controlled by the switch controller.

6. The ESD protection block according to claim 5, wherein: The switch controller includes an inverter, a first capacitor, a control switch, and a second capacitor. The inverter is coupled between the first voltage source that powers the ESD protection block and ground, and the first capacitor is coupled between the first voltage source and the input terminal of the inverter. The control switch is coupled between the gate of the protection transistor and ground; • The output terminal of the inverter is coupled to the gate of the protection transistor; and The second capacitor is coupled between the external pin and the control terminal of the control switch.

7. The ESD protection block according to claim 6, wherein: The inverter is implemented by a first transistor and a second transistor, wherein the first transistor is a P-type MOS transistor and the second transistor is an N-type MOS transistor; The source of the first transistor is coupled to the first voltage source, the gate of the first transistor is coupled to the gate of the second transistor, thereby forming the input terminal of the inverter, the drain of the first transistor is coupled to the drain of the second transistor, thereby forming the output terminal of the inverter, and the source of the second transistor is coupled to ground; The control switch is implemented by a control transistor that is an N-type MOS transistor; and The drain of the control transistor is coupled to the gate of the protection transistor, the source of the control transistor is coupled to ground, and the gate of the control transistor is coupled to the external pin through the second capacitor.

8. The ESD protection block according to claim 7, wherein: The first transistor, the second transistor, the control transistor, and the protection transistor are manufactured using thick oxide, rather than the thin oxide used in the thin oxide MOS transistors within the internal circuitry; and • The first voltage source supplying power to the ESD protection block is greater than the voltage input applied to the internal circuit system.

9. The ESD protection block according to claim 7, wherein the control transistor is larger than the first transistor of the inverter.

10. The ESD protection block according to claim 9, wherein: • When the first voltage source is absent, the inverter is inactive and the voltage level at the output terminal of the inverter is low, wherein the protection transistor does not conduct regardless of whether an ESD event occurs at the external pin, thereby electrically disconnecting the internal circuitry from the external pin. • During the short-circuit transient phase of the first voltage source or when an ESD event occurs in association with the first voltage source, the first capacitor pulls the voltage level at the input terminal of the inverter high, which causes the voltage level at the output terminal of the inverter to be low, wherein the protection transistor does not conduct regardless of whether the ESD event occurs at the external pin, and thereby electrically disconnects the internal circuitry from the external pin; • When the first voltage source is stably present and an ESD event occurs at the external pin, the second capacitor pulls the voltage level at the gate of the control transistor high, which turns the control transistor to ground, wherein the turned-on control transistor pulls the output terminal of the inverter and the gate of the protection transistor to a low voltage level, and the turned-on control transistor is larger than the first transistor of the inverter; and • When the first voltage source is stably present and no ESD event occurs at the external pin, the control transistor is not turned on, and the voltage level at the output terminal of the inverter is high, causing the protection transistor to turn on, and the external pin is electrically connected to the internal circuitry.

11. The ESD protection block according to claim 7, wherein: The switch controller further includes a first resistor and a second resistor; and The first resistor is coupled between the input terminal of the inverter and ground, and the second resistor is coupled between the gate of the control transistor and ground.

12. An electronic device comprising: External pins; • Internal circuitry system; as well as • Electrostatic discharge (ESD) protection block, coupled between the external pins and the internal circuitry, wherein: • The internal circuit system includes multiple thin oxide MOS transistors, and the ESD protection block is made of thick oxide instead of the thin oxide used in the multiple thin oxide MOS transistors within the internal circuit system, such that the breakdown voltage of the internal circuit system is lower than the breakdown voltage of the ESD protection block. The ESD protection block is configured to connect the external pin to the internal circuitry or disconnect the external pin from the internal circuitry based on both the state of the first voltage source powering the ESD protection block and the presence of an ESD event at the external pin. • When the first voltage source is absent, when an ESD event occurs at the external pin and / or in association with the first voltage source, the external pin is disconnected from the internal circuitry; and • When the first voltage source supplying power to the ESD protection block is stably present and no ESD event occurs at the external pin or is not associated with the first voltage source, the external pin is connected to the internal circuitry.

13. The electronic device according to claim 12, wherein: The ESD protection block includes: a protection switch coupled between the external pin and the internal circuitry; and a switch controller configured to control the protection switch to be on or off based on both the state of the first voltage source powering the ESD protection block and the presence of an ESD event at the external pin. The switch controller is configured to de-energize the protection switch when the first voltage source is absent, when the first voltage source is in a power-on transient phase, or when an ESD event occurs at the external pin and / or in association with the first voltage source, thereby disconnecting the external pin from the internal circuitry. The switch controller is configured to turn on the protection switch, such that the external pin is connected to the internal circuitry, when the first voltage source supplying power to the ESD protection block is stably present and no ESD event occurs at the external pin or is not associated with the first voltage source.

14. The electronic device of claim 13, wherein the ESD protection block further comprises an ESD clamping unit coupled between the external pin and ground and before the protection switch and the switch controller, wherein the ESD clamping unit is configured to limit the voltage level at the external pin to below the breakdown voltage of the protection switch and the switch controller.

15. The electronic device of claim 12, wherein the external pin is configured to provide a second voltage source to power the internal circuitry, and the second voltage source is lower than the first voltage source powering the ESD protection block.

16. The electronic device of claim 12, wherein the external pin is configured to provide a logic input signal to the internal circuitry, and the logic input signal of the internal circuitry is lower than the first voltage source powering the ESD protection block.

17. The electronic device of claim 12, further comprising a low-dropout regulator (LDO), wherein the LDO is coupled between the first voltage source and the internal circuitry, and the internal circuitry is powered by a regulated version of the first voltage source provided by the LDO.

18. The electronic device of claim 17, further comprising a clamping unit coupled between the first voltage source and ground and coupled before the LDO, wherein the clamping unit is configured to clamp a voltage level applied to the LDO to a value below the breakdown voltage of the LDO during the energizing transient phase of the first voltage source.

19. The electronic device of claim 18, wherein the LDO and the clamping unit are manufactured using thick oxide instead of the thin oxide used in the plurality of thin oxide MOS transistors within the internal circuitry, such that the breakdown voltage of the internal circuitry is lower than the breakdown voltage of the LDO and the clamping unit.

20. A method for operating an electrostatic discharge (ESD) protection block of an electronic device to protect thin oxide metal oxide semiconductor (MOS) transistors within an internal circuit system of the electronic device, the ESD protection block comprising a switch controller and a protection switch coupled between an external pin of the electronic device and the internal circuit system, the method comprising: • When the first voltage source supplying power to the ESD protection block is absent, the external pin is disconnected from the internal circuit system by turning off the protection switch; • During the power-on transient phase of the first voltage source supplying power to the ESD protection block, the external pin is disconnected from the internal circuitry by disconnecting the protection switch; • When an ESD event occurs at the external pin and / or in association with the first voltage source, the external pin is disconnected from the internal circuitry by turning off the protection switch; as well as • When the first voltage source supplying power to the ESD protection block is stably present and no ESD event occurs at the external pin or is not associated with the first voltage source, the external pin is connected to the internal circuitry by closing the protection switch, wherein: The opening or closing of the protective switch is controlled by the switch controller based on both the state of the first voltage source and the presence of the ESD event at the external pin; and • The breakdown voltage of the thin oxide MOS transistor within the internal circuit system is lower than the breakdown voltage of the protection switch and the switch controller.

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