Light-emitting diode chip with improved heat conduction and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode chip with improved thermal conductivity and a method for manufacturing the same, belonging to the field of optoelectronic manufacturing technology. The light-emitting diode chip comprises: an epitaxial layer, a first insulating layer, a metal support layer, a second insulating layer, and an electrode block. The epitaxial layer, the first insulating layer, and the metal support layer are stacked in sequence, the second insulating layer being located on the metal support layer, and the electrode block being located on the second insulating layer and connected to the epitaxial layer via vias. The electrode block is insulated from the metal support layer. Embodiments of the present disclosure can improve the thermal conductivity of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode chip with improved heat conduction and a preparation method thereof. Background Art

[0002] Light emitting diodes (LEDs) are a highly influential new product in the optoelectronics industry. They have the characteristics of small size, long service life, rich colors, and low energy consumption. They are widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.

[0003] In related technologies, a light-emitting diode chip generally includes a substrate, an epitaxial layer, an insulating layer, and two electrode blocks. The epitaxial layer includes an n-type layer, a multi-quantum well layer, and a p-type layer stacked in sequence on the substrate. The surface of the n-type layer has a groove exposing the p-type layer. The insulating layer is located on the surface of the epitaxial layer and in the groove. The insulating layer has two through holes exposing the n-type layer and the p-type layer, respectively. The two electrode blocks are located on the insulating layer and are connected to the p-type layer and the n-type layer, respectively, through the two through holes.

[0004] Since the area where the light-emitting diode chip generates the most heat is where the electrode block connects to the epitaxial layer, this area is usually surrounded by an insulating layer and has poor heat dissipation. In addition, the chip is easily deformed when under pressure and has poor stability. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode chip with improved thermal conductivity and a method for manufacturing the same, which can improve the thermal conductivity of the chip and enhance the heat dissipation effect and stability of the chip. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode chip with improved thermal conduction, wherein the light-emitting diode chip includes: an epitaxial layer, a first insulating layer, a metal support layer, a second insulating layer and an electrode block; the epitaxial layer, the first insulating layer and the metal support layer are stacked in sequence, the second insulating layer is located on the metal support layer, the electrode block is located on the second insulating layer and is connected to the epitaxial layer through a via, and the electrode block is insulated from the metal support layer.

[0007] Optionally, the metal support layer has two through holes exposing the first insulating layer, the second insulating layer is at least located on the hole walls of the through holes, and the electrode block is located in the through holes.

[0008] Optionally, the first insulating layer has a first via hole exposing the epitaxial layer, the first via hole corresponds to the through hole, and the first via hole is located in the corresponding through hole, and the electrode block is connected to the epitaxial layer through the first via hole.

[0009] Optionally, the first insulating layer further has a second via hole, and the metal support layer is connected to the epitaxial layer through the second via hole.

[0010] Optionally, the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer, and the first semiconductor layer, the multi-quantum well layer, and the second semiconductor layer are stacked in sequence, and the second semiconductor layer has a groove exposing the first semiconductor layer; the light-emitting diode chip also includes: a first current conducting layer, a second current conducting layer, and a third insulating layer, the first current conducting layer is located on the surface of the second semiconductor layer, the second current conducting layer is located on the surface of the first semiconductor layer in the groove, the third insulating layer is located at least in the groove, separating the first current conducting layer and the second current conducting layer, the first insulating layer is located on the side of the first current conducting layer and the second current conducting layer away from the first semiconductor layer, and there are two electrode blocks, and the two electrode blocks are respectively connected to the first current conducting layer and the second current conducting layer through vias.

[0011] Optionally, the orthographic projections of the first current conducting layer and the metal support layer on the surface of the first semiconductor layer close to the multi-quantum well layer at least partially overlap; the orthographic projections of the second current conducting layer and the metal support layer on the surface of the first semiconductor layer close to the multi-quantum well layer at least partially overlap.

[0012] Optionally, the thickness of the metal support layer is not less than 1 μm.

[0013] Optionally, the thickness of the electrode block is not less than 5 μm.

[0014] Optionally, the light-emitting diode chip further includes an encapsulation layer, the encapsulation layer is located on the second insulating layer, and a surface of the encapsulation layer away from the epitaxial layer is flush with a surface of the electrode block away from the epitaxial layer.

[0015] On the other hand, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode chip with improved thermal conduction, the method comprising: providing a substrate; forming an epitaxial layer, a first insulating layer and a metal support layer in sequence on the substrate; forming a second insulating layer on the metal support layer; making an electrode block on the second insulating layer, the electrode block being connected to the epitaxial layer through a via, and the electrode block being insulated from the metal support layer.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode chip provided by the embodiment of the present disclosure includes an epitaxial layer, a first insulating layer and a metal support layer stacked on a substrate, the second insulating layer is located on the surface of the metal support layer, and two electrode blocks are provided on the second insulating layer. In this way, the two insulating layers sandwich the metal support layer, thereby isolating the electrode blocks and the metal support layer, preventing the metal support layer from being directly electrically connected to the electrode blocks, which would cause a short circuit between the two electrode blocks.

[0018] Compared to related technologies that surround the epitaxial layer with an insulating layer, the metal support layer has excellent heat transfer properties. Therefore, even if a large amount of heat is generated in the connection area between the electrode block and the epitaxial layer, the metal support layer can effectively conduct the heat to the chip, thereby improving the chip's thermal conductivity. Furthermore, compared to related technologies, this chip removes the substrate on the side of the chip, further enhancing the chip's heat dissipation. Furthermore, compared to the insulating layer in related technologies, the metal support layer has superior strength, supporting the electrode block and improving the chip's impact resistance. Therefore, during the pressure-bearing process of chip transfer, it is less likely to deform under pressure, thereby improving the chip's stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 is a structural schematic diagram of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0021] Figure 2 is a structural schematic diagram of another light-emitting diode chip provided by an embodiment of the present disclosure;

[0022] Figure 3 This is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0023] Figure 4 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0024] Figure 5 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0025] Figure 6 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0026] Figure 7This is a schematic diagram of a process for preparing a light-emitting diode chip provided in an embodiment of the present disclosure.

[0027] The descriptions of the marks in the figure are as follows:

[0028] 10. Substrate;

[0029] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer; 24. groove;

[0030] 31, first insulating layer; 311, first via hole; 312, second via hole; 32, second insulating layer; 33, third insulating layer; 331, third via hole;

[0031] 40. Metal support layer; 41. Through hole;

[0032] 50. Electrode block;

[0033] 61. First current conducting layer; 62. Second current conducting layer;

[0034] 70. Encapsulation layer. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0036] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0037] Figure 1 FIG. 1 is a schematic diagram of the structure of a light-emitting diode chip provided by an embodiment of the present disclosure. Figure 1As shown, the light emitting diode chip includes: an epitaxial layer 20 , a first insulating layer 31 , a metal support layer 40 , a second insulating layer 32 and two electrode blocks 50 .

[0038] like Figure 1 As shown, the epitaxial layer 20, the first insulating layer 31 and the metal support layer 40 are stacked in sequence, the second insulating layer 32 is located on the metal support layer 40, the electrode block 50 is located on the second insulating layer 32 and is connected to the epitaxial layer 20 through a via, and the electrode block 50 is insulated from the metal support layer 40.

[0039] The light-emitting diode chip provided by the embodiment of the present disclosure includes an epitaxial layer 20, a first insulating layer 31 and a metal support layer 40 stacked on a substrate 10. The metal support layer 40 has two through holes 41 exposing the first insulating layer 31. The second insulating layer 32 is located on the surface of the metal support layer 40. Two electrode blocks 50 are provided on the second insulating layer 32. In this way, the two insulating layers sandwich the metal support layer 40, thereby isolating the electrode blocks 50 and the metal support layer 40, preventing the metal support layer 40 from being directly electrically connected to the electrode blocks 50, which would cause the two electrode blocks 50 to short-circuit.

[0040] Compared to the related art, which uses an insulating layer to surround the epitaxial layer 20, the metal support layer 40 has excellent heat transfer properties. Therefore, even if a large amount of heat is generated in the connection area between the electrode block 50 and the epitaxial layer 20, the metal support layer 40 can effectively conduct the heat to the chip, thereby improving the chip's thermal conductivity. Furthermore, compared to the related art, this chip removes the substrate 10 on the side of the chip, further enhancing the chip's heat dissipation. Furthermore, compared to the insulating layer in the related art, the metal support layer 40 has superior strength, supporting the electrode block 50 and improving the chip's impact resistance. Therefore, during the chip's transfer and pressure process, it is less likely to deform under pressure, thereby improving the chip's stability.

[0041] Alternatively, as Figure 1 As shown, the epitaxial layer 20 includes a first semiconductor layer 21 , a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence. The second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21 .

[0042] A groove 24 is formed on the surface of the epitaxial layer 20 to expose the first semiconductor layer 21 , so that the first semiconductor layer 21 is electrically connected to the electrode block 50 .

[0043] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0044] As an example, the first semiconductor layer 21 is an n-type layer, and the electrode block 50 connected to the first semiconductor layer 21 is an n-type electrode. The second semiconductor layer 23 is a p-type layer, and the electrode block 50 connected to the second semiconductor layer 23 is a p-type electrode.

[0045] Optionally, the first semiconductor layer 21 is a magnesium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 1 μm.

[0046] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0047] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0048] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0049] Optionally, the second semiconductor layer 23 is an n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 1 μm.

[0050] Alternatively, as Figure 1 As shown, the metal support layer 40 has two through holes 41 exposing the first insulating layer 31 , the second insulating layer 32 is at least located on the hole walls of the through holes 41 , and the electrode block 50 is located in the through holes 41 .

[0051] By providing a through hole 41 on the metal support layer 40, and the second insulating layer 32 extending from the surface of the metal support layer 40 into the through hole 41, the electrode block and the metal support layer are isolated by the second insulating layer, thereby preventing the metal support layer from being directly electrically connected to the electrode block, thereby preventing the problem of short circuit between the two electrode blocks.

[0052] Alternatively, as Figure 1 As shown, the first insulating layer 31 has a first via hole 311 exposing the epitaxial layer 20 . The first via hole 311 corresponds to the through hole 41 and is located inside the corresponding through hole 41 . The electrode block 50 is connected to the epitaxial layer 20 through the first via hole 311 .

[0053] One of the two first via holes 311 exposes the first semiconductor layer of the epitaxial layer 20 , and the other of the two first via holes 311 exposes the second semiconductor layer of the epitaxial layer 20 , so that the two electrode blocks 50 can be electrically connected to different semiconductor layers respectively.

[0054] like Figure 1As shown, the light-emitting diode chip further includes: a first current conducting layer 61, a second current conducting layer 62, and a third insulating layer 33. The first current conducting layer 61 is located on the surface of the second semiconductor layer 23, the second current conducting layer 62 is located on the surface of the first semiconductor layer 21 within the groove 24, and the third insulating layer 33 is located at least within the groove 24, separating the first current conducting layer 61 and the second current conducting layer 62. The first insulating layer 31 is located on the side of the first current conducting layer 61 and the second current conducting layer 62 away from the first semiconductor layer 21.

[0055] There are two electrode blocks 50 , and the two electrode blocks 50 are respectively connected to the first current conducting layer 61 and the second current conducting layer 62 through vias.

[0056] Exemplarily, both the first current conducting layer 61 and the second current conducting layer 62 may be indium tin oxide (ITO) layers.

[0057] Among them, the indium tin oxide film layer has good transmittance and low resistivity, which facilitates carrier conduction and improves injection efficiency.

[0058] For example, both the first current conducting layer and the second current conducting layer may be metal layers, as metal has good electrical conductivity, which can improve injection efficiency.

[0059] For example, the first current conducting layer and the second current conducting layer may both be Au layers, Al layers, etc.

[0060] By providing the first current conducting layer 61 , the current transmitted from the electrode block 50 can be extended to various regions of the second semiconductor layer 23 through the first current conducting layer 61 , thereby improving the light emitting effect of the chip.

[0061] like Figure 1 As shown, the second current conducting layer 62 is located on the third insulating layer 33 and at least in the first via hole 311 in the groove 24 .

[0062] By providing the second current conducting layer 62 , the current transmitted from the electrode block 50 can be extended to the first semiconductor layer 21 through the second current conducting layer 62 , so that the two semiconductor layers of the epitaxial layer 20 are energized and emit light.

[0063] like Figure 1 As shown, the first insulating layer 31 is located on the second current conducting layer 62 , and the first insulating layer 31 is located on the third insulating layer 33 . The first insulating layer 31 has a first via hole 311 exposing the second current conducting layer 62 . The first via hole 311 is opposite to the through hole 41 .

[0064] In the disclosed embodiment, a first insulating layer 31 is provided to isolate the second current-conducting layer 62 from the metal support layer 40. The first insulating layer 31 is also provided with a first via 311 that exposes the second current-conducting layer 62, allowing the electrode block 50 to connect to the second current-conducting layer 62 sequentially through the via 41 and the first via 311. Furthermore, the third insulating layer 33 has a third via 331 that exposes the first semiconductor layer 21. At least a portion of the second current-conducting layer 62 is located within the third via 331 and is connected to the first semiconductor layer 21, allowing the electrode block 50 to connect to the first semiconductor layer 21 sequentially through the via 41, the first via 311, the second current-conducting layer 62, and the third via 331.

[0065] For example, Figure 1 As shown, the first insulating layer 31 is located on the third insulating layer 33, and when the first insulating layer 31 extends to the area on the second semiconductor layer 23 opposite to the through hole 41, a first via 311 can be set at a position on the first insulating layer 31 opposite to the through hole 41, and the first via 311 is connected to the via hole on the third insulating layer 33 that exposes the first current conducting layer 61, so that the electrode block 50 can be connected to the first current conducting layer 61 through the through hole 41 and the first via 311.

[0066] Alternatively, as Figure 1 As shown, the orthographic projections of the first current conducting layer 61 and the metal support layer 40 on the surface of the first semiconductor layer 21 close to the multi-quantum well layer 22 at least partially overlap.

[0067] By arranging at least a portion of the first current conducting layer 61 opposite the metal support layer 40, the area of ​​the first current conducting layer 61 facing the metal support layer 40 can be increased, thereby improving the heat transfer effect between the first current conducting layer 61 and the metal support layer 40. This allows heat generated by the chip at the first current conducting layer 61 to be more easily transferred to the metal support layer 40, thereby improving the thermal conductivity and heat dissipation of the chip.

[0068] like Figure 1 As shown, the orthographic projections of the second current conducting layer 62 and the metal support layer 40 on the surface of the first semiconductor layer 21 close to the multi-quantum well layer 22 at least partially overlap.

[0069] By arranging at least a portion of the second current conducting layer 62 opposite the metal support layer 40, the area of ​​the second current conducting layer 62 facing the metal support layer 40 can be increased, thereby improving the heat transfer effect between the second current conducting layer 62 and the metal support layer 40. This allows the heat generated by the chip at the second current conducting layer 62 to be more easily transferred to the metal support layer 40, thereby improving the thermal conductivity and heat dissipation of the chip.

[0070] For example, the first insulating layer 31 , the second insulating layer 32 and the third insulating layer 33 may all be silicon oxide or silicon nitride layers.

[0071] For example, the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 can each be a distributed Bragg reflector (DBR layer), which includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer can be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0072] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0073] In addition to its passivation function, the DBR layer is also used to reflect light emitted from the multi-quantum well layer 22 to the DBR layer to the light-emitting surface of the chip, thereby improving the light-emitting effect.

[0074] Figure 2 FIG. 1 is a schematic diagram of the structure of another light-emitting diode chip provided by an embodiment of the present disclosure. Figure 2 As shown, the first insulating layer 31 further has a second via hole 312 , and the metal support layer 40 is connected to the epitaxial layer 20 through the second via hole 312 .

[0075] For example, Figure 2 As shown, the first insulating layer 31 has a second via 312, which is located outside the through-hole 41 and opposite the metal support layer 40. The first current conducting layer 61 on the second semiconductor layer 23 is connected to the metal support layer 40 through the second via 312. Because there are two insulating layers between the second semiconductor layer 23 and the metal support layer 40, the third insulating layer 33 also has a second via 312. The second via 312 on the first insulating layer 31 is connected to the second via 312 on the third insulating layer 33, thereby connecting the first current conducting layer 61 to the metal support layer 40.

[0076] The second via 312 allows the first current conducting layer 61 to be directly connected to the metal support layer 40 , making it easier for heat to be transferred from the first current conducting layer 61 to the metal support layer 40 , thereby improving the thermal conductivity of the chip and enhancing the heat dissipation effect of the chip.

[0077] Alternatively, as Figure 1 As shown, the light emitting diode chip further includes an encapsulation layer 70 , which is located on the second insulating layer 32 . The surface of the encapsulation layer 70 away from the epitaxial layer 20 is flush with the surface of the electrode block 50 away from the epitaxial layer 20 .

[0078] The encapsulation layer 70 is provided to cover the electrode block 50 to improve the connection reliability of the electrode block 50 on the chip. The surface of the encapsulation layer 70 is flush with the surface of the electrode block 50 away from the epitaxial layer 20, and only the end face of the electrode block 50 is exposed. This ensures that the electrode block 50 is electrically connected and prevents a large portion of the electrode block 50 from being exposed to the external environment, thereby improving the reliability of the electrode block 50.

[0079] For example, the encapsulation layer 70 may be an organic insulating material layer such as epoxy resin.

[0080] Optionally, the thickness of the metal support layer 40 is not less than 1 μm. For example, the thickness of the metal support layer 40 is 2 μm.

[0081] By setting the thickness of the metal support layer 40 within the above range, it is possible to avoid the metal support layer 40 being too thin to support the electrode block 50 and improve the chip's impact resistance.

[0082] Optionally, the metal support layer 40 includes at least one of an Au layer, a Cu layer, a Ni layer, and an Al layer.

[0083] Exemplarily, the metal support layer 40 may be a Cu layer.

[0084] Optionally, the thickness of the electrode block 50 is not less than 5 μm. For example, the thickness of the electrode block 50 is 6 μm.

[0085] By setting the thickness of the electrode block 50 within the above range, it is possible to avoid the electrode block 50 being too thin to penetrate the first insulating layer 31 , the metal support layer 40 and the second insulating layer 32 to connect to the semiconductor layer in the epitaxial layer 20 .

[0086] Optionally, the electrode block 50 includes at least one of an Au layer, a Cu layer, a Ni layer, and a Sn layer.

[0087] Exemplarily, the electrode block 50 may be a Ni layer.

[0088] Figure 3 This is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure. Figure 1 The light emitting diode chip shown. Figure 3 As shown, the preparation method comprises:

[0089] S11: providing a substrate 10.

[0090] S12 : forming an epitaxial layer 20 , a first insulating layer 31 and a metal support layer 40 in sequence on the substrate 10 .

[0091] The metal support layer 40 has two through holes 41 exposing the first insulating layer 31 , and the first insulating layer 31 has first via holes 311 respectively exposing the two semiconductor layers of the epitaxial layer 20 . The first via holes 311 correspond one-to-one to the through holes 41 , and the first via holes 311 are located in the corresponding through holes 41 .

[0092] S13 : forming a second insulating layer 32 on the metal support layer 40 .

[0093] The second insulating layer 32 is at least located in the through hole 41 and on the surface of the first insulating layer 31 .

[0094] S14 : forming an electrode block 50 on the second insulating layer 32 .

[0095] The electrode block 50 is connected to the epitaxial layer 20 through a via, and the electrode block 50 is insulated from the metal support layer 40 .

[0096] The light-emitting diode chip prepared by this preparation method includes an epitaxial layer 20, a first insulating layer 31, and a metal support layer 40 stacked on a substrate 10. The metal support layer 40 has two through-holes 41 that expose the first insulating layer 31. A second insulating layer 32 is located on the surface of the metal support layer 40. Two electrode blocks 50 are provided on the second insulating layer 32. In this way, by sandwiching the metal support layer 40 between the two insulating layers, the electrode blocks 50 and the metal support layer 40 are isolated, preventing the metal support layer 40 from directly electrically connecting to the electrode blocks 50, which would cause the two electrode blocks 50 to short-circuit. Compared with the related art method of surrounding the epitaxial layer 20 with an insulating layer, the metal support layer 40 has excellent heat transfer performance. Therefore, even if a large amount of heat is generated in the connection area between the electrode blocks 50 and the epitaxial layer 20, the metal support layer 40 can effectively transfer the heat to the chip, thereby improving the chip's thermal conductivity. At the same time, compared with the related art, the substrate 10 on the side of the chip is removed, further enhancing the chip's heat dissipation effect. Moreover, the metal support layer 40 has better strength than the insulating layer in the related art, and can support the electrode block 50 and improve the impact resistance of the chip. Therefore, during the process of chip transfer and pressure, it is not easy to be compressed and deformed, thereby improving the stability of the chip.

[0097] In step S11, the substrate 10 is a sapphire substrate 10, a silicon substrate 10, or a silicon carbide substrate 10. The substrate 10 can be a flat substrate 10 or a patterned substrate 10.

[0098] As an example, in the embodiment of the present disclosure, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 is a commonly used substrate 10 with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 10 or a sapphire flat sheet substrate 10.

[0099] The sapphire substrate 10 may be pre-treated by placing it in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. For example, in the embodiment of the present disclosure, the sapphire substrate 10 is baked for 15 minutes.

[0100] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0101] Figure 4 FIG. 1 is a schematic diagram of a process for preparing a light-emitting diode chip according to an embodiment of the present disclosure. Figure 4 As shown, growing the epitaxial layer 20 on the substrate 10 in step S12 may include: sequentially forming a first semiconductor layer 21 , a multi-quantum well layer 22 and a second semiconductor layer 23 on the sapphire substrate 10 by MOCVD technology.

[0102] The first semiconductor layer 21 is an n-type layer, and the electrode block 50 connected to the first semiconductor layer 21 is an n-type electrode. The second semiconductor layer 23 is a p-type layer, and the electrode block 50 connected to the second semiconductor layer 23 is a p-type electrode.

[0103] Optionally, the first semiconductor layer 21 is an indium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 1 μm.

[0104] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0105] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0106] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0107] Optionally, the second semiconductor layer 23 is an n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 1 μm.

[0108] In the embodiment of the present disclosure, the first semiconductor layer 21 is a p-type GaN layer. When growing the p-type GaN layer, the growth pressure of the p-type GaN layer can be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer can be 800°C to 1000°C.

[0109] In the embodiment of the present disclosure, the second semiconductor layer 23 is an n-type GaN layer. The growth temperature of the n-type GaN layer can be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer can be 100 torr to 300 torr.

[0110] In the disclosed embodiment, when growing the multi-quantum well layer 22, the MOCVD chamber pressure is controlled at 200 Torr. When growing the InGaN quantum well layer, the chamber temperature is 760°C to 780°C. When growing the GaN quantum barrier layer, the chamber temperature is 860°C to 890°C. These process conditions produce high-quality multi-quantum well layers 22.

[0111] like Figure 4 As shown, after the epitaxial layer 20 is grown in step S12 , the step further includes: etching the second semiconductor layer 23 to form a groove 24 exposing the first semiconductor layer 21 .

[0112] Specifically, the method may include: etching the second semiconductor layer 23 by dry etching to expose the first semiconductor layer 21 .

[0113] like Figure 5 As shown, step S12 may include the following steps before growing the metal support layer 40:

[0114] In the first step, a first current conducting layer 61 is formed on the surface of the second semiconductor layer 23 .

[0115] Exemplarily, the first current conducting layer 61 may be an indium tin oxide film layer or a metal layer.

[0116] In the second step, a third insulating layer 33 is formed on the surface of the first current conducting layer 61 . The third insulating layer 33 extends to the surface of the second semiconductor layer 23 and into the groove 24 . The third insulating layer 33 is located on the surface of the first semiconductor layer 21 .

[0117] Exemplarily, the third insulating layer 33 may be a silicon oxide or silicon nitride layer.

[0118] For example, the third insulating layer 33 may be a DBR layer. The DBR layer includes a plurality of SiO2 layers and TiO2 layers that are periodically and alternately stacked. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0119] In the third step, a third via hole 331 is formed by etching the third insulating layer 33 .

[0120] In the fourth step, a second current conducting layer 62 is formed on the third insulating layer 33 , and the second current conducting layer 62 is at least located in the third via hole 331 in the groove 24 .

[0121] Exemplarily, the second current conducting layer 62 may be an indium tin oxide film layer or a metal layer.

[0122] In the fifth step, a first insulating layer 31 is formed on the second current conducting layer 62 .

[0123] The first insulating layer 31 is located on the third insulating layer 33 . The first insulating layer 31 has a first via hole 311 exposing the second current conducting layer 62 . The first via hole 311 is opposite to the through hole 41 .

[0124] like Figure 5 As shown, the first insulating layer 31 extends to the area on the second semiconductor layer 23 opposite to the through hole 41. A first via 311 can be set at a position on the first insulating layer 31 opposite to the through hole 41, and the first via 311 is connected to the via on the third insulating layer 33 that exposes the first current conducting layer 61.

[0125] Exemplarily, the first insulating layer 31 may be a silicon oxide or silicon nitride layer.

[0126] For example, the first insulating layer 31 may be a DBR layer. The DBR layer includes a plurality of SiO2 layers and TiO2 layers that are periodically and alternately stacked. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0127] like Figure 6 As shown, growing the metal support layer 40 in step S12 may include: forming the metal support layer 40 on the surface of the first insulating layer 31 .

[0128] The metal support layer 40 has two through holes 41 exposing the first insulating layer 31 .

[0129] Optionally, the thickness of the metal support layer 40 is not less than 1 μm. For example, the thickness of the metal support layer 40 is 2 μm.

[0130] Optionally, the metal support layer 40 includes at least one of an Au layer, a Cu layer, a Ni layer, and an Al layer. Exemplarily, the metal support layer 40 may be a Cu layer.

[0131] like Figure 7 As shown, the second insulating layer 32 grown on the surface of the metal support layer 40 in step S13 is at least located in the through hole 41 and extends to the surface of the first insulating layer 31 .

[0132] Exemplarily, the second insulating layer 32 may be a silicon oxide or silicon nitride layer.

[0133] For example, the second insulating layer 32 may be a DBR layer. The DBR layer includes a plurality of SiO2 layers and TiO2 layers that are periodically and alternately stacked. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0134] like Figure 7 As shown, in step S14, two electrode blocks 50 are made on the second insulating layer 32. The two electrode blocks 50 are located at least in the through hole 41 and the first via hole 311. The two electrode blocks 50 are connected to the two semiconductor layers of the epitaxial layer 20 through the two first via holes 311 respectively.

[0135] Optionally, the thickness of the electrode block 50 is not less than 5 μm. For example, the thickness of the electrode block 50 is 6 μm.

[0136] Optionally, the electrode block 50 includes at least one of an Au layer, a Cu layer, a Ni layer, and a Sn layer. Exemplarily, the electrode block 50 may be a Ni layer.

[0137] like Figure 7 As shown, after manufacturing the two electrode blocks 50 , the process further includes forming a packaging layer 70 on the surface of the second insulating layer 32 .

[0138] The surface of the encapsulation layer 70 away from the epitaxial layer 20 is flush with the surface of the electrode block 50 away from the epitaxial layer 20 .

[0139] For example, the encapsulation layer 70 may be an organic insulating material layer such as epoxy resin.

[0140] like Figure 1 As shown, after the encapsulation layer 70 is completed, the following steps are further performed: using laser or chemical etching to peel off the substrate 10 and complete surface cleaning.

[0141] Finally, conventional methods are used to cut the chip according to the preset size to complete the chip unit production.

[0142] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A light-emitting diode chip, characterized in that: The light-emitting diode chip comprises: an epitaxial layer (20), a first insulating layer (31), a metal support layer (40), a second insulating layer (32), an electrode block (50) and a second current conducting layer (62); The epitaxial layer (20), the first insulating layer (31) and the metal support layer (40) are stacked in sequence, the second insulating layer (32) is located on the metal support layer (40), the electrode block (50) is located on the second insulating layer (32) and is connected to the epitaxial layer (20) through a via hole, and the electrode block (50) is insulated from the metal support layer (40); The second current conducting layer (62) is located on the surface of the epitaxial layer (20), and the orthographic projections of the second current conducting layer (62) and the metal support layer (40) on the surface of the epitaxial layer (20) at least partially overlap.

2. The light-emitting diode chip according to claim 1, characterized in that The metal support layer (40) has two through holes (41) exposing the first insulating layer (31); the second insulating layer (32) is at least located on the hole walls of the through holes (41); and the electrode block (50) is located in the through holes (41).

3. The light-emitting diode chip according to claim 2, characterized in that: The first insulating layer (31) has a first via hole (311) exposing the epitaxial layer (20), the first via hole (311) corresponds to the through hole (41), and the first via hole (311) is located in the corresponding through hole (41), and the electrode block (50) is connected to the epitaxial layer (20) through the first via hole (311).

4. The light-emitting diode chip according to claim 2, characterized in that: The first insulating layer (31) also has a second via hole (312), and the metal support layer (40) is connected to the epitaxial layer (20) through the second via hole (312).

5. The light-emitting diode chip according to claim 3, characterized in that The epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22), and a second semiconductor layer (23); the first semiconductor layer (21), the multi-quantum well layer (22), and the second semiconductor layer (23) are stacked in sequence; and the second semiconductor layer (23) has a groove (24) exposing the first semiconductor layer (21); The light-emitting diode chip further comprises: a first current conducting layer (61), a second current conducting layer (62) and a third insulating layer (33); the first current conducting layer (61) is located on the surface of the second semiconductor layer (23); the second current conducting layer (62) is located on the surface of the first semiconductor layer (21) in the groove (24); the third insulating layer (33) is at least located in the groove (24) to separate the first current conducting layer (61) and the second current conducting layer (62); the first insulating layer (31) is located on a side of the first current conducting layer (61) and the second current conducting layer (62) away from the first semiconductor layer (21); There are two electrode blocks (50), and the two electrode blocks (50) are respectively connected to the first current conducting layer (61) and the second current conducting layer (62) through via holes.

6. The light-emitting diode chip according to claim 5, characterized in that The orthographic projections of the first current conducting layer (61) and the metal support layer (40) on the surface of the first semiconductor layer (21) close to the multi-quantum well layer (22) at least partially overlap; The orthographic projections of the second current conducting layer (62) and the metal support layer (40) on the surface of the first semiconductor layer (21) close to the multi-quantum well layer (22) at least partially overlap.

7. The light-emitting diode chip according to any one of claims 1 to 6, characterized in that: The thickness of the metal support layer (40) is not less than 1 μm.

8. The light-emitting diode chip according to any one of claims 1 to 6, characterized in that: The thickness of the electrode block (50) is not less than 5 μm.

9. The light-emitting diode chip according to any one of claims 1 to 6, characterized in that: The light-emitting diode chip further comprises a packaging layer (70), the packaging layer (70) being located on the second insulating layer (32), and the surface of the packaging layer (70) away from the epitaxial layer (20) being flush with the surface of the electrode block (50) away from the epitaxial layer (20).

10. A method for preparing a light emitting diode chip, characterized in that: The preparation method comprises: providing a substrate; forming an epitaxial layer, a first insulating layer, and a metal support layer in sequence on the substrate, and forming a second current conducting layer on the epitaxial layer, wherein the orthographic projections of the second current conducting layer and the metal support layer on the surface of the epitaxial layer at least partially overlap; forming a second insulating layer on the metal support layer; An electrode block is manufactured on the second insulating layer. The electrode block is connected to the epitaxial layer through a via hole, and the electrode block is insulated from the metal support layer.

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