Digital Logic Self-Testing Method, Device, Electronic Device and Medium for System on Chip

Abstract

An embodiment of the present disclosure discloses a digital logic self-test method, device, electronic device, and medium for a system-on-chip. The method includes: determining a logic vector corresponding to a logic object to be tested in the system-on-chip and a target number of the logic vectors; testing the logic object to be tested based on the logic vectors to obtain a test result of the logic object to be tested; compressing the test result to obtain a compression result; generating a test completion signal for the logic object to be tested in response to the logic object to be tested completing the test of the target number of logic vectors; and transmitting the test completion signal and the compression result to a system-on-chip control module through an interrupt transfer method. The fast transmission of the test completion signal and the compression result is achieved, effectively reducing the transmission time of the compression result, thereby reducing the waiting time for the comparison result of the compression result, greatly improving the test efficiency, and solving the problems such as the long waiting time for the comparison result of the compression result in the prior art.

Description

Technical Field

[0001] The present disclosure relates to testing technologies, and in particular to a digital logic self-test method, device, electronic device, and medium for a system-on-chip. Background Art

[0002] With the development of the testing technology of System-On-a-Chip (SOC for short), Design For Test (DFT for short) technology has been applied to the circuit design of integrated circuits, improving the testability of integrated circuits. Among them, implementing the internal logic test of a system-on-chip based on Logic Built-in Self-Test (LBIST for short) is an important test method for a system-on-chip. By setting special structures into the circuit during the design stage of the system-on-chip, the internal signals of the system-on-chip circuit can be observed outside the circuit. For example, a scan chain is formed by replacing ordinary registers with shift registers, enabling the signal values of the internal flip-flops of the circuit to be controlled and observed from the outside. In related technologies, the internal self-test of the system-on-chip is usually completed through the IEEE1687 protocol. Since the IEEE1687 protocol uses an IJTAG (Internal JTAG (Joint Test Action Group)) serial network for transmission, after the test vector ends, the obtained response result digital signature (that is, the characteristic symbol obtained by compressing the response result (or test result), also called the compression result. For example, the characteristic symbol obtained by compressing the response result through a Multiple Input Signature Register MISR) needs to be serially shifted and compared with the reference result, or the obtained response result needs to be serially shifted to a peripheral interface for comparison with a processor (CPU). The comparison and analysis results of the response result digital signature in both of these two methods require a long waiting time, resulting in low self-test efficiency. Summary of the Invention

[0003] In order to solve the problems in the prior art such as the long waiting time for the comparison result of the compression result leading to low self-test efficiency, the present disclosure is proposed. Embodiments of the present disclosure provide a digital logic self-test method, device, electronic device, and medium for a system-on-chip.

[0004] According to one aspect of the embodiments of the present disclosure, there is provided a method for digital logic self-testing of a system-on-chip, including: determining a logic vector corresponding to a logic object to be tested in the system-on-chip and a target number of the logic vectors; testing the logic object to be tested based on the logic vector to obtain a test result of the logic object to be tested; compressing the test result to obtain a compressed result corresponding to the test result; generating a test completion signal for the logic object to be tested in response to the logic object to be tested completing the test of the target number of logic vectors; and transmitting the test completion signal and the compressed result to a system-on-chip control module through an interrupt transfer mode.

[0005] According to another aspect of the embodiments of the present disclosure, there is provided a device for digital logic self-testing of a system-on-chip, including: a first determination module for determining a logic vector corresponding to a logic object to be tested in the system-on-chip and a target number of the logic vectors; a first processing module for testing the logic object to be tested based on the logic vector to obtain a test result of the logic object to be tested; a second processing module for compressing the test result to obtain a compressed result corresponding to the test result; a third processing module for generating a test completion signal for the logic object to be tested in response to the logic object to be tested completing the test of the target number of logic vectors; and a fourth processing module for transmitting the test completion signal and the compressed result to a system-on-chip control module through an interrupt transfer mode.

[0006] According to still another aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium storing a computer program for executing the method for digital logic self-testing of a system-on-chip according to any one of the above embodiments of the present disclosure.

[0007] According to yet another aspect of the embodiments of the present disclosure, there is provided an electronic device, where the electronic device includes: a processor; a memory for storing executable instructions of the processor; the processor for reading the executable instructions from the memory and executing the instructions to implement the method for digital logic self-testing of a system-on-chip according to any one of the above embodiments of the present disclosure; or, the electronic device includes: the device for digital logic self-testing of a system-on-chip according to any one of the above embodiments of the present disclosure.

[0008] Based on the digital logic self-test method, device, electronic device, and medium of the system-on-chip provided in the above embodiments of the present disclosure, when testing a logic object to be tested in the system-on-chip based on a logic vector, after the logic object to be tested completes a target number of logic vectors, the test completion signal corresponding to the logic object to be tested and the compressed result of the test result can be quickly transmitted to the system-on-chip control module through an interrupt transmission method, so that the system-on-chip control module can obtain the compressed result in real time and quickly. Compared with serial shift transmission through the IJTAG network, the transmission time of the compressed result is effectively reduced, thereby reducing the waiting time for the comparison result of the compressed result, greatly improving the test efficiency, and solving problems such as the long waiting time for the comparison result of the compressed result in the prior art.

[0009] The following will further describe the technical solutions of the present disclosure in detail through the accompanying drawings and embodiments. Description of the Drawings

[0010] By describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation to the present disclosure. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0011] Figure 1 is an exemplary application scenario of the digital logic self-test method of the system-on-chip provided by the present disclosure;

[0012] Figure 2 is a schematic flowchart of the digital logic self-test method of the system-on-chip provided by an exemplary embodiment of the present disclosure;

[0013] Figure 3 is a schematic flowchart of step 205 provided by an exemplary embodiment of the present disclosure;

[0014] Figure 4 is a schematic flowchart of step 2051 provided by an exemplary embodiment of the present disclosure;

[0015] Figure 5 is a schematic diagram of the principle of the signal response optimization circuit provided by an exemplary embodiment of the present disclosure;

[0016] Figure 6 is a schematic flowchart of the digital logic self-test method of the system-on-chip provided by another exemplary embodiment of the present disclosure;

[0017] Figure 7 is a schematic diagram of the principle of the signal response optimization circuit provided by another exemplary embodiment of the present disclosure;

[0018] Figure 8It is a schematic flow chart of a digital logic self - test method for a system - on - chip provided by another exemplary embodiment of the present disclosure;

[0019] Figure 9 It is a schematic diagram of the principle of action of a test acceleration enabling signal provided by an exemplary embodiment of the present disclosure;

[0020] Figure 10 It is a schematic structural diagram of a signal response optimization circuit provided by another exemplary embodiment of the present disclosure;

[0021] Figure 11 It is a schematic flow chart of a digital logic self - test method for a system - on - chip provided by another exemplary embodiment of the present disclosure;

[0022] Figure 12 It is a schematic structural diagram of a digital logic self - test device for a system - on - chip provided by an exemplary embodiment of the present disclosure;

[0023] Figure 13 It is a schematic structural diagram of a fourth processing module 505 provided by an exemplary embodiment of the present disclosure;

[0024] Figure 14 It is a schematic structural diagram of a first processing unit 5051 provided by an exemplary embodiment of the present disclosure;

[0025] Figure 15 It is a schematic structural diagram of a signal response optimization circuit 50511 provided by an exemplary embodiment of the present disclosure;

[0026] Figure 16 It is a schematic structural diagram of a fourth processing module 505 provided by another exemplary embodiment of the present disclosure;

[0027] Figure 17 It is a schematic structural diagram of a fourth processing module 505 provided by another exemplary embodiment of the present disclosure;

[0028] Figure 18 It is a schematic structural diagram of a signal response optimization circuit 50511 provided by another exemplary embodiment of the present disclosure;

[0029] Figure 19 It is a schematic structural diagram of a signal response optimization circuit 50511 provided by another exemplary embodiment of the present disclosure;

[0030] Figure 20 It is a schematic structural diagram of a digital logic self - test device for a system - on - chip provided by another exemplary embodiment of the present disclosure;

[0031] Figure 21 It is a schematic timing diagram of a logic self - test provided by an exemplary embodiment of the present disclosure;

[0032] Figure 22It is a schematic structural diagram of an application embodiment of the electronic device of the present disclosure;

[0033] Figure 23 It is a schematic structural diagram of another application embodiment of the electronic device of the present disclosure. Detailed implementation manners

[0034] Next, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all embodiments of the present disclosure. It should be understood that the present disclosure is not limited by the exemplary embodiments described herein.

[0035] It should be noted that: Unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0036] Those skilled in the art can understand that the terms "first", "second", etc. in the embodiments of the present disclosure are only used to distinguish different steps, devices, or modules, etc., and neither represent any specific technical meaning nor indicate an inevitable logical order between them.

[0037] It should also be understood that in the embodiments of the present disclosure, "a plurality of" may refer to two or more, and "at least one" may refer to one, two, or more.

[0038] It should also be understood that for any component, data, or structure mentioned in the embodiments of the present disclosure, unless otherwise clearly defined or given a contrary indication in the context, it is generally understood to be one or more.

[0039] In addition, the term "and / or" in the present disclosure is only a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the associated objects before and after.

[0040] It should also be understood that the present disclosure emphasizes the differences between the various embodiments. Their similarities or similarities can be referred to each other. For the sake of brevity, they will not be described one by one.

[0041] At the same time, it should be understood that for the sake of description, the dimensions of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0042] The following description of at least one exemplary embodiment is actually only illustrative and in no way a limitation on the present disclosure and its application or use.

[0043] Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered as part of the specification.

[0044] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

[0045] Embodiments of the present disclosure can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing technology environments including any of the above systems, and so on.

[0046] Terminal devices, computer systems, servers, and other electronic devices can be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logic, data structures, and so on, which perform specific tasks or implement specific abstract data types. The computer system / server can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0047] Overview of the present disclosure

[0048] In the process of implementing the present disclosure, the inventors found that with the development of the test technology of System-On-a-Chip (SOC for short), Design For Test (DFT for short) technology has been applied to the circuit design of integrated circuits, improving the testability of integrated circuits. Among them, implementing the internal logic test of the system-on-chip based on Logic Built-in Self-Test (LBIST for short) is an important test method for the system-on-chip. By setting special structures into the circuit during the design stage of the system-on-chip, the internal signals of the system-on-chip circuit can be observed outside the circuit. For example, a scan chain is formed by replacing ordinary registers with shift registers, enabling the signal values of the internal flip-flops of the circuit to be controlled and observed from the outside. In related technologies, the internal self-test of the system-on-chip is usually completed through the IEEE1687 protocol. Since the IEEE1687 protocol uses the IJTAG (Internal JTAG (Joint Test Action Group)) serial network transmission, after the test vector ends, the obtained response result digital signature (that is, the characteristic symbol obtained by compressing the response result (or test result), also called the compression result, such as the characteristic symbol obtained by compressing the response result through the Multiple Input Signature Register MISR) needs to be serially shifted and compared with the reference result, or the obtained response result needs to be serially shifted to the peripheral interface for comparison by the processor (CPU). In both cases, the comparison and analysis results of the response result digital signature need to wait for a long time, resulting in low self-test efficiency.

[0049] Exemplary overview

[0050] Figure 1This is an exemplary application scenario of the digital logic self-test method for a system-on-chip provided by the present disclosure. In a system-on-chip, the test circuit logic implanted during the design phase can control the entire system of the system-on-chip, some subsystems, and some digital logic circuits in the subsystem, etc., to wait for the logic object to be tested to enter the logic self-test mode. The test circuit logic can include logic circuits such as a test controller, a logic vector generator, an input strobe, and a test result compressor. Among them, the test controller is used to control the measurement processes related to the start and end of the test, etc. The logic vector generator is used to generate logic vectors for testing. The input strobe is used to implement the input switching between the normal operation and the test mode. The logic object to be tested responds to the logic vectors for testing and obtains test results. The test result compressor is used to compress the test results of the logic object to be tested and obtain a compressed result. By using the digital logic self-test method for the system-on-chip of the present disclosure, after the logic object to be tested completes the test of the target number of logic vectors, a test completion signal for the logic object to be tested can be generated, and the test completion signal and the compressed result of the test result are transmitted to the system-on-chip control module through the interrupt transmission method, so that the system-on-chip control module can obtain the compressed result in real time and quickly through the interrupt. Compared with the serial shift transmission through the IJTAG network, the transmission time of the compressed result is effectively reduced, thereby reducing the waiting time for the comparison result of the compressed result, greatly improving the test efficiency, and solving the problems such as the long waiting time for the comparison result of the compressed result in the prior art.

[0051] Exemplary method

[0052] Figure 2 This is a schematic flowchart of the digital logic self-test method for a system-on-chip provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to any system-on-chip, specifically, for example, in the system-on-chip of a vehicle computing platform, such as Figure 2 shown, and includes the following steps:

[0053] Step 201, determine the logic vectors corresponding to the test of the logic object to be tested in the system-on-chip and the target number of the logic vectors.

[0054] Among them, the system-on-chip can be a system integrated in a chip in any scenario. For example, in the scenario of autonomous driving, it can be a system-on-chip for vehicle autonomous driving control, and there is no specific limitation. The system-on-chip can include subsystems such as a central processing unit (CPU), a microcontroller unit (MCU), a memory, and peripheral circuits. Each subsystem can include one or more corresponding circuit units according to its function. The logic object to be tested can be one or more subsystems in the system-on-chip, or can also be some circuit units in the subsystem, and can be specifically set according to actual requirements. The test logic vectors corresponding to the logic object to be tested can be generated based on a pre-configured logic vector generation method, and the target number of logic vectors can be set according to actual requirements. Each logic vector can be a binary number with a preset number of bits. For example, an 8-bit binary number 11101011 can be specifically set according to actual requirements.

[0055] Step 202: Test the logic object to be tested based on the logic vectors to obtain the test result of the logic object to be tested.

[0056] Among them, the test result of the logic object to be tested includes the response results of the logic object to be tested in response to each logic vector. During the test, the logic vectors are shifted into the scan chain of the logic object to be tested to implement the test of the logic object to be tested. The scan chain is implanted with shift registers, enabling users to control and observe the signal values of internal flip-flops of the circuit from the outside. A shift register is a device based on the cascade of flip-flops that operates under several identical time pulses. The output of each flip-flop is connected to the "data" input terminal of the next flip-flop in the flip-flop chain, enabling the circuit to shift one bit (also called a bit) to the left or right in sequence within each time pulse and output at the output terminal. The specific principle will not be elaborated here.

[0057] Step 203: Compress the test result to obtain the compression result corresponding to the test result.

[0058] Among them, the compression result is the result obtained by compressing the test result into a relatively small binary number. Since the test results of the logic objects to be tested in the system-on-chip usually require a large amount of storage space, in order to save storage space, the test results are compressed. The specific compression method can be set according to actual requirements. For example, any implementable compression circuit can be used. Specifically, for example, a multi-input signature register (abbreviation: MISR) can be used to compress the test result and store the compression result, and there is no specific limitation.

[0059] When the logic object to be tested completes the test of the target number of logic vectors, the compression results of the test results corresponding to each logic vector can be obtained.

[0060] Step 204: Generate a test completion signal for the logic object under test in response to the logic object under test completing the testing of the target number of logic vectors.

[0061] Among them, the test completion signal is used to indicate that the logic object under test has completed the current logic self-test. During the testing process, the completion of the testing of the target number of logic vectors can be detected by any feasible means. For example, it can be implemented through a counting register. First, the target number can be written into the counting register. For each completed logic vector test, the value in the counting register is decremented by 1. When the value in the counting register becomes 0, it indicates that the testing of the target number of logic vectors has been completed, which can be specifically set according to actual requirements. The test completion signal can be represented by setting it high or "1", and there is no specific limitation.

[0062] Step 205: Transmit the test completion signal and the compression result to the on-chip system control module through the interrupt transfer method.

[0063] Among them, the interrupt transfer method means that the device implementing this method in the present disclosure stores the test completion signal and the compression result in an area agreed with the on-chip system control module (for example, in a target register that the on-chip system control module can access through the bus), sends an interrupt signal to the on-chip system control module, and the on-chip system control module responds to the interrupt signal and directly obtains the test completion signal and the compression result from the corresponding area through the bus. The test completion signal is used to notify the on-chip system control module that the logic object under test has completed the current logic self-test, and the compression result is used to compare with the reference result to determine whether the logic function of the logic object under test is normal. The on-chip system control module can be a module in the on-chip system that controls the logic self-test, such as a central processing unit (CPU), which can be specifically set according to actual requirements. In the present disclosure, the bus can be any feasible bus supported by the on-chip system, such as an APB (Advanced Peripheral Bus), and there is no specific limitation.

[0064] For the digital logic self-test method of the on-chip system provided in this embodiment, after the logic object under test completes the testing of the target number of logic vectors, the test completion signal and the compression result can be transmitted to the on-chip system control module through the interrupt transfer method, so that the on-chip system control module can obtain the compression result in real time and quickly. Compared with the serial shift transmission through the IJTAG network, the transmission time of the compression result is effectively reduced, thereby reducing the waiting time for the comparison result of the compression result, greatly improving the test efficiency, and solving problems such as the long waiting time for the comparison result of the compression result in the prior art.

[0065] In an optional example, Figure 3 is a schematic flowchart of Step 205 provided by an exemplary embodiment of the present disclosure. In this example, Step 205 can specifically include the following steps:

[0066] Step 2051: Write the test completion signal and the compression result into the target register.

[0067] Among them, the target register can be any implementable register, and the system - on - chip control module can access the target register through the bus to obtain the test completion signal and the compression result in the target register.

[0068] Step 2052: Send an interrupt signal to the system - on - chip control module through the bus, so that the system - on - chip control module, in response to the interrupt signal, obtains the test completion signal and the compression result from the target register.

[0069] Among them, the interrupt signal is used to notify the system - on - chip control module that the test completion signal and the compression result have been written into the target register, and the system - on - chip control module can obtain the test completion signal and the compression result from the target register in response to the interrupt signal.

[0070] In the present disclosure, by writing the test completion signal and the compression result into the target register and sending an interrupt signal to the system - on - chip control module through the bus, so that the system - on - chip control module, in response to the interrupt signal, quickly obtains the test completion signal and the compression result from the target register, fast transmission based on the interrupt transfer mode is realized.

[0071] In an optional example, Figure 4 FIG. is a schematic flowchart of step 2051 provided by an exemplary embodiment of the present disclosure. In this example, writing the test completion signal and the compression result into the target register in step 2051 includes:

[0072] Step 20511: Write the test completion signal into the first register in the target register.

[0073] Specifically, the test completion signal can be written into the first register through the completion signal response circuit. The completion signal response circuit can be composed of "AND" logic and / or "OR" logic, as long as it can transmit the test completion signal to the first register, and can be specifically set according to actual requirements.

[0074] Step 20512: Parallel - write each bit value included in the compression result into the second register in the target register.

[0075] Among them, each bit value included in the compression result can realize the parallel writing of each bit value through a preset compression result response circuit.

[0076] Among them, the compression result includes at least one bit value, which can be specifically set according to actual requirements. For example, the compression result includes 32 bit values, that is, the compression result is a 32 - bit binary number. Each bit value can be parallel - written into the second register through the compression result response circuit.

[0077] Exemplarily, Figure 5 FIG. 1 is a schematic diagram of the principle of a signal response optimization circuit provided by an exemplary embodiment of the present disclosure. In this example, the signal response optimization circuit includes a complete signal response circuit and a compressed result response circuit. Here, LBIST represents Logic Built-in Self-Test, which refers to the digital logic self-test of the logic object under test in this example. LBIST_EN represents the enable of the logic self-test mode, LBIST_DONE represents the test completion signal, MISR represents the Multiple Input Signature Register, and LBIST_MISR[0]-LBIST_MISR

[31] represent the compressed results obtained by compression through MISR. The compressed results include 32 bit values. Each bit value is correspondingly connected to an AND logic circuit. A compressed result response circuit is formed by 32 parallel AND logic circuits, so as to realize writing each bit value of the compressed result into the second register in parallel in the logic self-test mode. Similarly, the test completion signal LBIST_DONE is connected to an AND logic circuit to realize writing the test completion signal into the first register, and the test completion signal can be written in parallel with the compressed result, further improving the transmission efficiency.

[0078] The present disclosure can effectively reduce the shift time and improve the test efficiency by writing each bit value of the compressed result into the target register in parallel without serial shifting through the IJTAG network.

[0079] In an alternative example, Figure 6 FIG. 2 is a schematic flowchart of a digital logic self-test method for a system-on-chip provided by another exemplary embodiment of the present disclosure. In this example, the testing of the logic object under test based on the logic vector in step 202 includes:

[0080] Step 2021, in response to any one of the logic vectors in the logic vector completing the test of the logic object under test, transmitting the capture enable signal corresponding to the logic vector to the system-on-chip control module through an interrupt transmission method, so that the system-on-chip control module can collect the compressed result of the test result corresponding to the logic vector after receiving the capture enable signal.

[0081] Among them, during the logic self-test process, for each logic vector, after the logic vector completes the test on the logic object to be tested, a capture enable signal corresponding to the logic vector can be generated, and the capture enable signal is transmitted to the on-chip system control module through the interrupt transfer method. The capture enable signal is used to notify the on-chip system control module that the test of the logic vector is completed, and the compressed result of the test result corresponding to the logic vector can be collected. After receiving the capture enable signal, the on-chip system control module can collect the compressed result of the test result corresponding to the logic vector for comparison with the reference result corresponding to the logic vector to determine whether the test result of the logic vector is normal. The capture enable signal can also be first written into the third register through the capture enable response circuit and an interrupt signal can be sent to the on-chip system control module, or the on-chip system control module detects the third register, determines the capture enable signal, and then collects the compressed result corresponding to the logic vector, which can be specifically set according to actual requirements.

[0082] Exemplarily, Figure 7 FIG. 5 is a schematic diagram of the principle of the signal response optimization circuit provided by another exemplary embodiment of the present disclosure. In this example, in addition to the foregoing completion signal response circuit and compressed result response circuit, the signal response optimization circuit further includes a capture enable response circuit, which is composed of an "AND" logic circuit. The capture enable signal Capture_en and the logic self-test mode enable LBIST_EN are used as the inputs of the capture enable response circuit to complete the capture of the compressed results corresponding to each logic vector in the logic self-test mode. During the test, the compressed result corresponding to each logic vector can be transmitted to the on-chip system control module through the IJTAG network, or can be written into the second register in parallel through LBIST_MISR[0]-LBIST_MISR

[31] , and the on-chip system control module obtains the compressed result corresponding to the logic vector from the second register. It can be specifically set according to actual requirements. Since the generation principle of the logic vector is realized by shifting, the compression principle of the MISR is that each input of the MISR is connected to the output of the scan chain in the logic object to be tested, the number of stages of the MISR is the number of scan chains, and the MISR compresses multiple outputs into a characteristic value. As the tests of each logic vector are continuously completed, the MISR state changes continuously. After each logic vector is completed, there is a corresponding MISR state, that is, each logic vector corresponds to a compressed result. Until the target number of logic vectors are completed, the MISR state stabilizes and the compressed result of the final test result is obtained. The specific principle of the MISR will not be elaborated here.

[0083] The present disclosure enables the system - on - chip control module to capture the compressed results of the test results corresponding to each logic vector by transmitting a capture enable signal to the system - on - chip control module after each logic vector is completed, facilitating the analysis of whether the response of the logic object under test to each logic vector is correct and providing convenience for debugging the system on chip.

[0084] Figure 8 It is a schematic flowchart of the digital logic self - test method of the system on chip provided by another exemplary embodiment of the present disclosure.

[0085] In an optional example, the transmitting the test completion signal and the compressed result to the system - on - chip control module by the interrupt transfer method in step 205 includes:

[0086] Step 20501, determining the state of the configured test acceleration enable signal, where the test acceleration enable signal is used to indicate the transmission method of the test completion signal and the compressed result.

[0087] Among them, the test acceleration enable signal can be configured according to the user's setting when entering the logic self - test mode. For example, the test acceleration enable signal can be configured to the fourth register. 1 indicates enabling, that is, it is necessary to transmit the test completion signal and the compressed result by the interrupt transfer method, and 0 indicates disabling, that is, the test completion signal and the compressed result are transmitted through the traditional on - line system test logic path (serial transmission path in the IJTAG network).

[0088] Step 20502, in response to the state of the test acceleration enable signal being enabled, transmitting the test completion signal and the compressed result to the system - on - chip control module by the interrupt transfer method.

[0089] Among them, the state of the test acceleration enable signal being enabled means that the test completion signal and the compressed result need to be quickly transmitted by the interrupt transfer method in this test. Therefore, in response to the state of the test acceleration enable signal being enabled, the test completion signal and the compressed result are transmitted to the system - on - chip control module by the interrupt transfer method.

[0090] The method of the present disclosure further includes:

[0091] Step 206, in response to the state of the test acceleration enable signal being disabled, transmitting the test completion signal and the compressed result to the system - on - chip control module through the on - line system test logic path.

[0092] Among them, the state of the test acceleration enable signal being disabled means that it is not necessary to transmit the test completion signal and the compressed result by the interrupt transfer method. Therefore, in response to the state of the test acceleration enable signal being disabled, the test completion signal and the compressed result are transmitted to the system - on - chip control module through the on - line system test logic path.

[0093] Exemplarily,Figure 9 This is a schematic diagram of the principle of action of the test acceleration enable signal provided by an exemplary embodiment of the present disclosure. In this example, the test acceleration enable signal is configured through the fourth register. When the state of the test acceleration enable signal in the fourth register is enabled, the test completion signal and the compression result can be written into the first register and the second register respectively. The capture enable signal can also be written into the third register after each logic vector is completed.

[0094] The present disclosure realizes the coexistence of the interrupt transfer mode and the IJTAG network transfer mode by configuring the state of the test acceleration enable signal. The user can select the transfer mode according to their own needs. When the user needs to quickly transfer the test completion signal and the compression result to the on-chip system control module, the state of the test acceleration enable signal can be configured to be enabled. When performing a logic self-test, if the state of the test acceleration enable signal is detected to be enabled, the test completion signal and the compression result will be quickly transferred to the on-chip system control module through the interrupt transfer mode. When the user wants to adopt the traditional transfer mode, the state of the test acceleration enable signal can also be configured to be disabled. Then, during the logic self-test, if the state of the test acceleration enable signal is detected to be disabled, the test completion signal and the compression result will be serially shifted to the peripheral interface through the on-line system test logic path in the IJTAG network and given to the on-chip system control module, thus providing the user with the selection function of two transfer modes and effectively improving the user experience.

[0095] In an alternative example, when there are multiple logic objects to be tested, the corresponding signals of each logic object to be tested can be written into the corresponding register through an "OR" logic.

[0096] Exemplarily, Figure 10 This is a schematic diagram of the structure of the signal response optimization circuit provided by another exemplary embodiment of the present disclosure. In this example, the interrupt transfer mode transmission of the test completion signal LBIST_DONE, the compression results LBIST_MISR[0]-LBIST_MISR

[31] , and the capture enable signal Capture_en related to the test results of two logic objects to be tested can be realized. When testing any logic object to be tested, the compression result and the test completion signal of this logic object to be tested can be quickly transferred to the on-chip system control module through the interrupt transfer mode. After a logic vector is completed, the capture enable signal can be transferred to the on-chip system control module through the interrupt transfer mode. When there are more logic objects to be tested, such as 3 logic objects to be tested, it can be at Figure 10After the "OR" logic circuit in , add another stage of "OR" logic. Perform an "OR" operation on the test completion signal LBIST_DONE, compression results LBIST_MISR[0]-LBIST_MISR

[31] , and capture enable signal Capture_en of the third logic object to be tested with the outputs of the corresponding "OR" logic in the figure respectively, to realize the connection of various signals of multiple logic objects to be tested with the corresponding registers. The specific principle will not be elaborated one by one.

[0097] In the present disclosure, a group of registers is shared by multiple logic objects to be tested, effectively reducing the number of registers and improving the utilization efficiency of the registers. During testing, since a group of registers is shared by multiple logic objects to be tested, and the writing of the test completion signals and compression results of different logic objects to be tested is achieved through OR logic. To further ensure the effective testing of each logic object to be tested, different logic objects to be tested can perform logic self-tests at different times, so as to ensure that only one logic object to be tested is in the logic self-test mode at the same moment, so that the test completion signal and compression result written into this group of registers are the test completion signal and compression result of this logic object to be tested, avoiding the situation that multiple logic objects to be tested are in the logic self-test mode at the same time and affecting each other when writing the test completion signals and compression results of each logic object to be tested into this group of registers, and ensuring the accuracy and effectiveness of the test results. For example Figure 10 For the first "OR" logic in , when both the first logic object to be tested and the second logic object to be tested are in the logic self-test mode, as long as one of the test completion signals is completed, it will be written into the first register, and it is impossible to determine which logic object to be tested the test completion signal belongs to. Therefore, it is necessary to ensure that among multiple logic objects to be tested sharing a group of registers at the same moment, only one logic object to be tested is in the logic self-test mode, and different logic objects to be tested perform logic self-tests at different times. If each logic object to be tested is provided with its own exclusive register, parallel logic self-tests of multiple logic objects to be tested can be realized, which can be specifically set according to actual requirements.

[0098] Figure 11 It is a schematic flowchart of the digital logic self-test method of the system-on-chip provided by another exemplary embodiment of the present disclosure.

[0099] In an optional example, before determining the logic vector corresponding to the logic test of the logic object to be tested on the system-on-chip and the target quantity of the logic vector in step 201, it further includes:

[0100] Step 301, in response to receiving a request to enter the idle state sent by the system-on-chip control module, control the target subsystem where the logic object to be tested is located to enter the idle state.

[0101] Among them, the request to enter the idle state is used to request the target subsystem where the logic object to be tested is located to enter the idle state, preparing for entering the logic self-test mode.

[0102] Step 302: Return a first confirmation signal to the on-chip system control module. The first confirmation signal is used to notify the on-chip system control module that the target subsystem has entered the idle state.

[0103] Among them, after the target subsystem enters the idle state, a first confirmation signal is returned to the on-chip system control module to notify the on-chip system control module that the target subsystem has entered the idle state and can enter the logic self-test mode.

[0104] Step 303: In response to receiving the logic self-test mode signal sent by the on-chip system control module in response to the first confirmation signal, control the logic object to be tested to switch from the functional mode to the logic self-test mode, and return a second confirmation signal to the on-chip system control module. The second confirmation signal is used to notify the on-chip system control module that the logic object to be tested has switched to the logic self-test mode.

[0105] Among them, the logic self-test mode signal is used to control the logic object to be tested in the target subsystem to enter the logic self-test mode. After receiving the first confirmation signal, the on-chip system control module can send the logic self-test mode signal to the target subsystem to control the logic object to be tested to switch from the functional mode to the logic self-test mode. The on-chip system control module can send this logic self-test mode signal through the IJTAG network. After the logic object to be tested switches to the logic self-test mode, a second confirmation signal is returned to the on-chip system control module to notify the on-chip system control module that the logic object to be tested has switched to the logic self-test mode and can start the logic self-test.

[0106] Step 304: In response to receiving the initial logic vector writing command sent by the on-chip system control module in response to the second confirmation signal, write the initial logic vector and the target number of logic vectors into the corresponding registers respectively. The initial logic vector is used to generate the target number of logic vectors.

[0107] Among them, the initial logic vector writing command can include the initial vector to be written, the target number of logic vectors, and the write command. After receiving the second confirmation signal, the on-chip system control module determines that the logic object to be tested has switched to the logic self-test mode and can send the initial logic vector writing command to the target subsystem. The test circuit logic of the target subsystem can respond to the initial logic vector writing command and write the initial logic vector and the target number of logic vectors into the corresponding registers respectively for the logic self-test of the logic object to be tested.

[0108] The present disclosure interacts with a target subsystem through a system-on-chip control module, ensuring that the target subsystem enters the logic self-test mode and starts the logic self-test after entering the idle state, enabling the target subsystem to utilize the idle time for logic self-test without affecting the normal operation of the target subsystem.

[0109] In an alternative example, after transmitting the test completion signal and the compression result to the system-on-chip control module by means of interrupt transfer in step 205, the method of the present disclosure further includes:

[0110] Step 401, in response to receiving a soft reset request sent by the system-on-chip control module, performing a soft reset on the target subsystem where the logic object under test is located, so that the target subsystem enters the initial functional state.

[0111] Among them, a soft reset means resetting the relevant registers in the target subsystem to the initial state of the functional mode, so that the target subsystem enters the initial functional state. After the system-on-chip control module completes the acquisition of the test completion signal and the compression result and the comparison with the reference result, it can turn off the target subsystem where the logic object under test is located or control the LBIST_EN signal of the logic object under test to change from high level to low level, ending the current logic self-test. Since in the logic self-test mode, the relevant registers are configured to the state in the logic self-test mode and are not applicable to the functional mode, in order to enable the target subsystem to enter the normal working state, it is necessary to reset the relevant registers to the initial state of the functional mode. The relevant registers may include the shift registers of the scan chain in the logic object under test and other registers that may be involved. The specific registers involved in the logic self-test can be set according to actual requirements, and the present disclosure does not make any limitations.

[0112] Step 402, in response to the target subsystem where the logic object under test is located completing the soft reset, returning a third confirmation signal to the system-on-chip control module, where the third confirmation signal is used to notify the system-on-chip control module that the target subsystem has entered the initial functional state.

[0113] Among them, when the target subsystem enters the initial functional state, a third confirmation signal is returned to the system-on-chip control module to notify the system-on-chip control module that the target subsystem has entered the initial functional state and can start normal operation.

[0114] Step 403, in response to receiving a working state request signal sent by the system-on-chip control module in response to the third confirmation signal, returning the current working state information to the system-on-chip control module, so that the system-on-chip control module allocates work tasks for the target subsystem according to the current working state information.

[0115] Among them, after determining that the target subsystem has entered the initial functional state, the system-on-chip control module can allocate corresponding work tasks to the target subsystem according to the current working state of the target subsystem. The current working state information of the target subsystem may include a wake-up state and an idle state, which can be specifically set according to actual requirements.

[0116] After the logic self-test of the logic object to be tested is completed, the present disclosure controls the target subsystem where the logic object to be tested is located to perform a soft reset, ensuring that after the target subsystem is reset to the initial functional state, it then enters the working mode and executes work tasks, thereby ensuring the effective switching between the logic self-test mode and the working mode of the target subsystem, ensuring the normal operation of the target subsystem, and avoiding the occurrence of working failures caused by the configuration of relevant registers of the target subsystem in the logic self-test mode not being suitable for the working mode.

[0117] The digital logic self-test method of the system-on-chip of the present disclosure can accelerate the transmission of the logic self-test compression result of the internal module of the subsystem of the system-on-chip to the system-on-chip control module, so as to quickly compare it with the reference result to obtain a verification result, reducing the time for serial shifting and sending to the advanced peripheral bus through the IJTAG network; and it can also directly implement the comparison of the intermediate compression results corresponding to each logic vector (or test vector), further improving the test efficiency; in addition, it can also support the coexistence of the interrupt transfer mode and the IJTAG network serial shifting transfer mode, improving the flexibility and generality of the test.

[0118] In the present disclosure, each embodiment or each optional example can be implemented separately, or can be implemented in any combination manner without conflict, which can be specifically set according to actual requirements.

[0119] Any digital logic self-test method of the system-on-chip provided by the embodiments of the present disclosure can be executed by any suitable device with data processing capabilities, including but not limited to: terminal devices and servers, etc. Or, any digital logic self-test method of the system-on-chip provided by the embodiments of the present disclosure can be executed by a processor. For example, the processor executes any digital logic self-test method mentioned in the embodiments of the present disclosure by calling the corresponding instructions stored in the memory. This will not be elaborated further below.

[0120] Exemplary device

[0121] Figure 12 It is a schematic structural diagram of a digital logic self-test device of a system-on-chip provided by an exemplary embodiment of the present disclosure. The device of this embodiment can be used to implement the corresponding method embodiment of the present disclosure, such as Figure 12 The shown device includes: a first determination module 501, a first processing module 502, a second processing module 503, a third processing module 504, and a fourth processing module 505.

[0122] The first determination module 501 is configured to determine a logic vector corresponding to a logic object to be tested in a system-on-chip and a target number of the logic vectors; the first processing module 502 is configured to test the logic object to be tested based on the logic vectors determined by the first determination module 501 to obtain a test result of the logic object to be tested; the second processing module 503 is configured to compress the test result obtained by the first processing module 502 to obtain a compression result corresponding to the test result; the third processing module 504 is configured to generate a test completion signal for the logic object to be tested in response to the logic object to be tested completing the test of the target number of logic vectors; the fourth processing module 505 is configured to transmit the test completion signal generated by the third processing module 504 and the compression result to a system-on-chip control module in an interrupt transfer manner.

[0123] In an alternative example, Figure 13 is a schematic structural diagram of the fourth processing module 505 provided by an exemplary embodiment of the present disclosure. In this example, the fourth processing module 505 includes: a first processing unit 5051 and a second processing unit 5052.

[0124] The first processing unit 5051 is configured to write the test completion signal and the compression result into a target register; the second processing unit 5052 is configured to send an interrupt signal to the system-on-chip control module through a bus, so that the system-on-chip control module obtains the test completion signal and the compression result from the target register in response to the interrupt signal.

[0125] Figure 14 is a schematic structural diagram of the first processing unit 5051 provided by an exemplary embodiment of the present disclosure.

[0126] In an alternative example, the first processing unit 5051 includes: a signal response optimization circuit 50511. The signal response optimization circuit 50511 is connected to the target register and is configured to write the test completion signal and the compression result into the target register in a logic self-test mode.

[0127] Figure 15 is a schematic structural diagram of the signal response optimization circuit 50511 provided by an exemplary embodiment of the present disclosure.

[0128] In an alternative example, the signal response optimization circuit 50511 includes: a completion signal response circuit 50511a, a compression result response circuit 50511b, and a capture enable response circuit 50511c.

[0129] A completion signal response circuit 50511a for writing the test completion signal into a first register in the target register; a compressed result response circuit 50511b for writing each bit value included in the compressed result into a second register in the target register in parallel; a capture enable response circuit 50511c for, in response to any one of the logic vectors in the logic vector completing the test on the logic object under test, writing the capture enable signal corresponding to the logic vector into a third register in the target register, so that after the on-chip system control module detects the capture enable signal in the third register, it collects the compressed result corresponding to the logic vector.

[0130] In an alternative example, Figure 16 FIG. 5 is a schematic structural diagram of a fourth processing module 505 provided by another exemplary embodiment of the present disclosure. In this example, the fourth processing module 505 includes: a first determination unit 5051a, a third processing unit 5052a, and a fourth processing unit 5053a.

[0131] The first determination unit 5051a is configured to determine the state of a configured test acceleration enable signal, where the test acceleration enable signal is used to indicate the transmission manner of the test completion signal and the compressed result; the third processing unit 5052a is configured to, in response to the state of the test acceleration enable signal being enabled, transmit the test completion signal and the compressed result to the on-chip system control module through an interrupt transmission manner; the fourth processing unit 5053a, in response to the state of the test acceleration enable signal being not enabled, transmits the test completion signal and the compressed result to the on-chip system control module through an on-line system test logic path.

[0132] In an alternative example, Figure 17 FIG. 13 is a schematic structural diagram of a fourth processing module 505 provided by still another exemplary embodiment of the present disclosure. In this example, the fourth processing module 505 includes: a first determination unit 5051a, a first processing unit 5051, and a fourth processing unit 5053a. Among them, the first processing unit 5051 includes a signal response optimization circuit 50511, and the signal response optimization circuit 50511 includes a completion signal response circuit 50511a, a compressed result response circuit 50511b, and a capture enable response circuit 50511c. The first determination unit 5051a is configured to determine the state of a configured test acceleration enable signal, where the test acceleration enable signal is used to indicate the transmission manner of the test completion signal and the compressed result, and the signal response optimization circuit 50511 is configured to, in response to the state of the test acceleration enable signal being enabled, transmit the test completion signal, the compressed result, and the capture enable signal to corresponding registers.

[0133] Exemplarily, Figure 18It is a schematic structural diagram of a signal response optimization circuit 50511 provided by another exemplary embodiment of the present disclosure. In this example, the signal response optimization circuit 50511 can achieve fast transmission of test completion signals, compression results, and capture enable signals of multiple logic objects to be tested. Based on two logic objects to be tested, for each additional logic object to be tested, one more level of "OR" logic circuit is added. Each level of "OR" logic circuit includes an "OR" logic circuit for OR operation of test completion signals, M "OR" logic circuits for OR operation of each bit value (a total of M bit values) of the compression result, and an "OR" logic circuit for OR operation of capture enable signals, ultimately realizing the OR operation of relevant signals of multiple logic objects to be tested, so that each logic object to be tested can transmit the relevant signals obtained from the test to the corresponding register in the logic self-test mode. Among them, all the "AND" logic circuits and "OR" logic circuits for transmitting test completion signals form a completion signal response circuit, all the "AND" logic circuits and "OR" logic circuits for transmitting compression results form a compression result response circuit, and all the "AND" logic circuits and "OR" logic circuits for transmitting capture enable signals form a capture enable response circuit. The specific transmission principle of each signal can be referred to the foregoing content and will not be elaborated here.

[0134] Exemplarily, Figure 19 It is a schematic structural diagram of a signal response optimization circuit 50511 provided by still another exemplary embodiment of the present disclosure. In this example, it includes three logic objects to be tested. Each logic object to be tested can implement logic self-test through its respective test circuit logic, obtain a test completion signal and a compression result, and obtain a capture enable signal after each logic vector is completed. It is transmitted to the corresponding register through the signal response optimization circuit 50511, and an interrupt signal is sent to the on-chip system control module, enabling the on-chip system control module to quickly obtain the data in the corresponding register.

[0135] Figure 20 It is a schematic structural diagram of a digital logic self-test device of an on-chip system provided by another exemplary embodiment of the present disclosure.

[0136] In an optional example, the device of the present disclosure further includes: a first control module 601, a first confirmation module 602, a second control module 603, and a third control module 604.

[0137] The first control module 601 is configured to control the target subsystem where the logic object to be tested is located to enter the idle state in response to receiving the request to enter the idle state sent by the on-chip system control module; the first confirmation module 602 is configured to return a first confirmation signal to the on-chip system control module, and the first confirmation signal is used to notify the on-chip system control module that the target subsystem has entered the idle state; the second control module 603 is configured to control the logic object to be tested to switch from the functional mode to the logic self-test mode in response to receiving the logic self-test mode signal sent by the on-chip system control module in response to the first confirmation signal, and return a second confirmation signal to the on-chip system control module, and the second confirmation signal is used to notify the on-chip system control module that the logic object to be tested has switched to the logic self-test mode; the third control module 604 is configured to write the initial logic vector and the target quantity of the logic vector into the corresponding registers respectively in response to receiving the initial logic vector writing command sent by the on-chip system control module in response to the second confirmation signal, and the initial logic vector is used to generate the target quantity of logic vectors.

[0138] In an alternative example, the device of the present disclosure further includes: a reset module 701, a second confirmation module 702, and a first return module 703.

[0139] The reset module 701 is configured to perform a soft reset on the target subsystem where the logic object to be tested is located in response to receiving the soft reset request sent by the on-chip system control module, so that the target subsystem enters the initial functional state; the second confirmation module 702 is configured to return a third confirmation signal to the on-chip system control module in response to the target subsystem where the logic object to be tested completes the soft reset, and the third confirmation signal is used to notify the on-chip system control module that the target subsystem has entered the initial functional state; the first return module 703 is configured to return the current working state information to the on-chip system control module in response to receiving the working state request signal sent by the on-chip system control module in response to the third confirmation signal, so that the on-chip system control module allocates a work task for the target subsystem according to the current working state information.

[0140] In an alternative example, Figure 21It is a timing diagram of the logic self-test provided by an exemplary embodiment of the present disclosure. Among them, 801 is the first capture enable signal (Capture_en), which is transmitted to the on-chip system control module to enable the on-chip system control module to collect the compression result of the currently completed logic vector. 802 - 804 are all capture enable signals, and the specific principle will not be elaborated one by one. 805 is the test completion signal (LBIST_DONE) after the last capture enable signal is completed, which is used to notify the on-chip system control module to collect the compression result. 806 means that after the last capture enable signal is completed, the compression result (LBIST_MISR) is stable. After the test completion signal (LBIST_DONE) and the compression result (LBIST_MISR) are transmitted and authenticated to the on-chip system control module through the IJTAG network, the on-chip system control module issues a command to the target subsystem through the IJTAG network to control the test completion signal (LBIST_DONE) to change from high level to low level. 807 is that after the on-chip system control module completes the collection and comparison of the test completion signal (LBIST_DONE) and the compression result (LBIST_MISR) through the interrupt transfer method, it directly closes the target subsystem through the interrupt or changes the LBIST_EN of the logic object under test from high level to low level to end the logic self-test process. 808 is that after the on-chip system control module completes the collection and comparison of the test completion signal (LBIST_DONE) and the compression result (LBIST_MISR) through the IJTAG network, it issues a command to the target subsystem through the IJTAG network to control the LBIST_EN to change from high level to low level. Since the timing diagram includes the timings of both the interrupt transfer method and the IJTAG network transfer method, the timings of LBIST_DONE and LBIST_EN are distinguished by solid lines and dashed lines, such as 807 and 808. 809 is the bus clock (APB_CLK), which is used for the synchronization of the interaction communication between the target subsystem and the on-chip system control module. In this example, the bus is the APB bus.

[0141] Each embodiment or each optional example in the present disclosure can be implemented independently, or can be combined and implemented in any combination manner without conflict, and can be specifically set according to actual needs.

[0142] Exemplary electronic device

[0143] The embodiment of the present disclosure also provides an electronic device, including: a memory for storing a computer program;

[0144] a processor for executing the computer program stored in the memory, and when the computer program is executed, implementing the digital logic self-test method of the on-chip system described in any one of the above embodiments of the present disclosure.

[0145] Figure 22 It is a schematic structural diagram of an application embodiment of the electronic device of the present disclosure. In this embodiment, the electronic device 10 includes one or more processors 11 and a memory 12.

[0146] The processor 11 may be a central processing unit (CPU) or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0147] The memory 12 may include one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 11 may run the program instructions to implement the methods of the various embodiments of the present disclosure described above and / or other desired functions. Various contents such as input signals, signal components, noise components, etc. may also be stored in the computer-readable storage medium.

[0148] In one example, the electronic device 10 may further include: an input device 13 and an output device 14, and these components are interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0149] For example, the input device 13 may be the above-mentioned microphone or microphone array for capturing the input signal of the sound source.

[0150] In addition, the input device 13 may further include, for example, a keyboard, a mouse, and so on.

[0151] The output device 14 may output various information to the outside, including the determined distance information, direction information, etc. The output device 14 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0152] Of course, for simplicity, Figure 22 only some of the components related to the present disclosure in the electronic device 10 are shown, and components such as buses, input / output interfaces, etc. are omitted. In addition, according to specific application situations, the electronic device 10 may further include any other appropriate components.

[0153] In an alternative example, Figure 23It is a schematic structural diagram of another application embodiment of the electronic device of the present disclosure. In this embodiment, the electronic device 10 includes the digital logic self-test device of the system-on-chip described in any of the above embodiments.

[0154] Exemplary computer program product and computer-readable storage medium

[0155] In addition to the above methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions that, when run by a processor, cause the processor to execute the steps in the methods according to various embodiments of the present disclosure described in the "Exemplary Methods" section above of this specification.

[0156] The computer program product may be written in any combination of one or more programming languages for programming code to perform the operations of the embodiments of the present disclosure. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, executed as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0157] Furthermore, an embodiment of the present disclosure may also be a computer-readable storage medium, on which computer program instructions are stored, and the computer program instructions, when run by a processor, cause the processor to execute the steps in the methods according to various embodiments of the present disclosure described in the "Exemplary Methods" section above of this specification.

[0158] The computer-readable storage medium may adopt any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0159] The basic principles of the present disclosure have been described in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present disclosure. Additionally, the specific details disclosed above are only for illustrative and facilitating understanding purposes, rather than limitations. The above details do not limit the present disclosure to necessarily adopting the above specific details for implementation.

[0160] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For system embodiments, since they basically correspond to method embodiments, they are described relatively simply. For relevant parts, reference can be made to the corresponding descriptions in the method embodiments.

[0161] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present disclosure are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The word "or" and "and" used herein refer to the word "and / or" and can be used interchangeably with each other, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to" and can be used interchangeably with each other.

[0162] The methods and apparatuses of the present disclosure can be implemented in many ways. For example, the methods and apparatuses of the present disclosure can be implemented through software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of the steps for the method is only for illustration purposes. The steps of the method of the present disclosure are not limited to the above specifically described order, unless otherwise specifically stated in other ways. Additionally, in some embodiments, the present disclosure can also be implemented as a program recorded in a recording medium, and these programs include machine-readable instructions for implementing the methods according to the present disclosure. Therefore, the present disclosure also covers the recording medium storing the programs for executing the methods according to the present disclosure.

[0163] It should also be noted that in the apparatuses, equipment, and methods of the present disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present disclosure.

[0164] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0165] The above description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize some of their variations, modifications, alterations, additions, and subcombinations.

Claims

1. A digital logic self - test method for a system - on - chip, comprising: Determine the logic vectors corresponding to the logic objects to be tested in the system - on - chip and the target quantity of the logic vectors; Test the logic objects to be tested based on the logic vectors to obtain the test results of the logic objects to be tested; Compress the test results to obtain the compressed results corresponding to the test results; In response to the logic objects to be tested completing the logic vector tests of the target quantity, generate a test completion signal for the logic objects to be tested; Transmit the test completion signal and the compressed results to the system - on - chip control module by means of interrupt transfer; Wherein, before determining the logic vectors corresponding to the logic objects to be tested in the system - on - chip and the target quantity of the logic vectors, it further includes: In response to receiving a request to enter the idle state sent by the system - on - chip control module, control the target subsystem where the logic object to be tested is located to enter the idle state; Return a first confirmation signal to the system - on - chip control module, and the first confirmation signal is used to notify the system - on - chip control module that the target subsystem has entered the idle state; In response to receiving a logic self - test mode signal sent by the system - on - chip control module in response to the first confirmation signal, control the logic object to be tested to switch from the functional mode to the logic self - test mode, and return a second confirmation signal to the system - on - chip control module, and the second confirmation signal is used to notify the system - on - chip control module that the logic object to be tested has switched to the logic self - test mode; In response to receiving an initial logic vector writing command sent by the system - on - chip control module in response to the second confirmation signal, write the initial logic vector and the target quantity of the logic vectors into the corresponding registers respectively, and the initial logic vector is used to generate the target quantity of logic vectors.

2. The method according to claim 1, wherein, The transmitting the test completion signal and the compressed results to the system - on - chip control module by means of interrupt transfer includes: Write the test completion signal and the compressed results into the target register; Send an interrupt signal to the system - on - chip control module through the bus, so that the system - on - chip control module, in response to the interrupt signal, obtains the test completion signal and the compressed results from the target register.

3. The method according to claim 2, wherein, The writing the test completion signal and the compressed results into the target register includes: Write the test completion signal into the first register in the target register; Write each bit value included in the compressed results into the second register in the target register in parallel.

4. According to the method of claim 1, the testing the logic objects to be tested based on the logic vectors includes: In response to any one of the logic vectors in the logic vectors completing the test of the logic object to be tested, transmit the capture enable signal corresponding to the logic vector to the system - on - chip control module by means of interrupt transfer, so that the system - on - chip control module, after receiving the capture enable signal, acquires the compressed results of the test results corresponding to the logic vector.

5. The method according to claim 1, wherein Transmitting the test completion signal and the compression result to the on-chip system control module through the interrupt transmission method includes: Determining the state of the configured test acceleration enable signal, where the test acceleration enable signal is used to indicate the transmission method of the test completion signal and the compression result; In response to the state of the test acceleration enable signal being enabled, transmitting the test completion signal and the compression result to the on-chip system control module through the interrupt transmission method; The method further includes: In response to the state of the test acceleration enable signal being disabled, transmitting the test completion signal and the compression result to the on-chip system control module through the online system test logic path.

6. The method according to claim 1, wherein, After transmitting the test completion signal and the compression result to the on-chip system control module through the interrupt transmission method, the method further includes: In response to receiving a soft reset request sent by the on-chip system control module, performing a soft reset on the target subsystem where the logic object under test is located, so that the target subsystem enters the initial functional state; In response to the target subsystem where the logic object under test is located completing the soft reset, returning a third confirmation signal to the on-chip system control module, where the third confirmation signal is used to notify the on-chip system control module that the target subsystem has entered the initial functional state; In response to receiving a working state request signal sent by the on-chip system control module in response to the third confirmation signal, returning the current working state information to the on-chip system control module, so that the on-chip system control module allocates a work task to the target subsystem according to the current working state information.

7. A digital logic self-test device for an on-chip system, including: A first determination module, configured to determine a logic vector corresponding to the test of the logic object under test in the on-chip system and the target quantity of the logic vector; A first processing module, configured to test the logic object under test based on the logic vector to obtain a test result of the logic object under test; A second processing module, configured to compress the test result to obtain a compression result corresponding to the test result; A third processing module, configured to generate a test completion signal of the logic object under test in response to the logic object under test completing the test of the target quantity of logic vectors; A fourth processing module, configured to transmit the test completion signal and the compression result to the on-chip system control module through the interrupt transmission method; It further includes: A first control module, configured to control the target subsystem where the logic object under test is located to enter the idle state in response to receiving an enter idle state request sent by the on-chip system control module; A first confirmation module, configured to return a first confirmation signal to the on-chip system control module, where the first confirmation signal is used to notify the on-chip system control module that the target subsystem has entered the idle state; A second control module, configured to, in response to receiving a logic self-test mode signal sent by the system-on-chip control module in response to the first confirmation signal, control the logic object under test to switch from a functional mode to a logic self-test mode, and return a second confirmation signal to the system-on-chip control module, where the second confirmation signal is used to notify the system-on-chip control module that the logic object under test has switched to the logic self-test mode; A third control module, configured to, in response to receiving an initial logic vector writing command sent by the system-on-chip control module in response to the second confirmation signal, write the initial logic vector and the target quantity of the logic vectors into corresponding registers respectively, where the initial logic vector is used to generate the target quantity of logic vectors.

8. The apparatus according to claim 7, wherein The fourth processing module includes: A first processing unit, configured to write the test completion signal and the compression result into a target register; A second processing unit, configured to send an interrupt signal to the system-on-chip control module through a bus, so that the system-on-chip control module, in response to the interrupt signal, obtains the test completion signal and the compression result from the target register.

9. The device according to claim 8, wherein The first processing unit includes: A signal response optimization circuit, connected to the target register, configured to write the test completion signal and the compression result into the target register in a logic self-test mode.

10. The device according to claim 9, wherein The signal response optimization circuit includes: A completion signal response circuit, configured to write the test completion signal into a first register in the target register; A compression result response circuit, configured to write each bit value included in the compression result into a second register in the target register in parallel; A capture enable response circuit, configured to, in response to any one of the logic vectors in the logic vectors completing the test of the logic object under test, write a capture enable signal corresponding to the logic vector into a third register in the target register, so that the system-on-chip control module, after detecting the capture enable signal in the third register, acquires the compression result corresponding to the logic vector.

11. A computer-readable storage medium, where the storage medium stores a computer program, and the computer program is used to execute the digital logic self-test method of the system-on-chip according to any one of claims 1-6 above.

12. An electronic device, where the electronic device includes: A processor; A memory for storing executable instructions of the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the digital logic self-test method of the system-on-chip according to any one of claims 1-6 above; Or, The electronic device includes: The digital logic self-test device of the system-on-chip according to any one of claims 7-10 above.

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