Pocket-structured Si / Ge heterojunction gate-all-around tunneling field-effect transistor and preparation method thereof

Abstract

The present invention discloses a Si / Ge heterojunction surround-gate tunneling field-effect transistor with a pocket structure and a method for preparing the same. The transistor comprises a semiconductor Si substrate, on which is provided a source region of a heavily P-type semiconductor Ge, a heavily N-type semiconductor Si drain region, and an STI oxide layer disposed between the source and drain regions. A channel region of a lightly N-type semiconductor Si and a pocket region of a heavily N-type semiconductor Si are disposed between the source and drain regions. A semiconductor Ge protrusion is embedded in the pocket region on the side of the source region, forming a Ge / Si heterojunction structure. A heterogeneous gate electrode is disposed between the channel region and the pocket region, with sidewall regions disposed on the side of the heterogeneous gate electrode. A gate dielectric layer is disposed on the surfaces of the channel region and the pocket region. The transistor has a higher on-state current, a steeper subthreshold swing slope, stronger gate control capability, and excellent radio frequency characteristics. It can also suppress bipolar current and improve the subthreshold characteristics of the tunneling field-effect transistor.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a Si / Ge heterojunction gate-all-around tunneling field-effect transistor with a pocket structure and a preparation method thereof. Background Art

[0002] With the rapid advancement of semiconductor device technology, power consumption is a major obstacle to scaling semiconductor devices to the nanometer scale in accordance with Moore's Law. The power consumption of a single device does not linearly correlate with its size; rather, the rate of power reduction is smaller than the rate of size reduction. Therefore, the power consumption per unit area of ​​an integrated circuit actually increases as the device feature size shrinks. To address this issue, reducing the supply voltage is an effective way to reduce power consumption. However, the subthreshold swing of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) at room temperature is limited to 60mV / decade. This limitation prevents the supply voltage from decreasing at the same rate as the physical size of semiconductor devices. Furthermore, as devices scale down, they experience problems such as insufficient gate control capability and degradation of subthreshold performance.

[0003] Tunneling field-effect transistors (TFETs) are based on the quantum mechanical principle of band-to-band tunneling. This operating mechanism is unaffected by temperature and the Boltzmann distribution of carriers, and can overcome the subthreshold swing limitations of MOSFET devices. However, they still face challenges such as low on-state current, bipolar current flow, and poor RF characteristics.

[0004] The existence of these issues has seriously hindered further device scaling, which is clearly incompatible with the low-power devices required by the modern semiconductor industry. The industry has long pursued the goal of ensuring a steep subthreshold slope while also maintaining high on-state current, stronger gate control capability, increasing device transconductance, reducing parasitic capacitance, enhancing device RF characteristics, increasing the gain-bandwidth product, and the product of the cutoff frequency and transconductance frequency, while suppressing the generation of bipolar currents and improving device off-state performance. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a pocket-structured Si / Ge heterojunction gate-all-around tunneling field-effect transistor and a preparation method thereof. The transistor has a higher on-state current, a steeper subthreshold swing slope, a stronger gate control capability, and excellent radio frequency characteristics. At the same time, it can suppress bipolar current and improve the subthreshold characteristics of the tunneling field-effect transistor.

[0006] To achieve the above object, the present invention is implemented by adopting the following technical solutions:

[0007] A Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure, the transistor comprising a semiconductor Si substrate, on which a source region of a P-type heavily doped semiconductor Ge, a drain region of an N-type heavily doped semiconductor Si, and an STI oxide layer disposed between the source and drain regions are provided, the STI oxide layer being connected to the source and drain regions, respectively; a channel region of an N-type lightly doped semiconductor Si and a pocket region of an N-type heavily doped semiconductor Si are disposed between the source and drain regions, a semiconductor Ge protrusion embedded in the pocket region is disposed on the side of the source region, the embedded protrusion forming a Ge / Si heterojunction structure; a heterogeneous gate electrode is disposed between the channel region and the pocket region, a sidewall region is disposed on the side of the heterogeneous gate electrode, and a gate dielectric layer is disposed on the surfaces of the channel region and the pocket region.

[0008] Optionally, the doping element for P-type doping is B.

[0009] Optionally, the N-type doping element includes As or Sb.

[0010] Optionally, the source region P-type heavily doped concentration is 1×10 20 cm -3 The doping concentration of the N-type heavily doped drain region is 1×10 18 cm -3 ; The doping concentration of the N-type lightly doped channel region is 1×10 15 ~2×10 16 cm -3 ; The doping concentration of N-type heavy doping in the Pocket area is 10 18 cm -3 ~10 19 cm -3 .

[0011] Optionally, the heterogeneous gate electrode is composed of two or three conductive metals with different work functions, the work function of the metal materials used for the heterogeneous gate electrode gradually increases from the source region to the drain region, and the difference between the work functions of different metal materials must not be less than 0.1 eV.

[0012] Optionally, when the heterogeneous gate electrode is composed of two conductive metals with different work functions, the length of the conductive metal material close to the source region is 1 / 3 of the thickness of the heterogeneous gate electrode, and the length of the conductive metal material close to the drain region is 2 / 3 of the thickness of the heterogeneous gate electrode; when the heterogeneous gate electrode is composed of three conductive metals with different work functions, the thicknesses of the three conductive metal materials are the same, which are each 1 / 3 of the thickness of the heterogeneous gate electrode.

[0013] Optionally, the source region side protrusion is embedded in the Pocket region to a depth of 8 to 10 nm, and the protrusion embedded in the Pocket region is 3 to 5 nm away from the gate dielectric layer.

[0014] Optionally, the gate dielectric layer is made of a high dielectric constant material with a dielectric constant of 20 to 100, and the gate dielectric layer includes HfO2 with a thickness of 2 nm or ZrO2 with a thickness of 2 to 5 nm.

[0015] Optionally, the sidewall region is a stack of silicon oxide and silicon nitride, and is arranged on both sides or all around the heterogeneous gate electrode; when the sidewall region is arranged on both sides of the heterogeneous gate electrode, the thickness of the sidewall region is 80Å~100Å, and when the sidewall region is arranged all around the heterogeneous gate electrode, the thickness of the sidewall region is 50Å~60Å.

[0016] A method for preparing a Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure, comprising:

[0017] A groove-shaped Pocket structure is etched on one end of a semiconductor Si substrate using etching technology, and Ge material is deposited in the groove and on one side of the groove;

[0018] A C4F8 layer is formed on a semiconductor Si substrate using a deposition technique, and the C4F8 layer in the channel region and the pocket region is removed using a mask exposure technique;

[0019] Under the action of the resist C4F8, reactive ion etching is used to etch out the suspended area;

[0020] A layer of STI oxide is formed on the etched semiconductor Si substrate through an HDP filling process;

[0021] forming a gate dielectric layer on the surface of the suspended region by oxidation or deposition;

[0022] Using an ion implantation process, a P-type heavily doped source region doped with B is formed at one end of a semiconductor Si substrate where Ge material is deposited, and an N-type heavily doped drain region doped with As or Sb is formed at the other end. From the source region to the drain region, an N-type heavily doped pocket region doped with As or Sb and an N-type lightly doped channel region doped with As or Sb are formed in sequence;

[0023] Using deposition and etching processes, a metal material with a work function that increases gradually from the source region to the drain region is deposited on the gate dielectric layer. The deposited metal material cooperates with the gate dielectric layer to form a heterogeneous gate electrode of the device.

[0024] By using deposition and etching processes, sidewall regions are formed on both sides or around the heterogeneous gate electrode.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The present invention provides a Si / Ge heterojunction gate-all-around tunneling field-effect transistor with a pocket structure and a preparation method thereof. A recessed pocket region is formed in the region of the channel region near the source region. The protrusion and the source region are made of germanium material, which has a narrow bandgap and a small carrier mass, thereby increasing the tunneling probability. At the same time, the introduction of the recessed pocket structure reduces the tunneling barrier and tunneling distance, achieving a steeper tunneling junction, reducing the generation of interface traps and gate leakage, reducing device power consumption, and improving the device's radio frequency characteristics.

[0027] The present invention uses a high dielectric constant material as the gate dielectric layer. The thicker the gate dielectric layer, the smaller the probability of electron tunneling. The larger the dielectric constant of the gate dielectric layer material, the stronger the gate control ability.

[0028] The present invention adopts a gate dielectric layer to wrap the channel region and the pocket region. The gate structure has a stronger gate control capability, and obtains better driving capability, subthreshold characteristics and device radio frequency characteristics.

[0029] The heterogeneous gate electrode material of the present invention uses two or three metals with different work functions. Since the on-state characteristics of the tunneling field-effect transistor are determined by the material on the side close to the source region, while the off-state characteristics and bipolar characteristics are determined by the material on the side close to the drain region, the tunneling band structure at the source-channel is changed by using heterogeneous gate electrode metal materials with different work functions in different regions. The low-work-function metal material is used close to the source region to reduce the tunneling distance, thereby improving the on-state current, subthreshold characteristics, and radio frequency characteristics. The high-work-function metal material is used close to the drain region to suppress the generation of bipolar current.

[0030] When more than 50% of the gate dielectric layer is not wrapped by the heterogeneous gate electrode, the gate control capability is stronger, and the radio frequency parameters such as gain bandwidth, cutoff frequency and transconductance frequency product are more superior; when not less than 50% of the gate dielectric layer is wrapped by the heterogeneous gate electrode, the radio frequency characteristics are even better.

[0031] The STI oxide of the present invention is used to isolate the silicon and avoid the generation of sidewall leakage current of the device;

[0032] The gate of the present invention has sidewalls on both sides or around it, which are used to protect the gate, separate the source and drain ion implantation areas, and prevent the source and drain penetration problem from occurring. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 FIG2 is a schematic structural diagram of a Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure according to an embodiment of the present invention;

[0034] Figure 2 Shown Figure 1 Schematic cross-section diagram;

[0035] Figure 3 The present invention is shown Figure 1 Schematic diagram of the cross section of the middle groove pocket area;

[0036] Figure 4 Shown is a process flow chart of the present invention.

[0037] In the figure, 101 is a semiconductor Si substrate; 102 is an STI oxide layer; 103 is a channel region; 1031 is a pocket region; 104 is a drain region; 105 is a gate dielectric layer; 106 is a source region; 107 is a heterogeneous gate electrode; and 108 is a sidewall region. DETAILED DESCRIPTION

[0038] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0039] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0040] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0041] Example 1

[0042] like Figure 1 and Figure 4As shown, a Si / Ge heterojunction gate-all-around tunneling field effect transistor with a pocket structure comprises a semiconductor Si substrate 101 on which a doping element B with a doping concentration of 1×10 20 cm -3 The source region 106 of the P-type heavily doped semiconductor Ge is doped with As at a concentration of 1×10 18 cm -3 The drain region 104 of the N-type heavily doped semiconductor Si and the STI oxide layer 102 provided between the source region 106 and the drain region 104 , the STI oxide layer 102 is connected to the source region 106 and the drain region 104 respectively, and the source region 106 and the drain region 104 are higher than the STI oxide layer 102 .

[0043] There is a doping element between the source region 106 and the drain region 104, which is As with a doping concentration of 1×10 15 cm -3 The channel region 103 of the N-type lightly doped semiconductor Si is doped with As at a concentration of 10 18 cm -3 The pocket region 1031 of the N-type heavily doped semiconductor Si is connected to the source region 106, and the channel region 103 is connected to the drain region 104. A semiconductor Ge protrusion embedded in the pocket region 1031 with an embedding depth of 8 nm is provided on the side of the source region 106, and the embedded protrusion forms a Ge / Si heterojunction structure.

[0044] A heterogeneous gate electrode 107 is provided between the channel region 103 and the pocket region 1031 . The lower end of the heterogeneous gate electrode 107 is connected to the STI oxide layer 102 . The heterogeneous gate electrode 107 is composed of two conductive metals with different work functions, namely aluminum and copper. The work function of the metal material used for the heterogeneous gate electrode 107 gradually increases from the source region 106 to the drain region 104 , and the difference in work function between different metal materials must not be less than 0.1 eV. The thickness of the conductive metal material near the source region 106 is 1 / 3 of the thickness of the heterogeneous gate electrode 107 , and the length of the conductive metal material near the drain region 104 is 2 / 3 of the thickness of the heterogeneous gate electrode 107 .

[0045] Sidewall spacers 108 are provided on both sides of the heterogeneous gate electrode 107. The sidewall spacers are composed of a stack of silicon oxide and silicon nitride, with the silicon nitride layer provided on the silicon oxide layer. The thickness of the sidewall spacers is 80Å~100Å. A gate dielectric layer 105 is provided between the sidewall spacers 108 and the source region 106 and the drain region 104, respectively. The gate dielectric layer 105 covers the surface of the channel region 103 and the pocket region. Less than 50% of the area of ​​the channel region 103 and the pocket region 1031 is covered by the gate dielectric layer 105. The sidewall spacers 108 are connected to the channel region 103, the pocket region 1031, the STI oxide layer 102 and the gate dielectric layer 105. The gate dielectric layer 105 is 3nm away from the semiconductor Ge protrusion. The gate dielectric layer 105 is made of a high dielectric constant material with a dielectric constant of 20~100. The gate dielectric layer 105 is HfO2 with a thickness of 2nm.

[0046] Example 2

[0047] like Figure 1 and Figure 4 As shown, a Si / Ge heterojunction gate-all-around tunneling field effect transistor with a pocket structure comprises a semiconductor Si substrate 101 on which a doping element B with a doping concentration of 1×10 20 cm -3 The source region 106 of the P-type heavily doped semiconductor Ge is doped with Sb at a concentration of 1×10 18 cm -3 The drain region 104 of the N-type heavily doped semiconductor Si and the STI oxide layer 102 provided between the source region 106 and the drain region 104 , the STI oxide layer 102 is connected to the source region 106 and the drain region 104 respectively, and the source region 106 and the drain region 104 are higher than the STI oxide layer 102 .

[0048] The doping element is Sb with a doping concentration of 2×10 16 cm -3 The channel region 103 of the N-type lightly doped semiconductor Si is doped with Sb at a concentration of 10 19 cm -3 The pocket region 1031 of the N-type heavily doped semiconductor Si is connected to the source region 106, and the channel region 103 is connected to the drain region 104. A semiconductor Ge protrusion embedded in the pocket region 1031 with an embedding depth of 10 nm is provided on the side of the source region 106, and the embedded protrusion forms a Ge / Si heterojunction structure.

[0049] A heterogeneous gate electrode 107 is provided between the channel region 103 and the pocket region 1031 . The lower end of the heterogeneous gate electrode 107 is connected to the STI oxide layer 102 . The heterogeneous gate electrode 107 is composed of three conductive metals with different work functions: aluminum, copper, and beryllium. The work function of the metal materials used in the heterogeneous gate electrode 107 gradually increases from the source region 106 to the drain region 104 , and the difference in work function between different metal materials must not be less than 0.1 eV. The three conductive metal materials have the same length, each being 1 / 3 of the length of the heterogeneous gate electrode 107 .

[0050] A spacer region 108 is provided around the heterogeneous gate electrode 107. The spacer region is a stack of silicon oxide and silicon nitride, with the silicon nitride layer provided on the silicon oxide layer. The thickness of the spacer region is 50Å~60Å. A gate dielectric layer 105 is provided between the spacer region 108 and the source region 106 and the drain region 104 respectively. The gate dielectric layer 105 is connected to the channel region 103 and the pocket region 1031. More than 50% of the area of ​​the channel region 103 and the pocket region 1031 is covered by the gate dielectric layer 105. The spacer region 108 is connected to the channel region 103, the pocket region 1031, the STI oxide layer 102 and the gate dielectric layer 105. The gate dielectric layer 105 is 5nm away from the semiconductor Ge protrusion. The gate dielectric layer 105 is made of a high dielectric constant material with a dielectric constant of 20~100. The gate dielectric layer 105 is ZrO2 with a thickness of 2~5nm.

[0051] Example 3

[0052] like Figures 1 to 4 As shown, based on the Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure described in Example 1 and Example 2, this embodiment provides a method for preparing a Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure, comprising the following steps:

[0053] S1, using etching technology to etch a groove-shaped Pocket structure on one end of the semiconductor Si substrate, and depositing Ge material in the groove and on one side of the groove;

[0054] S2, using a deposition technique to generate a C4F8 layer on a semiconductor Si substrate, and using a mask exposure technique to remove the C4F8 layer in the channel region and the pocket region;

[0055] S3, under the action of the resist C4F8, using reactive ion etching to etch out the suspended area;

[0056] S4, forming a layer of STI oxide on the etched semiconductor Si substrate through an HDP filling process to isolate the semiconductor Si substrate from the silicon and prevent sidewall leakage current of the device;

[0057] S5, forming a gate dielectric layer on the surface of the suspended region by oxidation or deposition;

[0058] S6, using an ion implantation process, forming a P-type heavily doped source region doped with B at one end of a Ge material deposited on a semiconductor Si substrate, and forming an N-type heavily doped drain region doped with As or Sb at the other end, and sequentially forming an N-type heavily doped pocket region doped with As or Sb and an N-type lightly doped channel region doped with As or Sb from the source region to the drain region;

[0059] S7, using deposition and etching processes, depositing metal materials with increasing work functions from the source region to the drain region on the gate dielectric layer, depositing metal aluminum on the side close to the source region, and depositing metal copper on the side close to the drain region. The deposited metal materials cooperate with the gate dielectric layer to form a heterogeneous gate electrode of the device;

[0060] S8, using deposition and etching processes to deposit a layer of silicon oxide and silicon nitride on the surface of the heterogeneous gate electrode, and using an etching process to remove the silicon oxide and silicon nitride on the top of the gate structure to form sidewalls on both sides of the gate.

[0061] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure, characterized by: The transistor includes a semiconductor Si substrate, on which a source region of a P-type heavily doped semiconductor Ge, a drain region of an N-type heavily doped semiconductor Si, and an STI oxide layer provided between the source region and the drain region are provided, wherein the STI oxide layer is connected to the source region and the drain region respectively; a channel region of an N-type lightly doped semiconductor Si and a pocket region of an N-type heavily doped semiconductor Si are provided between the source region and the drain region, a semiconductor Ge protrusion embedded in the pocket region is provided on the side of the source region, and the embedded protrusion forms a Ge / Si heterojunction structure; a heterogeneous gate electrode is provided between the channel region and the pocket region, a sidewall region is provided on the side of the heterogeneous gate electrode, and a gate dielectric layer is provided on the surface of the channel region and the pocket region; the heterogeneous gate electrode is composed of two or three conductive metals with different work functions, the work function of the metal material used for the heterogeneous gate electrode gradually increases from the source region to the drain region, and the work function difference between the different metal materials shall not be less than 0.1 eV.

2. The Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure according to claim 1, characterized in that: The doping element for P-type doping is B.

3. The Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure according to claim 2, characterized in that: The doping element for N-type doping includes As or Sb.

4. The Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure according to claim 3, characterized in that: The doping concentration of the heavily P-type doped source region is 1×10 20 cm -3 The doping concentration of the N-type heavily doped drain region is 1×10 18 cm -3 ; The doping concentration of the N-type lightly doped channel region is 1×10 15 ~2×10 16 cm -3 ; The doping concentration of N-type heavy doping in the Pocket area is 10 18 cm -3 ~10 19 cm -3 .

5. The Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure according to claim 1, characterized in that: When the heterogeneous gate electrode is composed of two conductive metals with different work functions, the length of the conductive metal material close to the source region is 1 / 3 of the thickness of the heterogeneous gate electrode, and the length of the conductive metal material close to the drain region is 2 / 3 of the thickness of the heterogeneous gate electrode; when the heterogeneous gate electrode is composed of three conductive metals with different work functions, the thickness of the three conductive metal materials is the same, which is 1 / 3 of the thickness of the heterogeneous gate electrode respectively.

6. The Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure according to claim 1, characterized in that: The side protrusions of the source region are embedded in the Pocket region to a depth of 8 to 10 nm, and the protrusions embedded in the Pocket region are 3 to 5 nm away from the gate dielectric layer.

7. The Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure according to claim 1, characterized in that: The gate dielectric layer adopts a high dielectric constant material with a dielectric constant of 20 to 100, and the gate dielectric layer includes HfO2 with a thickness of 2 nm or ZrO2 with a thickness of 2 to 5 nm.

8. The Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure according to claim 1, characterized in that: The sidewall region is a stack of silicon oxide and silicon nitride, and is arranged on both sides or around the heterogeneous gate electrode; when the sidewall region is arranged on both sides of the heterogeneous gate electrode, the thickness of the sidewall region is 80Å~100Å, and when the sidewall region is arranged around the heterogeneous gate electrode, the thickness of the sidewall region is 50Å~60Å.

9. A method for preparing a Si / Ge heterojunction all-around-gate tunneling field-effect transistor with a pocket structure according to any one of claims 1 to 8, characterized in that: include: A groove-shaped Pocket structure is etched on one end of a semiconductor Si substrate using etching technology, and Ge material is deposited in the groove and on one side of the groove; A C4F8 layer is formed on a semiconductor Si substrate using a deposition technique, and the C4F8 layer in the channel region and the pocket region is removed using a mask exposure technique; Under the action of the resist C4F8, reactive ion etching is used to etch out the suspended area; A layer of STI oxide is formed on the etched semiconductor Si substrate through an HDP filling process; forming a gate dielectric layer on the surface of the suspended region by oxidation or deposition; Using an ion implantation process, a P-type heavily doped source region doped with B is formed at one end of a semiconductor Si substrate where Ge material is deposited, and an N-type heavily doped drain region doped with As or Sb is formed at the other end. From the source region to the drain region, an N-type heavily doped pocket region doped with As or Sb and an N-type lightly doped channel region doped with As or Sb are formed in sequence; Using deposition and etching processes, a metal material with a work function that increases gradually from the source region to the drain region is deposited on the gate dielectric layer. The deposited metal material cooperates with the gate dielectric layer to form a heterogeneous gate electrode of the device. By using deposition and etching processes, sidewall regions are formed on both sides or around the heterogeneous gate electrode.

Images