A termination structure of a shield gate power MOSFET and a manufacturing method thereof

Abstract

The application relates to the technical field of semiconductors, and provides a terminal structure of a shield gate power MOSFET and a manufacturing method thereof. The terminal structure of the shield gate power MOSFET contains a P well region and a region of an N+ source region, and an avalanche tolerance enhancement structure is added on the basis of a conventional shield gate power MOSFET dicing groove region. The avalanche tolerance enhancement structure comprises additional groove field oxide and additional groove polysilicon. By adding an additional terminal groove structure in the dicing groove of a conventional shield gate power MOSFET wafer, the current intensity and the current density of the total avalanche hole current of the source region are reduced, the anti-avalanche breakdown characteristic of the device is improved, the avalanche tolerance EAS is increased, and therefore the reliability of the device is improved; one N+ photoetching is reduced, and the chip circulation time and the chip manufacturing cost are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a terminal structure of a shield gate power MOSFET and a manufacturing method thereof. BACKGROUND

[0002] The most important research direction of power MOSFET is to continuously reduce power consumption (including on-state loss and switching loss) and improve the robustness of device dynamic performance. Today, power trench MOSFET devices have been applied in most power application circuits, and the characteristics of the devices are continuously approaching the one-dimensional limit of silicon material (which represents the theoretical relationship between the on-state resistance and the breakdown voltage of the drift region of the device). The RESURF technology (Reduced Surface Field) can make the power trench MOSFET device with a withstand voltage of 600V exceed the one-dimensional limit of silicon material. Similarly, according to the working principle of RESURF, the industry also proposes a split gate (shield gate) trench (Split-Gate Trench) MOSFET device structure, which can break the one-dimensional limit of silicon material in the low-voltage and medium-voltage (20V-300V) range, has lower on-state loss, and has superior device performance.

[0003] The method for increasing the avalanche tolerance of a conventional shield gate power MOSFET is to provide a path for avalanche hole current by setting some regions (i.e. dummy structure) with only P well region and without N+ source region in the source region to reduce the size and current density of cell avalanche hole current. The scribe groove of the conventional shield gate power MOSFET does not have a trench structure.

[0004] The problem of the method for increasing the avalanche tolerance of the conventional shield gate power MOSFET is that the regions (i.e. dummy structure) with only P well region and without N+ source region cannot generate forward current due to the absence of N+ source region, so the existence of these structures increases the chip area and improves the chip cost; in addition, N+ lithography needs to be increased to manufacture the dummy structure. SUMMARY

[0005] In order to solve the technical problems existing in the prior art, the main purpose of the present application is to provide a terminal structure of a shield gate power MOSFET and a manufacturing method thereof, which changes some regions (i.e. dummy structure) with only P well region and without N+ source region into regions (i.e. conventional cell structure) with both P well region and N+ source region, and adds an avalanche tolerance enhancement structure in the scribe groove region of the conventional shield gate power MOSFET.

[0006] The first aspect of the present application provides a terminal structure of a shield gate power MOSFET, containing a P-well region and an N+ source region, and an avalanche tolerance enhancement structure added on the basis of a conventional shield gate power MOSFET scribe groove region, wherein the avalanche tolerance enhancement structure is an avalanche tolerance enhancement structure groove, comprising additional groove field oxide and additional groove polysilicon.

[0007] The terminal structure of the shield gate power MOSFET comprises an N+ substrate, an N- epitaxial layer, a terminal groove field oxide layer, a P-well, an N+ source region, a dielectric layer, a back metal, additional groove field oxide, a front metal, a terminal groove polysilicon, and additional groove polysilicon.

[0008] As a further aspect of the present application, the avalanche tolerance enhancement structure groove is arranged in a scribe groove outside a terminal structure groove stop ring of the shield gate power MOSFET.

[0009] As a further aspect of the present application, when an avalanche occurs after a device in an inductive circuit is turned off, a reverse peak voltage generated by a load inductance is applied to a drain of the device, a terminal groove ring bears a withstand voltage, the groove ring generates an electric field repelling avalanche holes, and no avalanche holes are generated around a field oxide layer of the terminal groove ring.

[0010] As a further aspect of the present application, the electric field generated by the additional N-type polysilicon in the avalanche tolerance enhancement structure groove is directed from the periphery to the additional N-type polysilicon.

[0011] As a further aspect of the present application, under the action of the electric field generated by the additional N-type polysilicon in the avalanche tolerance enhancement structure groove, avalanche holes are attracted around the additional groove field oxide.

[0012] As a further aspect of the present application, in addition to being discharged through the source region, the hole current also flows to the avalanche tolerance enhancement structure groove.

[0013] As a further aspect of the present application, after the avalanche current flows to the terminal avalanche enhancement structure, the electric field of the additional groove ring located in the scribe groove is directed from the periphery of the additional groove to the N-type polysilicon in the additional groove.

[0014] As a further aspect of the present application, when the device in the inductive circuit is turned off, part of the terminal avalanche hole current flows to the source region, enters the P-well, and is discharged to the source metal, and the other part of the terminal avalanche hole current is adsorbed on the side wall and the bottom of the additional groove field oxide under the action of the lateral electric field.

[0015] As a further scheme of the present application, when the device in the inductive circuit starts to work, the avalanche hole current in the source region disappears automatically, and the electron current flowing from the N+ source region into the region in the terminal dicing groove recombines with the avalanche hole current in the region, and the remaining avalanche hole current around the avalanche tolerance enhancement structure disappears.

[0016] As a further scheme of the present application, the avalanche tolerance enhancement structure groove structure is a groove array in the dicing groove.

[0017] In a second aspect, the present application provides a manufacturing method of a terminal structure of a shield gate power MOSFET, which comprises the following steps:

[0018] A. Forming an N- epitaxial layer on an N+ substrate;

[0019] B. Forming a trench and an avalanche tolerance enhancement structure groove of the avalanche tolerance enhancement structure of the avalanche tolerance enhancement structure by trench photoetching and etching on the N- epitaxial layer, and the avalanche tolerance enhancement structure groove is formed synchronously in the process;

[0020] C. Growing a field oxide layer and an additional trench field oxide layer on the trench sidewall, and the additional trench field oxide layer is formed synchronously in the process;

[0021] D. Depositing polysilicon and performing polysilicon diffusion to form an N-type polysilicon, and the additional trench polysilicon is formed synchronously in the process;

[0022] E. Forming an N-type shield gate in the source region and a terminal trench polysilicon in the terminal by polysilicon photoetching and etching, and the terminal trench polysilicon is an entirety and is not divided into two sections;

[0023] F. Forming an isolation oxide layer: depositing an oxide film by chemical vapor deposition, and then etching the oxide film to a specified depth to form an isolation oxide layer with a thickness, and at this time, the trench sidewall above the isolation oxide layer has no oxide layer;

[0024] G. Forming a gate oxide layer above the trench by thermal oxidation;

[0025] H. Depositing an N-type polysilicon and performing etching to form a control gate;

[0026] I. Forming a P-well by boron implantation and diffusion, and forming an N+ source region by arsenic implantation and diffusion;

[0027] J. Forming a dielectric layer, which is a USG layer and a PSG layer;

[0028] K. Forming a contact hole by contact hole photoetching and etching, and performing P-type high-doped implantation through the contact hole;

[0029] L. Forming a front metal by front metal sputtering, photoetching and etching;

[0030] M, passivation layer deposition, photoetching and etching, forming passivation layer lead window;

[0031] N, metal evaporation, forming back metal.

[0032] As a further scheme of the present application, in step B, when the trench is formed, the trench includes a source region trench and a termination trench.

[0033] As a further scheme of the present application, the present application can also be provided with a termination avalanche tolerance enhancement structure in the scribe groove outside the last termination trench ring and the termination trench cutoff ring and in the scribe groove at the same time.

[0034] Compared with the prior art, the present application has the following beneficial effects:

[0035] The present application reduces the current intensity and current density of the total avalanche hole current of the source region by adding an additional termination trench structure in the scribe groove of the conventional shield gate power MOSFET wafer, improves the anti-avalanche breakdown characteristics of the device, increases the avalanche tolerance EAS, and thus improves the reliability of the device.

[0036] The present application reduces one N+ photoetching compared with the manufacturing method of the conventional shield gate power MOSFET, reduces the chip circulation time and chip manufacturing cost.

[0037] Under the same chip area condition, the present application reduces the on-resistance and improves the performance of the product.

[0038] These aspects or other aspects of the present application will be more apparent in the following description of the embodiments. It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the present application. In the drawings:

[0040] Figure 1 It is a schematic diagram of the source region and termination structure of a shield gate power MOSFET in an embodiment of the present application;

[0041] Figure 2 It is a schematic diagram of the avalanche hole current flow direction of the source region and termination structure of a shield gate power MOSFET in an embodiment of the present application.

[0042] In the figure, reference numerals: 1-N+ substrate, 2-N- epitaxial layer, 3-terminal trench field oxide layer, 4-isolation oxide layer, 5-gate oxide layer, 6-shield gate, 7-P well, 8-N+ source region, 9-dielectric layer, 10-back metal, 11-control gate, 12-trench, 13-front metal, 14-terminal trench polysilicon, 15-contact hole, 3A-additional trench field oxide layer, 12A-avalanche resistance enhancement structure trench, 14A-additional trench polysilicon.

[0043] The purposes, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0044] This part will describe the specific embodiments of the present application in detail, the preferred embodiments of the present application are shown in the accompanying drawings, the role of the drawings is to supplement the description of the text part with figures, so that people can intuitively and visually understand each technical feature and the overall technical scheme of the present application, but it cannot be understood as a limitation on the protection scope of the present application.

[0045] In the description of the present application, one or more is the meaning of several, more than two is the meaning of more than two, greater than, less than, more than, etc. Understand as not including the number, above, below, within, etc. Understand as including the number.

[0046] In the description of the present application, the continuous label of the method steps is for the convenience of examination and understanding, and adjusting the implementation order between the steps will not affect the technical effect reached by the technical scheme of the present application, in combination with the overall technical scheme of the present application and the logical relationship between the steps.

[0047] In the description of the present application, unless otherwise explicitly limited, the setting words should be understood in a broad sense, and the person skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical scheme.

[0048] The method for increasing the avalanche resistance of the conventional shield gate power MOSFET is to set some regions with only P well region and without N+ source region (i.e. dummy structure) in the source region to provide the path of avalanche hole current, so as to reduce the size and current density of cell avalanche hole current. The scribing groove of the conventional shield gate power MOSFET does not have a trench structure.

[0049] The problem of the method for increasing the avalanche resistance of the conventional shield gate power MOSFET is that the regions with only P well region and without N+ source region (i.e. dummy structure) cannot generate forward current due to the absence of N+ source region, so the existence of these structures will increase the chip area and improve the chip cost; in addition, N+ lithography needs to be increased to manufacture the dummy structure.

[0050] Therefore, the application provides a terminal structure of a shield gate power MOSFET and a manufacturing method thereof, some regions with only P well regions but without N+ source regions (i.e. dummy structure) are changed into regions with both P well regions and N+ source regions (i.e. normal cell structure), and an avalanche tolerance enhancement structure is added in the dicing groove region of the normal shield gate power MOSFET.

[0051] Referring to Figure 1 and Figure 2 An embodiment of the application provides a terminal structure of a shield gate power MOSFET, in order to reduce the size of source region avalanche hole current, the application changes some regions with only P well regions but without N+ source regions (i.e. dummy structure) into regions with both P well regions and N+ source regions (i.e. normal cell structure), and adds an avalanche tolerance enhancement structure in the dicing groove region of the normal shield gate power MOSFET, the avalanche tolerance enhancement structure comprises additional trench field oxide and additional trench polysilicon.

[0052] Referring to Figure 1 The terminal structure of the shield gate power MOSFET comprises an N+ substrate 1, an N- epitaxial layer 2, a terminal trench field oxide layer 3, a P well 7, an N+ source region 8, a dielectric layer 9, a back metal 10, additional trench field oxide 3A, a front metal 13, a terminal trench polysilicon 14 and additional trench polysilicon 14A.

[0053] The trench of the avalanche tolerance enhancement structure is arranged in the dicing groove outside the terminal structure trench stop ring of the shield gate power MOSFET; referring to Figure 2 The dashed box represents the avalanche enhancement structure. I on the left of the dashed line represents the source region, II in the middle of the dashed line represents the first terminal region, and III on the right of the dashed line represents the second terminal region, the second terminal region is located in the dicing groove region, and the first terminal region and the second terminal region constitute the terminal region of the application. The avalanche enhancement structure is located in the second terminal region, i.e. the dicing groove region, i.e. region III.

[0054] The cell structure comprises: an N+ substrate 1, an N- epitaxial layer 2, a terminal trench field oxide layer 3, an isolation oxide layer 4 between the shield gate and the control gate, a gate oxide layer 5, a shield gate 6, a P well 7, an N+ source region 8, a dielectric layer 9, a back metal 10, a control gate 11, a trench 12, a front metal 13, a terminal trench polysilicon 14 and a contact hole 15.

[0055] The application does not need N+ lithography, and one lithography is reduced compared with the manufacturing method of the normal shield gate power MOSFET. Under the condition of the same chip area, the current density of the on-state current is increased, the on-state resistance is reduced, and the performance of the product is improved due to the absence of regions without N+ source regions.

[0056] Referring to Figure 1 and Figure 2 as shown in the figure, Figure 2 is a schematic diagram of the avalanche hole current flow direction of the shielding gate power MOSFET of the present application. In the present embodiment, when the device in the inductive circuit is turned off, the reverse peak voltage generated by the load inductance is applied to the drain of the device, and the terminal trench ring bears the voltage, and the trench ring generates an electric field repelling the avalanche holes, and no avalanche holes are generated around the field oxide layer of the terminal trench ring.

[0057] In the present embodiment, the electric field generated by the additional N-type polysilicon in the avalanche tolerance enhancement structure trench 12A is directed from the periphery to the additional N-type polysilicon. Under the action of this electric field, the avalanche holes are attracted around the additional trench field oxide layer 3A under the action of the electric field generated by the additional N-type polysilicon in the avalanche tolerance enhancement structure trench 12A, and the hole current flows to the avalanche tolerance enhancement structure trench 12A in addition to being discharged through the source region, so that the hole current is basically discharged through the source region, and a small part of it flows to the terminal, mainly to the avalanche tolerance enhancement structure trench 12A.

[0058] Referring to Figure 2 as shown in the figure, the arrow A in the figure represents the total avalanche hole current to the device, A1 represents the avalanche hole current discharged to the source region, and A2 represents the avalanche hole current discharged to the terminal region. Therefore, by using the present structure, the avalanche hole current flowing into the source region is reduced, the avalanche breakdown resistance of the device is improved, the avalanche tolerance EAS is increased, and the reliability of the device is improved.

[0059] The working principle of the present application is that the additional trench ring located in the scribe groove is N-type polysilicon, and the electric field direction is from the periphery of the additional trench to the N-type polysilicon in the additional trench.

[0060] In the present embodiment, when the device in the inductive circuit is turned off, part of the terminal avalanche hole current flows to the source region, enters the P-well 7 and is discharged to the source metal, and the other part of the terminal avalanche hole current is attracted to the additional trench field oxide side wall and the additional trench field oxide bottom under the action of the lateral electric field, thereby reducing the current intensity and current density of the total avalanche hole current of the source region.

[0061] In the present embodiment, the avalanche tolerance enhancement structure trench 12A structure proposed by the present application is a series of equidistant trenches 12 arranged in the scribe groove.

[0062] The avalanche enhancement structure of the present application has the same effect as the traditional avalanche enhancement structure, both of which reduce the current density of avalanche hole current flowing through the effective cell structure, and the equivalent effect is equivalent to moving the avalanche enhancement structure of the source region in the traditional structure to the scribing groove. Since the total length of the terminal is not increased, the present application can save the chip area occupied by the traditional avalanche enhancement structure, that is, under the condition of the same chip area, the present application can increase the forward conduction current density, reduce the conduction resistance, and improve the product performance.

[0063] In an embodiment of the present application, a manufacturing method of the terminal structure of the shield gate power MOSFET is also provided, and the manufacturing method comprises the following steps:

[0064] A, forming an N-epitaxial layer 2 on the N+ substrate 1;

[0065] B, performing trench 12 photolithography and etching on the N-epitaxial layer 2 to form the trench 12 (including the source region trench and the terminal trench) and the avalanche tolerance enhancement structure trench 12A of the avalanche tolerance enhancement structure, and the avalanche tolerance enhancement structure trench 12A is formed synchronously in the process;

[0066] C, growing a field oxide layer and an additional trench field oxide layer 3A on the sidewall of the trench 12, and the additional trench field oxide layer 3A is formed synchronously in the process;

[0067] D, depositing polysilicon and performing polysilicon diffusion to form N-type polysilicon, and the terminal trench 12 additional polysilicon is formed synchronously in the process;

[0068] E, performing polysilicon photolithography and etching to form N-type shield gate in the source region, and the terminal trench polysilicon is formed in the terminal, and the terminal trench polysilicon is an integral whole and is not divided into two sections;

[0069] F, forming an isolation oxide layer 4: depositing an oxide film by a chemical vapor deposition (CVD) method, and then etching the oxide film to a specified depth to form an isolation oxide film (also called an intermediate oxide film) with a thickness, at this time, the sidewall of the trench 12 above the isolation oxide layer 4 is not provided with an oxide layer;

[0070] G, forming a gate oxide layer 5 above the trench 12 by a thermal oxidation method;

[0071] H, depositing N-type polysilicon and performing etching to form a control gate;

[0072] I, performing boron implantation and diffusion to form a P-well 7, and then performing arsenic implantation and diffusion to form an N+ source region 8; compared with the traditional shield gate power MOSFET, the present application saves N+ photolithography.

[0073] J, forming a dielectric layer 9, which is a USG layer and a PSG layer;

[0074] K, contact hole 15 photoetching and etching to form contact hole 15, and P type high doping injection through contact hole 15;

[0075] L, front metal 13 sputtering, photoetching and etching to form front metal 13;

[0076] M, passivation layer deposition, photoetching and etching to form passivation layer lead window;

[0077] N, metal evaporation to form back metal 10.

[0078] It should be noted that: the present application can also be in the terminal last groove ring and terminal groove cut-off ring outside the scribe groove and in the scribe groove simultaneously setting terminal avalanche tolerance enhancement structure and scribe groove avalanche tolerance enhancement structure, so that the avalanche tolerance EAS is better and the working frequency is higher.

[0079] To sum up, the present application increases an additional terminal groove structure in the scribe groove of the conventional shield gate power MOSFET wafer, reduces the current intensity and current density of the total avalanche hole current of the source region, improves the anti-avalanche breakdown characteristics of the device, increases the avalanche tolerance EAS, and thus improves the reliability of the device.

[0080] The present application reduces one N+ photoetching compared with the manufacturing method of the conventional shield gate power MOSFET, reduces the chip circulation time and chip manufacturing cost.

[0081] Under the same chip area condition, the present application reduces the on-resistance and improves the performance of the product.

[0082] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent flow transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A termination structure for a shielded gate power MOSFET, characterized in that, The region containing the P-well region and the N+ source region is supplemented with an avalanche tolerance enhancement structure on the basis of the conventional shielded gate power MOSFET dicing groove region. The avalanche tolerance enhancement structure is an avalanche tolerance enhancement structure trench (12A). The avalanche tolerance enhancement structure includes additional trench field oxygen and additional trench polysilicon. The terminal structure of the shielded gate power MOSFET includes an N+ substrate (1), an N- epitaxial layer (2), a terminal trench field oxide layer (3), a P-well (7), an N+ source region (8), a dielectric layer (9), a back metal (10), an additional trench field oxide layer (3A), a front metal (13), a terminal trench polysilicon (14), an additional trench polysilicon (14A), an isolation oxide layer (4), a shielded gate (6), a control gate (11), a gate oxide layer (5), and a trench (12). The P-well (7) is the P-well region, the N+ source region (8) is the N+ source region, the additional trench field oxide layer (3A) is the additional trench field oxide, and the additional trench polysilicon (14A) is the additional trench polysilicon. The back metal (10), the N+ substrate (1), the N- epitaxial layer (2), the P-well (7), the N+ source region (8), the dielectric layer (9), and the front metal (13) are arranged sequentially in a first direction and form a source region, a first terminal region, and a second terminal region sequentially in a second direction, wherein the second direction is perpendicular to the first direction; the dicing area of ​​the conventional shielded gate power MOSFET is the second terminal region; In the source region, the trench (12) is disposed in the N-epi-epitaxy layer (2), the P-well (7) and the N+ source region (8). The trench (12) is connected to the dielectric layer (9) on the side facing the dielectric layer (9). The terminal trench field oxide layer (3), the shielding gate (6), the isolation oxide layer (4) and the control gate (11) are sequentially disposed in the trench (12) in the first direction. The control gate (11) is connected to the dielectric layer (9) on the side facing the dielectric layer (9). The gate oxide layer (5) is disposed in the trench (12). The control gate (11) and the gate oxide layer (5) are arranged in the second direction. The oxide layer (5) is connected to the dielectric layer (9) on the side facing the dielectric layer (9). In the first terminal region, the trench (12) is disposed in the N-epitaxial layer (2), the P-well (7) and the N+ source region (8). The side of the trench (12) facing the dielectric layer (9) is connected to the dielectric layer (9). The terminal trench field oxide layer (3) is disposed in the trench (12). The additional trench polysilicon (14A) is disposed in the terminal trench field oxide layer (3). The side of the terminal trench field oxide layer (3) and the additional trench polysilicon (14A) facing the dielectric layer (9) are both connected to the dielectric layer (9). In the second terminal region, the avalanche tolerance enhancement structure trench (12A) is disposed in the N- epitaxial layer (2), the P-well (7) and the N+ source region (8). The side of the avalanche tolerance enhancement structure trench (12A) facing the dielectric layer (9) is connected to the dielectric layer (9). The additional trench field oxide layer (3A) is disposed in the avalanche tolerance enhancement structure trench (12A). The additional trench polysilicon (14A) is disposed in the additional trench field oxide layer (3A). The sides of the additional trench field oxide layer (3A) and the additional trench polysilicon (14A) facing the dielectric layer (9) are both connected to the dielectric layer (9).

2. The termination structure of the shielded gate power MOSFET according to claim 1, characterized in that, The avalanche tolerance enhancement structure trench (12A) is disposed in a scribe groove outside the terminal structure trench cutoff ring of the shielded gate power MOSFET.

3. The termination structure of the shielded gate power MOSFET according to claim 2, characterized in that, The terminal structure of the shielded gate power MOSFET is applied to the device in the inductive circuit. When the device in the inductive circuit is turned off and avalanche occurs, the load inductor generates a reverse spike voltage applied to the drain of the device. The terminal trench ring is subjected to withstand voltage. The terminal trench ring generates an electric field that repels avalanche holes. No avalanche holes are generated around the field oxide layer of the terminal trench ring. The back metal (10) is the drain. The terminal trench ring is a ring structure formed by the terminal trench polysilicon (14) and the terminal trench field oxide layer (3). The field oxide layer of the terminal trench ring is the terminal trench field oxide layer (3).

4. The termination structure of the shielded gate power MOSFET according to claim 3, characterized in that, Under the influence of the electric field generated by the additional N-type polysilicon in the avalanche tolerance enhancement structure trench (12A), avalanche holes are attracted around the additional trench field oxide layer (3A); the additional trench polysilicon (14A) is the additional N-type polysilicon.

5. The termination structure of the shielded gate power MOSFET according to claim 4, characterized in that, In addition to being discharged through the source region, the hole current also flows to the avalanche tolerance enhancement structure trench (12A), and the N+ source region (8) is the source region.

6. The termination structure of the shielded gate power MOSFET according to claim 5, characterized in that, After the avalanche current flows to the terminal avalanche reinforcement structure, the electric field direction of the additional trench ring located in the dicing groove is from the periphery of the additional trench to the N-type polysilicon in the additional trench. The terminal avalanche reinforcement structure is the avalanche tolerance reinforcement structure groove (12A), and the additional groove ring located in the dicing groove is an annular structure formed by the avalanche tolerance reinforcement structure groove (12A) and the additional groove polysilicon (14A). The additional groove is the avalanche tolerance reinforcement structure groove (12A), and the N-type polysilicon is the additional groove polysilicon (14A).

7. The termination structure of the shielded gate power MOSFET according to claim 6, characterized in that, When the devices in the inductive circuit are turned off, part of the terminal avalanche hole current flows to the source region, enters the P-well (7), and is discharged to the source region metal. The other part of the terminal avalanche hole current is adsorbed on the sidewall and bottom of the additional trench field oxygen under the action of the transverse electric field. The N+ source region (8) is provided with metal, the source region metal is the metal in the N+ source region (8), the additional trench field oxygen sidewall is the sidewall of the avalanche tolerance enhancement structure trench (12A), and the additional trench field oxygen bottom is the bottom of the avalanche tolerance enhancement structure trench (12A).

8. The termination structure of the shielded gate power MOSFET according to claim 7, characterized in that, When the devices in the inductive circuit are turned on, the avalanche hole current in the source region disappears automatically. After the electron current flowing down from the N+ source region (8) enters the area in the terminal dicing slot, it combines with the avalanche hole current in that area, and the remaining avalanche hole current around the avalanche tolerance enhancement structure disappears.

9. The termination structure of the shielded gate power MOSFET according to claim 8, characterized in that, The avalanche tolerance enhancement structure groove (12A) is composed of grooves (12) with equal spacing in the diced groove.

10. A method for manufacturing a termination structure of a shielded gate power MOSFET, characterized in that, The manufacturing method includes the following steps: A. An N- epitaxial layer (2) is formed on an N+ substrate (1); B. Photolithography and etching are performed on the N-epitaxial layer (2) to form at least two trenches (12) located in the source region and the first terminal region, and an avalanche tolerance enhancement structure trench (12A) located in the second terminal region. During this process, the trenches (12) and the avalanche tolerance enhancement structure trench (12A) are formed simultaneously. C. Terminal trench field oxide layer (3) and additional trench field oxide layer (3A) are grown on the sidewall of the trench (12) and the sidewall of the avalanche tolerance enhancement structure trench (12A), respectively. During this process, the terminal trench field oxide layer (3) and the additional trench field oxide layer (3A) are formed simultaneously. D. Polycrystalline silicon is deposited on the additional trench field oxide layer (3A) and the terminal trench field oxide layer (3) located in the first terminal area, and polycrystalline phosphorus diffusion is performed to form N-type polycrystalline silicon. The N-type polycrystalline silicon includes terminal trench polycrystalline silicon (14) formed on the terminal trench field oxide layer (3) and additional trench polycrystalline silicon (14A) formed on the additional trench field oxide layer (3A). During this process, the terminal trench polycrystalline silicon (14) and the additional trench polycrystalline silicon (14A) are formed simultaneously. The terminal trench polycrystalline silicon (14) is a whole and is not divided into upper and lower sections. E. Polycrystalline lithography and etching to form an N-type shielding gate on the trench (12) located in the source region, wherein the N-type shielding gate is a shielding gate (6); F. Forming an isolation oxide layer (4) on the shielding gate (6): Deposit an oxide film using chemical vapor deposition and then etch the oxide film back to the specified depth. At this time, there is no oxide layer on the sidewall of the trench (12) above the isolation oxide layer (4). The sidewall of the trench (12) above the isolation oxide layer (4) is the side of the trench (12) away from the N+ substrate (1). G. A gate oxide layer (5) is formed above the trench (12) located in the source region by thermal oxidation. The gate oxide layer (5) is located above the shielding gate (6). H. Deposit N-type polysilicon on the gate oxide layer (5) and etch it back to form a control gate (11); I. Boron implantation and diffusion are performed to form a P-well (7), followed by arsenic implantation and diffusion to form an N+ source region (8); J. Form a dielectric layer (9), which is made of USG layer and PSG layer; K. Contact holes (15) are formed by photolithography and etching, and P-type high doping is performed through contact holes (15); L, front metal (13) is sputtered, photolithographically and etched to form front metal (13); M, passivation layer deposition, photolithography and etching, to form passivation layer lead windows; N, the metal evaporates, forming the back metal (10); In the terminal structure of the shielded gate power MOSFET prepared by the manufacturing method described above, the back metal (10), the N+ substrate (1), the N- epitaxial layer (2), the P-well (7), the N+ source region (8), the dielectric layer (9), and the front metal (13) are arranged sequentially in a first direction and form a source region, a first terminal region, and a second terminal region sequentially in a second direction, wherein the second direction is perpendicular to the first direction; the first direction is an upward direction. In the source region, the trench (12) is disposed in the N-epi-epitaxy layer (2), the P-well (7) and the N+ source region (8). The trench (12) is connected to the dielectric layer (9) on the side facing the dielectric layer (9). The terminal trench field oxide layer (3), the shielding gate (6), the isolation oxide layer (4) and the control gate (11) are sequentially disposed in the trench (12) in the first direction. The control gate (11) is connected to the dielectric layer (9) on the side facing the dielectric layer (9). The gate oxide layer (5) is disposed in the trench (12). The control gate (11) and the gate oxide layer (5) are arranged in the second direction. The oxide layer (5) is connected to the dielectric layer (9) on the side facing the dielectric layer (9). In the first terminal region, the trench (12) is disposed in the N-epitaxial layer (2), the P-well (7) and the N+ source region (8). The side of the trench (12) facing the dielectric layer (9) is connected to the dielectric layer (9). The terminal trench field oxide layer (3) is disposed in the trench (12). The additional trench polysilicon (14A) is disposed in the terminal trench field oxide layer (3). The side of the terminal trench field oxide layer (3) and the additional trench polysilicon (14A) facing the dielectric layer (9) are both connected to the dielectric layer (9). In the second terminal region, the avalanche tolerance enhancement structure trench (12A) is disposed in the N- epitaxial layer (2), the P-well (7) and the N+ source region (8). The side of the avalanche tolerance enhancement structure trench (12A) facing the dielectric layer (9) is connected to the dielectric layer (9). The additional trench field oxide layer (3A) is disposed in the avalanche tolerance enhancement structure trench (12A). The additional trench polysilicon (14A) is disposed in the additional trench field oxide layer (3A). The sides of the additional trench field oxide layer (3A) and the additional trench polysilicon (14A) facing the dielectric layer (9) are both connected to the dielectric layer (9).

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