Semiconductor light emitting element and semiconductor light emitting device

Abstract

A semiconductor light emitting device has a semiconductor light emitting element. The semiconductor light emitting element (20) has a semiconductor laminate (30) having an n-type layer (32) and a p-type layer (36), and one or more n-exposed portions (30e) that are recessed portions exposed by the n-type layer (32); a p-wiring electrode layer (42) disposed on the p-type layer (36); an insulating layer (44) continuously covering inner side surfaces (30s) of the one or more n-exposed portions (30e) and a portion of an upper side of the p-wiring electrode layer (42), having an opening portion (44a) exposing the n-type layer (32); an n-wiring electrode layer (46) disposed on the p-type layer (36) and the p-wiring electrode layer (42) in contact with the n-type layer (32) at the opening portion (44a); and one or more first n-connection members (51) respectively connecting the n-wiring electrode layer (46) at one or more first n-terminal regions (51r), the n-wiring electrode layer (46) and the p-type layer (36) being disposed below the one or more first n-terminal regions (51r).

Description

[0001] This application is a divisional application of the Chinese Patent Application No. 202080003367.2, filed on May 14, 2020, entitled “Semiconductor Light Emitting Element and Semiconductor Light Emitting Device”, which claims priority to Japanese Patent Application No. 2018-107371, filed on May 24, 2018. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor light emitting element and a semiconductor light emitting device. BACKGROUND

[0003] Conventionally, a semiconductor light emitting element mounted to a wiring pattern formed on a mounting substrate via a bump flip chip is known (for example, refer to Patent Literature 1 and the like). The semiconductor light emitting element described in Patent Literature 1 has a structure in which a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially stacked on a substrate, and an exposed portion in which the first semiconductor layer is exposed from the second semiconductor layer is formed. Further, the semiconductor light emitting element described in Patent Literature 1 has a second electrode and an insulating film sequentially stacked on the second semiconductor layer, and a first electrode stacked on the exposed portion and the insulating film. Thus, the semiconductor light emitting element described in Patent Literature 1 has a so-called double-layer wiring structure. Further, in the semiconductor light emitting element described in Patent Literature 1, the bumps are arranged in a high density directly below the light emitting element, so that heat is dissipated via the bumps, and the exposed portion is not overlapped with the bumps, so that the insulating film is not broken when flip chip mounting.

[0004] (Prior Art Documents)

[0005] (Patent Literature)

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2018-107371

[0007] Heat generated in the vicinity of the light emitting layer of the semiconductor light emitting element described in Patent Literature 1 is dissipated to the mounting substrate via the bumps. In the semiconductor light emitting element described in Patent Literature 1, heat generated in the vicinity of the light emitting layer is conducted to the bumps via the insulating film having low thermal conductivity, and thus the heat dissipation property is low. Therefore, in the semiconductor light emitting element described in Patent Literature 1, particularly, in a case where a large current is supplied to the semiconductor light emitting element, the reliability can be reduced. SUMMARY

[0008] In order to solve such a problem, an object of the present disclosure is to provide a semiconductor light emitting element and a semiconductor light emitting device having high heat dissipation property.

[0009] To solve the problem, one aspect of the semiconductor light emitting element according to the present disclosure has a semiconductor stack having an n-type layer, a light emitting layer disposed above the n-type layer, and a p-type layer disposed above the light emitting layer, the semiconductor stack having one or more n-exposed portions that are recessed portions exposing the n-type layer; a p-wiring electrode layer disposed on the p-type layer; an insulating layer continuously covering inner side surfaces of the one or more n-exposed portions and a portion of an upper side of the p-wiring electrode layer, the insulating layer having an opening portion exposing the n-type layer at a bottom surface of the one or more n-exposed portions; an n-wiring electrode layer in contact with the n-type layer at the opening portion, the n-wiring electrode layer being disposed above the p-type layer and the p-wiring electrode layer via the insulating layer; and one or more first n-connection members that are conductive members for electrical connection with the outside, the one or more first n-connection members being connected to the n-wiring electrode layer at one or more first n-terminal regions, the one or more first n-terminal regions including at least a portion of an area above the opening portion in a plan view, the n-wiring electrode layer and the p-type layer being disposed below the one or more first n-terminal regions in a cross section parallel to a stacking direction of the semiconductor stack.

[0010] Thus, the first n-connection members are disposed above the opening portion where the insulating layer having low thermal conductivity is not formed, and thus a heat dissipation path not via the insulating layer can be formed. Therefore, compared to a case where the first n-connection members are disposed above the insulating layer, the heat dissipation property of the semiconductor light emitting element can be improved. Also, the amount of heat generated near the inner side surfaces of the n-exposed portions of the semiconductor light emitting element is large, but the first n-connection members are disposed above the inner side surfaces, and thus heat generated near the inner side surfaces of the n-exposed portions can be dissipated via the first n-connection members. Therefore, the heat dissipation property of the semiconductor light emitting element can be further improved.

[0011] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, the semiconductor light emitting element can further have one or more second n-connection members that are conductive members for electrical connection with the outside, the one or more second n-connection members being connected to the n-wiring electrode layer at one or more second n-terminal regions of the n-wiring electrode layer disposed outside the one or more n-exposed portions.

[0012] Thus, the semiconductor light emitting element has the second n-connection members, and thus a further heat dissipation path can be formed, and therefore the heat dissipation property of the semiconductor light emitting element can be further improved.

[0013] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, the one or more first n-connection members can be apart from the one or more second n-connection members.

[0014] Thus, the first n connecting member and the second n connecting member are separated from each other, so that the mounting load in the longitudinal direction can be dispersed, and the insulation layer can be prevented from being broken.

[0015] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, the one or more first n connecting members can have a larger particle diameter than the n wiring electrode layer.

[0016] Thus, the one or more first n connecting members can have a larger particle diameter than the n wiring electrode layer, so that the one or more first n connecting members can have a lower hardness than the n wiring electrode layer. Thus, when the semiconductor light emitting element is mounted on the mounting substrate, the one or more first n connecting members can absorb the force applied to the semiconductor light emitting element. Thus, in the semiconductor light emitting element according to the present disclosure, the force applied to the insulation layer near the inner side surface of the n exposed portion during mounting can be reduced, and thus, the insulation layer can be prevented from being broken.

[0017] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, the one or more first n connecting members can have a larger particle diameter than the n wiring electrode layer.

[0018] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, the one or more first n connecting members can have a larger particle diameter than the n wiring electrode layer.

[0019] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, the one or more first n connecting members can have a larger particle diameter than the n wiring electrode layer.

[0020] Also, in order to solve the problem, one aspect of the semiconductor light emitting device according to the present disclosure has the semiconductor light emitting element, and a mounting substrate having a first wiring electrode and a second wiring electrode, the one or more first n connecting members are joined to the first wiring electrode of the mounting substrate, and the p wiring electrode layer is joined to the second wiring electrode of the mounting substrate via the p connecting member as a conductive member in the area exposed from the n wiring electrode layer and the insulating layer.

[0021] Thus, the first n connecting member is disposed above the opening portion where the insulating layer having low thermal conductivity is not formed, and the first n connecting member is connected to the mounting substrate via the first wiring electrode, whereby a heat dissipation path from the n-type layer to the mounting substrate without passing through the insulating layer can be formed. Therefore, compared to the case where the first n connecting member is disposed above the insulating layer, the heat dissipation property of the semiconductor light emitting element can be improved. Also, the amount of heat generated near the inner side surface of the n exposed portion of the semiconductor light emitting element is large, but the first n connecting member is disposed above the inner side surface, whereby the heat generated near the inner side surface of the n exposed portion can be dissipated to the mounting substrate via the first n connecting member. Therefore, the heat dissipation property of the semiconductor light emitting element can be further improved.

[0022] Also, in one aspect of the semiconductor light emitting device according to the present disclosure, the end portion of the joining surface of the one or more first n connecting members to the first wiring electrode can be disposed apart from the end portion of the first wiring electrode of the mounting substrate on the inner side of the first wiring electrode.

[0023] Thus, the first n connecting member is not disposed at the end portion of the first wiring electrode, whereby the first n connecting member can be prevented from being short-circuited with the adjacent second wiring electrode and p connecting member.

[0024] Also, in one aspect of the semiconductor light emitting device according to the present disclosure, the particle diameter on the opening portion of the one or more first n connecting members can be larger than the particle diameter on the p-type layer in a cross section parallel to the stacking direction.

[0025] Such a particle size distribution of the first n connecting member is, for example, formed at the time of mounting the semiconductor light emitting element on a mounting substrate. In the mounting of the semiconductor light emitting element of the present disclosure, FCB mounting is used, for example. The FCB mounting is constituted by a load step, and a step of applying ultrasonic waves after the load step. In the load step, the opening portion is lower (i.e., recessed) than the p-type layer at the periphery at the time of compression, and thus the compression rate of the first n connecting member is higher on the p-type layer at the periphery than on the opening portion. Therefore, the first n connecting member is harder on the p-type layer at the periphery than on the opening portion. Therefore, when the first n connecting portion is joined to the mounting substrate in the step of applying ultrasonic waves, the hardened first n connecting member at the periphery becomes an obstacle, and the first n connecting portion is difficult to expand in a direction parallel to the stacking surface. Therefore, it is possible to suppress short-circuiting of the first n connecting member and the adjacent p connecting member.

[0026] Also, in one aspect of the semiconductor light emitting device according to the present disclosure, in a cross section parallel to the stacking direction, the one or more first n connecting members can have side walls that expand outward as they get closer to the n wiring electrode layer on the n wiring electrode layer side.

[0027] In this way, the side walls of the first n connecting member expand, and accordingly, compared to a case where the side walls do not expand, it is possible to increase the area of the first n terminal region. Therefore, it is possible to dissipate heat from a wider area by the first n connecting member. Therefore, it is possible to improve the heat dissipation properties of the semiconductor light emitting element.

[0028] Also, to solve the problem, one aspect of the semiconductor light emitting element according to the present disclosure has: a semiconductor stack having an n-type layer, a light emitting layer disposed above the n-type layer, and a p-type layer disposed above the light emitting layer, and the semiconductor stack has one or more n-exposed portions that are recessed portions exposing the n-type layer; a p wiring electrode layer disposed on the p-type layer; an insulating layer continuously covering inner side surfaces of the one or more n-exposed portions and a portion of the upper side of the p wiring electrode layer, having an opening portion exposing the n-type layer at a bottom surface of the one or more n-exposed portions; and an n wiring electrode layer in contact with the n-type layer at the opening portion, disposed above the p-type layer and the p wiring electrode layer via the insulating layer, having one or more first n terminal regions set as regions in which a conductive member configured to be electrically connected to the outside is disposed, in a planar view, the one or more first n terminal regions include at least a portion of a region above the opening portion, in a cross section parallel to a stacking direction of the semiconductor stack, the n wiring electrode layer and the p-type layer are disposed below the one or more first n terminal regions.

[0029] Thus, the first n-terminal region for disposing the conductive member is provided above the opening portion in which the insulating layer having low thermal conductivity is not formed, and thus, in a case where the conductive member is disposed in the first n-terminal region, a heat dissipation path not passing through the insulating layer can be formed. Therefore, compared to a case where the conductive member is disposed above the insulating layer, the heat dissipation property of the semiconductor light emitting element can be improved. Further, the heat amount near the inner side surface of the n-exposed portion of the semiconductor light emitting element is large, but the first n-terminal region is disposed above the inner side surface, and thus, in a case where the conductive member is disposed in the first n-terminal region, the heat generated near the inner side surface of the n-exposed portion can be dissipated via the conductive member. Therefore, the heat dissipation property of the semiconductor light emitting element can be further improved.

[0030] Further, in one aspect of the semiconductor light emitting element according to the present disclosure, the total area of the one or more first n-terminal regions can be larger than the total area of the n-wiring electrode layer disposed outside the one or more n-exposed portions, in plan view of the n-wiring electrode layer.

[0031] Thus, the total area of the first n-terminal region is enlarged, and thus, in a case where the conductive member is disposed in the first n-terminal region, the heat dissipation path can be increased, and therefore, the heat dissipation property of the semiconductor light emitting element can be improved.

[0032] Further, in one aspect of the semiconductor light emitting element according to the present disclosure, the area of each of the one or more first n-terminal regions can be larger near the end portion of the semiconductor light emitting element, in plan view of the n-wiring electrode layer.

[0033] In the central portion of the semiconductor light emitting element, the connecting member that becomes the heat dissipation path exists in all directions, and thus, in the edge portion of the semiconductor light emitting element, only the connecting member that becomes the heat dissipation path exists in the inner side direction, and therefore, the heat dissipation property of the edge portion of the semiconductor light emitting element can be lowered. However, in the semiconductor light emitting element according to the present disclosure, the area of the first n-terminal region near the end portion is enlarged, and thus, the heat dissipation path can be increased, and therefore, the heat dissipation property of the edge portion can be improved.

[0034] Further, in one aspect of the semiconductor light emitting element according to the present disclosure, the area of the opening portion can be larger near the end portion of the semiconductor light emitting element, in plan view of the n-wiring electrode layer.

[0035] As described above, in the edge portion of the semiconductor light emitting element, the heat dissipation property can be lowered. However, in the semiconductor light emitting element according to the present disclosure, the area of the opening portion near the end portion is enlarged, and thus, the heat can be dispersed and the heat dissipation path can be increased, and therefore, the heat dissipation property of the edge portion can be improved.

[0036] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, the center of the one or more first n-terminal regions can be located within the region of the opening portion in a plan view of the n-wiring electrode layer.

[0037] Thus, the center of the first n-terminal region is located within the region of the opening portion, whereby the central portion of the conductive member such as the first n-connecting member provided in the first n-terminal region is located in the opening portion. Therefore, much of the force applied to the conductive member at the time of mounting is applied to the opening portion where no insulating layer is provided. Thus, the force applied to the insulating layer at the time of mounting can be reduced, whereby the breakage of the insulating layer can be suppressed.

[0038] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, the center of the one or more first n-terminal regions can coincide with the center of the opening portion in a plan view of the n-wiring electrode layer.

[0039] Thus, the center of the first n-terminal region coincides with the center of the opening portion, whereby the central portion of the conductive member such as the first n-connecting member provided in the first n-terminal region is located in the center of the opening portion. Therefore, much of the force applied to the conductive member at the time of mounting is applied to the opening portion where no insulating layer is provided. Thus, the force applied to the insulating layer at the time of mounting can be reduced, whereby the breakage of the insulating layer can be suppressed.

[0040] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, one or more second n-terminal regions as regions where a conductive member for electrical connection with the outside is provided can be provided on the n-wiring electrode layer other than the one or more n-exposed portions.

[0041] Thus, the second n-terminal region is provided, whereby in a case where a conductive member is provided in the second n-terminal region, a further heat dissipation path can be formed, and thus the heat dissipation property of the semiconductor light emitting element can be further improved.

[0042] Also, in one aspect of the semiconductor light emitting element according to the present disclosure, the sum of the areas of the one or more first n-terminal regions and the one or more second n-terminal regions can be larger than the sum of the areas of the n-wiring electrode layer other than the one or more n-exposed portions in a plan view of the n-wiring electrode layer.

[0043] Thus, the areas of the first n-terminal region and the second n-terminal region are enlarged, whereby in a case where a conductive member is provided in the first n-terminal region and the second n-terminal region, the heat dissipation path can be increased, and thus the heat dissipation property of the semiconductor light emitting element can be improved.

[0044] According to the present disclosure, a semiconductor light emitting element and a semiconductor light emitting device having high heat dissipation can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0045] FIG. 1 is a schematic plan view showing the entire structure of the semiconductor light emitting device according to Embodiment 1.

[0046] FIG. 2A is a schematic cross-sectional view showing the entire structure of the semiconductor light emitting device according to Embodiment 1.

[0047] FIG. 2B is a schematic cross-sectional view showing the entire structure of the semiconductor light emitting device according to the modification of Embodiment 1.

[0048] FIG. 3 is a schematic plan view showing the structure of the semiconductor light emitting element according to Embodiment 1.

[0049] FIG. 4 is a plan view showing the n-wiring electrode layer disposed outside the n-exposed portion according to Embodiment 1.

[0050] FIG. 5 is a plan view showing the first n-terminal region according to Embodiment 1.

[0051] FIG. 6A is a schematic cross-sectional view showing the first step of the manufacturing method of the semiconductor light emitting device according to Embodiment 1.

[0052] FIG. 6B is a schematic cross-sectional view showing the second step of the manufacturing method of the semiconductor light emitting device according to Embodiment 1.

[0053] FIG. 6C is a schematic cross-sectional view showing the third step of the manufacturing method of the semiconductor light emitting device according to Embodiment 1.

[0054] FIG. 6D is a schematic cross-sectional view showing the fourth step of the manufacturing method of the semiconductor light emitting device according to Embodiment 1.

[0055] FIG. 6E is a schematic cross-sectional view showing the fifth step of the manufacturing method of the semiconductor light emitting device according to Embodiment 1.

[0056] FIG. 6F is a schematic cross-sectional view showing the sixth step of the manufacturing method of the semiconductor light emitting device according to Embodiment 1.

[0057] FIG. 6Gis a schematic cross-sectional view showing the seventh step of the manufacturing method of the semiconductor light emitting device according to Embodiment 1.

[0058] FIG. 6H is a schematic cross-sectional view showing the eighth step of the manufacturing method of the semiconductor light emitting device according to Embodiment 1.

[0059] FIG. 7 is a graph showing the relationship between the average particle diameter of Au and the hardness.

[0060] FIG. 8 is a graph for explaining the measurement method of the particle diameter.

[0061] FIG. 9 is a graph showing the relationship between the particle diameter and the thickness when the first n connecting member according to Embodiment 1 is crushed.

[0062] FIG. 10 is a schematic cross-sectional view showing the structure of the first n connecting member of the semiconductor light emitting device according to Embodiment 1.

[0063] FIG. 11A is a plan view showing the first positional relationship between the first n terminal region and the opening portion according to Embodiment 1.

[0064] FIG. 11B is a plan view showing the second positional relationship between the first n terminal region and the opening portion according to Embodiment 1.

[0065] FIG. 12 is a plan view showing the structure of the semiconductor light emitting element according to Modification 1 of Embodiment 1.

[0066] FIG. 13 is a cross-sectional view showing the structure of the semiconductor light emitting element according to Modification 1 of Embodiment 1.

[0067] FIG. 14 is a plan view showing the structure of the semiconductor light emitting element according to Modification 2 of Embodiment 1.

[0068] FIG. 15 is a cross-sectional view showing the structure of the semiconductor light emitting element according to Modification 2 of Embodiment 1.

[0069] FIG. 16 is a schematic plan view showing the entire structure of the semiconductor light emitting element according to Embodiment 2.

[0070] FIG. 17 is a schematic cross-sectional view showing the entire structure of the semiconductor light emitting element according to Embodiment 2.

[0071] FIG. 18is a plan view showing the n-wiring electrode layer outside the n-exposing portion according to Embodiment 2.

[0072] FIG. 19 is a plan view showing the first n-terminal region and the second n-terminal region according to Embodiment 2.

[0073] FIG. 20A is a schematic plan view showing the structure of the semiconductor light emitting element according to Embodiment 2 used in the simulation.

[0074] FIG. 20B is a schematic plan view showing the structure of the semiconductor light emitting element according to the comparative example used in the simulation.

[0075] FIG. 21 is a graph showing the simulation results of the heat generation distribution of each semiconductor light emitting element and the temperature distribution of the temperature Tj of the light emitting layer according to Embodiment 2 and the comparative example.

[0076] FIG. 22 is a graph showing the simulation results of the relationship between the maximum value of the temperature Tj of the light emitting layer and the current amount of each semiconductor light emitting element according to Embodiment 2 and the comparative example.

[0077] FIG. 23A is a schematic cross-sectional view showing the first step of the manufacturing method of the semiconductor light emitting element according to Embodiment 2.

[0078] FIG. 23B is a schematic cross-sectional view showing the second step of the manufacturing method of the semiconductor light emitting element according to Embodiment 2.

[0079] FIG. 23C is a schematic cross-sectional view showing the third step of the manufacturing method of the semiconductor light emitting element according to Embodiment 2.

[0080] FIG. 24 is a schematic cross-sectional view showing the entire structure of the semiconductor light emitting device according to Embodiment 3.

[0081] FIG. 25A is a schematic cross-sectional view showing the first step of the manufacturing method of the semiconductor light emitting device according to Embodiment 3.

[0082] FIG. 25B is a schematic cross-sectional view showing the second step of the manufacturing method of the semiconductor light emitting device according to Embodiment 3.

[0083] FIG. 25C is a schematic cross-sectional view showing the third step of the manufacturing method of the semiconductor light emitting device according to Embodiment 3.

[0084] FIG. 26Ais a schematic cross-sectional view showing the entire structure of a semiconductor light emitting device to which a modification of Embodiment 3 is applied.

[0085] FIG. 26B is a schematic cross-sectional view showing the entire structure of a semiconductor light emitting device to which another modification of Embodiment 3 is applied.

[0086] FIG. 27 is a schematic cross-sectional view showing the entire structure of a semiconductor light emitting device to which Embodiment 4 is applied.

[0087] FIG. 28A is a schematic cross-sectional view showing a first step of a manufacturing method of a semiconductor light emitting device to which Embodiment 4 is applied.

[0088] FIG. 28B is a schematic cross-sectional view showing a second step of a manufacturing method of a semiconductor light emitting device to which Embodiment 4 is applied.

[0089] FIG. 28C is a schematic cross-sectional view showing a third step of a manufacturing method of a semiconductor light emitting device to which Embodiment 4 is applied. DETAILED DESCRIPTION

[0090] Hereinafter, with respect to the embodiments of the present disclosure, description is made with reference to the drawings. Also, the embodiments described below all show one specific example of the present disclosure. Therefore, the numerical values, shapes, materials, constituent elements, arrangement of constituent elements, and connection modes and the like shown in the following embodiments are one example and not intended to limit the gist of the present disclosure.

[0091] Also, each of the drawings is a schematic view and is not necessarily a strict view. Therefore, the scale and the like in each of the drawings are not necessarily consistent. Also, in each of the drawings, the same symbol is added to substantially the same structure, and repeated description is omitted or simplified.

[0092] Also, in the present specification, the terms "upper" and "lower" do not indicate the upward direction (plumb upward direction) and the downward direction (plumb downward direction) of the absolute spatial recognition, but are used as terms defined by the relative positions based on the stacking order of the layers in the stacked structure. Also, the terms "upper" and "lower" are applicable not only to the case where two constituent elements are arranged apart from each other with other constituent elements present between the two constituent elements, but also to the case where two constituent elements are arranged in a state of contacting each other.

[0093] (Embodiment 1)

[0094] A semiconductor light emitting element and a semiconductor light emitting device to which Embodiment 1 is applied are described.

[0095] [1-1. Entire Structure]

[0096] First, for the entire structure of the semiconductor light emitting element and the semiconductor light emitting device to which the present embodiment pertains, the following will be described. FIGS. 1-3 FIG. 1 FIG. 2A are a schematic plan view and a cross-sectional view, respectively, showing the entire structure of the semiconductor light emitting device 10 to which the present embodiment pertains. FIG. 1 shows a plan view of the semiconductor light emitting element 20 and the mounting substrate 11. FIG. 2A shows a cross section of the semiconductor light emitting device 10 along the II-II line of FIG. 1 . Also, in each of the following drawings, the direction perpendicular to the main surface of the mounting substrate 11 is set as the Z-axis direction, and the two directions perpendicular to the Z-axis direction and to each other are set as the X-axis direction and the Y-axis direction. FIG. 1 FIG. 2A

[0097] The semiconductor light emitting device 10 is a light emitting device provided with the semiconductor light emitting element 20, as shown in FIG. 1 FIG. 2A The semiconductor light emitting device 10 has the mounting substrate 11 and the semiconductor light emitting element 20, as shown in

[0098] The mounting substrate 11 is a base that mounts the semiconductor light emitting element 20, as shown in FIG. 2A The mounting substrate 11 has the substrate 12, the first wiring electrode 15, and the second wiring electrode 16.

[0099] The substrate 12 is a base of the mounting substrate, for example, a ceramic substrate composed of a sintered body of AlN. The first wiring electrode 15 and the second wiring electrode 16 are conductive layers formed on the substrate 12, for example, formed of Au. The first wiring electrode 15 and the second wiring electrode 16 are insulated from each other.

[0100] The semiconductor light emitting element 20 is a light emitting element that utilizes a semiconductor layer, and has the growth substrate 22, the semiconductor layer stack 30, the p-wiring electrode layer 42, the insulating layer 44, and the n-wiring electrode layer 46. In the present embodiment, the semiconductor light emitting element 20 further has the plurality of seed metal layers 56, the one or more first n-connection members 51, and the p-connection member 60.

[0101] The growth substrate 22 is a substrate on which the semiconductor layer stack 30 is stacked. In the present embodiment, as a light-transmissive substrate, a sapphire substrate and a GaN substrate are used for the growth substrate 22.

[0102] As shown in FIG. 2A ​​​​​It is shown that the semiconductor laminate 30 has an n-type layer 32, a light emitting layer 34, and a p-type layer 36. The semiconductor laminate 30 has one or more n-exposed portions 30e that are recessed portions exposed as the n-type layer 32. The n-exposed portion 30e has a bottom surface 30b that is a bottom of the n-exposed portion 30e, and an inner side surface 30s that is a surface extending from the bottom surface 30b in a laminating direction. Here, the laminating direction is a direction perpendicular to a main surface of the growth substrate 22 (i.e., the Z-axis direction of each figure). In the present embodiment, the n-exposed portion 30e is a circular-shaped recessed portion with a diameter of about 70 μm. Also, the shape of the n-exposed portion 30e is not limited to a circular shape, and can be a rectangular shape or the like. Also, the number of n-exposed portions 30e, if one or more, is not particularly limited. For example, the number of n-exposed portions 30e can be a plurality.

[0103] The n-type layer 32 is a layer including an n-type semiconductor layer disposed above the growth substrate 22. In the present embodiment, as the n-type semiconductor layer for the n-type layer 32, an n-type GaN-based layer is used. The n-type layer 32 can include a plurality of layers such as an n-type cladding layer.

[0104] The light emitting layer 34 is an active layer disposed above the n-type layer 32. In the present embodiment, as the light emitting layer 34, an InGaN-based layer is used.

[0105] The p-type layer 36 is a layer including a p-type semiconductor layer disposed above the light emitting layer 34.

[0106] In the present embodiment, as the p-type semiconductor layer for the p-type layer 36, a p-type GaN-based layer is used. The p-type layer 36 can include a plurality of layers such as a p-type cladding layer.

[0107] The p-wiring electrode layer 42 is a conductive layer disposed on the p-type layer 36. In the present embodiment, the p-wiring electrode layer 42 is a laminate having, in order on the p-type layer 36, an Ag layer with a thickness of 0.2 μm, a Ti layer with a thickness of 0.7 μm, and an Au layer with a thickness of 0.3 μm. The p-wiring electrode layer 42 is joined to the second wiring electrode 16 of the mounting substrate 11 via a p-connection member 60 that is a conductive member in a region exposed from the n-wiring electrode layer 46 and the insulating layer 44.

[0108] The insulating layer 44 is a layer composed of an insulating material that continuously covers the inner side surface 30s of the one or more n-exposed portions 30e and a portion of the upper side of the p-wiring electrode layer 42 and has an opening portion 44a that exposes the n-type layer 32 at the bottom surface of the one or more n-exposed portions 30e. In the present embodiment, the insulating layer 44 is a layer composed of SiO2 having a thickness of 1.0 μm. Also, the opening portion 44a is a circular opening having a diameter of about 60 μm. Moreover, the shape of the opening portion 44a is not limited to a circular shape and can be a rectangular shape or the like.

[0109] The n-wiring electrode layer 46 is a conductive layer that is disposed above the p-type layer 36 and the p-wiring electrode layer 42 via the insulating layer 44 and that is in contact with the n-type layer 32 at the opening portion 44a. In the present embodiment, the n-wiring electrode layer 46 is a laminate having an Al layer having a thickness of 0.3 μm, a Ti layer having a thickness of 0.3 μm, and an Au layer having a thickness of 1.0 μm, which are sequentially laminated from the semiconductor laminate 30 side.

[0110] The seed metal layer 56 is a conductive layer that becomes a base of the first n-connection member 51 and the p-connection member 60 and is disposed between the first n-connection member 51 and the n-wiring electrode layer 46 and between the p-connection member 60 and the p-wiring electrode layer 42. In the present embodiment, the surface of the seed metal layer 56 on the side farther from the semiconductor laminate 30 is composed of Au. More specifically, the seed metal layer 56 is a laminate of a Ti layer having a thickness of 0.1 μm and an Au layer having a thickness of 0.3 μm, which are sequentially laminated from the semiconductor laminate 30 side.

[0111] The one or more first n-connection members 51 are each a conductive member for electrical connection with the outside. In the present embodiment, the one or more first n-connection members 51 are joined to the first wiring electrode 15 of the mounting substrate 11. The one or more first n-connection members 51 are each joined to the n-wiring electrode layer 46 at one or more first n-terminal regions 51r. In other words, the n-wiring electrode layer 46 has one or more first n-terminal regions 51r that are regions in which the conductive members for electrical connection with the outside are disposed. The one or more first n-connection members 51 can also be a metal having a thermal conductivity of 100 W / m·K or more. In the present embodiment, as the one or more first n-connection members 51, bumps composed of Au having a thermal conductivity of 300 W / m·K or more are used. Moreover, for the first n-connection member having a thermal conductivity of 100 W / m·K or more, any one of Au, Ag, Al, and Cu or an alloy composed of a combination thereof can be used. Also, the number of the first n-connection members 51 and the first n-terminal regions 51r is not particularly limited if it is one or more. For example, the first n-connection members 51 and the first n-terminal regions 51r can each be a plurality.

[0112] Each of the more than one first n-terminal region 51r includes at least a portion of the region above the opening 44a. And, as FIG. 2A As shown, in a cross section parallel to the stacking direction of the semiconductor stack 30, below one or more first n-terminal regions 51r, an n-wiring electrode layer 46 and a p-type layer 36 are disposed.

[0113] The p-connection member 60 is a conductive member for external electrical connection. In this embodiment, the p-connection member 60 is engaged with the second wiring electrode 16 of the mounting substrate 11. The p-connection member 60 is connected to the p-wiring electrode layer 42 in the p-terminal region 60r. In other words, the p-terminal region 60r is provided in the p-wiring electrode layer 42 as a region for configuring the conductive member for external electrical connection. In this embodiment, the p-connection member 60 is a bump made of Au.

[0114] [1-2. Functions and Effects]

[0115] Next, the function and effect of the semiconductor light-emitting element 20 and the semiconductor light-emitting device 10 involved in this embodiment will be explained.

[0116] As described above, in the n-wiring electrode layer 46 of the semiconductor light-emitting element 20 according to this embodiment, one or more first n-terminal regions 51r are provided as first n-connection members 51 for electrical connection with the outside. Each of the one or more first n-terminal regions 51r includes at least a portion of the region above the opening 44a.

[0117] In other words, including, FIG. 2A The diagram shows two scenarios: one where the first n-terminal region 51r exists in the entire area above the opening 44a, and another where the first n-terminal region 51r exists only in a portion of the area above the opening 44a. Here, for the case where the first n-terminal region 51r exists only in a portion of the area above the opening 44a, the method used... FIG. 2B Please provide an explanation. FIG. 2B This is a schematic cross-sectional view showing the overall structure of the semiconductor light-emitting device 10b according to a modified example of this embodiment.

[0118] like FIG. 2B As shown, the semiconductor light-emitting device 10b differs from the semiconductor light-emitting device 10 in the structure of the first n-terminal region 51r and the first n-connecting member 51; the other structures are identical. In the semiconductor light-emitting device 10b, the first n-terminal region 51r exists only in a portion of the area above the opening 44a. In other words, the first n-connecting member 51 is only disposed in a portion of the area above the opening 44a.

[0119] Thus, the first n-terminal region 51r for disposing the conductive member is provided above the opening portion 44a where the insulating layer 44 having low thermal conductivity is not formed, and accordingly, in a case where the conductive member is disposed in the first n-terminal region 51r, a heat dissipation path not via the insulating layer 44 can be formed. Therefore, compared to a case where the conductive member is disposed above the insulating layer 44, the heat dissipation property of the semiconductor light emitting element 20 can be improved.

[0120] Also, even in a case where a part of the opening portion 44a is exposed in one or more first n-terminal regions 51r of the semiconductor light emitting element 20, the heat generated near the inner side surface (right side surface of the n-exposed portion 30e) of the n-exposed portion 30e can be dissipated via the first n-connecting member 51, and therefore, the heat dissipation property of the semiconductor light emitting element 20 can be improved. FIG. 2B

[0121] Also, in the present embodiment, in a cross section parallel to the stacking direction of the semiconductor stack 30, the n-wiring electrode layer 46 and the p-type layer 36 are disposed below one or more first n-terminal regions 51r. Here, the amount of heat generated near the inner side surface 30s of the n-exposed portion 30e of the semiconductor light emitting element 20 is large, but the first n-terminal region 51r is provided above the inner side surface 30s, and accordingly, in a case where the first n-connecting member 51 as the conductive member is disposed in the first n-terminal region, the heat generated near the inner side surface 30s of the n-exposed portion 30e can be dissipated via the first n-connecting member 51. Therefore, the heat dissipation property of the semiconductor light emitting element 20 can be further improved.

[0122] Next, the structure of one or more first n-terminal regions 51r of the semiconductor light emitting element 20 according to the present embodiment will be described in detail with reference to FIGS. 3-5 . FIG. 3 is a schematic plan view showing the structure of the semiconductor light emitting element 20 according to the present embodiment. In FIG. 3 , a plan view of the n-wiring electrode layer 46 of the semiconductor light emitting element 20 is shown. FIG. 4 is a plan view showing the n-wiring electrode layer 46 disposed outside the n-exposed portion 30e according to the present embodiment. FIG. 5 is a plan view showing the first n-terminal region 51r according to the present embodiment.

[0123] In the present embodiment, the total area of one or more first n-terminal regions 51r shown in FIG. 5 is larger than the total area of the n-wiring electrode layer 46 disposed outside the n-exposed portion 30e shown in FIG. 4 .

[0124] ​In this way, the total area of ​​the first n terminal region 51r is increased. Accordingly, when the first n connecting member 51 is arranged in the first n terminal region 51r, the heat dissipation path can be increased, thereby improving the heat dissipation of the semiconductor light-emitting element 20.

[0125] [1-3. Manufacturing Method]

[0126] Next, regarding the manufacturing method of the semiconductor light-emitting device 10 according to this embodiment, using... FIGS. 6A-6H Please provide an explanation. FIGS. 6A-6H This is a schematic cross-sectional view showing the various steps of the manufacturing method of the semiconductor light-emitting device 10 according to this embodiment.

[0127] First, such as FIG. 6A The diagram shows a growth substrate 22 prepared, on which a semiconductor stack 30 is stacked on one of the main surfaces of the growth substrate 22. In this embodiment, using an epitaxial growth technique based on MOCVD (metal-organic chemical vapor deposition), an n-type layer 32 comprising an n-type GaN layer, a light-emitting layer 34 comprising an InGaN layer, and a p-type layer 36 comprising a p-type GaN layer are sequentially stacked on one of the main surfaces of the growth substrate 22, which is composed of a sapphire substrate and a GaN substrate. Next, a portion of the p-type layer 36, the light-emitting layer 34, and the n-type layer 32 are removed, thereby forming one or more n-exposed portions 30e that are recesses exposing the n-type layer 32. In this embodiment, a portion of the p-type layer 36, the light-emitting layer 34, and the n-type layer 32 is removed using dry etching.

[0128] Next, as FIG. 6B The diagram shows a p-type wiring electrode layer 42 of a predetermined shape formed on a p-type layer 36. In this embodiment, a resist pattern with openings in the region where the p-type layer 36 is disposed is formed using photolithography. Next, an Ag film with a thickness of 0.2 μm is formed by sputtering, and the resist film and the Ag on the resist film are removed by a stripping method, thereby forming an Ag layer as a reflective metal patterned in a predetermined shape. Next, a stacked film consisting of a Ti film with a thickness of 0.7 μm covering the Ag layer and an Au film with a thickness of 0.3 μm is formed by sputtering. Next, a resist pattern covering the p-type layer 36 is formed using photolithography, excess stacked film in areas other than the p-type layer 36 is removed by wet etching, and the resist film is removed by organic washing. Thus, a p-type wiring electrode layer 42 consisting of an Ag layer, a Ti layer, and an Au layer is formed.

[0129] Next, as FIG. 6CAs shown, an insulating layer 44 is formed. In this embodiment, an oxide film composed of SiO2 with a thickness of 1.0 μm is formed over the entire semiconductor stack 30 and the p-wire electrode layer 42. Next, a resist pattern is formed for a portion of the openings of the n-type layer 32 and the p-type layer 36. After removing the oxide film in the portions where the resist pattern is not formed by wet etching, the resist film is removed. Thus, the opening 44a of the n-type layer 32 and the insulating layer 44 with the opening of the p-wire electrode layer 42 are formed.

[0130] Next, as FIG. 6D As shown, an n-wire electrode layer 46 of a predetermined shape is formed on the insulating layer 44 and the opening 44a. In this embodiment, a resist pattern covering the exposed area of ​​the p-wire electrode layer 42 is formed. After forming a laminated film consisting of an Al film with a thickness of 0.3 μm, a Ti film with a thickness of 0.3 μm, and an Au film with a thickness of 1.0 μm using the EB (electron beam) vapor deposition method, the resist film and the laminated film on the resist film are removed by a stripping method, thereby forming the n-wire electrode layer 46 consisting of an Al layer, a Ti layer, and an Au layer. Here, in the n-wire electrode layer 46, a region is provided where one or more first n-connection members 51 are configured as conductive members for external electrical connection, namely one or more first n-terminal regions 51r. Furthermore, in the exposed area of ​​the p-wire electrode layer 42, a region is provided where p-connection members 60 are configured as conductive members for external electrical connection, namely p-terminal regions 60r.

[0131] Next, as FIG. 6E As shown, a seed metal film 56M is formed covering one or more first n-terminal regions 51r and p-terminal regions 60r. In this embodiment, a Ti film and an Au film are sequentially formed over the entire surface of the semiconductor stack 30, which includes one or more first n-terminal regions 51r and p-terminal regions 60r, using the EB method or sputtering method, thereby forming the seed metal film 56M.

[0132] Next, as FIG. 6F As shown, one or more first n-terminal regions 51r are formed respectively. Furthermore, a p-connector 60 is formed in the p-terminal region 60r. In this embodiment, a resist pattern with openings in one or more first n-terminal regions 51r and p-terminal regions 60r is formed using photolithography. After forming Au gold plating at the openings of the resist pattern using DC electrolytic gold plating, the resist film is removed.

[0133] Next, as FIG. 6GAs shown, the seed metal layer 56 is formed by removing the seed metal film 56M from the region where the first n connecting member 51 and the p connecting member 60 are not provided. In this embodiment, the Au film and the Ti film forming the seed metal film 56M are selectively etched to remove the seed metal film 56M. In this way, the seed metal layer 56 is formed.

[0134] Next, as shown in FIG. 6, the semiconductor light emitting element 20 is flip-chip bonded to the mounting substrate 11. In this embodiment, the first wiring electrode 15 and the second wiring electrode 16 composed of an Au layer are formed on the mounting substrate 11, and the one or more first n connecting members 51 and p connecting members 60 as Au bumps of the semiconductor light emitting element 20 are bonded to the first wiring electrode 15 and the second wiring electrode 16 of the mounting substrate 11, respectively. More specifically, the semiconductor light emitting element 20 is pressed against the mounting substrate 11, a load is applied, and the semiconductor light emitting element is heated to about 150°C, and ultrasonic vibration is applied. Accordingly, the one or more first n connecting members 51 and p connecting members 60 are solidly bonded to the first wiring electrode 15 and the second wiring electrode 16, respectively, to become one body. FIG. 6H As shown, the mounting substrate 11 is prepared, and the semiconductor light emitting element 20 is flip-chip bonded to the mounting substrate 11. In this embodiment, the first wiring electrode 15 and the second wiring electrode 16 composed of an Au layer are formed on the mounting substrate 12 to prepare the mounting substrate 11. Further, one or more first n connecting members 51 and p connecting members 60 as Au bumps of the semiconductor light emitting element 20 are bonded to the first wiring electrode 15 and the second wiring electrode 16 of the mounting substrate 11, respectively. More specifically, the semiconductor light emitting element 20 is pressed against the mounting substrate 11, a load is applied, and the semiconductor light emitting element is heated to about 150°C, and ultrasonic vibration is applied. Accordingly, the one or more first n connecting members 51 and p connecting members 60 are solidly bonded to the first wiring electrode 15 and the second wiring electrode 16, respectively, to become one body.

[0135] As described above, the semiconductor light emitting device 10 according to this embodiment is manufactured.

[0136] [1-4. Structure of first n connecting member and first n terminal region]

[0137] Next, the structure of the first n connecting member 51 and the first n terminal region 51r of the semiconductor light emitting device 10 manufactured by the above-described manufacturing method will be described. First, regarding the particle diameter and the hardness of the first n connecting member 51, the relationship between the average particle diameter and the hardness of Au is shown in FIG. 7. FIGS. 7-9 The relationship between the particle diameter and the hardness of Au is shown in FIG. 7. FIG. 7 The relationship between the particle diameter and the hardness of Au is shown in FIG. 7. FIG. 8 The measurement method of the particle diameter is shown in FIG. 8. FIG. 9 The relationship between the particle diameter and the thickness of the first n connecting member 51 when crushed is shown in FIG. 9.

[0138] As described above, the semiconductor light emitting device 10 according to this embodiment is manufactured. FIG. 7 As shown, the larger the average particle diameter of the first n connecting member 51, the lower the hardness. In general, the particle diameter and the hardness of a metal have a negative correlation.

[0139] In this case, the hardness of the metal depends on the amount of plastic deformation of the metal when a load is applied. Further, the amount of plastic deformation is affected by the length of the mobile, the propagation, and the obstacle to the movement, the length of the slip surface, and the direction of the metal crystal.

[0140] A metal crystal having a large particle diameter, a long length of a slip line, if stress is applied, stress is concentrated on a crystal boundary, plastic deformation easily occurs near the same. That is, a metal crystal having a large particle diameter is soft.

[0141] Here, a method of measuring the particle diameter of the first n-connecting member 51 used in the present embodiment is shown below. In the present embodiment, after a cross section of the first n-connecting member 51 is formed, a method of cutting off is applied to measure the particle diameter with respect to an observation area observed in a Scanning Ion Microscopy image (SIM image) of a scanning electron microscope.

[0142] At this time, as FIG. 8 shown, in a case where a crystal having an average particle diameter d exists n times per one side in a square of L, the area of the square becomes L 2 , and the area of one crystal grain becomes π(d / 2) 2 . Also, in a case where the observation area is large with respect to the crystal grain, n 2 crystal grains exist in the square, and thus the area occupied by all the crystal grains becomes n 2 x π(d / 2) 2 , and becomes the area of the square = the area occupied by all the crystal grains, and thus becomes L 2 = n 2 x π(d / 2) 2 . If it is expressed as d, it can be expressed by a relational expression of d = 2L / n / (π) 1 / 2 . Using this relational expression, the number of crystal boundaries intersecting a straight line drawn in the observation area L x L (dotted line of the point FIG. 8 ) is taken as the number n of the crystal, and the average particle diameter d of the first n-connecting member 51 is found. Also, in FIG. 8 , the straight line of the dotted line intersects six crystal boundaries, and thus becomes n = 6.

[0143] As FIG. 9 shown, in a case where the thickness is about 8 μm and the particle diameter is about 2.6 μm in a state where the load with respect to the first n-connecting member 51 is 0 N, in a state where the load is 10 N, the thickness becomes about 5 μm and the particle diameter becomes about 1.6 μm. Further, in a state where the load with respect to the first n-connecting member 51 is 35 N, the thickness becomes about 3.8 μm and the particle diameter becomes about 0.9 μm. In this way, the first n-connecting member 51 decreases in particle diameter as the load increases. According to the graph shown in FIG. 7 , in a case where the particle diameter of the first n-connecting member 51 decreases, the hardness increases. In this way, the first n-connecting member 51 is crushed at the time of mounting, and accordingly, the particle diameter of the first n-connecting member 51 decreases and the hardness increases. In the present embodiment, as FIG. 6FAs shown, in a cross section parallel to the stacking direction, the height on the opening portion 44a of the one or more first n-connection members 51 is lower than the height on the p-type layer 36 at the time of mounting. That is, the one or more first n-connection members 51 are recessed on the opening portion 44a. Therefore, in mounting the semiconductor light emitting element 20 on the mounting substrate 11, the particle diameter of the region on the p-type layer 36 of the one or more first n-connection members 51 is smaller than the particle diameter of the region on the opening portion 44a of the one or more first n-connection members 51. Therefore, in the semiconductor light emitting element 20 according to the present embodiment, in a cross section parallel to the stacking direction, the particle diameter on the opening portion 44a of the one or more first n-connection members 51 is larger than the particle diameter on the p-type layer 36.

[0144] Also, in the semiconductor light emitting element 20 according to the present embodiment, the particle diameter of the one or more first n-connection members 51 as the Au-plated layer is larger than the particle diameter of the n-wiring electrode layer 46 composed of the Au layer formed by the EB evaporation method.

[0145] Thus, by setting the particle diameter of the one or more first n-connection members 51 to be larger than the n-wiring electrode layer 46, the hardness of the one or more first n-connection members 51 can be set to be lower than the hardness of the n-wiring electrode layer 46. Therefore, in mounting the semiconductor light emitting element 20 on the mounting substrate 11, the force applied to the semiconductor light emitting element 20 can be absorbed by the one or more first n-connection members 51. Therefore, in the semiconductor light emitting element 20 according to the present embodiment, the force applied to the insulating layer 44 at the inner side surface portion of the n-exposed portion 30e at the time of mounting can be reduced compared to the case where the particle diameter of the one or more first n-connection members 51 is the same as the n-wiring electrode layer 46, and thus, the breakage of the insulating layer 44 can be suppressed.

[0146] Next, the structure of the one or more first n-connection members 51 according to the present embodiment will be described with reference to FIG. 10 FIG. 6. FIG. 10 is a schematic cross-sectional view showing the structure of the first n-connection member 51 of the semiconductor light emitting device 10 according to the present embodiment.

[0147] As FIG. 10 As shown, the end portion 51e in the bonding surface with the first wiring electrode 15 of the first n-connection member 51 is disposed apart from the end portion 15e of the first wiring electrode 15 of the mounting substrate 11 on the inner side of the first wiring electrode 15. In other words, the end portion 51e in the bonding surface with the first wiring electrode 15 of the first n-connection member 51 does not extend to the end portion 15e of the first wiring electrode 15.

[0148] Thus, the first n connecting member 51 is not disposed at the end portion 15e of the first wiring electrode 15, whereby the first n connecting member 51 can be prevented from short-circuiting with the adjacent second wiring electrode 16 and the p connecting member 60.

[0149] Such a structure of the first n connecting member 51 is achieved as described above by crushing the first n connecting member 51 to be joined with the first wiring electrode 15. On the other hand, for example, in a case where the first n connecting member 51 is melted to be joined with the first wiring electrode 15 using a solder having a low melting point as the first n connecting member 51, the melted first n connecting member 51 spreads to the end portion 15e of the first wiring electrode 15. Thus, the first n connecting member 51 is easily short-circuited with the second wiring electrode 16 and the p connecting member 60.

[0150] Also, as FIG. 10 It is shown that, in a cross section parallel to the stacking direction, the side wall 51w of the first n connecting member 51 can spread outward more as it approaches the n wiring electrode layer 46 on the n wiring electrode layer 46 side. That is, the first n connecting member 51 can form a rounded corner on the n wiring electrode layer 46 side.

[0151] Thus, the side wall 51w of the first n connecting member 51 spreads, whereby the area of the first n terminal region 51r can be enlarged as compared with a case where the side wall 51w does not spread. Thus, the first n connecting member 51 can perform heat dissipation over a wider area. Thus, the heat dissipation property of the semiconductor light emitting device 10 can be improved.

[0152] Here, for example, the first n connecting member 51 can be formed by a manufacturing method as follows, FIG. 10 the shape of the side wall 51w of the first n connecting member 51 shown in

[0153] First, after the semiconductor light emitting element shown in FIG. 6G is performed, the semiconductor light emitting element is subjected to heat treatment at 150°C for one hour in an atmosphere. Thus, the first n connecting member 51n and the wiring electrode layer 46 are each recrystallized, whereby the particle diameter is enlarged. In a case where the first n connecting member 51 subjected to such heat treatment is pressed against the mounting substrate 11 and joined, the hardness of the region of the n wiring electrode layer 46 side of the first n connecting member 51, where the particle diameter is large, is lower than that of the region of the mounting substrate 11 side, and thus is crushed to a large extent. Thus, the side wall 51w of the region of the n wiring electrode layer 46 side of the first n connecting member 51 spreads more outward than the side wall 51w of the region of the mounting substrate 11 side. Thus, the shape of the side wall 51w of the first n connecting member 51 shown in FIG. 10

[0154] ​Next, for the region of the n-wiring electrode layer 46 in which one or more first n-connection members 51 are arranged, i.e., one or more first n-terminal regions 51r, the following is described. FIG. 11A and FIG. 11B are plan views showing respective positional relationships between the first n-terminal region 51r and the opening portion 44a in the embodiment. FIG. 11A and FIG. 11B are plan views showing respective positional relationships between the first n-terminal region 51r and the opening portion 44a in the embodiment. FIG. 11A and FIG. 11B are plan views showing respective positional relationships between the first n-terminal region 51r and the opening portion 44a in the embodiment.

[0155] As FIG. 11A shown in the plan view of the n-wiring electrode layer 46, the center 51rc of the first n-terminal region 51r is within the region of the opening portion 44a.

[0156] Thus, by arranging the center 51rc of the first n-terminal region 51r within the region of the opening portion 44a, the central portion of the conductive member such as the first n-connection member 51 arranged in the first n-terminal region 51r is arranged in the opening portion 44a. Therefore, many of the forces applied to the conductive member at the time of mounting are applied to the opening portion 44a in which the insulating layer 44 is not arranged. Thus, the forces applied to the insulating layer 44 at the time of mounting can be reduced, and thus, the breakage of the insulating layer 44 can be suppressed. Also, in this case, in the case where the shape of the first n-terminal region 51r is circular, the center 51rc of the first n-terminal region 51r is the center of the circle. Also, in the case where the shape of the first n-terminal region 51r is not circular, for example, the center of gravity of the first n-terminal region 51r can be set as the center 51rc of the first n-terminal region 51r.

[0157] Also, as FIG. 11B shown in the plan view of the n-wiring electrode layer 46, the center 51rc of the first n-terminal region 51r can coincide with the center 44ac of the opening portion 44a.

[0158] Thus, by making the center 51rc of the first n-terminal region 51r coincide with the center 44ac of the opening portion 44a, the central portion of the conductive member such as the first n-connection member 51 arranged in the first n-terminal region 51r is arranged in the center 44ac of the opening portion 44a. Therefore, many of the forces applied to the conductive member at the time of mounting are applied to the opening portion 44a in which the insulating layer 44 is not arranged. Thus, the forces applied to the insulating layer 44 at the time of mounting can be reduced, and thus, the breakage of the insulating layer 44 can be suppressed.

[0159] Further, in this embodiment, the center 44ac of the opening portion 44a is set as the center of gravity of the opening portion 44a, as with the center 51rc of the first n-terminal region 51r. Further, the state prescribed by the description that the center 51rc coincides with the center 44ac includes not only the state in which the center 51rc completely coincides with the center 44ac, but also the state in which the centers substantially coincide. For example, the state prescribed by the description that the center 51rc coincides with the center 44ac includes the state in which the distance between the center 51rc and the center 44ac is about 5% or less of the maximum dimension of the opening portion 44a.

[0160] [1-5. Modified example 1]

[0161] Next, the semiconductor light emitting element to which the modified example 1 of the present embodiment relates will be described with reference to FIG. 12 and FIG. 13 . FIG. 12 and FIG. 13 are plan views and cross-sectional views showing the structure of the semiconductor light emitting element 20a to which the present modified example relates. FIG. 12 shows a plan view in the planar view of the n-wiring electrode layer 46 of the semiconductor light emitting element 20a. FIG. 13 shows a part of the cross section of the XIII-XIII line of FIG. 12 .

[0162] As FIG. 12 and FIG. 13 shows the semiconductor light emitting element 20a to which the present modified example relates, the semiconductor light emitting element 20 to which the embodiment 1 relates is different in that the first n-connection members 51b and 51s have different sizes. In the semiconductor light emitting element 20a, the first n-terminal regions 51rb and 51rs corresponding to the first n-connection members 51b and 51s, respectively, are set. In the semiconductor light emitting element 20a, in the planar view of the n-wiring electrode layer 46, the area of each of the one or more first n-terminal regions is larger closer to the end portion 20ae of the semiconductor light emitting element 20a. In FIG. 12 and FIG. 13 , the area of the first n-terminal region 51rb closer to the end portion 20ae of the semiconductor light emitting element 20a is larger than the area of the first n-terminal region 51rs farther from the end portion 20ae with respect to the first n-terminal region 51rb.

[0163] In the central portion of the semiconductor light emitting element 20a, the connecting member that becomes the heat dissipation path exists in all directions, and for this reason, in the edge portion of the semiconductor light emitting element 20a, the connecting member that becomes the heat dissipation path exists only in the inner direction, and thus, the heat dissipation property can be lowered in the edge portion of the semiconductor light emitting element 20a. However, in the semiconductor light emitting element 20a according to the present modified example, the area of the first n terminal region 51rb close to the end portion 20ae is enlarged, and thus, the heat dissipation path can be increased, and thus, the heat dissipation property of the edge portion can be improved.

[0164] [1-6. Modified example 2]

[0165] Next, the semiconductor light emitting element according to the modified example 2 of the present embodiment will be described with reference to FIG. 14 and FIG. 15 . FIG. 14 and FIG. 15 are plan views and cross-sectional views showing the structure of the semiconductor light emitting element 20b according to the present modified example. FIG. 14 shows a plan view in the planar view of the n wiring electrode layer 46 of the semiconductor light emitting element 20b. FIG. 15 shows FIG. 14 a part of the cross section of the XV-XV line.

[0166] As FIG. 14 and FIG. 15 show, the semiconductor light emitting element 20b according to the present modified example differs from the semiconductor light emitting element 20 according to the embodiment 1 in that the opening portions 44ab and 44as have different sizes.

[0167] In the semiconductor light emitting element 20b, in the planar view of the n wiring electrode layer 46, the area of the opening portion is larger on the side closer to the end portion 20be of the semiconductor light emitting element 20b. In FIG. 14 and FIG. 15 , the area of the opening portion 44ab closer to the end portion 20be of the semiconductor light emitting element 20b is larger than the opening portion 44as farther from the end portion 20be with respect to the opening portion 44ab. Thus, in the present modified example, the area of the n exposed portion 30eb closer to the end portion 20be of the semiconductor light emitting element 20b is larger than the n exposed portion 30es farther from the end portion 20be with respect to the n exposed portion 30eb.

[0168] As described in the modified example 1 of the present embodiment, in the edge portion of the semiconductor light emitting element 20b, the heat dissipation property can be lowered. However, in the semiconductor light emitting element 20b according to the present modified example, the area of the opening portion 44ab closer to the end portion 20be is enlarged, and thus, the heat generation source can be dispersed, and the heat dissipation path can be increased, and thus, the heat dissipation property of the edge portion can be improved.

[0169] (Implementation Method 2)

[0170] The semiconductor light-emitting element and semiconductor light-emitting device according to Embodiment 2 will be described. The semiconductor light-emitting element and semiconductor light-emitting device according to this embodiment differ from those according to Embodiment 1 in that, in addition to the first n-terminal region, it also has a second n-terminal region where a second n-connecting member is disposed. Hereinafter, the semiconductor light-emitting element and semiconductor light-emitting device according to this embodiment will be described focusing on the differences between them and those according to Embodiment 1.

[0171] [2-1. Overall Structure]

[0172] First, regarding the structure of the semiconductor light-emitting element involved in this embodiment, using... FIG. 16 as well as FIG. 17 Please provide an explanation. FIG. 16 as well as FIG. 17 These are schematic plan views and cross-sectional views showing the overall structure of the semiconductor light-emitting element 120 according to this embodiment. FIG. 16 A plan view of the wiring electrode layer 46 of the semiconductor light-emitting element 120n is shown. FIG. 17 Show FIG. 16 A portion of the cross section of the semiconductor light-emitting element 120 of the XVII-XVII line.

[0173] like FIG. 17 As shown, the semiconductor light-emitting element 120 according to this embodiment includes a growth substrate 22, a semiconductor stack 30, a p-wire electrode layer 42, an insulating layer 44, and an n-wire electrode layer 46. In this embodiment, the semiconductor light-emitting element 120 also includes a plurality of seed metal layers 56, one or more first n-connection members 51, one or more second n-connection members 152, and a p-connection member 60.

[0174] One or more second n-connecting members 152 are conductive members for external electrical connection. Each of the one or more second n-connecting members 152 is connected to the n-wiring electrode layer 46 in one or more second n-terminal regions 152r disposed on the n-wiring electrode layer 46 other than the n-exposed portion 30e. In other words, one or more second n-terminal regions 152r are provided on the n-wiring electrode layer 46 other than the n-exposed portion 30e as regions for configuring conductive members for external electrical connection. Furthermore, in this embodiment, a seed metal layer 56 is also disposed between the second n-connecting member 152 and the n-wiring electrode layer 46. The number of second n-connecting members 152 is not particularly limited if there is one or more. For example, the number of second n-connecting members 152 may also be multiple.

[0175] Further, although not shown in the drawings, the semiconductor light emitting element 120 according to the present embodiment is mounted to the mounting substrate 11 according to Embodiment 1, and thus a semiconductor light emitting device can be formed.

[0176] [2-2. Action and Effect]

[0177] Next, the action and effect of the semiconductor light emitting element 120 according to the present embodiment will be described.

[0178] As described above, on the n-wiring electrode layer 46 disposed outside the exposed portion 30e of the semiconductor light emitting element 120n according to the present embodiment, one or more second n-terminal regions 152r are provided as regions in which the conductive member configured to be electrically connected to the outside is disposed. Further, the number of the second n-terminal regions 152r is not particularly limited if it is one or more. For example, the number of the second n-terminal regions 152r can also be a plurality.

[0179] Thus, by providing the second n-terminal regions 152r, in the case where the conductive member such as the second n-connecting member 152 is disposed on the second n-terminal regions 152r, a heat dissipation path other than the heat dissipation path of the semiconductor light emitting element 20 according to Embodiment 1 can also be formed, and thus the heat dissipation of the semiconductor light emitting element 120 can be further improved compared to the semiconductor light emitting element 20 according to Embodiment 1.

[0180] Next, the structure of the one or more first n-terminal regions 51r and the one or more second n-terminal regions 152r of the semiconductor light emitting element 120 according to the present embodiment will be described in detail with reference to FIG. 18 and FIG. 19 FIG. 18 is a plan view showing the n-wiring electrode layer 46 disposed outside the n-exposed portion 30e according to the present embodiment. FIG. 19 is a plan view showing the first n-terminal regions 51r and the second n-terminal regions 152r according to the present embodiment.

[0181] In the present embodiment, in a plan view of the n-wiring electrode layer 46, FIG. 19 the sum of the areas of the one or more first n-terminal regions 51r and the one or more second n-terminal regions 152r shown in FIG. 18 is greater than the sum of the areas of the n-wiring electrode layer 46 disposed outside the n-exposed portion 30e shown in

[0182] ​Thus, the area of the first n-terminal region 51r and the second n-terminal region 152r is enlarged, and accordingly, in a case where the electrically conductive member is arranged in the first n-terminal region 51r and the second n-terminal region 152r, the heat dissipation path can be increased, and thus, the heat dissipation property of the semiconductor light emitting element 120 can be improved.

[0183] Also, in the present embodiment, as FIG. 16 and FIG. 17 are shown, the one or more first n-connection members 51 are apart from the one or more second n-connection members 152. Thus, the first n-connection members 51 are apart from the second n-connection members 152, and accordingly, at the time of mounting, the mounting load can be dispersed, and the breakage of the insulating layer 44 can be suppressed.

[0184] [2-3. Simulation results]

[0185] Next, the heat dissipation property of the semiconductor light emitting element 120 according to the present embodiment will be described using simulation results.

[0186] FIG. 20A and FIG. 20B are schematic plan views showing the structure of the semiconductor light emitting element according to the present embodiment and the comparative example used in the simulation, respectively. As FIG. 20A is shown, the semiconductor light emitting element 120 used in the present simulation has 42 first n-connection members 51, 36 second n-connection members 152, and 8 p-connection members 60. Also, in order to explain the effect of the semiconductor light emitting element 120 according to the present embodiment, the semiconductor light emitting element according to the comparative example is also simulated. The semiconductor light emitting element 1120 according to the comparative example is the same as the semiconductor light emitting element 120 according to the present embodiment except that it does not have the first n-connection members 51a. FIG. 20B is shown, the semiconductor light emitting element 120 according to the present embodiment is different from the semiconductor light emitting element 1120 according to the comparative example in that it does not have the first n-connection members 51a, and is the same in other respects.

[0187] The simulation results of each of the semiconductor light emitting elements shown in FIG. 20A and FIG. 20B will be described using FIG. 21 and FIG. 22 . FIG. 21 is a graph showing the simulation results of the heat generation distribution and the temperature distribution of each of the semiconductor light emitting elements according to the present embodiment and the comparative example. In FIG. 21 , the maximum value of the heat generation amount, and the maximum value and the average value of the temperature are also shown. FIG. 22 is a graph showing the simulation results of the relationship between the maximum value of the temperature Tj of the light emitting layer 34 and the current amount of each of the semiconductor light emitting elements according to the present embodiment and the comparative example.

[0188] The simulation was performed on the light emission output, voltage, and temperature distribution of the GaN-based LED using the one-dimensional band structure in the semiconductor layer and software capable of calculating the three-dimensional current distribution and temperature distribution. The growth substrate 22 of each semiconductor light emitting element involved in the present embodiment and comparative example was set to a sapphire substrate having a thickness of 100 μm and a thermal conductivity of 50 W / m / K, the semiconductor layer stack 30 was set to GaN having a thickness of 12 μm and a thermal conductivity of 120 W / m / K, the first n connecting member 51, the second n connecting member 152, and the p connecting member 60 were set to Au having a thickness of 15 μm and a thermal conductivity of 300 W / m / K. Further, the substrate 12 of the mounting substrate 11 on which each semiconductor light emitting element was mounted was set to AlN having a thickness of 300 μm and a thermal conductivity of 170 W / m / K. Furthermore, the simulation was performed under the condition that a heat sink having a thickness of 2 mm, a thermal conductivity of 400 W / m / K, and a temperature Tc of 105°C was in contact with the entire main surface of the mounting substrate 11 on the side on which each semiconductor light emitting element was not mounted. Further, the temperature Tj of the light emitting layer 34 when a voltage was applied to the light emitting layer 34 of the semiconductor layer stack 30 of each semiconductor light emitting element and a current of 1 A to 6 A was supplied was calculated.

[0189] As FIG. 21 the upper paragraph shows, in each semiconductor element involved in the present embodiment and comparative example, the heat generation was concentrated in the n-exposed portion 30e in which case. The average value of the heat generation per unit time was 7.7 x 10 5 W / cm 3 in the comparative example, and 7.9 x 10 5 W / cm 3 in the present embodiment, and the maximum value of the heat generation per unit time was 3.9 x 10 6 W / cm 3 in the comparative example, and 4.0 x 10 6 W / cm 3 in the present embodiment, and the values were equivalent.

[0190] However, the temperature of the semiconductor light emitting element 120 involved in the present embodiment was suppressed compared to the semiconductor light emitting element 1120 involved in the comparative example.

[0191] Specifically, as FIG. 21 the lower paragraph shows, in the semiconductor light emitting element 1120 involved in the comparative example, the temperature Tj of the light emitting layer was high in the vicinity of the n-exposed portion 30e, and became 150°C to 165°C, and exceeded 170°C in the edge portion of the semiconductor light emitting element 1120.

[0192] On the other hand, in the semiconductor light emitting element 120 according to the present embodiment, the temperature Tj near the n-exposed portion 30e is 115°C, and the temperature of the edge portion is also suppressed to 135°C or lower. Thus, in the semiconductor light emitting element 120 according to the present embodiment, the temperature is suppressed because heat is efficiently dissipated from the n-exposed portion 30e to the mounting substrate 11 and the heat sink via the first n-connection member 51 disposed at the n-exposed portion 30e having a large amount of heat generation.

[0193] Also, as FIG. 22 shown, the semiconductor light emitting element 120 according to the present embodiment can more suppress the temperature Tj of the light emitting layer for each current supply than the semiconductor light emitting element according to the comparative example. Here, it is known that in a semiconductor light emitting element, if the temperature Tj of the light emitting layer 34 exceeds 150°C, the reliability is significantly damaged. In the semiconductor light emitting element according to the comparative example, if the amount of supplied current becomes 4 A or more, the temperature Tj of the light emitting layer 34 exceeds 150°C, and thus the reliability is damaged. On the other hand, in the semiconductor light emitting element 120 according to the present embodiment, the temperature Tj of the light emitting layer is suppressed to 150°C or lower in any case where the amount of supplied current is 0 A to 6 A. Thus, according to the semiconductor light emitting element 120 according to the present embodiment, the temperature rise of the light emitting layer 34 can be suppressed because one or more first n-connection members 51 are provided.

[0194] [2-4. Manufacturing method]

[0195] Next, the manufacturing method of the semiconductor light emitting element 120 according to the present embodiment will be described with reference to FIGS. 23A-23C FIG. 9. FIGS. 23A-23C is a schematic cross-sectional view showing each process of the manufacturing method of the semiconductor light emitting element 120 according to the present embodiment.

[0196] First, as with the manufacturing method of the semiconductor light emitting element 20 according to Embodiment 1, as FIG. 23A shown, the semiconductor layer stack 30, the p-wiring electrode layer 42, the insulating layer 44, the n-wiring electrode layer 46, and the seed metal film 56M are sequentially formed on the growth substrate 22. Here, on the n-wiring electrode layer 46, one or more first n-terminal regions 51r and one or more second n-terminal regions 152r as regions where conductive members for external electrical connection are disposed are defined. Also, on the p-wiring electrode layer 42, a p-terminal region 60r as a region where a conductive member for external electrical connection is disposed is defined.

[0197] Next, as FIG. 23BAs shown, one or more first n terminal regions 51r are formed in one or more first n terminal regions 51, and one or more second n terminal regions 152r are formed in one or more second n terminal regions 152. Also, a connection member 60 is formed in a p terminal region 60r. In this embodiment, a resist pattern is formed in the one or more first n terminal regions 51r, the one or more second n terminal regions 152r, and the p terminal region 60r opening by a photolithography technique, and after Au plating is formed in the opening of the resist pattern by a DC electrolytic gold plating method, the resist film is removed.

[0198] Next, as shown in FIG. 6A, a seed metal film 56M is formed in the one or more first n terminal regions 51r, the one or more second n terminal regions 152r, and the p terminal region 60r opening. FIG. 23C As shown, the regions of the seed metal film 56M in which the first n connection member 51, the second n connection member 152, and the p connection member 60 are not disposed are removed, thereby forming a seed metal layer 56. In this embodiment, the Au film and the Ti film forming the seed metal film 56M are selectively etched, thereby removing the seed metal film 56M. In this way, the seed metal layer 56 is formed.

[0199] As described above, the semiconductor light emitting element 120 according to the present embodiment is manufactured. Also, the semiconductor light emitting element 120 is mounted on the mounting substrate 11, thereby enabling the semiconductor light emitting device according to the present embodiment to be manufactured. Also, in the present embodiment, in addition to the one or more first n connection members 51, the one or more second n connection members 152 are also bonded to the first wiring electrode 15 of the mounting substrate 11.

[0200] (Embodiment 3)

[0201] The semiconductor light emitting element and the semiconductor light emitting device according to Embodiment 3 are described. The semiconductor light emitting device according to the present embodiment differs from the semiconductor light emitting device according to Embodiment 1 mainly in that the first n connection member and the p connection member are disposed to be bonded to the semiconductor light emitting element after the mounting substrate. Hereinafter, the semiconductor light emitting element and the semiconductor light emitting device according to the present embodiment are described focusing on the differences from the semiconductor light emitting element and the semiconductor light emitting device according to Embodiment 1.

[0202] [3-1. Overall Structure]

[0203] First, the structure of the semiconductor light emitting element and the semiconductor light emitting device according to the present embodiment is described using FIG. 10. FIG. 24 FIG. 24 is a schematic cross-sectional view showing the overall structure of the semiconductor light emitting device 210 according to the present embodiment. FIG. 24 is a cross-section of the semiconductor light emitting device 210 according to the present embodiment. FIG. 2A

[0204] As shown in FIG. 10, the semiconductor light emitting device 210 according to the present embodiment includes a mounting substrate 11, a semiconductor light emitting element 120, and a sealing resin 13.​​FIG. 24 As shown, the semiconductor light-emitting device according to this embodiment includes a mounting substrate 11 and a semiconductor light-emitting element 220.

[0205] The semiconductor light-emitting element 220 includes a growth substrate 22, a semiconductor laminate 30, a p-wire electrode layer 42, an insulating layer 44, and an n-wire electrode layer 46. In this embodiment, the semiconductor light-emitting element 220 also includes one or more first n-connection members 251 and p-connection members 260. In this embodiment, the one or more first n-connection members 251 and p-connection members 260 are formed after the mounting substrate 11 and bonded to the semiconductor light-emitting element 220; therefore, a seed metal layer 56 is not present.

[0206] Each of the above and one first n-connecting components 251 is a conductive component for external electrical connection. Each of the above and one first n-connecting components 251 is connected to the n-wiring electrode layer 46 in one or more first n-terminal regions 251r. In other words, the n-wiring electrode layer 46 has one or more first n-terminal regions 251r designated as areas for configuring conductive components for external electrical connection. Furthermore, the number of first n-connecting components 251 and first n-terminal regions 251r is not particularly limited if there is one or more. For example, the number of first n-connecting components 251 and first n-terminal regions 251r can also be multiple.

[0207] The p-connector 260 is a conductive component for external electrical connection. The p-connector 260 is connected to the p-wiring electrode layer 42 in the p-terminal region 260r. In other words, the p-terminal region 260r is defined in the p-wiring electrode layer 42 as a region for configuring the conductive component for external electrical connection.

[0208] In the semiconductor light-emitting device 210 according to this embodiment, the same effect as that of the semiconductor light-emitting device 10 according to Embodiment 1 can also be obtained.

[0209] [3-2. Manufacturing Method]

[0210] Next, regarding the manufacturing method of the semiconductor light-emitting device 210 according to this embodiment, using... FIGS. 25A-25C Please provide an explanation. FIGS. 25A-25C This is a schematic cross-sectional view showing the various steps of the manufacturing method of the semiconductor light-emitting device 210 according to this embodiment.

[0211] First, similar to the manufacturing method of the semiconductor light-emitting device 10 according to Embodiment 1, such as FIG. 25AAs shown, on the growth substrate 22, a semiconductor layer stack 30, a p-wiring electrode layer 42, an insulating layer 44, and an n-wiring electrode layer 46 are formed in this order. Here, on the n-wiring electrode layer 46, one or more first n-terminal regions 251r as regions where conductive members for electrical connection with the outside are arranged are provided. Also, on the p-wiring electrode layer 42, a p-terminal region 260r as a region where a conductive member for electrical connection with the outside is arranged is provided.

[0212] Next, as shown in FIG. 6, the semiconductor light emitting element 220 and the semiconductor light emitting device 210 are manufactured. FIG. 25B As shown, the mounting substrate 11 is prepared. In the present embodiment, one or more first n-connection members 251 and p-connection members 260 are formed on the first wiring electrode 15 and the second wiring electrode 16 of the mounting substrate 11, respectively.

[0213] Next, as shown in FIG. 6, the semiconductor light emitting element 220 and the semiconductor light emitting device 210 are manufactured. FIG. 25C As shown, the one or more first n-connection members 251 and p-connection members 260 formed on the mounting substrate 11 are joined to the one or more first n-terminal regions 251r of the n-wiring electrode layer 46 and the p-terminal region 260r of the p-wiring electrode layer 42, respectively.

[0214] As described above, the semiconductor light emitting element 220 and the semiconductor light emitting device 210 according to the present embodiment are manufactured.

[0215] [3-3. Modification]

[0216] Next, a modification of the semiconductor light emitting element and the semiconductor light emitting device according to the present embodiment will be described with reference to FIG. 7. FIG. 26A and FIG. 26B Next, a modification of the semiconductor light emitting element and the semiconductor light emitting device according to the present embodiment will be described with reference to FIG. 7. FIG. 26A is a schematic cross-sectional view showing the entire structure of the semiconductor light emitting device 210a according to the present modification.

[0217] As shown in FIG. 7, the semiconductor light emitting device 210a according to the present modification includes a mounting substrate 11 and a semiconductor light emitting element 220a. FIG. 26A As shown in FIG. 7, the semiconductor light emitting device 210a according to the present modification includes a mounting substrate 11 and a semiconductor light emitting element 220a.

[0218] The semiconductor light emitting element 220a includes a growth substrate 22, a semiconductor layer stack 30, a p-wiring electrode layer 42, an insulating layer 44, and an n-wiring electrode layer 46. In the present modification, the semiconductor light emitting element 220a further includes one or more first n-connection members 251a and p-connection members 260.

[0219] The one or more first n connecting members 251a are each a conductive member for electrical connection to the outside. The one or more first n connecting members 251a are each connected to the n wiring electrode layer 46 in the one or more first n terminal regions 251ar. In other words, the n wiring electrode layer 46 has the one or more first n terminal regions 251ar defined as regions in which the conductive members for electrical connection to the outside are disposed. Moreover, the number of the first n connecting members 251a and the first n terminal regions 251ar is not particularly limited if it is one or more. For example, the number of the first n connecting members 251a and the first n terminal regions 251ar can each be plural.

[0220] In the present modification, as between the one or more first n connecting members 251a and the n wiring electrode layer 46, FIG. 26A a hollow portion 251av is formed. Such a hollow portion 251av is formed when the first n connecting members 251a are joined to the n wiring electrode layer 46 after the first n connecting members 251a are formed in the mounting substrate 11. For example, the mounting load when the first n connecting members 251a are joined to the n wiring electrode layer 46 is set to be lower than when the first n connecting members 251 of the semiconductor light emitting device 210 according to Embodiment 3 are joined, thereby forming the hollow portion 251av.

[0221] As described above, in the one or more first n terminal regions 251ar of the semiconductor light emitting element 220a, there can be regions in which the one or more first n connecting members 251a are not connected.

[0222] Moreover, the shape of the hollow formed between the one or more first n connecting members 251a and the n wiring electrode layer 46 according to the present modification is not limited to FIG. 26A the example shown. For example, the hollow can be formed in the entire region above the opening portion 44a. For such an example of a hollow, a description will be given using FIG. 26B . FIG. 26B is a schematic cross-sectional view showing the entire structure of a semiconductor light emitting device 210b according to another modification of the present embodiment.

[0223] As FIG. 26B shown, the semiconductor light emitting element 220b included in the semiconductor light emitting device 210b has one or more first n connecting members 251b. The one or more first n connecting members 251b are each connected to the n wiring electrode layer 46 in the one or more first n terminal regions 251br.

[0224] In the semiconductor light emitting element 220b, a hollow portion 251bv is formed between the one or more first n connecting members 251b and the n wiring electrode layer 46. The semiconductor light emitting device 210b differs from the semiconductor light emitting device 210a in the structure of the one or more first n connecting members 251b and the hollow portion 251bv, and is otherwise identical. In the semiconductor light emitting device 210b, the hollow portion 251bv is formed in the entire region above the opening portion 44a. Such a hollow portion 251bv is formed when the first n connecting members 251b are joined to the n wiring electrode layer 46 after the first n connecting members 251b are formed in the mounting substrate 11. For example, the mounting load when the first n connecting members 251b are joined to the n wiring electrode layer 46 is set to be lower than when the first n connecting members 251 of the semiconductor light emitting device 210 related to Embodiment 3 are joined, and thus the hollow portion 251bv is formed in the entire region above the opening portion 44a.

[0225] As described above, even in the one or more first n terminal regions 251br of the semiconductor light emitting element 220b, in which the one or more first n connecting members 251b are not connected to the n wiring electrode layer 46, heat generated near the inner side surface of the n exposed portion can be diffused via the one or more first n connecting members 251b, and thus the heat dissipation of the semiconductor light emitting element can be improved.

[0226] In the semiconductor light emitting devices 210a and 210b related to this modification example, the same effects as the semiconductor light emitting device 10 related to Embodiment 1 can be obtained.

[0227] (Embodiment 4)

[0228] A semiconductor light emitting element and a semiconductor light emitting device related to Embodiment 4 are described. The semiconductor light emitting device related to this embodiment differs from the semiconductor light emitting device related to Embodiment 1 mainly in that the first n connecting member and the p connecting member are joined to each other after being disposed in both the semiconductor light emitting element and the mounting substrate. Hereinafter, the semiconductor light emitting element and the semiconductor light emitting device related to this embodiment are described focusing on the differences from the semiconductor light emitting element and the semiconductor light emitting device related to Embodiment 1.

[0229] [4-1. Overall Structure]

[0230] First, the structure of the semiconductor light emitting element and the semiconductor light emitting device related to this embodiment is described using FIG. 10. FIG. 27 is a schematic cross-sectional view showing the overall structure of a semiconductor light emitting device 310 related to this embodiment. FIG. 27 is a schematic cross-sectional view showing the overall structure of a semiconductor light emitting device 310 related to this embodiment. FIG. 27 is a schematic cross-sectional view showing the overall structure of a semiconductor light emitting device 310 related to this embodiment. FIG. 2AThe semiconductor light emitting device 10 of the present embodiment has the same cross section as the semiconductor light emitting device 10 of Embodiment 1.

[0231] As FIG. 27 As shown, the semiconductor light emitting device of the present embodiment includes a mounting substrate 11 and a semiconductor light emitting element 320.

[0232] The semiconductor light emitting element 320 includes a growth substrate 22, a semiconductor stack 30, a p-wiring electrode layer 42, an insulating layer 44, and an n-wiring electrode layer 46. In the present embodiment, the semiconductor light emitting element 320 further includes a seed metal layer 56, one or more first n-connection members 351, and a p-connection member 360.

[0233] The one or more first n-connection members 351 are each a conductive member for electrical connection to the outside. The one or more first n-connection members 351 are each connected to the n-wiring electrode layer 46 at one or more first n-terminal regions 351r. In other words, the n-wiring electrode layer 46 has one or more first n-terminal regions 351r defined as regions in which the conductive members for electrical connection to the outside are disposed. The number of first n-connection members 351 and first n-terminal regions 351r, if one or more, is not particularly limited. For example, the number of first n-connection members 351 and first n-terminal regions 351r can each be plural.

[0234] In the present embodiment, the first n-connection members 351 include a set of element-side n-connection members 51n and mounting substrate-side n-connection members 251n.

[0235] The element-side n-connection members 51n have the same structure as the first n-connection members 51 described in Embodiment 1. The mounting substrate-side n-connection members 251n have the same structure as the first n-connection members 251 described in Embodiment 3. The element-side n-connection members 51n are disposed closer to the semiconductor stack 30 than the mounting substrate-side n-connection members 251n.

[0236] The p-connection member 360 is a conductive member for electrical connection to the outside. The p-connection member 360 is connected to the p-wiring electrode layer 42 at a p-terminal region 360r. In other words, the p-wiring electrode layer 42 has the p-terminal region 360r defined as a region in which the conductive member for electrical connection to the outside is disposed.

[0237] In the present embodiment, the p-connection member 360 includes a set of element-side p-connection members 60p and mounting substrate-side p-connection members 260p.

[0238] The component-side p-connection member 60p has the same structure as the p-connection member 60 according to Embodiment 1. The substrate-side p-connection member 260p has the same structure as the p-connection member 260 according to Embodiment 3. The component-side p-connection member 60p is positioned closer to the semiconductor stack 30 than the substrate-side p-connection member 260p.

[0239] In the semiconductor light-emitting device 310 according to this embodiment, the same effect as that of the semiconductor light-emitting device 10 according to Embodiment 1 can also be obtained.

[0240] [4-2. Manufacturing Method]

[0241] Next, regarding the manufacturing method of the semiconductor light-emitting device 310 according to this embodiment, using... FIGS. 28A-28C Please provide an explanation. FIGS. 28A-28C This is a schematic cross-sectional view showing the various steps of the manufacturing method of the semiconductor light-emitting device 310 according to this embodiment.

[0242] First, similar to the manufacturing method of the semiconductor light-emitting device 10 according to Embodiment 1, such as FIG. 28A As shown, a semiconductor stack 30, a p-wire electrode layer 42, an insulating layer 44, an n-wire electrode layer 46, a seed metal layer 56, one or more device-side n-connection members 51n, and device-side p-connection members 60p are sequentially formed on a growth substrate 22. Here, one or more first n-terminal regions 351r are provided on the n-wire electrode layer 46 as regions for configuring conductive members for external electrical connection. And, on the p-wire electrode layer 42, p-terminal regions 360r are provided as regions for configuring conductive members for external electrical connection. Next, one or more device-side n-connection members 51n and device-side p-connection members 60p are formed on one or more first n-terminal regions 351r of the n-wire electrode layer 46 and on the p-terminal regions 360r of the p-wire electrode layer 42, respectively.

[0243] Next, as FIG. 28B As shown, the substrate 11 is prepared for mounting. In this embodiment, similar to the manufacturing method of the semiconductor light-emitting device 210 according to Embodiment 3, one or more substrate-side n-connection members 251n and substrate-side p-connection members 260p are formed on the first wiring electrode 15 and the second wiring electrode 16 of the substrate 11, respectively.

[0244] Next, one or more mounting substrate-side n-connection members 251n and mounting substrate-side p-connection members 260p formed on the mounting substrate 11 are respectively coupled to one or more element-side n-connection members 51n and element-side p-connection members 60p. Accordingly, as FIG. 28CAs shown, one or more first n-connection parts 351 and p-connection parts 360 are formed. Here, the one or more first n-connection parts 351 each include a set of element-side n-connection parts 51n and mounting substrate-side n-connection parts 251n, and the p-connection parts 360 include a set of element-side p-connection parts 60p and mounting substrate-side p-connection parts 260p.

[0245] As described above, the semiconductor light emitting element 320 and the semiconductor light emitting device 310 according to the present embodiment are manufactured.

[0246] (Modifications, etc.)

[0247] As described above, the semiconductor light emitting element and the semiconductor light emitting device according to the present disclosure have been described according to each of the embodiments, but the present disclosure is not limited to the above-described embodiments.

[0248] For example, in the above-described embodiments, the first n-terminal region provided on the n-wiring electrode layer 46 coincides with the region in which the first n-connection part is arranged on the n-wiring electrode layer 46, but they do not necessarily need to coincide. For example, the first n-connection part can not be arranged in the entire first n-terminal region, and a part of the first n-connection part can be arranged in a region other than the first n-terminal region.

[0249] Further, in the semiconductor light emitting element, the first n-terminal region, the second n-terminal region, and the p-terminal region provided in a state before the first n-connection part, the second n-connection part, and the p-connection part are arranged, for example, can be marked on the n-wiring electrode layer and the p-wiring electrode layer of the semiconductor light emitting element, and can be indicated in a specification or the like of the semiconductor light emitting element.

[0250] Further, a configuration obtained by applying various modifications to the above-described embodiments, or a configuration obtained by arbitrarily combining the constituent elements and functions of the above-described embodiments within a range not departing from the gist of the present disclosure, is also included in the present disclosure.

[0251] The semiconductor light emitting element and the semiconductor light emitting device according to the present disclosure can be applied to a projector or the like as a light source having, for example, high output and high efficiency.

[0252] KEY

[0253] 10, 10b, 210, 210a, 210b, 310 semiconductor light emitting device

[0254] 11 mounting substrate

[0255] 12 substrate

[0256] 15 first wiring electrode

[0257] 15e, 20ae, 20be, 51e end portion

[0258] 16 second wiring electrode

[0259] 20, 20a, 20b, 120, 220, 220a, 220b, 320, 1120 semiconductor light emitting element

[0260] 22 growth substrate

[0261] 30 semiconductor stack

[0262] 30b bottom surface

[0263] 30e, 30eb, 30es n-exposed portion

[0264] 30s inner side surface

[0265] 32 n-type layer

[0266] 34 light emitting layer

[0267] 36 p-type layer

[0268] 42 p-wiring electrode layer

[0269] 44 insulating layer

[0270] 44a, 44ab, 44as opening portion

[0271] 44ac, 51rc center

[0272] 46 n-wiring electrode layer

[0273] 51, 51b, 51s, 251, 251a, 251b, 351 first n-connection member

[0274] 51n element-side n-connection member

[0275] 51r, 51rb, 51rs, 251ar, 251br, 251r, 351r first n-terminal region

[0276] 51w side wall

[0277] 56 seed metal layer

[0278] 56M seed metal film

[0279] 60, 260, 360 p-connection member

[0280] 60p element-side p-connection member

[0281] 60r, 260r, 360r p-terminal region

[0282] 152 second n connecting member

[0283] 152r second n terminal region

[0284] 251av, 251bv hollow portion

[0285] 251n mounting substrate side n connecting member

[0286] 260p mounting substrate side p connecting member

Claims

1. A semiconductor light-emitting device, comprising a semiconductor light-emitting element and a mounting substrate having a first wiring electrode and a second wiring electrode, The semiconductor light-emitting element has: A semiconductor stack has an n-type layer, a light-emitting layer disposed above the n-type layer, and a p-type layer disposed above the light-emitting layer, the semiconductor stack having one or more n-exposed portions as recesses exposed by the n-type layer; p-wire electrode layer is disposed on the p-type layer; An insulating layer continuously covers the inner side surface of the one or more n-exposed portions and a portion above the p-wire electrode layer, and has an opening on the bottom surface of the one or more n-exposed portions that exposes the n-type layer. An n-type wiring electrode layer is in contact with the n-type layer at the opening and is disposed above the p-type layer and the p-type wiring electrode layer via the insulating layer; as well as As one or more first n connecting components for electrical connection with the outside, The one or more first n-connection components are bumps made of Au, which are solid-state bonded to the n-wiring electrode layer in one or more first n-terminal regions to form a single unit. In the plan view, the more than one first n-terminal region includes at least a portion of the region above the opening. In a cross-section parallel to the stacking direction of the semiconductor stack, below the one or more first n-terminal regions, the n-wiring electrode layer and the p-type layer are disposed. The one or more first n-connection components are coupled to the first wiring electrode of the mounting substrate. The p-wire electrode layer, in the region exposed from the n-wire electrode layer and the insulating layer, is bonded to the second wiring electrode of the mounting substrate via a p-connection member that serves as a conductive component. The particle size of the end of each of the more than one first n-connecting components that is closer to the n-wiring electrode layer is larger than the particle size of the end that is farther away from the n-wiring electrode layer.

2. The semiconductor light-emitting device as described in claim 1, It also has one or more second n connecting parts as conductive parts for external electrical connection. The one or more second n-connection components are respectively connected to the n-wiring electrode layer in one or more second n-terminal regions of the n-wiring electrode layer that are disposed outside the one or more n-exposed portions.

3. The semiconductor light-emitting device as described in claim 2, The one or more first n connecting parts are separated from the one or more second n connecting parts.

4. The semiconductor light-emitting device according to any one of claims 1 to 3, The particle size of the one or more first n-connection components is larger than the particle size of the n-wired electrode layer.

5. The semiconductor light-emitting device according to any one of claims 1 to 3, have: The p-connection component is disposed in the p-wiring electrode layer, in the region exposed from the n-wiring electrode layer and the insulating layer; and A seed metal layer is disposed between one or more first n-connection components and the n-wiring electrode layer, and between the p-connection component and the p-wiring electrode layer. The surface of the seed metal layer on the side furthest from the semiconductor stack is composed of Au. The one or more first n connecting components and the p connecting component are composed of Au.

6. The semiconductor light-emitting device according to any one of claims 1 to 3, have: The p-connection component is disposed in the p-wiring electrode layer, in the region exposed from the n-wiring electrode layer and the insulating layer; and A void is formed between one or more first n-connection components and the n-wire electrode layer.

7. The semiconductor light-emitting device according to any one of claims 1 to 3, It has a p-connection component, which is disposed in the p-wiring electrode layer in a region exposed from the n-wiring electrode layer and the insulating layer. The one or more first n-connection components each include a set of element-side n-connection components and a set of substrate-side n-connection components. The p-connection component includes a set of element-side p-connection components and a substrate-side p-connection component. The component-side n-connection is positioned closer to the semiconductor stack than the substrate-side n-connection. The element-side p-connection is positioned closer to the semiconductor stack than the mounting substrate-side p-connection.

8. The semiconductor light-emitting device according to any one of claims 1 to 3, The ends of the mating surfaces of the one or more first n connecting members and the first wiring electrode are configured to be separated from the ends of the first wiring electrode on the mounting substrate, inside the first wiring electrode.

9. The semiconductor light-emitting device according to any one of claims 1 to 3, In a cross section parallel to the stacking direction, the particle size at the opening of one or more first n-connecting components is larger than the particle size at the p-type layer.

10. The semiconductor light-emitting device according to any one of claims 1 to 3, In a cross section parallel to the stacking direction, the sidewalls of the one or more first n-connection components extend outward the closer they are to the n-wired electrode layer.

11. The semiconductor light-emitting device according to any one of claims 1 to 3, In a plan view of the n-wired electrode layer, the total area of ​​the one or more first n-terminal regions is larger than the total area of ​​the n-wired electrode layer disposed outside the one or more n-exposed portions.

12. The semiconductor light-emitting device according to any one of claims 1 to 3, In a plan view of the n-wire electrode layer, the area of ​​each of the more than one first n-terminal regions is larger for the first n-terminal region closer to the end of the semiconductor light-emitting element.

13. The semiconductor light-emitting device according to any one of claims 1 to 3, In a plan view of the n-wire electrode layer, the opening closer to the end of the semiconductor light-emitting element has a larger area.

14. The semiconductor light-emitting device according to any one of claims 1 to 3, In a plan view of the n-wired electrode layer, the center of the one or more first n-terminal regions is located within the region of the opening.

15. The semiconductor light-emitting device according to any one of claims 1 to 3, In a plan view of the n-wired electrode layer, the center of the one or more first n-terminal regions coincides with the center of the opening.

16. The semiconductor light-emitting device as claimed in claim 11, On the n-wire electrode layer, which is configured outside the one or more n-exposed portions, one or more second n-terminal regions are set as areas for conductive components configured for electrical connection with the outside.

17. The semiconductor light-emitting device as claimed in claim 14, On the n-wire electrode layer, which is configured outside the one or more n-exposed portions, one or more second n-terminal regions are set as areas for conductive components configured for electrical connection with the outside.

18. The semiconductor light-emitting device according to any one of claims 1 to 3, The particle size of the end of each of the more than one first n-connecting components that is farthest from the n-wired electrode layer is 0.9 μm or more and 2.6 μm or less.

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