A soft-switching control method for a dual-input photovoltaic DC circuit

Abstract

This invention relates to a soft-switching control method for a dual-input photovoltaic DC circuit. The circuit is a dual-input single-inductor buck converter, which includes a first DC input and a second DC input, and outputs DC power through switching transistors, inductors, and an output capacitor. The soft-switching control method includes: controlling the switching cycle of the switching transistors to achieve soft turn-on of all transistors, ensuring that the transistors to be turned on meet the zero-voltage turn-on condition; controlling the duty cycle and dead time of the switching transistors to control the inductor current to operate in a critical continuous conduction mode, utilizing the inductor current to charge and discharge the junction capacitance of the switching transistors during the dead time of the switching transistors, and achieving zero-voltage soft turn-on of all transistors by adjusting the output voltage and output current. This invention ensures that all transistors can maintain zero-voltage soft turn-on by adjusting their switching states under varying output voltage and output current conditions, improving the applicability of the converter.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and more particularly to a soft-switching control method for a dual-input photovoltaic DC circuit. Background Technology

[0002] With the increasing use of solar energy as a clean energy source, dual-input photovoltaic (PV) DC-DC converters are becoming increasingly important. How to effectively convert solar energy into storable DC power using multiple PV modules has become a key research focus for dual-input PV DC-DC converters. Dual-input single-inductor buck converters, as a dual-input PV DC-DC converter solution, offer advantages such as simple structure, small size, wide voltage regulation range, and ease of control, and are widely used in PV power generation systems. However, in practical engineering, dual-input single-inductor buck converters are typically controlled to operate at their maximum power point. Of the four switching transistors, in most cases only one pair can achieve zero-voltage soft turn-on, while the others can only be hard-turned on. This results in significant circuit turn-on losses and poor EMC (Electromagnetic Compatibility) performance.

[0003] A single-input buck converter can achieve zero-voltage soft turn-on simply by controlling it to operate in critical continuous conduction mode. During the dead time, the inductor current charges and discharges the junction capacitance of the switching transistor, causing the drain-source voltage to drop to 0 at the moment the switching transistor is turned on. However, for a dual-input single-inductor buck converter, the implementation of zero-voltage soft turn-on is more complex due to the difference between the input voltage and the switching state. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a soft-switching control method for a dual-input photovoltaic DC circuit, which can ensure that all switching transistors can maintain zero-voltage soft-switching by adjusting the switching state under the condition of changes in output voltage and output current, thereby improving the applicability of the converter.

[0005] The technical solution adopted by this invention to solve the above-mentioned technical problems is to provide a soft-switching control method for a dual-input photovoltaic DC circuit. The circuit is a dual-input single-inductor buck converter, which includes a first DC input and a second DC input, and outputs DC power through a switching transistor, an inductor, and an output capacitor. The soft-switching control method includes: controlling the switching cycle of the switching transistors to achieve soft turn-on of all switching transistors, and ensuring that the switching transistors to be turned on meet the zero-voltage turn-on condition; controlling the duty cycle and dead time of the switching transistors to control the inductor current to operate in a critical continuous conduction mode, using the inductor current to charge and discharge the junction capacitance of the switching transistors during the dead time of the switching transistors, and achieving zero-voltage soft turn-on of all switching transistors by adjusting the output voltage and output current.

[0006] Furthermore, the first DC input is connected to the switching transistor via a first input capacitor, and the second DC input is connected to the switching transistor via a second input capacitor. The connected switching transistors include a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor.

[0007] The positive terminal of the first DC input is connected to the drain of the first switching transistor, one end of the first input capacitor, one end of the output capacitor, and the positive terminal of the DC output. The negative terminal of the first DC input is connected to the source of the second switching transistor and the other end of the first input capacitor. One end of the inductor is connected to the source of the first switching transistor and the drain of the second switching transistor. The positive terminal of the second DC input is connected to the drain of the third switching transistor and one end of the second input capacitor. The negative terminal of the second DC input is connected to the source of the fourth switching transistor, the other end of the second input capacitor, the other end of the output capacitor, and the negative terminal of the DC output. The other end of the inductor is connected to the source of the third switching transistor and the drain of the fourth switching transistor.

[0008] Furthermore, the switching cycle control of all switching transistors is as follows: t o ~ t At time 1, the second and third switches are turned on, while the first and fourth switches are turned off, and the voltage across the inductor is... V in1 + V in2 - V o The inductor current increases. V in1 It is the first DC input. V in2 It is the second DC input. V o It is a DC output; t 1~ t At time 2, the third switch is turned on, and the first, second, and fourth switches are turned off. The inductor and the junction capacitance of the first and second switches resonate. The inductor current discharges the junction capacitance of the first switch, causing the drain-source voltage of the first switch to decrease and the junction capacitance of the second switch to charge. The drain-source voltage of the second switch rises, so that the first switch satisfies the zero-voltage turn-on condition. t 2~ t At time 3, the first and third switches are turned on, while the second and fourth switches are turned off, and the voltage across the inductor is... V in2 - V o , V in2 > V o When the inductor current rises, V in2 <V o When the inductor current decreases, V in2 = V o The inductor current remains constant. t 3~ t At time 4, the first switch is turned on, and the second, third, and fourth switches are turned off. The inductor and the junction capacitance of the third and fourth switches resonate. The inductor current charges the junction capacitance of the third switch, causing the drain-source voltage of the third switch to rise and discharge the junction capacitance of the fourth switch. The drain-source voltage of the fourth switch drops, thus satisfying the zero-voltage turn-on condition for the fourth switch. t 4~ t At time 5, the first and fourth switches are turned on, while the second and third switches are turned off. The voltage across the inductor is - V o The inductor current decreases; t 5~ t At time 6, the first, second, third, and fourth switches are all turned off. The inductor and the junction capacitances of the first, second, third, and fourth switches resonate. The inductor current charges the junction capacitances of the first and fourth switches, causing the drain-source voltages of the first and fourth switches to rise. This discharges the junction capacitances of the second and third switches, causing the drain-source voltages of the second and third switches to decrease, thus satisfying the zero-voltage turn-on condition for the second and third switches.

[0009] Furthermore, the output voltage regulation control is as follows: Ignoring the effect of dead time, the output voltage is: V o = D 2 V in1 + D 3 V in2 The duty cycle of the first switch is: D 1=1- D 2. The duty cycle of the fourth switch is: D 4=1- D 3. When the duty cycle of the second and third switching transistors is changed, the duty cycles of the first and fourth switching transistors also change accordingly. D 1. D 2. D 3. D4 represents the switching duty cycles of the first, second, third, and fourth switching transistors, respectively. The actual output voltage value is obtained through sampling. When the output voltage or the output voltage reference changes, the output voltage is PI-regulated to obtain the corresponding changes in the duty cycles of the first, second, third, and fourth switching transistors. Then, the dead time is appropriately increased based on the sampled values ​​of the first and second DC input voltages. The switching states of the first, second, third, and fourth switching transistors are changed through PWM modulation, thereby adjusting the output voltage to match the output voltage reference and achieving soft switching.

[0010] Furthermore, the output current regulation and control are as follows: Ignoring the effect of dead time, the output current is: I o = T [(1- D 2) D 2 V in1 +(1- D 3) D 3 V in2 ] / 2 L b , L b It's an inductor. T It is the common switching cycle of the first, second, third, and fourth switching transistors; the actual value of the output current is obtained through sampling. When the output current or the output current reference changes, the output current is PI-regulated. Since the output voltage and the output voltage reference remain unchanged, the duty cycles of the second and third switching transistors remain unchanged. Only the value of the switching cycle is changed. The correspondingly changed switching cycle is obtained through PI regulation. Then, the dead time is appropriately increased according to the sampled values ​​of the first and second DC input voltages. The switching states of the first, second, third, and fourth switching transistors are changed through PWM modulation, thereby adjusting the output current to match the output current reference and realizing soft switching.

[0011] Compared with the prior art, the present invention has the following beneficial effects: Through circuit modeling and analysis, the present invention proposes a soft-switching control method for a dual-input photovoltaic DC circuit. By controlling the duty cycle, switching period, and dead time of the switching transistors, the inductor current is controlled to operate in the critical continuous conduction mode. The inductor current is used to charge and discharge the junction capacitance of the switching transistors during the dead time of the switching transistors, thereby achieving zero-voltage soft turn-on of all switching transistors. After the above optimized control, the dual-input single-inductor buck converter can guarantee zero-voltage soft turn-on of all switching transistors under different output voltages and output currents, thus improving the applicability of the converter. Attached Figure Description

[0012] Appendix Figure 1It is a dual-input single-inductor buck converter circuit structure;

[0013] Appendix Figure 2 This is a switching timing diagram according to the present invention;

[0014] Appendix Figure 3 This is the switching mode diagram according to the present invention;

[0015] Appendix Figure 4 This is the control block diagram of a dual-input single-inductor buck converter.

[0016] The symbols in the above attached diagrams are named as follows: V in1 , V in2 These are the first and second DC inputs, respectively. C in1 , C in2 These are the first and second input capacitors, respectively. S 1. S 2. S 3. S 4 are the first, second, third, and fourth switching transistors, respectively; L b It is an inductor; C o It is the output capacitor; V o It is a DC output; u GS It is driven by a switching transistor; i Lb It is the inductor current; V DS1 , V DS2 , V DS3 , V DS4 These are the drain-source voltages of the first, second, third, and fourth switching transistors, respectively. t 0、 t 1. t 2. t 3. t 4. t 5. t 6 represent the seven time points in the switching timing diagram; R o It is a load; I o It is the output current; I oref It is the output current reference; V oref It is the output voltage reference; TIt is the common switching cycle of the first, second, third, and fourth switching transistors; D 1. D 2. D 3. D 4 represents the switching duty cycle of the first, second, third, and fourth switching transistors, respectively. Detailed Implementation

[0017] The invention will be further explained below with reference to the accompanying drawings and embodiments.

[0018] In order to realize the technical solution of the present invention and enable more engineers to understand the present invention, the following will combine specific implementation methods and control schemes to realize zero-voltage soft switching control of all switching transistors.

[0019] Figure 1 This invention demonstrates an application scenario where a dual-input single-inductor buck converter circuit structure is provided, including a first DC input. V in1 Second DC input V in2 First input capacitor C in1 Second input capacitor C in2 First switching transistor S 1. Second switching transistor S 2. Third switching transistor S 3. Fourth switching transistor S 4. Inductance L b Output capacitor C o and DC output V o .

[0020] Specifically, the first DC input V in1 The positive terminal is connected to the first switching transistor. S 1's drain, first input capacitor C in1 One end, output capacitor C o One end and DC output V o The positive terminal, the first DC input V in1 The negative terminal is connected to the second switching transistor. S 2's source and first input capacitor C in1 At the other end, the inductor L b one end and the first switching transistor S 1 source and second switch SThe drains of 2 are connected; the second DC input V in2 The positive terminal is connected to the third switching transistor. S 3. Drain and second input capacitor C in2 One end, the second DC input V in2 The negative terminal is connected to the fourth switching transistor. S 4 source and second input capacitors C in2 The other end, output capacitor C o The other end and DC output V o The negative terminal of the inductor L b The other end and the third switch S 3's source, fourth switch S The drains of 4 are connected.

[0021] Switching timing Figure 2 This indicates the first switching transistor of the dual-input single-inductor buck converter at different times. S 1. Second switching transistor S 2. Third switching transistor S 3. Fourth switching transistor S The overall on / off status of 4 corresponds to the six switching modes of the dual-input single-inductor buck converter at different time periods, as follows: Figure 3 .

[0022] Analysis of soft-switching implementation methods: Figure 3 (a) corresponds to Figure 2 of t o ~ t At time 1, the second switch transistor S 2 and the third switching transistor S 3. Turn on, first switch tube S 1 and the fourth switching transistor S 4. Turn off, inductor L b The voltage across the terminals is V in1 + V in2 - V o Inductor current i Lb rise; Figure 3 (b) corresponds to Figure 2 of t 1~ t At time 2, the third switch transistor S 3. Turn on, first switch tube S 1. Second switching transistorS 2 and the fourth switching transistor S 4. Turn-off, inductor and first switching transistor S 1. Second switching transistor S The junction capacitance of 2 resonates, and the inductor current... i Lb Give the first switching transistor S The junction capacitance of transistor 1 discharges, and the drain-source voltage of the first switching transistor... V DS1 The power supply to the second switching transistor is reduced. S The junction capacitance of transistor 2 is charged, and the drain-source voltage of the second switching transistor... V DS2 Rise, for the first switching transistor S This creates conditions for zero-voltage turn-on; Figure 3 (c) corresponds to Figure 2 of t 2~ t At time 3, the first switching transistor S 1 and the third switching transistor S 3. Turn on, second switch tube S 2 and the fourth switching transistor S 4. Turn off, inductor L b The voltage across the terminals is V in2 - V o , V in2 > V o Inductor current i Lb rise, V in2 < V o Inductor current i Lb decline, V in2 = V o Inductor current i Lb Remain unchanged; Figure 3 (d) corresponds to Figure 2 of t 3~ t At time 4, the first switching transistor S 1. Turn on, second switch tube S 2. Third switching transistor S 3 and the fourth switching transistor S 4. Turn off, inductor L b and the third switching transistor S 3. Fourth switching transistor S4's junction capacitance resonates, inductor current i Lb Give the third switching transistor S The junction capacitance of transistor 3 is charged, and the drain-source voltage of the third switching transistor is... V DS3 Rise, supplying power to the fourth switch. S The junction capacitance of transistor 4 discharges, and the drain-source voltage of the fourth switching transistor... V DS4 The fourth switch is descending. S This creates conditions for zero-voltage turn-on; Figure 3 (e) corresponds to Figure 2 of t 4~ t At time 5, the first switching transistor S 1 and the fourth switching transistor S 4. Turn on, second switch tube S 2 and the third switching transistor S 3. Turn off, inductor L b The voltage across the terminals is - V o Inductor current i Lb decline; Figure 3 (f) corresponds to Figure 2 of t 5~ t At time 6, the first switching transistor S 1. Second switching transistor S 2. Third switching transistor S 3 and the fourth switching transistor S All 4 are off, inductor L b and the first switching transistor S 1. Second switching transistor S 2. Third switching transistor S 3. Fourth switching transistor S 4's junction capacitance resonates, inductor current i Lb Give the first switching transistor S 1. Fourth switching transistor S The junction capacitance of transistor 4 is charged, and the drain-source voltage of the first switching transistor is... V DS1 The drain-source voltage of the fourth switching transistor V DS4 Rise, supplying power to the second switching transistor S 2. Third switching transistor S The junction capacitance of transistor 3 discharges, and the drain-source voltage of the second switching transistor... V DS2 The drain-source voltage of the third switching transistor V DS3 The second switching transistor is lowered.S 2 and the third switching transistor S This creates the conditions for zero-voltage turn-on of 3.

[0023] The control block diagram of the dual-input single-inductor buck converter is as follows: Figure 4 Analysis of control implementation methods: Figure 2 Dead time, i.e. t 1~ t 2 moments t 3~ t 4 moments t 5~ t At time 6, compared to the entire switching cycle T The proportion is very small, in calculating the output voltage. V o and output current I o At that time, the impact of dead time is negligible. According to Figure 2 and Figure 3 Analysis of output voltage V o and the first DC input voltage V in1 Second DC input voltage V in2 Duty cycle of the second switching transistor D 2. Duty cycle of the third switching transistor D 3 is related and can be expressed as: V o = D 2 V in1 + D 3 V in2 Ignoring the effect of dead time, the duty cycle of the first switching transistor... D 1 can be represented as: D 1=1- D 2. Duty cycle of the fourth switching transistor D 4 can be represented as: D 4=1- D 3. Change the duty cycle of the second switching transistor. D 2. Duty cycle of the third switching transistor D At time 3, the duty cycle of the first switching transistor is... D 1. Duty cycle of the fourth switching transistor D 4. The output voltage should also be changed accordingly. V o The actual value can be obtained through sampling, when the output voltage... V o or output voltage reference V oref When changes occur, the output voltage... V oBy performing PI regulation, the duty cycle of the first switching transistor is changed accordingly. D 1. Duty cycle of the second switching transistor D 2. Duty cycle of the third switching transistor D 3. Duty cycle of the fourth switching transistor D 4. Then, based on the first DC input voltage... V in1 Second DC input voltage V in2 By appropriately increasing the dead time of the sampled values ​​and changing the first switching transistor through PWM modulation, S 1. Second switching transistor S 2. Third switching transistor S 3. Fourth switching transistor S The switching state of 4 is used to regulate the output voltage. V o Matching output voltage reference V oref And achieve soft switching. Flow through the load. R o The current is the output current. I o Ignoring the impact of dead time, according to Figure 2 and Figure 3 Analysis of output current I o and the first DC input voltage V in1 Second DC input voltage V in2 Duty cycle of the second switching transistor D 2. Duty cycle of the third switching transistor D 3. Switching cycle T Inductance value L b Related, can be expressed as: I o = T [(1- D 2) D 2 V in1 +(1- D 3) D 3 V in2 ] / 2 L b Output current I o The actual value can be obtained through sampling, when the output current... I o or output current reference I oref When changes occur, the output current is affected. I oPI regulation is performed due to the output voltage. V o and output voltage reference V oref Since both remain unchanged, the duty cycle of the second switch is also unchanged. D 2. Duty cycle of the third switching transistor D 3 remains unchanged, therefore only the switching cycle is changed. T The value of is obtained by adjusting the PI controller of the output current to change the switching cycle accordingly. T Then, based on the first DC input voltage V in1 Second DC input voltage V in2 By appropriately increasing the dead time of the sampled values ​​and changing the first switching transistor through PWM modulation, S 1. Second switching transistor S 2. Third switching transistor S 3. Fourth switching transistor S The switching state of 4 is used to adjust the output current. I o Matching output current reference I oref And achieve soft switching.

[0024] The above embodiments are merely illustrative of the present invention and are not intended to limit the invention. Furthermore, steps not described in detail are well-known to those skilled in the art. Corresponding modifications and alterations covered within the inventive concept are all within the scope of the present invention.

Claims

1. A soft switching control method of a dual-input photovoltaic DC circuit, the circuit being a dual-input single-inductor buck converter, the dual-input single-inductor buck converter comprising a first DC input and a second DC input and outputting DC through a switching transistor, an inductor and an output capacitor, characterized in that, The soft switching control method comprises: By controlling the switching period of the switching tube, the soft opening of all switching tubes is realized, and the switching tube to be opened meets the zero voltage opening condition; By controlling the duty cycle and dead time of the switching tube, the inductor current is controlled to work in the critical continuous conduction mode, the inductor current is used to charge and discharge the junction capacitor of the switching tube in the dead time of the switching tube, and the zero voltage soft opening of all switching tubes is realized by adjusting the output voltage and output current; The first direct current input is connected with the first switching tube and the second switching tube through the first input capacitor, and the second direct current input is connected with the third switching tube and the fourth switching tube through the second input capacitor; The output voltage regulation control is as follows: ignoring the dead time effect, the output voltage is: V o = D 2 V in1 + D 3 V in2 , the first switch duty cycle is: D 1=1- D 2, the fourth switch duty cycle is: D 4=1- D 3, when the second switch duty cycle and the third switch duty cycle are changed, the first switch duty cycle and the fourth switch duty cycle are also changed, D 1、 D 2、 D 3、 D 4 are the first, second, third and fourth switch duty cycles, respectively; V in1 is the first DC input, V in2 is the second DC input, V o is the DC output; the actual output voltage is obtained by sampling, when the output voltage or the output voltage reference changes, the output voltage is regulated by PI, the first switch duty cycle, the second switch duty cycle, the third switch duty cycle and the fourth switch duty cycle are changed, and the dead time is increased according to the first DC input voltage and the second DC input voltage sampling value, the switching state of the first switch, the second switch, the third switch and the fourth switch is changed by PWM modulation, so as to regulate the output voltage to match the output voltage reference, and realize soft switching. The output current regulation control is as follows: ignoring the dead time effect, the output current is: I o = T [(1- D 2) D 2 V in1 +(1- D 3) D 3 V in2 ] / 2 L b , L b is the inductance, T is the common switching period of the first, second, third and fourth switching tubes; the actual value of the output current is obtained by sampling, and when the output current or the output current reference changes, the output current is regulated by PI. Since the output voltage and the output voltage reference are unchanged, the duty cycle of the second switching tube and the duty cycle of the third switching tube are unchanged, only the value of the switching period is changed, the corresponding changed switching period is obtained by PI regulation, and the dead time is increased according to the sampling values of the first and second direct current input voltages, and the switching states of the first, second, third and fourth switching tubes are changed by PWM modulation, so as to regulate the output current to match the output current reference, and realize soft switching.

2. The method of claim 1, wherein the soft switching control of the dual input photovoltaic DC circuit is characterized by, The positive pole of the first direct current input is connected with the drain electrode of the first switching tube, one end of the first input capacitor, one end of the output capacitor and the positive pole of the direct current output, the negative pole of the first direct current input is connected with the source electrode of the second switching tube and the other end of the first input capacitor, one end of the inductor and the source electrode of the first switching tube, and the drain electrode of the second switching tube are connected; the positive pole of the second direct current input is connected with the drain electrode of the third switching tube and one end of the second input capacitor, the negative pole of the second direct current input is connected with the source electrode of the fourth switching tube, the other end of the second input capacitor, the other end of the output capacitor and the negative pole of the direct current output, and the other end of the inductor and the source electrode of the third switching tube and the drain electrode of the fourth switching tube are connected.

3. The method of claim 2, wherein the soft switching control of the dual input photovoltaic DC circuit is characterized by, The switching period control of all switching tubes is as follows: t o ~ t 1 time, the second switch tube and the third switch tube open, the first switch tube and the fourth switch tube are off, the voltage across the inductor is V in1 + V in2 - V o , the inductor current rises; t 1~ t At time 2, the third switch is turned on, and the first, second and fourth switches are turned off. The inductor and the junction capacitances of the first and second switches resonate, the inductor current discharges the junction capacitance of the first switch, the drain-source voltage of the first switch decreases, the junction capacitance of the second switch is charged, and the drain-source voltage of the second switch increases, so that the first switch meets the zero-voltage turn-on condition. t 2 t 3 At time t3, the first and third switches are on, and the second and fourth switches are off. The voltage across the inductor is V in2 - V o , V in2 > V o The inductor current rises, V in2 < V o The inductor current falls, V in2 = V o The inductor current remains constant. t 3~ t 4th moment, the first switch tube is turned on, the second switch tube, the third switch tube and the fourth switch tube are turned off, the inductor and the junction capacitance of the third switch tube and the fourth switch tube resonate, the inductor current charges the junction capacitance of the third switch tube, the drain-source voltage of the third switch tube rises, discharges the junction capacitance of the fourth switch tube, the drain-source voltage of the fourth switch tube drops, so that the fourth switch tube meets the zero-voltage turn-on condition; t 4~ t At time 5, the first switch tube and the fourth switch tube are turned on, the second switch tube and the third switch tube are turned off, and the voltage across the inductor is V o , the inductor current decreases; t 5~ t 6th moment, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are all off, the inductor and the junction capacitance of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube resonate, the inductor current charges the junction capacitance of the first switch tube and the fourth switch tube, the drain-source voltage of the first switch tube and the fourth switch tube rises, discharges the junction capacitance of the second switch tube and the third switch tube, and the drain-source voltage of the second switch tube and the third switch tube drops, so that the second switch tube and the third switch tube meet the zero-voltage turn-on condition.

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