Quantum bit processing method
By configuring position sets in a qubit processor to perform single-qubit and two-qubit operations and utilizing the transfers and interactions between position sets, the high resource requirements for processing a large number of qubits in the NISQ era are solved, and efficient parallel processing of multiple qubit sets is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- QUANTUM MOTION TECH LTD
- Filing Date
- 2021-03-08
- Publication Date
- 2026-05-19
AI Technical Summary
In the NISQ era, processing a large number of qubits requires high resources and presents significant engineering challenges, making it difficult to scale up devices.
By configuring location sets to perform single-qubit and two-qubit operations, and by leveraging the transfers and interactions between location sets, resource requirements are reduced, enabling parallel processing of multiple sets of qubits.
It improves the processing power and throughput of quantum computing, reduces resource requirements, and adapts to the processing needs of a large number of qubits.
Smart Images
Figure CN115362455B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a qubit processing method and a qubit processor for performing the method. Background Technology
[0002] Quantum computing involves the manipulation and processing of qubits. A qubit, or quantum bit, is a quantum quantity parallel to the classical "bit" used in classical computing and contains information. There are many possible quantum computing schemes that can be used to manipulate qubits.
[0003] One quantum computing scheme involves manipulating qubits using a series of quantum logic gates. In such a gate-based approach, pulsed, local, and global electromagnetic waves and electrostatic potentials sequentially manipulate the states of fixed qubits and qubit pairs arranged on a lattice. The manipulation of the qubit states is controlled by manipulating the parameters of the electromagnetic waves and potentials to realize a series of quantum logic gates across the lattice. The configuration of the gates changes over time. Typically, the final stage of this process is the reading of the qubit states, most commonly reading all qubits in the lattice.
[0004] In the recent era of mesoscale quantum computing, or NISQ, the number and density of qubits on each device are increasing. For example, it is possible to use silicon metal-oxide-semiconductor (SiMOS) devices to generate dense two-dimensional grids of electron spin qubits that can be physically adapted to this growth.
[0005] However, executing a series of quantum logic gates on a device (e.g., running quantum algorithms) requires delivering a series of simultaneous and complex fast pulses to the device, the difficulty of which only increases with the number of qubits. Processing a large number of qubits in this way is resource-intensive and an engineering challenge. Therefore, scaling up such devices is difficult to imagine.
[0006] The goal is to create processors and processing methods suitable for the NISQ era. Summary of the Invention
[0007] A first aspect of the present invention provides a method for performing quantum computing in a qubit processor. The method includes the following steps: configuring a first position in a first set of positions to perform a first single-qubit operation; configuring a second position in the first set of positions to perform a second single-qubit operation; configuring a first position and a second position in the second set of positions to perform a two-qubit interaction; receiving a first qubit at the first position in the first set of positions at time t1; receiving a second qubit at the second position in the first set of positions at time t1; wherein both the first qubit and the second qubit are provided within a first set of qubits comprising n qubits, where n>2; performing the first single-qubit operation on the state of the first qubit at the first position in the first set of positions; performing the second single-qubit operation on the state of the second qubit at the second position in the first set of positions; and removing the first qubit from the first position in the first set of positions. The position is transferred to the first position in the second position set; the second qubit is transferred from the second position in the first position set to the second position in the second position set; a two-qubit interaction occurs between the first and second qubits in the second position set; the first qubit is transferred from the first position in the second position set to the first position in the read position set; the second qubit is transferred from the second position in the second position set to the second position in the read position set; at time t2, the first qubit of the second qubit group is received at the first position in the first position set, where t2 > t1; at time t2, the second qubit of the second qubit group is received at the second position in the first position set; the state of the first qubit at the first position in the read position set is read; and the state of the second qubit at the second position in the read position set is read.
[0008] Advantageously, processing qubits in this way reduces the resources required to perform qubit processing methods. During the compilation phase, each set of positions is configured to perform a specific single-qubit operation or a two-qubit operation. During the runtime phase, the configuration of each set of positions remains fixed, while the first and second qubits can be physically transferred from one set of positions to another to perform a series of processing steps. In this way, each group of qubits is processed in the same manner. That is, each qubit received at a specific position in the set of positions undergoes the same operation. The first and second positions in the first set of positions are configured to perform a first single-qubit operation and a second single-qubit operation, respectively. Therefore, the first qubit of each group of qubits is manipulated according to a predefined first single-qubit operation. Similarly, a second single-qubit operation is performed on the state of the second qubit of each group of qubits. The first and second positions in the second set of positions are configured to perform two-qubit interactions, so each first and second qubit in each group of qubits processed using this method will undergo two-qubit interactions in the second set of positions according to this configuration.
[0009] At a given location or set of locations, only one type of operation is performed until the device is reset in a subsequent compilation phase. For example, the set of locations can be configured to perform a Z-rotation at each location, and the amount of rotation can be tunable for each location within the set. Preferably, these locations are tuned to desired parameters during the compilation phase and remain constant during the runtime phase.
[0010] Both the first and second qubits are provided within a first qubit set comprising n qubits, where n is greater than 2. In the NISQ era, qubit processors are capable of handling large numbers of qubits. The number of qubits in the first qubit set is preferably greater than 50, more preferably greater than 100, allowing the qubit processing method to perform simulations that cannot be classically simulated. Typically, the number of positions in each location set will be the same as or greater than the number of qubits in the first qubit set. Each location preferably includes an electrode that can be configured to perform operations on the qubit. Optionally, the first qubit set can be supported in any location set and can be manipulated and transferred as units between location sets. This can be simplified by using fast global control to perform transfer steps between location sets.
[0011] A qubit processing method includes the following steps: at time t2, receiving the first qubit and the second qubit of a second qubit group at a first position and a second position in a first position set, respectively. At time t1 (t2>t1), receiving the first qubit and the second qubit of the first qubit group at the same first position and the same second position in the first position set, respectively. The advantage of this qubit processing method is that by starting processing of the second qubit group in the processor shortly after processing the first qubit group, multiple qubit groups can be processed simultaneously in the qubit processor. This can be achieved by spatially transferring the first qubit group. Simultaneous processing of multiple qubit groups increases throughput. Preferably, during the operational phase where operations can be performed on the qubits, the first qubit group and the second qubit group are separated by at least two unoccupied position sets. Optionally, the first qubit group and the second qubit group are separated by one unoccupied position set.
[0012] At time t tr At this point, the first and second qubits of the first qubit group can be transferred from the first and second positions in the second position set to the first and second positions in the third position set, respectively, at time t. tr Typically, this occurs after receiving the first set of qubits at the first location set, i.e., t tr >t1. The third position set is preferably an intermediate position set between the second position set and the read position set. Preferably, the transfer of the first qubit group from the second position set to the third position set occurs before the second qubit group is received at the first position set, i.e., t tr ≤ t2. Advantageously, this provides an empty set of positions between the first and second qubit groups within the processor. The first and second qubit groups can be separated by the minimum value of a single unoccupied set of positions. This distance can be maintained throughout the process, avoiding unintentional qubit interactions across the first and second qubit groups. Alternatively, multiple sets of qubits can be processed simultaneously and independently, occupying the same corresponding positions in different set of positions.
[0013] Typically, a qubit processor has N sets of locations, where N > 3. The value of N can be determined by the desired number of steps in the computer program. Preferably, one step is performed at each set of locations, so the N sets of locations can accommodate N programming steps. Typically, the state of the qubit is read at the end of the computation. Therefore, the Nth set of locations preferably includes the set of read locations.
[0014] Optionally, at time t r At point t, read the state of the first qubit of the first qubit group; at time t r At this point, read the state of the second qubit in the first qubit group; where tr > t2. In this example, at time t2, before the processing of the first qubit group is completed, the processing of the second qubit group starts being received at the first set of positions. Typically, the last step in this qubit processing method is to read the states of the qubits within the group. Advantageously, processing multiple qubit groups simultaneously by the qubit processor increases the processing power.
[0015] Each group of qubits is processed in the same way that the group traverses the qubit processor through a consecutive set of positions from the first set of positions to the read set of positions. Thus, if no errors occur, the state of the i-th qubit in each qubit group will be the same. Each qubit group typically includes n qubits, 1 ≤ i < n. Nevertheless, errors that will affect the state of one or more qubits are expected to occur. It is currently impossible to completely eliminate errors, so typically the quantum calculation is performed multiple times to reduce the impact of errors on the calculation. This method of processing qubits advantageously allows multiple qubit groups to be processed independently and simultaneously in the qubit processor, so as to repeatedly perform the same series of operations quickly and continuously multiple times to determine the average state of each qubit.
[0016] Preferably, each set of positions in the qubit processor can be configured to perform an operation on the states of the qubits in the qubit group. The operation optionally includes waiting or consists of waiting. Each qubit group is typically received by a consecutive set of positions, terminating at the read set of positions. Multiple qubits can be processed synchronously. Optionally, the qubit processing method further includes the following steps: at time t3, transferring the first qubit of the first qubit group from the first position in the third set of positions to the first position in the fourth set of positions; at time t3, transferring the second qubit of the first qubit group from the second position in the third set of positions to the second position in the fourth set of positions; at time t3, transferring the first qubit of the second qubit group from the first position in the first set of positions to the first position in the second set of positions; and at time t3, transferring the second qubit of the second qubit group from the second position in the first set of positions to the second position in the second set of positions; where t3 > t2. Advantageously, the transfer of multiple qubit groups between sets of positions can be performed synchronously and globally. The fourth set of positions is preferably an intermediate set of positions between the third set of positions and the read set of positions.
[0017] Generally, two-qubit interactions can be performed in the set of positions in the qubit processing method. Preferably, an n-qubit processing method further includes the following steps: performing an interaction between the i-th qubit and the (i + 1)-th qubit in the first qubit group, such that each qubit in the first qubit group interacts directly or indirectly with every other qubit in the first qubit group. For the first qubit group including n qubits, 1 ≤ i < n. The positions where interactions occur between specific qubit pairs can depend on the configuration of the set of positions and the positions within the set of positions. The i-th qubit and the (i + 1)-th qubit are preferably physically adjacent qubits in the group, and performing the interaction can include bringing the qubits closer together spatially to increase the tunnel coupling between the qubits, such that nearest-neighbor interactions are performed, such as nearest-neighbor Heisenberg exchange.
[0018] The qubit processing method includes the following steps: performing an interaction between two qubits. More generally, in an n-qubit group, interactions can be performed between any adjacent qubit pairs within the n-qubit group. However, the temporal and spatial intervals between consecutive qubit groups preferably ensure that there will be no inter-group qubit interactions. For example, the first qubit in the first qubit group does not interact with the first qubit in the second qubit group. Preferably, during the operation phase, the first qubit group and the second qubit group are separated by at least one set of unoccupied positions to avoid interactions between qubits belonging to different qubit groups. If the time taken to perform the manipulation and transfer steps is not equal between the sets of positions, two or more sets of unoccupied positions may be required between each occupied set of positions.
[0019] The set of unoccupied positions can be initialized. Optionally, any or all of the unoccupied sets of positions can be globally reset to "zero". The qubit processing method can further include: performing an initialization operation on the first set of positions. Performing the initialization operation can occur after the first and second qubits in the first qubit group are transferred from the first and second positions in the first set of positions, respectively, and before the first and second qubits in the second qubit group are received at the first and second positions in the first set of positions, respectively. This can advantageously prevent unwanted crosstalk in the case of imperfect transfer of qubits. Optionally, the qubit states can be measured after the first and second qubits in the first qubit group are transferred from the first and second positions in the first set of positions and before the initialization operation is performed. In this case, unless an error occurs, the measurement result will be zero. Therefore, this can be advantageously used to monitor the occurrence of errors and perform a global reset in case of an error.
[0020] Alternatively, the qubit may be an electron spin qubit, a trapped ion qubit, or a superconducting qubit. Electron spin qubits are suitable for quantum computing processes because they can be easily manipulated and coupled to other electron spin qubits. Trapped ion qubits advantageously provide stability, which can improve the fault tolerance of quantum computing. Superconducting qubits can provide long coherence times. Preferably, the qubit is an electron spin qubit in a silicon-based device because these advantageously provide long coherence times and are compatible with existing technologies.
[0021] The steps for transferring qubits between sets of locations typically depend on the type of qubits chosen. For example, the transfer steps can include electron shuttle, where electron spin qubits or trapped ion qubits can be "shuttled." This refers to the process where the local potential energy is modified to transfer charge. The electron will stabilize at a local minimum in the potential energy landscape and can shuttle forward by raising the potential energy at its current location and lowering the potential energy at the desired location, while maintaining a high barrier elsewhere to guide the electron. This approach is advantageous because it is reliable and fault-tolerant. Furthermore, transfers using electron shuttle allow for global control of the movement of multiple qubit groups via a processor.
[0022] Alternatively, the transfer step may include a SWAP operation. In a SWAP operation, two qubits are swapped. Optionally, the SWAP operation can be used to transfer superconducting qubits. In this example, a qubit can be present at each location in each set of locations, which can advantageously increase throughput.
[0023] Another aspect of the present invention provides a qubit processor. This qubit processor is capable of implementing the qubit processing method according to the first aspect of the present invention. Any feature of the qubit processing method can be implemented in the qubit processor, and any feature of the qubit processor can be used to execute the qubit processing method. Each aspect of the present invention has similar advantages. The qubit processor includes: a first set of positions, a second set of positions, and a set of readout positions. Each set of positions includes at least: a first position and a second position, the first and second positions being configured to receive a first qubit and a second qubit, respectively. The first position in the first set of positions is configured to perform a first single-qubit operation, and the second position in the first set of positions is configured to perform a second single-qubit operation. The first set of positions is configured to: receive a first qubit at a first position and receive a second qubit at a second position; perform a first single-qubit operation on the state of the first qubit; and perform a second single-qubit operation on the state of the second qubit. The first and second positions in the second set of positions are configured to perform two-qubit interactions. The first and second qubits are transferred from the first set of positions to the second set of positions. The second set of positions is configured to perform two-qubit interactions between the first qubit and the second qubit. The first and second qubits are transferred from the second position set to the read position set. This read position set is configured to read the state of the first and second qubits.
[0024] Preferably, the qubit processor is fabricated using SiMOS technology, where the high-density qubit arrangement can potentially have low power requirements. The qubit processor is preferably configured to process groups of n qubits, typically each set of locations is configured to have at least n locations to accommodate the n qubit group. Each of the n locations may include an electrode. Optionally, a voltage may be applied to one or more electrodes to achieve single-qubit or two-qubit operation. The number of processing steps depends on the implemented program. Typically, the number of steps N is greater than 3, and the qubit processor typically includes at least N set of locations.
[0025] Using SiMOS technology to fabricate qubit processors can provide a scalable architecture that allows for densely packed arrangements of qubits on a processing chip. The described n-qubit processing method may require N×n electrodes, and preferably N×n corresponding locations. This is an alternative to a √n×√n arrangement, on which N different processes can be executed sequentially. In the N×n location arrangement, the N location set preferably corresponds to N time steps, and then the n locations within each location set preferably correspond to the number of qubits in the group. Using SiMOS technology, a larger number of locations is possible, and the qubit processing method advantageously requires less input from the signal generator. Control of the qubit group during qubit processing is advantageously simplified.
[0026] The qubit processor optionally includes a third set of locations; wherein a voltage source is electrically connected to the first and third set of locations to apply voltage to both sets simultaneously. The third set of locations is preferably an intermediate set between the second set of locations and the read set of locations. An advantage of the described qubit processing method is that it enables the processing of multiple sets of qubits within the processor at any given time. The transfer of qubits along the processor from one set of locations to the next can advantageously be performed globally. For example, the same voltage source can be used to transfer both the first and second sets of qubits to the next set of locations, even if the first and second sets of qubits are spatially separated within the processor. Preferably, there are at least two unoccupied sets of locations separating each occupied set of locations. Advantageously, the voltage source can be electrically connected to each occupied set of locations to control the movement of multiple sets of qubits by the qubit processor.
[0027] A qubit processor can be established before running a qubit processing method as part of quantum computing. This typically involves locally tuning electrodes at each location such that each location in each set of locations can be configured to perform a specific manipulation or operation. The electrodes at a location can be configured to perform a single-qubit operation, or the electrodes at a pair of adjacent locations in a set of locations can be configured to interact between two qubits. The qubit processor is preferably configured before computation is performed. During the computation phase, the qubit processor configuration is preferably kept fixed such that each set of locations, and each location within a set of locations, performs the same operation for each consecutive group of qubits received.
[0028] Preferably, the qubit processing method includes a compilation phase, a runtime phase, and a readout phase. During the compilation phase, a first position and a second position in a first position set are configured to perform a first single-qubit operation and a second single-qubit operation, respectively. In one example, the first single-qubit operation is an X-rotation, and the second single-qubit operation is a Z-rotation. In another example, the first and second single-qubit operations are of the same type. The first and second positions in a second position set are also configured during the compilation phase to perform two-qubit interactions, such as exchange interactions.
[0029] Optionally, during the compilation phase, the voltage applied to the electrodes at locations within a set of locations within the qubit processor can be tuned. This tuning can optionally control the qubit logic gate rate at each location within the set of locations, as well as the electron tunneling rate between sets of locations. Voltage tuning at a specific set of locations can control the qubit-qubit coupling strength at each location within the set of locations. During the runtime phase, steps such as receiving qubits, performing operations, transferring qubits, and engaging in interactions can be performed. Operations are performed according to the configuration of each location within each set of locations set during the compilation phase. The tuning established during the compilation phase can provide control over the qubits and the quantum information they carry during the runtime phase.
[0030] Optionally, the runtime phase includes the following steps: synchronously receiving n qubit states at the k-th location set in a two-dimensional location grid; performing synchronization manipulation on the qubit states at the k-th location set (which may include waiting); and synchronously transferring the n qubit states from the k-th location set to the subsequent (k+1)-th location set.
[0031] Typically, alternating sets of positions are decoupled from each other, allowing manipulation to implement a set of single-qubit logic gates. In intermediate sets of positions, certain adjacent qubits can be coupled to each other, allowing manipulation to implement two-qubit logic gates.
[0032] Preferably, having completed the above runtime steps for all location sets, during the reading phase, the state of n qubits is read at the final location set (read location set).
[0033] Another aspect of the present invention provides a method for performing quantum computing in a qubit processor. The method includes the following steps: receiving a first qubit at a first position in a first set of positions; receiving a second qubit at a second position in the first set of positions; performing an operation on the state of the first qubit at the first position in the first set of positions; performing an operation on the state of the second qubit at the second position in the first set of positions; transferring the first qubit from the first position in the first set of positions to a first position in the second set of positions; transferring the second qubit from the second position in the first set of positions to a second position in the second set of positions; interacting between the first qubit and the second qubit in the second set of positions; transferring the first qubit from the first position in the second set of positions to a first position in a readout set of positions; transferring the second qubit from the second position in the second set of positions to a second position in the readout set of positions; reading the state of the first qubit at the first position in the readout set of positions; and reading the state of the second qubit at the second position in the readout set of positions.
[0034] Another aspect of the present invention provides a qubit processor. This qubit processor is capable of implementing the qubit processing method according to the first aspect of the present invention. Any feature of the qubit processing method can be implemented in the qubit processor, and any feature of the qubit processor can be used to execute the qubit processing method. Each aspect of the present invention has similar advantages. The qubit processor includes: a first set of positions, a second set of positions, and a set of readout positions. Each set of positions includes at least: a first position and a second position. The first set of positions is configured to: receive a first qubit at a first position and receive a second qubit at a second position; perform operations on the state of the first qubit and the state of the second qubit. The first qubit and the second qubit are transferred from the first set of positions to the second set of positions. The second set of positions is configured to interact between the first qubit and the second qubit. The first qubit and the second qubit are transferred from the second set of positions to the set of readout positions. The set of readout positions is configured to read the state of the first qubit and the state of the second qubit. Attached Figure Description
[0035] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which:
[0036] Figure 1 This is a schematic diagram of a quantum bit processor according to the first embodiment;
[0037] Figure 2 This is a schematic diagram of a quantum bit processor according to the second embodiment;
[0038] Figure 3This is a schematic diagram of a quantum bit processor according to the third embodiment;
[0039] Figure 4A This is a schematic diagram of the quantum bit processor according to the fourth embodiment at time ta;
[0040] Figure 4B This is a schematic diagram of the quantum bit processor according to the fourth embodiment at time tb>ta;
[0041] Figure 5 This is a schematic diagram of a quantum bit processor according to the fifth embodiment;
[0042] Figure 6A This is a schematic diagram of the quantum bit processor according to the sixth embodiment at time t1;
[0043] Figure 6B This is a schematic diagram of the quantum bit processor according to the sixth embodiment at time t2;
[0044] Figure 6C This is a schematic diagram of the quantum bit processor according to the sixth embodiment at time t3;
[0045] Figure 6D This is a schematic diagram of the quantum bit processor according to the sixth embodiment at time t4;
[0046] Figure 7 This is a schematic diagram of operation in the quantum bit processor according to the seventh embodiment;
[0047] Figure 8A This is a first schematic diagram of operation in the quantum bit processor according to the eighth embodiment;
[0048] Figure 8B This is a second schematic diagram of the operation in the quantum bit processor according to the eighth embodiment;
[0049] Figure 9 This is a flowchart of the operation in the quantum bit processor according to the ninth embodiment;
[0050] Figure 10A This is a first schematic diagram of operation in a quantum bit processor according to the tenth embodiment;
[0051] Figure 10B This is a second schematic diagram of the operation in the quantum bit processor according to the tenth embodiment;
[0052] Figure 10C This is a third schematic diagram of the operation in the quantum bit processor according to the tenth embodiment;
[0053] Figure 11 This is a flowchart of the operation in the qubit processor according to the eleventh embodiment;
[0054] Figure 12 This is a schematic top view of the quantum bit processor according to the twelfth embodiment;
[0055] Figure 13A This is a schematic top view of a quantum bit processor according to the thirteenth embodiment; and
[0056] Figure 13B This is a schematic diagram of a cross-sectional view of a qubit processor according to the thirteenth embodiment. Detailed Implementation
[0057] Figure 1 The first set of positions 101, 102, 103, and 107 in the first embodiment are schematically illustrated. Each set of positions 101-103, 107 is configured to support a group of qubits 108 and to manipulate the state of the qubits within that group. In this embodiment, each set of positions 101-103, 107 is configured to perform a predetermined operation on the qubits within the set. To perform a series of operations on the qubits in a quantum computing scheme, the group of qubits is traversed from one set of positions to the next. A qubit processing method comprising N steps can be implemented in this embodiment by comprising N sets of positions. The nth step is performed at the nth set of positions, where 1 ≤ n ≤ N. The Nth set of positions 107 is a readout set where the state of each qubit within the group can be read by a readout device 109.
[0058] Figure 2 Six adjacent set of positions 201, 202, 203, 204, 205, and 206 according to a second embodiment are schematically shown. In this embodiment, the time taken to perform the operation is the same for each set of positions 201-206. The qubit processing method is carried out through alternating operation steps and shuttle steps. During the operation steps, the set of qubits is manipulated according to a predetermined operation for that set of positions. During the shuttle steps, the set of qubits is shuttled from the nth set of positions to the (n+1)th set of positions, where 1 ≤ n ≤ N-1, and there are a total of N set of positions. This method of processing qubits advantageously allows for the continuous processing of multiple sets of qubits.
[0059] Figure 2The electrical connections between the six position sets 201-206 shown are illustrated. The first position set 201 and the fourth position set 204 are synchronously controlled by a first voltage source 211. Similarly, the second position set 202 and the fifth position set 205, and the third position set 203 and the sixth position set 206 are synchronously controlled by a second voltage source 212 and a third voltage source 213, respectively. Each of the voltage sources 211-213 is a fast pulse generator and is electrically connected to every other two position sets. See also... Figure 7 As described, the voltage applied by each voltage source can be modified to shuttle the set of qubits from the nth position set to the (n+1)th position set. Joint control of every two position sets using a single voltage source allows the set of qubits to fill every two position sets, and joint control of every two position sets using a single voltage source allows them to be shuttled simultaneously. See, for example, [link to example]. Figure 2 The first group of qubits in the first position set and the second group of qubits in the fourth position set can be manipulated according to predetermined operations of the first and fourth position sets, respectively. After the operation step, the first and second groups of qubits can be shuttled to the second and fifth position sets, respectively, by controlling the voltages applied to the first and second voltage sources. After the shuttle step, the first and second groups of qubits can be manipulated according to predetermined operations of the second and fifth position sets, respectively.
[0060] In an alternative embodiment, a SWAP operation is used to perform the transfer of a qubit group from one set of locations to a subsequent set of locations. In this example, each location in each set of locations can be occupied. The qubits are manipulated according to a pre-configured arrangement within a specific location, and then the SWAP operation is performed. During the SWAP operation, qubits in the nth set of locations that have undergone the nth manipulation operation are exchanged with qubits in the (n+1)th set of locations by coupling the nth set of locations, where 1 ≤ n ≤ N-1, and there are a total of N set of locations. In this way, the data qubit group travels through the processor from the first set of locations to the Nth set of locations, where the state of the data qubit group is read, and the auxiliary qubits travel in the opposite direction, thus performing a SWAP across the processor. The SWAP operation can be used to transfer any type of qubit, but it can be particularly advantageous in implementations using superconducting qubits. Similar to the shuttle requirement, the first and second qubit groups should be separated by at least two set of locations to avoid inter-group qubit interactions when multiple adjacent set of locations are coupled.
[0061] Qubit processing methods typically require multiple repetitions to establish representative statistical results. As described, processing consecutive groups of qubits simultaneously within a qubit processor allows for many repetitions.
[0062] If the operation and shuttle time for each location set is constant, the maximum value between every two location sets can be occupied, and thus each voltage source can be electrically connected to every two location sets to perform the transfer steps of the qubit group from one location set to the next. In another embodiment, the operation and shuttle time for each location set may not be constant. In this case, the N location sets can be divided into blocks, where the time spent performing the operation and shuttle steps is the same for each block. If the operation and shuttle time is not constant for each location set, it may be necessary to have more than two unoccupied location sets between each occupied location set. In this case, each location set in the block will be electrically connected to a different voltage source. Using a single voltage source to control multiple location sets simultaneously advantageously reduces the required number and complexity of control and interconnection resources in this qubit processing method.
[0063] In another embodiment, operations at a particular set of locations may take significantly longer (e.g., an order of magnitude or more) to execute than operations at other sets of locations. For example, an initialization operation at the first set of locations or a read operation at the Nth set of locations can take a long time to execute. In this example, the qubit processor may only be able to support a single qubit group. However, the resources required to transfer groups by the processor, and the complexity of similar processing, will still be reduced. If the qubit processor processes only one qubit group at a time, these transfer steps can be performed using only three voltage sources instead of N.
[0064] Figure 3This is an exemplary portion of a qubit processor circuit according to a third embodiment. Four location sets 301, 302, 303, and 304 are shown, wherein five electrodes 305, 306, 307, 308, and 309 are located at corresponding positions in each location set 301-304. Each location set 301-304 can receive a group of n qubits, wherein each electrode 305-309 can receive a qubit. In this embodiment, there are five qubits in each qubit group, n = 5. In the first location set 301, there are five single-qubit quantum logic gates 311, 312, 313, 314, and 315. In the second location set 302, the first and second electrodes, as well as the fourth and fifth electrodes, are coupled to form two-qubit quantum logic gates 321 and 322. The second location set 302 is configured such that the first and second qubits from the first location set 301, which have already undergone single-qubit operations in the first location set, interact with each other in the second location set 302. Similar interactions occur between the fourth and fifth qubits in the second location set 302. The bi-qubit quantum logic gates 323 and 324, schematically shown in the third location set 303 and the fourth location set 304 respectively, ensure that each qubit interacts directly or indirectly with the remaining qubits during this qubit processing method. This is generally achieved through interactions between adjacent qubits (i.e., the i-th qubit with the (i-1)-th and (i+1)-th qubits, 1 < i < n). In an alternative embodiment, the coupling of the two electrodes used for bi-qubit interactions can occur in any location set of the qubit processor.
[0065] Figure 4A and Figure 4B A portion of a qubit processor circuit according to a fourth embodiment is schematically illustrated. In this example, the qubit is an electron spin qubit, wherein an electron is confined within a quantum dot, and quantum information is contained in the electron's spin state. Three location sets 401, 402, and 403 are shown. Figure 4A In this embodiment, a set of n (n=5) qubits 405, 406, 407, 408, and 409, comprising five qubits, are manipulated according to control parameters preset for the first position set 401. In this embodiment, each electrode at a position in the first position set is configured as a single-qubit quantum logic gate 411, 412, 413, 414, or 415. During the operation steps in the first position set 401, each qubit 405-409 in this set of qubits thus undergoes single-qubit operation. At time t... aAt the point where, after the operation step in the first position set 401 and before the shuttle step from the first position set 401 to the second position set 402, the state of each qubit 405-409 is represented as follows: Where 1 ≤ i ≤ 5. As the shuttle time Δt increases... s Five qubits 405-409 are transferred to the second position set 402, as shown by the horizontal line.
[0066] exist Figure 4B In this context, qubits 405-409 are located in the second position set 402. The second position set includes a single-qubit quantum logic gate 422 and first and second two-qubit quantum logic gates 421 and 423. At operation time Δt... g During this period, the group of qubits 405-409 is manipulated by single-qubit quantum logic gate 422 and first and second two-qubit quantum logic gates 421 and 423. At time t... b At this point, the states of each qubit 405-409 are represented as Where 1 ≤ i ≤ 5. The operation performed depends on the tuning of control parameters preset before running the qubit processing program. The level of tuning is schematically represented by shading. For example, the rotation angle can be tuned for a single-qubit quantum logic gate, or the strength of the qubit-qubit interaction can be tuned for a two-qubit quantum logic gate. The control parameters remain fixed during the execution of a particular program but can be retuned to execute different programs.
[0067] Figure 5This is an exemplary portion of a qubit processor circuit according to a fifth embodiment, wherein the set of positions alternates between a decoupled configuration and a coupled configuration. Four set of positions 351, 352, 353, and 354 are shown, wherein five electrodes 355, 356, 357, 358, and 359 are located at corresponding positions in each set of positions 351-354. The first set of positions 351 and the third set of positions 353 are in a decoupled configuration. In the first set of positions 351, there are five single-qubit quantum logic gates 361, 362, 363, 364, and 365. The third set of positions 353 also has five single-qubit quantum logic gates 381, 382, 383, 384, and 385. The intermediate set of positions (i.e., the second set of positions 352 and the fourth set of positions 354) are in a coupled configuration, in which adjacent qubits are coupled to each other to implement two-qubit logic gates. In the second location set 352, qubits at the first electrode 355 and the second electrode 356, as well as qubits at the third electrode 357 and the fourth electrode 358, are coupled to form two-qubit quantum logic gates 371 and 372. In the fourth location set 354, two-qubit quantum logic gates 391 and 392 are configured to couple qubits at the second electrode 356 and the third electrode 357, and at the fourth electrode 358 and the fifth electrode 359, respectively. The two-qubit quantum logic gates 391 and 392 in the fourth location set 354 are offset from the two-qubit quantum logic gates 371 and 372 in the second location set 352. The arrangement of the two-qubit gates affects the direct or indirect interactions between qubits in the qubit processor. In an alternative embodiment, any adjacent electrode pairs can be coupled to implement two-qubit gates.
[0068] exist Figure 5 In the middle, the first to fourth time periods t 11 t 12 t 13 t 14 This schematically indicates the position of the qubit group at consecutive points in time within the processor. At time t... 11 At this point, the qubit set is transferred from the first position set 351 to the second position set 352. At time t... 12 At position 352, adjacent qubits in the qubit group at the second position set interact with each other. At time t... 13 At time t, the qubit set is transferred from the second position set 352 to the third position set 353. 14 At position 353, each qubit in the qubit group undergoes a single-qubit operation.
[0069] Figure 6A , Figure 6B , Figure 6C and Figure 6DA portion of a qubit processor circuit according to a sixth embodiment is schematically illustrated. Four location sets 451, 452, 453, and 454 with alternating coupled and decoupled configurations are shown. The positioning of qubit groups comprising five qubits 455, 456, 457, 458, and 459 in the qubit processor is shown at different time points during the runtime phase of the qubit processing method. The processing parameters of the qubit processor (i.e., qubit precession frequency and nearest-neighbor connectivity) are tuned during the compilation phase prior to the runtime phase. Selective tuning of nearest-neighbor connectivity forms single-qubit and two-qubit logic gates.
[0070] exist Figure 6A The first transfer step is depicted in the diagram. The qubit is shown at time t1, where the qubit state is represented as... , 1 ≤ i ≤ 5. The first set of positions 451 is configured in a decoupled arrangement with five single-qubit quantum logic gates 461, 462, 463, 464, and 465. Each qubit 455-459 in the qubit group that has undergone single-qubit operation at the single-qubit gates 461-465 of the first set of positions 451 over time Δt s It is transferred to the second position set 452, as shown by the horizontal line.
[0071] exist Figure 6B In the operation, at time t2>t1, qubits 455-459 in the qubit group are located in the second position set 452, which is configured in a coupled arrangement. With the operation time Δt... g The set of qubits 455-459 is manipulated. Interactions occur between the first qubit 455 and the second qubit 456 at the first two-qubit quantum logic gate 471, and between the third qubit 457 and the fourth qubit 458 at the second two-qubit quantum logic gate 472. A portion of the two-qubit quantum logic gate 473 is shown, where the fifth qubit 459 interacts with an adjacent qubit (not shown). At time t2, the qubit state is represented as... , 1 ≤ i ≤ 5.
[0072] Figure 6C It shows something similar to Figure 6A The second transfer step is shown in the diagram. At time t3 > t2, the qubit state is represented as... ,1 ≤ i ≤ 5. like Figure 6B As shown, qubits 455-459 have undergone a two-qubit operation in the second position set 452. At time Δt s During this period, qubit sets 455-459 were transferred from the second position set 452 to the third position set 453.
[0073] exist Figure 6D In the diagram, at time t4>t3, qubit sets 455-459 are shown at the third position set 453, where the qubit states are represented as follows: , 1 ≤ i ≤ 5. The third position set 453 is in a decoupled configuration. There are five single-qubit quantum logic gates 481, 482, 483, 484, and 485 at the third position set 453. During the operation time Δt... g During this period, each of the qubits 455-459 in this group of qubits underwent single-qubit operation.
[0074] Figure 7 The diagram schematically illustrates the qubit shuttle according to the seventh embodiment. The graph depicts the change in electric potential energy (in arbitrary units) with distance. This potential energy spans two trapping locations within two location sets 501 and 502. In this embodiment, the electron potential pattern can be altered to "trap" electrons and to transfer electrons from one location set to another. The shuttle time Δt... s During this period, at four time points t s1 t s2 t s3 t s4 The potential energy is shown at t, where t s1 <t s2 <t s3 <t s4 At time t s1 Electrons are captured in the first set of positions 501. By reversing the bias between the sets of positions 501 and 502, electrons are shuttled from the first set of positions 501 to the second set of positions 502. This results in an increase in the potential energy of the electrodes at the capture position in the first set of positions 501 and a decrease in the potential energy of the electrodes at the capture position in the second set of positions 502 during the shuttle step. Simultaneously, the potential energy of the surrounding electrodes is maintained above the capture threshold to confine the electrons to specific positions within the set of positions. As the bias voltage of the second set of positions 502 increases and the bias voltage of the first set of positions 501 decreases, the electrons move with the potential and shuttle from one set of positions to the next when they find a low potential. The shift bias locally generates a minimum moving potential for a single set of qubits. At time t... s4 At this location, electrons are captured in the second position set 502.
[0075] Figure 8A and Figure 8BA shuttle operation of a qubit is schematically illustrated. In this example, the processing time of the operation steps is the same in each set of locations 601, 602, 603, 604, 605, and 606. Therefore, each set of qubits can enter three set of locations of the qubit processor after the previous set of qubits. In this embodiment, six consecutive set of locations 601-606 are shown. Each electrode at each location is schematically represented by a square, and the electron potential of the electrode is represented by the depth of the shading. Darker shading corresponds to higher potential energy. Electron spin qubits 611 and 612 are shown by circles on the electrodes. In this embodiment, each set of locations 601-606 includes a "capture" location, which includes an electrode with low potential energy. Each capture location is surrounded by a confinement location that includes an electrode with high potential energy. Figure 8A In this process, the potentials of the first set of positions 601 and the fourth set of positions 604 are shifted, such that the potential wells of the electrodes at the corresponding capture positions 621 and 624 are reduced to below the capture threshold, and the electron spin qubits 611 and 612 are captured.
[0076] During the shuttle process, the potential energy of the second position set 602 and the fifth position set 605 is reduced, while the potential energy of the first position set 601 and the fourth position set 604 is increased. In this way, electrons transfer in parallel along the qubit processor. Figure 8B In the process, the electrons have already shuttled to the capture positions 622 and 625 within the second position set 602 and the fifth position set 605, respectively. The potential energy of the electrodes at the restrictive positions 631, 632, 633, 634, 635, 636, 641, 642, 643, 644, 645, and 646 surrounding the capture positions 621, 622, 623, 624, 625, and 626 is too high to capture the electrons. Therefore, these electrodes guide the electrons to selected positions within the position sets.
[0077] Figure 9 This is a flowchart describing the operations involving a single qubit in a qubit processing method. A qubit 701 is received at a position in the nth position set. This is achieved by applying an offset voltage to lower the potential well of the nth position set, thereby capturing an electron at the capture position. After capturing the qubit, operation 702 is performed on the qubit's state. This operation can be, for example, an X or Z rotation, and the parameters controlling this operation are predetermined during the compilation phase of the qubit processor. After manipulating the qubit state, the qubit is transferred 703 from its position in the nth position set to the corresponding position in the (n+1)th position set.
[0078] Figure 10A , Figure 10B and Figure 10C The diagram schematically illustrates a shuttle operation involving two qubits. Figure 10A In this process, the potential of the second set of positions 802 is shifted to capture the group of n qubits, where n = 2, within the second set of positions 802. In the second set of positions 802, electrodes are configured such that two qubits 831 and 832 are captured in capture positions 843 and 844, and separated by restraint positions 854, 855, and 856. Each qubit 831 and 832 undergoes a single-qubit operation in the second set of positions 802, which takes time Δt. g2 .
[0079] Figure 10B This illustrates the movement of electrons from the second position set 802 to the third position set 803 during the shuttle process. The time Δt taken for the shuttle process is shown. s2 In the third position set 803, two qubits 831 and 832, separated by confinement position 855 in the second position set 802, are brought together. This is achieved by configuring the electrodes at confinement positions 854-856 in the second position set 802 and the electrodes at confinement positions 857, 858, and 859 in the third position set 803 such that the second qubit 832 diagonally shuttles from the capture position 844 in the second position set 802 to the capture position 846 in the third position set 803. The first qubit 831 horizontally shuttles from the capture position 843 in the second position set 802 to the capture position 845 in the third position set 803. In the third position set 803, the tunneling coupling between the first qubit 831 and the second qubit 832 increases as they are in adjacent positions. This enables two-qubit interaction between the first qubit 831 and the second qubit 832 in the third position set 803. In this example, the two-qubit interaction increases with time Δt. g3 =Δt g2 occur.
[0080] exist Figure 10C The figure shows the time Δt spent during the second shuttle process. s3 =Δt s2 The movement of electrons involves the first set of qubits being shuttled from the third position set 803 to the fourth position set 804. In the fourth position 804, the second qubit 832 is diagonally shuttled away from the first qubit 831. The first qubit 831 and the second qubit 832 in the fourth position set 804 change with time Δt. g4 =Δt g2 A single-qubit operation is performed. While the first set of qubits is being transferred from the third set of positions 803 to the fourth set of positions 804, a second set of qubits is received at the first set of positions 801. This second set of qubits includes the third qubit 833 and the fourth qubit 834.
[0081] In this example, for each set of locations, the shuttle time Δt si They are equal, where i represents the set of positions from which the qubit group transfers. Similarly, for each set of positions, the operation time Δt... gi They are equal, where i represents the set of locations where the operation is performed. Typically, the operation time is significantly longer than the shuttle time Δt. gi >>Δt si For example, the operation time can be 1×10. -6 In the order of s, the shuttle time can be 1×10 -9 On the order of s. In other embodiments, the operation time and / or shuttle time may differ between the location sets, and the first and second qubit sets may be separated by more than two unoccupied location sets.
[0082] A voltage source is used to apply a global offset to a specific set of locations, allowing for shuttle travel along these sets of qubits while the underlying potential pattern remains constant. This shuttle process is fast, typically taking about one nanosecond. Thus, in Figure 10C The third qubit 833 and the fourth qubit 834 of the second set of qubits captured in the first position set 801 will undergo with Figure 10A , Figure 10B and Figure 10C The first qubit 831 and the second qubit 823 in the first group of qubits shown have the same pattern of interaction.
[0083] Figure 11 This is a flowchart describing the operation of two qubits in a qubit processing method. A first set of qubits is received at a first set of locations 901. Afterwards, the state of the qubits is manipulated according to predetermined parameters 902. Then, the first set of qubits is transferred from the first set of locations 903 to a second set of locations, where the state is manipulated again 904. After the operation phase in the second set of locations, the first set of qubits is transferred 905 to a third set of locations. In this embodiment, the operations in the first and second set of locations are single-qubit operations, and the operation in the third set of locations is a two-qubit operation. The potential scenario is such that the two-qubit interaction is typically performed by bringing the two qubits close together to increase tunneling coupling 906. For example, the first qubit can move horizontally, and the second qubit can move both horizontally and vertically, making the second qubit adjacent to the first qubit. After the interaction of the two qubits, the first set of qubits is transferred from the third set of locations 907 to a fourth set of locations. Simultaneously, a second set of qubits is received at the first set of locations 908. The second set of qubits undergoes the same operations, transfers, and interactions (steps 902-907) as the first set of qubits, but with a small time delay. Using this arrangement, multiple sets of qubits can be manipulated and processed in the same way.
[0084] Figure 12 A top view schematically illustrates an implementation of a qubit processor using electron spin qubits fabricated using SiMOS technology. A silicon-on-insulator (SOI) substrate, comprising a lower silicon layer, an intermediate insulating layer, and an upper silicon layer, is selectively etched to retain the raised “mesh” 1001 of silicon nanowires (SiNWs). The upper silicon layer is selectively etched to create the mesh, which is supported by the lower silicon layer and the intermediate insulating layer of the SOI substrate (not shown).
[0085] The mesh comprises a two-dimensional array of orthogonal nanowires referred to as horizontal SiNW 1002 and vertical SiNW 1003. A dielectric material such as silicon dioxide (SiO2) is arranged on top of the SiNWs to form an electrostatic barrier. Four surface electrodes 1011, 1012, 1013, and 1014 are disposed on a substantially flat region of the mesh at the intersection between the horizontal SiNW 1002 and the vertical SiNW 1003. Three exchange electrodes 1004, 1006, and 1008 are disposed on a substantially flat region of the horizontal SiNW 1002. Each exchange region below the exchange electrodes 1004, 1006, and 1008 can be coupled to two confinement regions, wherein the confinement regions are located below the surface electrodes 1011–1014. Figure 12 In the first surface electrode 1011 and the second surface electrode 1012 are positioned on opposite sides of the first exchange electrode 1004.
[0086] Each of the vertical SiNWs 1003 has two edges 1020, 1030, 1040, and 1050. Twenty edge electrodes 1021, 1022, 1023, 1024, 1025, 1031, 1032, 1033, 1034, 1035, 1041, 1042, 1043, 1044, 1045, 1051, 1052, 1053, 1054, and 1055 are disposed on each of the edges 1020, 1021-1025 of the first edge 1020, and the other edge electrodes 1031-1035 on the second edge 1030 to form an edge electrode pair. Similarly, each edge electrode 1041-1045 on the third edge 1040 is arranged opposite to the other edge electrodes 1051-1055 on the fourth edge 1050 to form an edge electrode pair. Each pair of edge electrodes is spaced 10 nanometers apart. Adjacent edge electrode pairs are spaced 10 nanometers apart. In an alternative embodiment, the spacing between edge electrodes across the SiNW can be up to 200 nanometers, and the spacing between edge electrodes along the SiNW can be up to 200 nanometers. Each edge electrode 1021-1025, 1031-1035, 1041-1045, 1051-1055 is configured such that quantum dots can be induced in the silicon mesh 1001 below the respective edge electrode. These quantum dots define locations where qubits can be received.
[0087] Surface electrodes 1011-1014 are formed of polycrystalline silicon. Corresponding conductive vias 1015, 1016, 1017, 1018 or vertical interconnects formed of gold are electrically connected to each of the surface electrodes 1011-1014. A bias potential can be applied to the surface electrodes 1011-1014 to induce confinement regions in the silicon mesh 1001 below the respective surface electrodes 1011-1014. Exchange electrodes 1004, 1006, 1008 also include conductive material and are electrically connected to corresponding conductive vias 1005, 1007, 1009, which include conductive material. A bias potential can be applied to the exchange electrodes 1004, 1006, 1008 to dope the regions below the exchange electrodes, thereby providing a method for exchanging quantum information between the vertical SiNWs 1003.
[0088] Similarly, edge electrodes 1021-1025, 1031-1035, 1041-1045, and 1051-1055 include conductive material and are electrically connected to corresponding conductive vias 1061, 1062, 1063, 1064, 1065, 1071, 1072, 1073, 1074, 1075, 1081, 1082, 1083, 1084, 1085, 1091, 1092, 1093, 1094, and 1095, all including conductive material. Figure 12 In this design, conductive vias are located at one end of each edge electrode. However, the location of the conductive vias does not affect the electrical performance of the device. Bias potentials can be applied to the edge electrodes 1021-1025, 1031-1035, 1041-1045, and 1051-1055 to induce quantum dots at the edges of the SiNW.
[0089] In an alternative embodiment, the exchange electrodes 1004, 1006, 1008, surface electrodes 1011-1014, edge electrodes 1021-1025, 1031-1035, 1041-1045, 1051-1055, and conductive vias 1005, 1007, 1009, 1015-1018, 1061-1065, 1071-1075, 1081-1085, 1091-1095 can be formed of any conductive material.
[0090] In the qubit processing method, edge electrodes 1021-1025, 1031-1035, 1041-1045, 1051-1055 and surface electrodes 1011-1014 can be used to support qubits in silicon mesh 1001, and exchange electrodes 1004, 1006 and 1008 can be used to perform two-qubit interactions.
[0091] exist Figure 12In the embodiment shown, the positions are parallel to the horizontal SiNW1002 as described in the previous figures. Each position in the position set includes an electrode. The movement of the qubit during the qubit processing method is substantially vertical. For example, a first qubit may (a) move from the first edge electrode 1021 of the first edge 1020 to the first surface electrode 1011, then (b) move to the second edge electrode 1022 of the first edge 1020, then (c) move to the third edge electrode 1023 of the first edge 1020, then (d) move to the fourth edge electrode 1034 of the second edge 1030, then (e) move to the third surface electrode 1013, and then (f) move to the fifth edge electrode 1035 of the second edge 1030. The second qubit can (a) move from the first edge electrode 1051 of the fourth edge 1050 to the second surface electrode 1012, then (b) move to the second edge electrode 1052 of the fourth edge 1050, then (c) move to the third edge electrode 1053 of the fourth edge 1050, then (d) move to the fourth edge electrode 1044 of the third edge 1040, then (e) move to the fourth surface electrode 1014, and then (f) move to the fifth edge electrode 1045 of the third edge 1040.
[0092] The first and second qubits form part of a qubit group, which will move as a group through the qubit processor. Steps (a)-(f) for the first qubit occur simultaneously with steps (a)-(f) for the second qubit. In step (a), each of the first and second qubits is transferred from the edge electrode to the first surface electrode 1011 and the second surface electrode 1012, respectively. At this time, a two-qubit interaction occurs between the first and second qubits. The two-qubit interaction is mediated by the first exchange electrode 1004. Single-qubit interaction can be performed at any pair of edge electrodes parallel to the horizontal SiNW 1002. In step (e), the first and second qubits are transferred to the third surface electrode 1013 and the fourth surface electrode 1014, respectively.
[0093] In an alternative embodiment, any number of edge electrodes can be present between adjacent horizontal SiNWs. Furthermore, exchange electrodes can be present between each surface electrode. The exchange electrodes can be controlled by selective bias to control the position of the two-qubit gates that provide mediation for the exchange interactions.
[0094] Figure 13A and Figure 13B The top view and cross-sectional side view of another implementation of the qubit processor are schematically shown, respectively. This implementation is similar to [see...]. Figure 12 The described implementation method.
[0095] exist Figure 13A In the SiNW mesh 2001, horizontal SiNW 2002 and vertical SiNW 2003 are provided. A first dielectric layer 2101 comprising silicon dioxide (SiO2) is provided on the SiNW mesh 2001. Exchange electrodes 2004 disposed on a region of the substantially planar surface of the horizontal SiNW 2002 can be configured to modulate the exchange interaction between confined regions below the first surface electrode 2011 and the second surface electrode 2012, respectively. The exchange electrodes 2004 are electrically connected to a conductive via 2005, and the first surface electrode 2011 and the second surface electrode 2012 are electrically connected to corresponding conductive vias 2015 and 2016.
[0096] Such as about Figure 12 As described, a metal edge electrode 2021 and a conductive via 2031 are disposed along the edge perpendicular to the SiNW 2003. A second dielectric layer 2102 is disposed on a grid 2001 covering the SiNWs 2002, 2003, the exchange electrode 2004, the first and second surface electrodes 2011, 2012, and the edge electrode 2021. A top electrode 2041 is disposed covering the vertical SiNW 2003.
[0097] In this embodiment, the widths of the horizontal SiNW 2002 and the vertical SiNW 2003 are substantially the same, but this is blurred in the top view because the second dielectric layer 2102 and the top electrode 2041 are positioned to cover the SiNW 2002 and 2003.
[0098] Figure 13B The processor is shown along Figure 13A A cross-sectional view of line A indicated in the diagram. A first dielectric layer 2101 is arranged to cover a vertical SiNW 2003. The SiNW 2003 has two edges 2020 and 2030. Two metal edge electrodes 2021 are positioned to cover the corresponding edges 2020 and 2030 of the SiNW 2003. Each of the two conductive vias 2031 is in electrical contact with one of the two metal edge electrodes 2021. A second dielectric layer 2102 is arranged to cover the SiNW 2003 and the metal edge electrodes 2021.
[0099] As will be recognized, an improved qubit processing method and a qubit processor for use in the NISQ era are provided, wherein the resources required to execute the method are reduced. Dense qubit architectures can be implemented in SiMOS devices for quantum computing. The simplified control of the large number of qubit arrays provided makes scaling up these devices feasible.
Claims
1. A method for performing quantum computing in a qubit processor, comprising the following steps: Configure the first position in the first position set to perform the first single-qubit operation; Configure the second position in the first position set to perform a second single-qubit operation; Configure the first and second positions in the second position set to perform two-qubit interactions; At time t1, the first qubit is received at the first position in the first set of positions; At time t1, the second qubit is received at the second position in the first set of positions; Wherein, both the first qubit and the second qubit are provided in a first qubit group comprising n qubits, where n > 2; the first single-qubit operation is performed on the state of the first qubit at the first position in the first position set; Perform the second single-qubit operation on the state of the second qubit at the second position in the first position set; The first qubit is transferred from the first position in the first position set to the first position in the second position set; The second qubit is transferred from the second position in the first position set to the second position in the second position set; The two-qubit interaction occurs between the first and second qubits in the second location set; The first qubit is transferred from the first position in the second position set to the first position in the read position set; The second qubit is transferred from the second position in the second position set to the second position in the read position set; At time t2, the first qubit of the second qubit group is received at the first position in the first position set, where t2 > t1; At time t2, the second qubit of the second qubit group is received at the second position in the first position set; Read the state of the first qubit at the first position in the set of read positions; and Read the state of the second qubit at the second position in the set of read positions.
2. The method according to claim 1, wherein: At time t tr At this point, the first qubit of the first qubit group is transferred from the first position in the second position set to the first position in the third position set; as well as At time t tr At this point, the second qubit of the first qubit group is transferred from the second position in the second position set to the second position in the third position set; Where t2 ≥ t tr > t1.
3. The method according to claim 1, wherein: At time t r At this location, read the state of the first qubit of the first qubit group; and At time t r At this point, read the state of the second qubit of the first qubit group; Among them, t r > t2.
4. The method according to claim 2, further comprising the following step: At time t3, the first qubit of the first qubit group is transferred from the first position in the third position set to the first position in the fourth position set; At time t3, the second qubit of the first qubit group is transferred from the second position in the third position set to the second position in the fourth position set; At time t3, the first qubit of the second qubit group is transferred from the first position in the first position set to the first position in the second position set; as well as At time t3, the second qubit of the second qubit group is transferred from the second position in the first position set to the second position in the second position set; Where t3 > t2.
5. The method according to claim 1, further comprising: Perform an initialization operation at the first location set.
6. The method according to claim 1, comprising N sets of locations, wherein, N > 3, where the set of reading positions is the Nth position set.
7. The method of claim 1, further comprising the following step: The i-th qubit in the first qubit group interacts with the (i+1)-th qubit in the first qubit group, such that each qubit in the first qubit group interacts directly or indirectly with every other qubit in the first qubit group, where 1 ≤ i < n.
8. The method according to claim 1, wherein, The first qubit in the first qubit group does not interact with the first qubit in the second qubit group.
9. The method according to claim 1, wherein, Each transfer step involves an electronic shuttle.
10. The method according to claim 9, wherein, The quantum bit is an electron spin quantum bit or a trapped ion quantum bit.
11. The method according to claim 1, wherein, Each transfer step includes a SWAP operation.
12. A qubit processor for performing the method according to any one of the preceding claims, comprising: First position set; Second position set; as well as Read the location set; Each set of locations includes at least a first location and a second location, wherein the first location and the second location are configured to receive a first qubit and a second qubit, respectively; Wherein, the first position in the first position set is configured to perform a first single-qubit operation, and the second position in the first position set is configured to perform a second single-qubit operation; The first set of locations is configured as follows: A first qubit is received at the first position and a second qubit is received at the second position; Perform the first single-qubit operation on the state of the first qubit; and Perform the second single-qubit operation on the state of the second qubit; Wherein, the first position and the second position in the second position set are configured to perform two-qubit interactions; and Wherein, the first qubit and the second qubit are transferred from the first position set to the second position set, wherein the second position set is configured to perform two-qubit interaction between the first qubit and the second qubit; Specifically, the first qubit and the second qubit are transferred from the second location set to the read location set; and The set of read positions is configured to read the state of the first qubit and the state of the second qubit.
13. The quantum bit processor according to claim 12, further comprising a third set of locations; wherein, A voltage source is electrically connected to the first set of locations and the third set of locations so as to apply voltage to both the first set of locations and the third set of locations simultaneously.