A SOC multi-clock glitch-free switching circuit

Abstract

The present invention provides a SOC multi-clock glitch-free switching circuit, which relates to the field of SOC integrated circuits. The present invention simplifies the steps required for multi-clock switching by setting a hardware circuit. When the system switches the clock, it only needs to set the corresponding clock code in the system register. The clock code is compiled into a one-hot encoded clock code by a first encoder and is respectively handed over to each clock branch; each clock branch determines whether it matches the clock connected to itself based on the clock code. If it matches, the corresponding clock is output to complete the clock switching; the present invention only needs to set the corresponding system register. For the software layer, it is not necessary to pay attention to the clock switching steps to obtain the desired clock, thereby solving the problem that the switching method of the prior art needs to be carried out in several steps. In addition, the present invention also provides a clock indication unit. The system can know the current real clock by reading the output signal of the clock indication unit.

Description

Technical Field

[0001] The present invention relates to the field of SOC integrated circuits, and in particular to a SOC multi-clock glitch-free switching circuit. Background Art

[0002] The common multi-clock glitch-free switching circuits in current SOCs mainly include two types: double-ended switching circuits and multi-ended switching circuits. For example, for the double-ended switching circuit, when performing clock switching on four clocks, namely clk1, clk2, clk3 and clk4, assuming that clk_out switches from clk2 to clk3, it may be necessary to first switch from clk2 to clk1, and then from clk1 to clk3. This switching method needs to be carried out in several steps, and may also require a transition clock. From the software layer, both the switching steps and the switching complexity are slightly cumbersome.

[0003] Therefore, it is necessary to provide a SOC multi-clock glitch-free switching circuit to solve the above technical problems. Summary of the Invention

[0004] In order to solve one of the above technical problems, the present invention provides a SOC multi-clock glitch-free switching circuit, which is arranged on a SOC system chip. The SOC system chip is provided with a system register, a plurality of clocks and a clock switching circuit. The system register is compiled with a clock code of the required clock through ordinary binary code; the clock switching circuit includes a first decoder, a plurality of clock branches and a circuit clock output unit.

[0005] Specifically, the first decoder is used to translate ordinary binary code into one-hot code, and includes an input end and an output end; the input end of the first decoder is electrically connected to the system register and receives the clock code compiled by the ordinary binary code, and the output end is used to send the clock code compiled by the one-hot code and is electrically connected to each clock branch respectively.

[0006] Specifically, the number of the clock branches is the same as the number of clocks, including an input selection unit, a synchronizer unit, a switch unit and a branch clock output unit; the input selection unit of the clock branch is set by an AND gate and includes a plurality of input terminals and an output terminal, wherein the number of input terminals of the input selection unit is the same as the number of clocks; the synchronizer unit includes a first synchronizer and a second synchronizer, and the first synchronizer and the second synchronizer are both set by a rising edge D flip-flop, including a D terminal, a Q terminal and a rising edge trigger terminal; the D terminal of the first synchronizer is electrically connected to the output terminal of the input selection unit, the rising edge trigger terminal is electrically connected to the corresponding clock, and the Q terminal is electrically connected to the second synchronizer; the D terminal of the second synchronizer is electrically connected to the Q terminal of the first synchronizer The rising edge trigger end is electrically connected with the corresponding clock, and the Q end serves as the output end of the synchronizer unit and is electrically connected with the switch unit; the switch unit is set by a falling edge D trigger, including a D end, a Q end and a falling edge trigger end; the D end of the switch unit is electrically connected with the output end of the synchronizer unit, the falling edge trigger end is electrically connected with the corresponding clock, and the Q end serves as the output end of the switch unit and is electrically connected with the branch clock output unit; the branch clock output unit is set by an AND gate, including two input ends and an output end, the input end of the branch clock output unit is electrically connected with the output end of the switch unit and the corresponding clock respectively, and the output end serves as the output end of the clock branch and is electrically connected with the circuit clock output unit.

[0007] One input terminal of the input selection unit is electrically connected to the output terminal of the first decoder, and the remaining input terminals are provided with NOT gates and are electrically connected to the output terminals of the switcher units except the current clock branch.

[0008] Specifically, the circuit clock output unit is set through an OR gate, including input ends and an output end with the same number as the clock branches; the input end of the circuit clock output unit is electrically connected to the output end of each clock branch respectively, and the output end serves as the output end of the clock switching circuit and outputs a clock electrical signal.

[0009] As a further solution, a sw_reg register is provided in the system register, and the sw_reg register is used to set a clock code of a required clock.

[0010] As a further solution, the clock encoding of the required clock can also be compiled through one-hot encoding.

[0011] As a further solution, when the system register directly compiles the clock code of the required clock through one-hot encoding, the first decoder can be removed and the system register can be directly electrically connected to each clock branch.

[0012] As a further solution, a clock indication unit is further provided. The clock indication unit is set by a second decoder. The second decoder is used to compile the one-hot code into an ordinary binary code. The second decoder includes an input end and an output end. The input end of the second decoder is electrically connected to the output end of each clock branch switch unit, and the output end of the second decoder outputs the ordinary binary code corresponding to the current clock.

[0013] As a further solution, when the system register directly compiles the clock code of the required clock through one-hot encoding, the second decoder can be withdrawn, and the output end of each clock branch switch unit can be directly brought out and used as the output end of the clock indication unit.

[0014] Compared with related technologies, the SOC multi-clock glitch-free switching circuit provided by the present invention has the following beneficial effects:

[0015] The present invention simplifies the steps required for multi-clock switching by setting up hardware circuits. When the system switches the clock, it only needs to set the corresponding clock code in the system register. The clock code is compiled into a one-hot encoded clock code by a first encoder and is respectively handed to each clock branch. Each clock branch determines whether it matches the clock connected to itself based on the clock code. If it matches, the corresponding clock is output to complete the clock switching. The present invention only requires setting the corresponding system register. For the software layer, there is no need to pay attention to the clock switching steps to obtain the desired clock, thus solving the problem that the switching method of the prior art requires several steps. In addition, the present invention also provides a clock indication unit. By reading the output signal of the clock indication unit, the system can know the current real clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 An overall circuit diagram of a SOC multi-clock glitch-free switching circuit provided by an embodiment of the present invention;

[0017] Figure 2 A clock branch circuit diagram of a SOC multi-clock glitch-free switching circuit provided by an embodiment of the present invention;

[0018] Figure 3 This is a structural diagram of an existing clock glitch-free switching circuit provided by an embodiment of the present invention.

[0019] Among them, the figure marks: 1. input selection unit; 2. first synchronizer; 3. second synchronizer; 4. switch unit; 5. branch clock output unit. DETAILED DESCRIPTION

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] like Figure 1 The present embodiment provides a SOC multi-clock glitch-free switching circuit, which is arranged on a SOC system chip. The SOC system chip is provided with a system register, a plurality of clocks and a clock switching circuit. The system register has a clock code of the required clock compiled by ordinary binary code; the clock switching circuit includes a first decoder, a plurality of clock branches and a circuit clock output unit.

[0022] Specifically, the first decoder is used to translate ordinary binary code into one-hot code, and includes an input end and an output end; the input end of the first decoder is electrically connected to the system register and receives the clock code compiled by the ordinary binary code, and the output end is used to send the clock code compiled by the one-hot code and is electrically connected to each clock branch respectively.

[0023] It should be noted that this embodiment uses a first decoder to convert ordinary binary code into a one-hot code, where each clock corresponds to one bit. For example, in one specific embodiment, if the clocks are clk1, clk2, clk3, and clk4, the clock code compiled using one-hot coding has a total of four bits, with bit 0 corresponding to clk1 and bit 3 corresponding to clk4. Because one-hot coding has the property of only one bit being 1 and the remaining bits being 0, it is well suited for clock switching. For example, if the current clock is clk2, the clock code is 4'b0010. To switch to clk3, the clock code only needs to be set to 4'b0100. The same setting method can be used for other situations.

[0024] like Figure 2As shown, specifically, the number of the clock branches is the same as the number of clocks, including an input selection unit 1, a synchronizer unit, a switch unit 4 and a branch clock output unit 5; the input selection unit 1 of the clock branch is set by an AND gate and includes a plurality of input terminals and an output terminal, wherein the number of input terminals of the input selection unit 1 is the same as the number of clocks; the synchronizer unit includes a first synchronizer 2 and a second synchronizer 3, and the first synchronizer 2 and the second synchronizer 3 are both set by a rising edge D flip-flop, including a D terminal, a Q terminal and a rising edge trigger terminal; the D terminal of the first synchronizer 2 is electrically connected to the output terminal of the input selection unit 1, the rising edge trigger terminal is electrically connected to the corresponding clock, and the Q terminal is electrically connected to the second synchronizer 3; the D terminal of the second synchronizer 3 is electrically connected to the first synchronizer 2, the rising edge trigger end is electrically connected to the corresponding clock, the Q end serves as the output end of the synchronizer unit and is electrically connected to the switch unit 4; the switch unit 4 is set by a falling edge D trigger, including a D end, a Q end and a falling edge trigger end; the D end of the switch unit 4 is electrically connected to the output end of the synchronizer unit, the falling edge trigger end is electrically connected to the corresponding clock, the Q end serves as the output end of the switch unit 4 and is electrically connected to the branch clock output unit 5; the branch clock output unit 5 is set by an AND gate, including two input ends and one output end, the input end of the branch clock output unit 5 is electrically connected to the output end of the switch unit 4 and the corresponding clock respectively, the output end serves as the output end of the clock branch, and is electrically connected to the circuit clock output unit.

[0025] One input terminal of the input selection unit 1 is electrically connected to the output terminal of the first decoder, and the remaining input terminals are provided with NOT gates and are electrically connected to the output terminals of the switch unit 4 except the current clock branch.

[0026] Specifically, the circuit clock output unit is set through an OR gate, including input ends and an output end with the same number as the clock branches; the input end of the circuit clock output unit is electrically connected to the output end of each clock branch respectively, and the output end serves as the output end of the clock switching circuit and outputs a clock electrical signal.

[0027] It should be noted that the clock switching circuit receives the clock code set by the system register and automatically switches the current output clock to the clock represented by the clock code. In order to illustrate the working principle of this circuit, this embodiment uses Figure 1 The four-clock circuit shown in the figure is explained. First, when the system switches the clock, it only needs to set the corresponding system register, which is a very convenient method for software. The clock code set in the system register is compiled into a one-hot encoded clock code sw[i] by the first encoder and then sent to each clock branch.

[0028] After the clock branch receives the clock code sw[i], it will be sent to the first synchronizer through the input selection unit 1. At this time, the input received by the first synchronizer is combinational logic, but it is obvious that only one input of the combinational logic input end changes at the same time, so there will be no competition and it is safe; the function of the synchronizer unit setting is to synchronize sw[i] under the system clock domain to the corresponding clock domain. After clock domain synchronization, the synchronizer unit sends the synchronized sw[i] to the switch unit 4. Switch unit 4 is a falling-edge-triggered D flip-flop whose trigger terminal is connected to the corresponding clock clki. The falling edge is selected primarily to avoid glitches caused by rising-edge triggering. Finally, switch unit 4 outputs the clock based on whether sw[i] matches the current clock. If the current clock is clki, represented by sw[i], a one-hot encoded sw_real[i] is obtained. sw_real[i] represents the one-hot encoding corresponding to the clock output of the circuit. sw_real[i] and the clock are simultaneously input into the branch clock output unit 5, which is an AND gate. If the two are synchronized and corresponding, the AND gate will output the corresponding clock signal to the circuit clock output unit. Otherwise, no clock is output. Since the circuit clock output unit is an OR gate, after receiving the clock signal, it uses it as the output terminal of the clock switching circuit and outputs the clock signal, completing the corresponding clock switching.

[0029] As a further solution, a sw_reg register is provided in the system register, and the sw_reg register is used to set a clock code of a required clock.

[0030] It should be noted that: this implementation reduces the software layer's concern for clock switching through hardware circuits. The software layer only needs to define the clock code of the required clock to obtain the desired clock, thereby increasing the practicality of the SOC chip.

[0031] As a further solution, the clock encoding of the required clock can also be compiled through one-hot encoding.

[0032] As a further solution, when the system register directly compiles the clock code of the required clock through one-hot encoding, the first decoder can be removed and the system register can be directly electrically connected to each clock branch.

[0033] It should be noted that if the clock code of the SOC chip is directly compiled using one-hot coding, it is possible to choose not to set the first decoder.

[0034] As a further solution, a clock indication unit is also provided. The clock indication unit is set by a second decoder. The second decoder is used to compile the one-hot code into an ordinary binary code, including an input end and an output end. The input end of the second decoder is electrically connected to the output end of each clock branch switch unit 4, and the output end of the second decoder outputs the ordinary binary code corresponding to the current clock.

[0035] As a further solution, when the system register directly compiles the clock code of the required clock through one-hot encoding, the second decoder can be withdrawn, and the output end of each clock branch switch unit can be directly brought out and used as the output end of the clock indication unit.

[0036] It should be noted that switching the clock takes several clock cycles, and the clock indication unit is used to indicate the current real clock and provide it to the software layer for viewing.

[0037] This circuit is extremely friendly to software control. The software only needs to set the corresponding system registers without paying attention to the switching steps. The circuit will output the corresponding clock electrical signal according to the register settings, thus solving the following problems: Figure 3 As shown, the switching method in the prior art needs to be carried out in several steps and may also require a transition clock. When the software switches the clock, the switching steps are cumbersome and complicated.

[0038] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A SOC multi-clock glitch-free switching circuit, provided on a SOC system chip, characterized in that: The SOC system chip is provided with a system register, a plurality of clocks and a clock switching circuit. The system register is encoded with a clock code of a required clock by ordinary binary code. The clock switching circuit includes a first decoder, a plurality of clock branches and a circuit clock output unit. The first decoder is used to translate ordinary binary code into one-hot code, and includes an input end and an output end; the input end of the first decoder is electrically connected to the system register and receives the clock code compiled from the ordinary binary code, and the output end is used to send the clock code compiled from the one-hot code and is electrically connected to each clock branch respectively; The number of the clock branches is the same as the number of clocks, and includes an input selection unit (1), a synchronizer unit, a switch unit (4) and a branch clock output unit (5); the input selection unit (1) of the clock branch is set by an AND gate and includes a plurality of input terminals and an output terminal, wherein the number of the input terminals of the input selection unit (1) is the same as the number of clocks; the synchronizer unit includes a first synchronizer (2) and a second synchronizer (3), and the first synchronizer (2) and the second synchronizer (3) are both set by a rising edge D trigger, including a D terminal, a Q terminal and a rising edge trigger terminal; the D terminal of the first synchronizer (2) is electrically connected to the output terminal of the input selection unit (1), the rising edge trigger terminal is electrically connected to the corresponding clock, and the Q terminal is electrically connected to the second synchronizer (3); the D terminal of the second synchronizer (3) is electrically connected to the first synchronizer (2) is electrically connected to the Q end, the rising edge trigger end is electrically connected to the corresponding clock, and the Q end serves as the output end of the synchronizer unit and is electrically connected to the switch unit (4); the switch unit (4) is set by a falling edge D trigger, including a D end, a Q end and a falling edge trigger end; the D end of the switch unit (4) is electrically connected to the output end of the synchronizer unit, the falling edge trigger end is electrically connected to the corresponding clock, and the Q end serves as the output end of the switch unit (4) and is electrically connected to the branch clock output unit (5); the branch clock output unit (5) is set by an AND gate, including two input ends and one output end, the input end of the branch clock output unit (5) is electrically connected to the output end of the switch unit (4) and the corresponding clock respectively, and the output end serves as the output end of the clock branch and is electrically connected to the circuit clock output unit; One input terminal of the input selection unit (1) is electrically connected to the output terminal of the first decoder, and the remaining input terminals are all provided with NOT gates and are electrically connected to the output terminals of the switch unit (4) except the current clock branch. The circuit clock output unit is set through an OR gate and includes input ends and an output end with the same number as the clock branches; the input end of the circuit clock output unit is electrically connected to the output end of each clock branch respectively, and the output end serves as the output end of the clock switching circuit and outputs a clock electrical signal.

2. The SOC multi-clock glitch-free switching circuit according to claim 1, characterized in that: The system register is provided with a sw_reg register, and the sw_reg register is used to set a clock code of a required clock.

3. The SOC multi-clock glitch-free switching circuit according to claim 1, characterized in that: The clock code of the required clock can also be compiled through one-hot encoding.

4. The SOC multi-clock glitch-free switching circuit according to claim 3, characterized in that: When the system register directly compiles the clock code of the required clock through one-hot encoding, the first decoder can be removed, and the system register is directly electrically connected to each clock branch.

5. The SOC multi-clock glitch-free switching circuit according to claim 1, characterized in that: A clock indication unit is also provided. The clock indication unit is set by a second decoder. The second decoder is used to compile the one-hot code into an ordinary binary code. The second decoder includes an input end and an output end. The input end of the second decoder is electrically connected to the output end of each clock branch switch unit (4) respectively. The output end of the second decoder outputs the ordinary binary code corresponding to the current clock.

6. The SOC multi-clock glitch-free switching circuit according to claim 5, characterized in that: When the system register directly compiles the clock code of the required clock through one-hot coding, the second decoder can be withdrawn, and the output end of each clock branch switch unit (4) is directly led out and used as the output end of the clock indication unit.

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