A storage unit resistant to side signal attacks

Abstract

The present application discloses a memory cell resistant to side signal attacks, which includes a write operation circuit having a pair of complementary storage nodes; a behavior mimicking circuit having the same structure as the write operation circuit, the behavior mimicking circuit having a pair of complementary pseudo storage nodes; and a read operation circuit connected to the write operation circuit. The behavior mimicking circuit is used to mimic the complementary state of the write operation circuit after the write operation circuit writes data, so as to ensure the consistency of power consumption of the memory cell resistant to side signal attacks when storing different data. The present application sets up a behavior mimicking circuit having the same structure as the write operation circuit. After the write operation circuit writes data, the behavior mimicking circuit is used to mimic the complementary state of the write operation circuit to ensure the consistency of power consumption of the memory cell resistant to side signal attacks when storing different data, thereby improving the memory cell's ability to resist power consumption attacks.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a storage unit that is resistant to side signal attacks. Background Art

[0002] Most current side-channel attack-resistant cells shield the power supply and internal storage nodes of the cell before a write operation. They then short-circuit a pair of complementary internal storage nodes to balance the internal storage nodes to half the power supply voltage VDD, thereby reducing the correlation between the cell's stored data and the cell's power consumption.

[0003] However, this presents a problem. When balancing the internal storage nodes of a cell, the connection between the internal storage nodes and the power supply is usually shielded. This results in the balance voltage being likely to deviate from half the power supply voltage (usually less than half the power supply voltage) when a pair of complementary internal storage nodes are short-circuited. This undermines the cell's ability to resist side-channel attacks, creating a risk of information leakage. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a storage unit that is resistant to side signal attacks, which is used to solve the technical problem in the prior art that when the storage unit stores nodes inside the balancing unit, the unit's anti-side channel attack function will be destroyed, thereby causing information leakage risks.

[0005] To achieve the above-mentioned and other related purposes, the present application provides a storage unit, comprising:

[0006] A write operation circuit having a pair of complementary storage nodes;

[0007] A behavior mimicking circuit having the same structure as the write operation circuit, wherein the behavior mimicking circuit has a pair of complementary pseudo storage nodes;

[0008] a read operation circuit connected to the write operation circuit;

[0009] The behavior simulation circuit is used to simulate the complementary state of the write operation circuit after the write operation circuit writes data, so as to ensure the consistency of power consumption of the anti-side signal attack storage unit when storing different data.

[0010] In an optional embodiment of the present application,

[0011] The anti-side signal attack storage unit includes 4 PMOS tubes and 12 NMOS tubes, the 4 PMOS tubes are defined as P1 tube to P4 tube, and the 10 NMOS tubes are defined as N1 tube to N10 tube; wherein,

[0012] Transistors N1 to N4 constitute the read operation circuit: the source of transistor N1 is connected to the first bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N2. The gate of transistor N2 is connected to the first storage node, and the source of transistor N2 is grounded. The source of transistor N4 is connected to the second bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N3. The gate of transistor N3 is connected to the second storage node, and the source of transistor N3 is grounded.

[0013] The P1 transistor, the P2 transistor, and the N5-N7 transistors constitute the write operation circuit: the drain of the N5 transistor is connected to the first bit line, the gate of the N5 transistor is connected to the write word line signal, the source of the N5 transistor is connected to the drain of the P1 transistor, the gate of the N6 transistor, and the gate of the P2 transistor to form a first storage node, the source of the P1 transistor is connected to the source of the P2 transistor and to the power supply, the gate of the P1 transistor is connected to the drain of the P2 transistor and the drain of the N6 transistor to form a second storage node, the source of the N6 transistor is grounded, the source of the N7 transistor is connected to the first storage node, the drain is connected to the second storage node, and the gate is connected to the refresh signal, wherein the N5 transistor serves as a transmission transistor of the write operation circuit, and the first storage node and the second storage node form a pair of complementary storage nodes;

[0014] Transistors P3, P4, and N8-N10 constitute the behavioral emulation circuit: the source of N8 is connected to the drain of N4, the gate of N8 is connected to a write emulation signal, the drain of N8 is connected to the drain of P3, the gate of N9, and the gate of P4 to form a first pseudo storage node of the behavioral emulation circuit, the source of P3 is connected to the source of P4 and to a power supply, the gate of P3 is connected to the drain of P4 and the drain of N9 to form a second pseudo storage node, the source of N9 is grounded, the source of N10 is connected to the second pseudo storage node of the behavioral emulation circuit, the drain is connected to the first pseudo storage node, and the gate is connected to a refresh signal. Transistor N8 serves as a transmission transistor of the behavioral emulation circuit, and the first pseudo storage node and the second pseudo storage node form a pair of complementary pseudo storage nodes.

[0015] In an optional embodiment of the present application, the anti-side signal attack storage unit includes 2 PMOS tubes and 12 NMOS tubes, the 2 PMOS tubes are defined as P1 tube and P2 tube, and the 12 NMOS tubes are defined as N1 tube to N12 tube; wherein,

[0016] Transistors N1 to N4 constitute the read operation circuit: the source of transistor N1 is connected to the first bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N2. The gate of transistor N2 is connected to the first storage node, and the source of transistor N2 is grounded. The source of transistor N4 is connected to the second bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N3. The gate of transistor N3 is connected to the second storage node, and the source of transistor N3 is grounded.

[0017] The P1 transistor, the N5 transistors to the N7 transistors, and the N11 transistor constitute the write operation circuit: the drain of the N5 transistor is connected to the first bit line, the gate of the N5 transistor is connected to the write word line signal, the source of the N5 transistor is connected to the drain of the P1 transistor, the drain of the N6 transistor, and the gate of the N7 transistor to form the second storage node of the write operation circuit, the source of the N6 transistor is connected to the source of the N7 transistor and to the ground, the gate of the P1 transistor is connected to the drain of the N7 transistor to form the first storage node of the write operation circuit, the source of the P1 transistor is connected to the power supply, the source of the N11 transistor is connected to the second storage node, the drain is connected to the first storage node, and the gate is connected to the refresh signal, wherein the N5 transistor serves as a transmission transistor of the write operation circuit, and the first storage node and the second storage node form a pair of complementary storage nodes;

[0018] Transistor P2, transistors N8-N10, and transistor N12 constitute the behavioral mimicry circuit: the source of transistor N8 is connected to the drain of transistor N4, and its gate is connected to a write mimicry signal; the drain of transistor N8 is connected to the drain of transistor P2, the drain of transistor N10, and the gate of transistor N9 to form a first pseudo storage node of the behavioral mimicry circuit; the source of transistor N10 is connected to the source of transistor N9 and to ground; the gate of transistor P2 is connected to the drain of transistor N9 to form a second pseudo storage node; the source of transistor P2 is connected to a power supply; the source of transistor N12 is connected to the second pseudo storage node, its drain is connected to the first pseudo storage node, and its gate is connected to a refresh signal; transistor N8 serves as a transmission transistor of the behavioral mimicry circuit; the first pseudo storage node and the second pseudo storage node form a pair of complementary pseudo storage nodes.

[0019] In an optional embodiment of the present application, the anti-side signal attack storage unit includes 4 PMOS tubes and 12 NMOS tubes, the 4 PMOS tubes are defined as P1 tube to P4 tube, and the 12 NMOS tubes are defined as N1 tube to N12 tube; wherein,

[0020] Transistors N1 to N4 constitute the read operation circuit: the source of transistor N1 is connected to the first bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N2. The gate of transistor N2 is connected to the first storage node, and the source of transistor N2 is grounded. The source of transistor N4 is connected to the second bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N3. The gate of transistor N3 is connected to the second storage node, and the source of transistor N3 is grounded.

[0021] The P1 transistor, the P2 transistor, the N5 transistor, the N7 transistor, the N8 transistor, and the N11 transistor constitute the write operation circuit: the drain of the N5 transistor is connected to the first bit line, and the gate is connected to the write word line signal; the source of the N5 transistor is connected to the drain of the P1 transistor, the drain of the N7 transistor, the gate of the P2 transistor, and the gate of the N8 transistor to form the second storage node of the write operation circuit; the source of the P1 transistor is connected to the source of the P2 transistor and is connected to the power supply; the drain of the P2 transistor is connected to the drain of the N8 transistor, the gate of the P1 transistor, and the gate of the N7 transistor to form the first storage node of the write operation circuit; the source of the N8 transistor is connected to the source of the N7 transistor and is connected to ground; the source of the N11 transistor is connected to the second storage node, the drain is connected to the first storage node, and the gate is connected to the refresh signal; wherein the N5 transistor serves as a transmission transistor of the write operation circuit; the first storage node and the second storage node constitute a pair of complementary storage nodes;

[0022] Transistor P3, transistor P4, transistor N6, transistor N9, transistor N10, and transistor N12 constitute the behavioral emulation circuit: the source of transistor N6 is connected to the drain of transistor N4, and its gate is connected to a write emulation signal; the source of transistor N6 is connected to the drain of transistor P3, the drain of transistor N9, the gate of transistor P4, and the gate of transistor N10 to form a first pseudo storage node of the behavioral emulation circuit; the source of transistor P4 is connected to the source of transistor P3 and to a power supply; the drain of transistor P4 is connected to the drain of transistor N10, the gate of transistor P3, and the gate of transistor N9 to form a second pseudo storage node; the source of transistor N10 is connected to the source of transistor N9 and to ground; the source of transistor N12 is connected to the first pseudo storage node, the drain to the second pseudo storage node, and the gate to a refresh signal. Transistor N6 serves as a transmission transistor of the behavioral emulation circuit; the first pseudo storage node and the second pseudo storage node form a pair of complementary pseudo storage nodes.

[0023] In an optional embodiment of the present application, the width-to-length ratios of the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit are equal, and both are greater than the width-to-length ratios of other MOS tubes in the anti-side signal attack storage unit except the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit.

[0024] In an optional embodiment of the present application, the ratio of the width-to-length ratio of the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit to the width-to-length ratio of other MOS tubes in the anti-side signal attack storage unit except the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit is between 2 and 3.

[0025] In an optional embodiment of the present application, during the data hold period, the first bit line and the second bit line of the word line are pulled to ground.

[0026] In an optional embodiment of the present application, in each write operation cycle, the written data is synchronously loaded into the first bit line and the word line and the second bit line to ensure that the potentials of the first bit line and the word line and the second bit line are the same.

[0027] In an optional embodiment of the present application, in each write operation cycle, before writing data, a refresh signal is enabled to make the first storage node and the second pseudo storage node in the same storage state, and the second storage node and the first pseudo storage node in the same storage state.

[0028] In an optional embodiment of the present application, during a write operation cycle, the write mimic signal is enabled at a falling edge of the write word line signal.

[0029] The side signal attack resistant storage unit of the present application is configured with a behavior mimicking circuit having the same structure as a write operation circuit. After the write operation circuit writes data, the behavior mimicking circuit is used to mimic the complementary state of the write operation circuit to ensure the consistency of power consumption of the side signal attack resistant storage unit when storing different data, thereby improving the ability of the storage unit to resist power consumption attacks.

[0030] In the side signal attack resistant storage unit of the present application, the complementary bit lines are pulled down to ground during the data retention period, which greatly reduces the overall power consumption of the storage unit and solves the common high power consumption problem of power consumption attack resistant units to a certain extent.

[0031] The side signal attack resistant storage unit of the present application can calibrate the leakage current by increasing the width-to-length ratio of the transmission tube in the write operation circuit and the behavior simulation circuit compared to other MOS tubes in the unit, and can prevent the charge accumulation caused by the leakage current from causing the storage node data error flip. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a circuit structure diagram of a first memory unit resistant to side signal attack according to an embodiment of the present application.

[0033] Figure 2 This is a waveform diagram of a write operation of a first memory cell resistant to side signal attacks according to an embodiment of the present application.

[0034] Figure 3 This is a schematic diagram of the write data retention and flipping of the first memory cell resistant to side signal attacks according to an embodiment of the present application.

[0035] Figure 4 This is a circuit structure diagram of a second storage unit resistant to side signal attack according to an embodiment of the present application.

[0036] Figure 5 This is a circuit structure diagram of a third storage unit resistant to side signal attack according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present application through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present application from the disclosure herein. The present application may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present application.

[0038] See also Figure 1-5 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present application. Therefore, the diagrams only show components related to the present application and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0039] See also Figure 1 、 Figure 4 and Figure 5 The present application discloses a storage unit that is resistant to side signal attacks. The storage unit includes a write operation circuit, a behavior imitation circuit, and a read operation circuit.

[0040] The write operation circuit has a pair of complementary storage nodes; the behavioral mimicry circuit has the same structure as the write operation circuit and has a pair of complementary pseudo storage nodes; the read operation circuit is connected to the write operation circuit; the behavioral mimicry circuit is used to mimic the complementary state of the write operation circuit after the write operation circuit writes data, so as to ensure the consistency of power consumption of the anti-side signal attack storage unit when storing different data.

[0041] By setting a behavioral mimicking circuit with the same structure as the write operation circuit in the storage unit, after the write operation circuit writes data, the behavioral mimicking circuit is used to mimic the complementary state of the write operation circuit to ensure the consistency of power consumption of the anti-side signal attack storage unit when storing different data ("0" and "1"), thereby improving the ability of the storage unit to resist power consumption attacks.

[0042] In the present application, the memory cell resistant to side signal attack is, for example, a self-simulating static random access memory cell, abbreviated as SISRAM cell.

[0043] The circuit structure of the memory unit for resisting side signal attack of this embodiment will be described below with reference to three different specific embodiments.

[0044] Example 1

[0045] Figure 1 FIG. 1 shows a circuit structure diagram of a storage unit that resists side signal attacks. Figure 1As shown, the lateral signal attack resistance storage unit includes 4 PMOS tubes and 12 NMOS tubes. The 4 PMOS tubes are defined as P1 tube to P4 tube, and the 10 NMOS tubes are defined as N1 tube to N10 tube.

[0046] Among them, the N1-N4 transistors constitute the read operation circuit: the source of the N1 transistor is connected to the bit line BL (first bit line), the gate is connected to the read word line signal RWL, and the drain is connected to the drain of the N2 transistor. The gate of the N2 transistor is connected to the first storage node QB, and the source of the N2 transistor is grounded GND. The source of the N4 transistor is connected to the bit line BLB (second bit line), the gate is connected to the read word line signal RWL, and the drain is connected to the drain of the N3 transistor. The gate of the N3 transistor is connected to the second storage node Q, and the source of the N3 transistor is grounded GND.

[0047] The P1 transistor, the P2 transistor, and the N5-N7 transistors constitute the write operation circuit: the drain of the N5 transistor is connected to the bit line BL (first bit line), the gate of the N5 transistor is connected to the write word line signal WWL, the source of the N5 transistor is connected to the drain of the P1 transistor, the gate of the N6 transistor, and the gate of the P2 transistor to form the second storage node Q, the source of the P1 transistor is connected to the source of the P2 transistor and is connected to the power supply VDD, the gate of the P1 transistor is connected to the drain of the P2 transistor and the drain of the N6 transistor to form the first storage node QB, the source of the N6 transistor is grounded, the source of the N7 transistor is connected to the first storage node QB, the drain is connected to the second storage node Q, and the gate is connected to the refresh signal WRITE, wherein the N5 transistor serves as a transmission transistor of the write operation circuit, the first storage node QB and the second storage node Q constitute a pair of complementary storage nodes, and the N7 transistor serves as a refresh transistor of the write operation circuit.

[0048] Transistors P3, P4, and N8-N10 constitute the behavioral emulation circuit: the source of N8 is connected to the drain of N4, the gate of N8 is connected to the write emulation signal FAKE, the drain of N8 is connected to the drain of P3, the gate of N9, and the gate of P4 to form a first pseudo storage node FQ of the behavioral emulation circuit, the source of P3 is connected to the source of P4 and to a power supply, the gate of P3 is connected to the drain of P4 and the drain of N9 to form a second pseudo storage node FQB, the source of N9 is grounded GND, the source of N10 is connected to the second pseudo storage node FQB of the behavioral emulation circuit, the drain is connected to the first pseudo storage node FQ, and the gate is connected to the refresh signal WRITE. Transistor N8 serves as a transmission transistor of the behavioral emulation circuit, the first pseudo storage node FQ and the second pseudo storage node FQB form a pair of complementary pseudo storage nodes, and transistor N7 serves as a refresh transistor of the behavioral emulation circuit.

[0049] In this embodiment, in the entire lateral signal attack-resistant memory cell, the width-to-length ratio (defined as the ratio of the width to the length of the conductive channel of the MOS transistor) of the pass transistor of the write operation circuit and the pass transistor of the behavior mimicking circuit are equal, and both are greater than the width-to-length ratio of the other MOS transistors in the lateral signal attack-resistant memory cell, excluding the pass transistor of the write operation circuit and the pass transistor of the behavior mimicking circuit. In one exemplary embodiment, the ratio of the width-to-length ratio of the pass transistor of the write operation circuit and the pass transistor of the behavior mimicking circuit to the width-to-length ratio of the other MOS transistors in the lateral signal attack-resistant memory cell, excluding the pass transistor of the write operation circuit and the pass transistor of the behavior mimicking circuit, is between 2 and 3, for example, 2.5.

[0050] As an example, in the entire lateral signal attack resistant storage unit, all MOS tubes except the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit in the lateral signal attack resistant storage unit can be composed of the minimum size MOS tube (length 60nm, width 120nm) of the 55nm process, and the width-to-length ratio of the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit is adjusted to 300nm.

[0051] The purpose of this is to calibrate the leakage current to prevent the accumulation of charge caused by leakage current from causing data errors at the storage node. This is because the write operation circuit and the behavior simulation circuit are composed of five corresponding MOS transistors, of which P1 (P3), P2 (P4), and N6 (N9) are data storage structures. Since the storage node Q / FQ only has pull-up transistors P1 and P3, the ability of the Q / FQ node to retain data '1' is obviously unquestionable. When the data stored at Q is '0', there are two leakage currents flowing through Q, one is I P1 , one is I N5 Since the width-to-length ratio of the N5 tube has been readjusted and the leakage current has been calibrated, there is always I N5 >I P1 , so when the data stored at Q point is '0', no charge will accumulate. When the FQ point is at '0' potential, the N3 transistor is turned on, so the situation at FQ point is the same as above.

[0052] The working principle of the side signal attack resistance storage unit of this embodiment is as follows:

[0053] (1) Write operation cycle:

[0054] The written data is simultaneously loaded onto the complementary bit lines BL / BLB;

[0055] refresh;

[0056] Write: write "1", write "0".

[0057] like Figure 2 The figure shows two consecutive write cycles for a memory cell protected against side signal attacks. The first write cycle writes data "0," and the second write cycle writes data "1." At the beginning of the write cycle, the WRITE signal is briefly enabled, resetting the circuit state via the refresh transistor N7 (N10). It is important to note that after the refresh transistor is turned on, a new current path is generated within the memory cell, flowing through the refresh transistor. This path always forms negative feedback with the gate node of one of the two PMOS transistors within the memory cell, while simultaneously forming positive feedback with the gate node of the other PMOS transistor. This ensures that the storage node potential is not pulled to VDD during the refresh transistor conduction period, but is instead balanced to an intermediate potential. Since the two PMOS transistors are identical, this intermediate potential is closer to half of VDD, ensuring that only a small amount of energy is consumed to complete the refresh process. Furthermore, during each refresh process, one storage node is pulled down from VDD to the intermediate potential, while the complementary storage node is pulled up from GND to the intermediate potential. Therefore, the energy consumed during each refresh process is always equal, regardless of the data previously stored in the cell. After the refresh process is completed, due to the unique triangular structure of the write operation circuit (behavioral simulation circuit), there is a pull-down tube only on the QB (FQB) point side. After the refresh tube is turned off, the charge at the QB (FQB) point is always released to GND through the pull-down tube, and the Q (FQ) point is always pulled up to VDD.

[0058] The above is the principle of the refresh process, and after each refresh, the anti-side signal attack storage unit will always obtain the same storage state, that is, Q (FQ) = 1, that is, in each write operation cycle, before writing data, the refresh signal is enabled first to make the first storage node and the second pseudo storage node in the same storage state, and the second storage node and the first pseudo storage node in the same storage state.

[0059] On the basis of the above, the data to be written is simultaneously loaded onto the complementary bit lines BL / BLB (that is, in each write operation cycle, the written data is synchronously loaded onto the first bit line and the second bit line of the word line to ensure that the potential of the first bit line and the second bit line of the word line are the same), ensuring that the potential of the complementary bit lines is the same. At this time, WWL is turned on (that is, the WWL signal is enabled) to synchronize the data on the bit line BL to the Q point. When the written data is '0', the Q point data is flipped and the N3 transistor is turned off. When the WWL generates a falling edge, the FAKE signal is enabled to turn on the N8 transistor. Since both N4 and N3 transistors are turned off, the behavior simulation circuit imitates the complementary state of the write operation circuit, so the data at the FQ point does not change and remains at a high potential. Figure 2As shown in the first cycle of Figure 1. If the data written is '1', the data at Q remains unchanged, and transistor N3 is turned on. The FAKE signal is enabled at the falling edge of WL, turning on transistor N3. The behavioral mimicry circuit simulates the data flip behavior, generating power consumption identical to the data flip behavior of the write operation circuit. This ensures that the same power consumption is generated regardless of whether the data written to the cell causes a data flip at Q. This also means that the power consumption of the memory cell protected against side signal attacks is essentially the same regardless of whether a data flip occurs, eliminating the correlation between the written data and the write power consumption (see Table 1).

[0060] (2) Read operation cycle:

[0061] Similar to a 6T SRAM (static random access memory) read operation, the bit lines BL and BLB are simultaneously precharged to a high potential at the start of the read operation. If the value stored at Q is '1', N3 turns on and N2 turns off. At this point, the RWL signal is enabled, causing BLB to discharge to ground. BL remains high, and the data '1' is read. If the value stored at Q is '0', N2 turns on and N3 turns off. After RWL is enabled, BL discharges to ground, while BLB remains high, thus reading the data '0'. Regardless of the data being read, a bit line is always pulled down to ground through the same path. Therefore, during the read cycle, the read data has little correlation with the read power consumption.

[0062] (3) Data retention period:

[0063] As can be seen from the write operation of the lateral signal attack resistant memory cell of this embodiment, the behavior mimicking circuit mimics the complementary state of the write operation circuit, and the two have the same structure. Therefore, no matter what the stored data is, the potential state inside the lateral signal attack resistant memory cell is always the same. In addition, since the potentials of a pair of complementary bit lines BL and BLB of the lateral signal attack resistant memory cell are always the same, no matter what the stored data is or how the external bit line potential changes, the leakage current when storing different data is always the same, thereby eliminating the correlation between the leakage current and the stored data.

[0064] It can be seen from the above working principle that the side signal attack resistant storage unit of this embodiment logically has the ability to resist power consumption attacks in all working cycles.

[0065] In addition, in the side signal attack resistant storage unit of the present application, during the data retention period, the complementary bit lines BL / BLB can be pulled down to the ground, which greatly reduces the overall power consumption of the unit and solves the common high power consumption problem of the power consumption attack resistant unit to a certain extent.

[0066] To verify the power consumption of the lateral signal attack-resistant memory cell of this embodiment during data flipping and data retention, a comparison was conducted with a conventional 6T-SRAM. The comparison results are shown in Table 1. In this comparison, the conductive channels of the N5 and N8 transistors in the entire lateral signal attack-resistant memory cell are 300 nm wide and 60 nm long. The other MOS transistors are the minimum-sized MOS transistors of a 55 nm process, with a width of 120 nm and a length of 60 nm.

[0067] Table 1 Comparison of power consumption of the memory cell against side signal attack between the traditional 6T-SRAM and this embodiment

[0068] Traditional 6T-SRAM SISRAM of this embodiment Data flip state power consumption / fJ 2.60375 2.87478 Data retention state power consumption / fJ 5.14*10E-4 2.87392

[0069] As can be seen from the table, compared with the huge difference in power consumption between the data flipping and data retention states of the traditional SRAM when writing data, the power consumption difference between the two states of the SISRAM unit of this embodiment is very small.

[0070] Example 2

[0071] Figure 2 FIG. 1 shows another circuit structure diagram of a storage unit that resists side signal attacks. Figure 2 As shown, the lateral signal attack resistance storage unit includes 4 PMOS tubes and 14 NMOS tubes. The 4 PMOS tubes are defined as P1 tube to P4 tube, and the 12 NMOS tubes are defined as N1 tube to N12 tube.

[0072] Among them, the N1-N4 tubes constitute the read operation circuit: the N1-N4 tubes constitute the read operation circuit: the source of the N1 tube is connected to the bit line BL (first bit line), the gate is connected to the read word line signal RWL, and the drain is connected to the drain of the N2 tube, the gate of the N2 tube is connected to the first storage node QB, the source of the N2 tube is grounded GND, the source of the N4 tube is connected to the bit line BLB (second bit line), the gate is connected to the read word line signal RWL, and the drain is connected to the drain of the N3 tube, the gate of the N3 tube is connected to the second storage node Q, and the source of the N3 tube is grounded GND.

[0073] The P1 transistor, the N5 transistors, the N7 transistors, and the N11 transistor constitute the write operation circuit: the drain of the N5 transistor is connected to the bit line BL (first bit line), the gate of the N5 transistor is connected to the write word line signal WWL, the source of the N5 transistor is connected to the drain of the P1 transistor, the drain of the N6 transistor, and the gate of the N7 transistor to constitute the second storage node Q of the write operation circuit, the source of the N6 transistor is connected to the source of the N7 transistor and to the ground GND, the gate of the P1 transistor is connected to the drain of the N7 transistor to constitute the first storage node QB of the write operation circuit, the source of the P1 transistor is connected to the power supply VDD, the source of the N11 transistor is connected to the second storage node Q, the drain is connected to the first storage node QB, and the gate is connected to the refresh signal WRITE, wherein the N5 transistor serves as a transmission transistor of the write operation circuit, the first storage node Q and the second storage node QB constitute a pair of complementary storage nodes, and the N11 transistor serves as a refresh transistor of the write operation circuit.

[0074] Transistor P2, transistors N8-N10, and transistor N12 constitute the behavioral mimicry circuit: the source of transistor N8 is connected to the drain of transistor N4, and its gate is connected to the write mimicry signal FAKE. The drain of transistor N8 is connected to the drain of transistor P2, the drain of transistor N10, and the gate of transistor N9 to form a first pseudo storage node FQ of the behavioral mimicry circuit. The source of transistor N10 is connected to the source of transistor N9 and to ground GND. The gate of transistor P2 is connected to the drain of transistor N9 to form a second pseudo storage node FQB. The source of transistor P2 is connected to power supply VDD. The source of transistor N12 is connected to the second pseudo storage node FQB, its drain is connected to the first pseudo storage node FQ, and its gate is connected to the refresh signal WRITE. Transistor N8 serves as a transmission transistor of the behavioral mimicry circuit. The first pseudo storage node and the second pseudo storage node form a pair of complementary pseudo storage nodes. Transistor N12 serves as a refresh transistor of the write operation circuit.

[0075] In this embodiment, in the entire lateral signal attack-resistant memory cell, the width-to-length ratios of the pass transistors of the write operation circuit and the behavior mimicking circuit are equal, and both are greater than the width-to-length ratios of the other MOS transistors in the lateral signal attack-resistant memory cell, excluding the pass transistors of the write operation circuit and the behavior mimicking circuit. In one exemplary embodiment, the ratio of the width-to-length ratios of the pass transistors of the write operation circuit and the behavior mimicking circuit to the width-to-length ratios of the other MOS transistors in the lateral signal attack-resistant memory cell, excluding the pass transistors of the write operation circuit and the behavior mimicking circuit, is between 2 and 3, for example, 2.5.

[0076] The purpose of this is to calibrate the leakage current to prevent the charge accumulation caused by the leakage current from causing the storage node data to be incorrectly flipped.

[0077] The working principle of the lateral signal attack resistance storage unit of this embodiment is similar to that of the lateral signal attack resistance storage unit of the first embodiment, and will not be described in detail here.

[0078] In addition, in the side signal attack resistant storage unit of the present application, during the data retention period, the complementary bit lines BL / BLB can be pulled down to the ground, which greatly reduces the overall power consumption of the unit and solves the common high power consumption problem of the power consumption attack resistant unit to a certain extent.

[0079] Example 3

[0080] Figure 3 FIG. 4 shows a circuit structure diagram of a third type of memory cell that resists side signal attacks. Figure 3 As shown, the lateral signal attack resistance storage unit includes 4 PMOS tubes and 12 NMOS tubes. The 4 PMOS tubes are defined as P1 tube to P4 tube, and the 12 NMOS tubes are defined as N1 tube to N12 tube.

[0081] Among them, the N1-N4 transistors constitute the read operation circuit: the source of the N1 transistor is connected to the bit line BL (first bit line), the gate is connected to the read word line signal RWL, and the drain is connected to the drain of the N2 transistor. The gate of the N2 transistor is connected to the first storage node QB, and the source of the N2 transistor is grounded. The source of the N4 transistor is connected to the bit line BLB (second bit line), the gate is connected to the read word line signal RWL, and the drain is connected to the drain of the N3 transistor. The gate of the N3 transistor is connected to the second storage node Q, and the source of the N3 transistor is grounded.

[0082] The P1 transistor, the P2 transistor, the N5 transistor, the N7 transistor, the N8 transistor, and the N11 transistor constitute the write operation circuit: the drain of the N5 transistor is connected to the bit line BL (first bit line), and the gate is connected to the write word line signal WWL. The source of the N5 transistor is connected to the drain of the P1 transistor, the drain of the N7 transistor, the gate of the P2 transistor, and the gate of the N8 transistor to form the second storage node Q of the write operation circuit. The source of the P1 transistor is connected to the source of the P2 transistor and is also connected to the power supply VDD. The drain of the P2 transistor is connected to the drain of the N8 transistor and the gate of the P1 transistor. The gate of the N7 tube is connected to form the first storage node QB of the write operation circuit, the source of the N8 tube is connected to the source of the N7 tube and is connected to the ground GND, the source of the N11 tube is connected to the second storage node Q, the drain is connected to the first storage node QB, and the gate is connected to the refresh signal WRITE, wherein the N5 tube serves as a transmission tube of the write operation circuit, the first storage node QB and the second storage node Q form a pair of complementary storage nodes, and the N11 tube serves as a refresh tube of the write operation circuit.

[0083] The P3 transistor, the P4 transistor, the N6 transistor, the N9 transistor, the N10 transistor, and the N12 transistor constitute the behavior simulation circuit: the source of the N6 transistor is connected to the drain of the N4 transistor, and the gate is connected to the write simulation signal FAKE. The source of the N6 transistor is connected to the drain of the P3 transistor, the drain of the N9 transistor, the gate of the P4 transistor, and the gate of the N10 transistor to form the first pseudo storage node FQ of the behavior simulation circuit. The source of the P4 transistor is connected to the source of the P3 transistor and is also connected to the power supply. The drain of the P4 transistor is connected to the drain of the N10 transistor and the gate of the P3 transistor. The gate of the N9 tube is connected to form a second pseudo storage node FQB, the source of the N10 tube is connected to the source of the N9 and is connected to the ground GND, the source of the N12 tube is connected to the first pseudo storage node FQ, the drain is connected to the second pseudo storage node FQB, and the gate is connected to the refresh signal WRITE, wherein the N6 tube serves as a transmission tube of the behavioral simulation circuit, the first pseudo storage node and the second pseudo storage node form a pair of complementary pseudo storage nodes, and the N12 tube serves as a refresh tube of the write operation circuit.

[0084] In this embodiment, in the entire lateral signal attack-resistant memory cell, the width-to-length ratios of the pass transistors of the write operation circuit and the behavior mimicking circuit are equal, and both are greater than the width-to-length ratios of the other MOS transistors in the lateral signal attack-resistant memory cell, excluding the pass transistors of the write operation circuit and the behavior mimicking circuit. In one exemplary embodiment, the ratio of the width-to-length ratios of the pass transistors of the write operation circuit and the behavior mimicking circuit to the width-to-length ratios of the other MOS transistors in the lateral signal attack-resistant memory cell, excluding the pass transistors of the write operation circuit and the behavior mimicking circuit, is between 2 and 3, for example, 2.5.

[0085] The purpose of this is to calibrate the leakage current to prevent the charge accumulation caused by the leakage current from causing the storage node data to be incorrectly flipped.

[0086] The working principle of the lateral signal attack resistance storage unit of this embodiment is similar to that of the lateral signal attack resistance storage unit of the first embodiment, and will not be described in detail here.

[0087] In addition, in the side signal attack resistant storage unit of the present application, during the data retention period, the complementary bit lines BL / BLB can be pulled down to the ground, which greatly reduces the overall power consumption of the unit and solves the common high power consumption problem of the power consumption attack resistant unit to a certain extent.

[0088] In the description herein, many specific details are provided, such as examples of components and / or methods, to provide a complete understanding of the embodiments of the present application. However, those skilled in the art will recognize that embodiments of the present application can be practiced without one or more specific details or by other devices, systems, assemblies, methods, components, materials, parts, etc. In other cases, well-known structures, materials, or operations are not specifically shown or described in detail to avoid blurring the aspects of the embodiments of the present application.

[0089] It should also be understood that one or more of the elements shown in the figures may also be implemented in a more separate or more integrated manner, or even removed because they are inoperable in certain circumstances or provided because they may be useful depending on the application.

[0090] In addition, unless otherwise expressly indicated, any marking arrows in the drawings should be regarded as illustrative only and not limiting. Furthermore, unless otherwise indicated, the term "or" as used herein is generally intended to mean "and / or." Where a term is unclear in providing separation or combination capabilities, the combination of components or steps will also be considered as indicated.

[0091] The above description of the embodiments shown in the present application (including the content described in the abstract of the specification) is not intended to be an exhaustive list or to limit the present application to the precise form disclosed herein. Although the specific embodiments of the present application and the examples of the present application are described herein for illustrative purposes only, as those skilled in the art will recognize and understand, various equivalent modifications are possible within the spirit and scope of the present application. As noted, these modifications can be made to the present application according to the above description of the embodiments described in the present application, and these modifications will be within the spirit and scope of the present application.

[0092] This paper generally describes the system and method as details that help to understand the application. In addition, various specific details have been given to provide an overall understanding of the embodiments of the present application. However, those skilled in the relevant art will recognize that the embodiments of the present application can be put into practice without one or more specific details, or can be put into practice using other devices, systems, accessories, methods, components, materials, parts, etc. In other cases, known structures, materials and / or operations are not particularly shown or described in detail to avoid confusion in various aspects of the embodiments of the present application.

[0093] Thus, although the present application has been described herein with reference to specific embodiments thereof, freedom of modification, various changes and substitutions are also within the foregoing disclosure, and it should be understood that in some cases, some features of the present application will be adopted without the corresponding use of other features without departing from the scope and spirit of the claimed invention. Therefore, many modifications can be made to adapt a particular environment or material to the true scope and spirit of the present application. The present application is not intended to be limited to the specific terminology used in the claims below and / or the specific embodiments disclosed as the best mode contemplated for carrying out the present application, but the present application will include any and all embodiments and equivalents falling within the scope of the appended claims. Therefore, the scope of the present application will be determined solely by the appended claims.

Claims

1. A storage unit resistant to side signal attacks, characterized in that: include: A write operation circuit having a pair of complementary storage nodes; A behavior mimicking circuit having the same structure as the write operation circuit, wherein the behavior mimicking circuit has a pair of complementary pseudo storage nodes; a read operation circuit connected to the write operation circuit; The behavior simulation circuit is used to simulate the complementary state of the write operation circuit after the write operation circuit writes data, so as to ensure the consistency of power consumption of the anti-side signal attack storage unit when storing different data; The anti-side signal attack storage unit includes 4 PMOS tubes and 12 NMOS tubes, the 4 PMOS tubes are defined as P1 tube to P4 tube, and the 10 NMOS tubes are defined as N1 tube to N10 tube; wherein, Transistors N1 to N4 constitute the read operation circuit: the source of transistor N1 is connected to the first bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N2. The gate of transistor N2 is connected to the first storage node, and the source of transistor N2 is grounded. The source of transistor N4 is connected to the second bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N3. The gate of transistor N3 is connected to the second storage node, and the source of transistor N3 is grounded. The P1 transistor, the P2 transistor, and the N5-N7 transistors constitute the write operation circuit: the drain of the N5 transistor is connected to the first bit line, the gate of the N5 transistor is connected to the write word line signal, the source of the N5 transistor is connected to the drain of the P1 transistor, the gate of the N6 transistor, and the gate of the P2 transistor to form a first storage node, the source of the P1 transistor is connected to the source of the P2 transistor and to the power supply, the gate of the P1 transistor is connected to the drain of the P2 transistor and the drain of the N6 transistor to form a second storage node, the source of the N6 transistor is grounded, the source of the N7 transistor is connected to the first storage node, the drain is connected to the second storage node, and the gate is connected to the refresh signal, wherein the N5 transistor serves as a transmission transistor of the write operation circuit, and the first storage node and the second storage node form a pair of complementary storage nodes; Transistors P3, P4, and N8-N10 constitute the behavioral emulation circuit: the source of N8 is connected to the drain of N4, the gate of N8 is connected to a write emulation signal, the drain of N8 is connected to the drain of P3, the gate of N9, and the gate of P4 to form a first pseudo storage node of the behavioral emulation circuit, the source of P3 is connected to the source of P4 and to a power supply, the gate of P3 is connected to the drain of P4 and the drain of N9 to form a second pseudo storage node, the source of N9 is grounded, the source of N10 is connected to the second pseudo storage node of the behavioral emulation circuit, the drain is connected to the first pseudo storage node, and the gate is connected to a refresh signal. Transistor N8 serves as a transmission transistor of the behavioral emulation circuit, and the first pseudo storage node and the second pseudo storage node form a pair of complementary pseudo storage nodes.

2. A storage unit resistant to side signal attacks, characterized in that: include: A write operation circuit having a pair of complementary storage nodes; A behavior mimicking circuit having the same structure as the write operation circuit, wherein the behavior mimicking circuit has a pair of complementary pseudo storage nodes; a read operation circuit connected to the write operation circuit; The behavior simulation circuit is used to simulate the complementary state of the write operation circuit after the write operation circuit writes data, so as to ensure the consistency of power consumption of the anti-side signal attack storage unit when storing different data; The anti-side signal attack storage unit includes 2 PMOS tubes and 12 NMOS tubes, the 2 PMOS tubes are defined as P1 tube and P2 tube respectively, and the 12 NMOS tubes are defined as N1 tube to N12 tube respectively; wherein, Transistors N1 to N4 constitute the read operation circuit: the source of transistor N1 is connected to the first bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N2. The gate of transistor N2 is connected to the first storage node, and the source of transistor N2 is grounded. The source of transistor N4 is connected to the second bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N3. The gate of transistor N3 is connected to the second storage node, and the source of transistor N3 is grounded. The P1 transistor, the N5 transistors to the N7 transistors, and the N11 transistor constitute the write operation circuit: the drain of the N5 transistor is connected to the first bit line, the gate of the N5 transistor is connected to the write word line signal, the source of the N5 transistor is connected to the drain of the P1 transistor, the drain of the N6 transistor, and the gate of the N7 transistor to form the second storage node of the write operation circuit, the source of the N6 transistor is connected to the source of the N7 transistor and to the ground, the gate of the P1 transistor is connected to the drain of the N7 transistor to form the first storage node of the write operation circuit, the source of the P1 transistor is connected to the power supply, the source of the N11 transistor is connected to the second storage node, the drain is connected to the first storage node, and the gate is connected to the refresh signal, wherein the N5 transistor serves as a transmission transistor of the write operation circuit, and the first storage node and the second storage node form a pair of complementary storage nodes; Transistor P2, transistors N8-N10, and transistor N12 constitute the behavioral mimicry circuit: the source of transistor N8 is connected to the drain of transistor N4, and its gate is connected to a write mimicry signal. The drain of transistor N8 is connected to the drain of transistor P2, the drain of transistor N10, and the gate of transistor N9 to form a first pseudo storage node of the behavioral mimicry circuit. The source of transistor N10 is connected to the source of transistor N9 and to ground. The gate of transistor P2 is connected to the drain of transistor N9 to form a second pseudo storage node. The source of transistor P2 is connected to a power supply. The source of transistor N12 is connected to the second pseudo storage node, its drain is connected to the first pseudo storage node, and its gate is connected to a refresh signal. Transistor N8 serves as a transmission transistor of the behavioral mimicry circuit. The first pseudo storage node and the second pseudo storage node form a pair of complementary pseudo storage nodes.

3. A storage unit resistant to side signal attacks, characterized in that: include: A write operation circuit having a pair of complementary storage nodes; A behavior mimicking circuit having the same structure as the write operation circuit, wherein the behavior mimicking circuit has a pair of complementary pseudo storage nodes; a read operation circuit connected to the write operation circuit; The behavior simulation circuit is used to simulate the complementary state of the write operation circuit after the write operation circuit writes data, so as to ensure the consistency of power consumption of the anti-side signal attack storage unit when storing different data; The anti-side signal attack storage unit includes 4 PMOS tubes and 12 NMOS tubes, the 4 PMOS tubes are defined as P1 tube to P4 tube, and the 12 NMOS tubes are defined as N1 tube to N12 tube; wherein, Transistors N1 to N4 constitute the read operation circuit: the source of transistor N1 is connected to the first bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N2. The gate of transistor N2 is connected to the first storage node, and the source of transistor N2 is grounded. The source of transistor N4 is connected to the second bit line, the gate is connected to the read word line signal, and the drain is connected to the drain of transistor N3. The gate of transistor N3 is connected to the second storage node, and the source of transistor N3 is grounded. The P1 transistor, the P2 transistor, the N5 transistor, the N7 transistor, the N8 transistor, and the N11 transistor constitute the write operation circuit: the drain of the N5 transistor is connected to the first bit line, and the gate is connected to the write word line signal; the source of the N5 transistor is connected to the drain of the P1 transistor, the drain of the N7 transistor, the gate of the P2 transistor, and the gate of the N8 transistor to form the second storage node of the write operation circuit; the source of the P1 transistor is connected to the source of the P2 transistor and is connected to the power supply; the drain of the P2 transistor is connected to the drain of the N8 transistor, the gate of the P1 transistor, and the gate of the N7 transistor to form the first storage node of the write operation circuit; the source of the N8 transistor is connected to the source of the N7 transistor and is connected to ground; the source of the N11 transistor is connected to the second storage node, the drain is connected to the first storage node, and the gate is connected to the refresh signal; wherein the N5 transistor serves as a transmission transistor of the write operation circuit; the first storage node and the second storage node constitute a pair of complementary storage nodes; Transistor P3, transistor P4, transistor N6, transistor N9, transistor N10, and transistor N12 constitute the behavioral emulation circuit: the source of transistor N6 is connected to the drain of transistor N4, and its gate is connected to a write emulation signal; the source of transistor N6 is connected to the drain of transistor P3, the drain of transistor N9, the gate of transistor P4, and the gate of transistor N10 to form a first pseudo storage node of the behavioral emulation circuit; the source of transistor P4 is connected to the source of transistor P3 and to a power supply; the drain of transistor P4 is connected to the drain of transistor N10, the gate of transistor P3, and the gate of transistor N9 to form a second pseudo storage node; the source of transistor N10 is connected to the source of transistor N9 and to ground; the source of transistor N12 is connected to the first pseudo storage node, the drain to the second pseudo storage node, and the gate to a refresh signal. Transistor N6 serves as a transmission transistor of the behavioral emulation circuit; the first pseudo storage node and the second pseudo storage node form a pair of complementary pseudo storage nodes.

4. The storage unit for resisting side signal attack according to any one of claims 1 to 3, characterized in that: The width-to-length ratios of the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit are equal, and both are greater than the width-to-length ratios of other MOS tubes in the anti-side signal attack storage unit except the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit.

5. The storage unit for resisting side signal attack according to claim 4, characterized in that: The ratio of the width-to-length ratio of the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit to the width-to-length ratio of other MOS tubes in the anti-side signal attack storage unit except the transmission tube of the write operation circuit and the transmission tube of the behavior simulation circuit is between 2 and 3.

6. The storage unit for resisting side signal attack according to any one of claims 1 to 3, characterized in that: During the data hold period, the first bit line and the second bit line of the word line are pulled to ground.

7. The storage unit for resisting side signal attack according to any one of claims 1 to 3, characterized in that: In each write operation cycle, the written data is synchronously loaded into the first bit line and the word line and the second bit line to ensure that the potentials of the first bit line and the word line and the second bit line are the same.

8. The storage unit for resisting side signal attack according to claim 7, characterized in that: In each write operation cycle, before writing data, a refresh signal is enabled to make the first storage node and the second dummy storage node in the same storage state, and the second storage node and the first dummy storage node in the same storage state.

9. The storage unit for resisting side signal attack according to any one of claims 1 to 3, characterized in that: During a write operation cycle, the write mimic signal is enabled at the falling edge of the write word line signal.

Images