Sensing circuit and test device

Abstract

A sensing circuit generates a sensing result based on a read voltage from a non-transitory memory. The sensing circuit includes four transistors and a switching group. A first transistor is coupled between an operating voltage and a first node. A second transistor is coupled between the first node and a second node. A third transistor is coupled between the second node and a reference ground voltage. The control terminals of the first, second, and third transistors all receive the read voltage. A fourth transistor is coupled between the operating voltage and the first node. The switching group forms or disconnects a conduction path between the control terminal of the fourth transistor and the second node based on a control signal, and the sensing result is obtained from the first node.

Description

Technical Field

[0001] The present invention relates to a sensing circuit for a memory, characterized by a sensing circuit operable in multiple test modes. Background Technology

[0002] In recent years, microcontrollers (MCUs) have been widely used in portable electronic products and white goods. Non-volatile memory (NVM), especially one-time programmable (OTP) memory and multi-time programmable (MTP) memory, are key components of microcontrollers. OTP and MTP memories are used to store the program code of related applications, enabling microcontrollers to be used in a variety of electronic products.

[0003] However, OTP and MTP memories can develop defects due to process variations. Among these, the most serious defect is transistor leakage in both OTP and MTP memories, particularly the drain-to-source leakage current in N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). Due to the leakage path in the transistor, OTP memories (or MTP memories) may experience increased quiescent current and read bit errors, leading to abnormally high power consumption and potentially causing microcontroller malfunction. Generally, OTP memories (or MTP memories) with low-impedance leakage paths can be detected during chip probing (CP) testing to prevent defective products from entering the packaging stage and increasing manufacturing costs. However, leakage paths with high impedance are difficult to detect.

[0004] Figure 1 The diagram illustrates the basic circuit structure of an OTP (or MTP) memory. Please see... Figure 1The OTP memory (or MTP memory) 100 may include a current source 101, a load 102, and a transistor Mc. A sense amplifier 103 may receive the read voltage Vsen from the OTP memory (or MTP memory) 100 to generate a sensing result. Ideally, when the transistor Mc is programmed with a write voltage equivalent to a bit value "0" during the CP detection phase, the transistor Mc is turned off and the read voltage Vsen is at a high voltage level (close to the operating voltage). At this time, a sensing result equivalent to a bit value "0" can be obtained via the sense amplifier 103. However, when the transistor Mc is programmed with a write voltage equivalent to a bit value "0" and the transistor Mc has a leakage current path with low impedance characteristics (see...),... Figure 1 When the reading voltage Vsen is at a relatively low level (between ground potential and half operating voltage), the sensing amplifier 103 obtains a sensing result equivalent to a bit value "1". Through the above detection method, OTP memory (or MTP memory) 100 with leakage current paths having low impedance characteristics can be screened out.

[0005] However, when transistor Mc is programmed with a write voltage equivalent to a bit value "0" and transistor Mc has a leakage current path with high impedance characteristics (see...) Figure 1 When the reading voltage Vsen is at a relatively high level (greater than half the operating voltage), as shown by the dashed line, the sensing amplifier 103 obtains the same sensing result as the ideal state, which is equivalent to a bit value of "0". In other words, the above detection method cannot detect the OTP memory (or MTP memory) 100 with a leakage current path exhibiting high impedance characteristics, thus mistakenly passing the CP test stage. Furthermore, in actual application of the backend product, the leakage current path of the OTP memory (or MTP memory) 100 may switch from a high sensing voltage characteristic to a low sensing voltage characteristic under low system voltage operation, causing general failure of the OTP memory (or MTP memory) 100. This situation will reduce product reliability and create customer complaint risks.

[0006] Therefore, this invention proposes a solution to enable the detection of OTP (or MTP) memory with leakage current paths having high impedance characteristics during the CP testing phase. Summary of the Invention

[0007] The present invention provides a sensing circuit and a test apparatus including the aforementioned sensing circuit, which enables non-transitory memories with leakage current paths having high impedance characteristics to be detected during the CP test phase.

[0008] The sensing circuit of the present invention generates a sensing result based on a read voltage of a non-transitory memory. The sensing circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a switching group. The first transistor is coupled between an operating voltage and a first node. The second transistor is coupled between the first node and a second node. The third transistor is coupled between the second node and a reference ground voltage. The control terminals of the first transistor, the second transistor, and the third transistor all receive the read voltage. The fourth transistor is coupled between the operating voltage and the first node. The switching group forms or disconnects a conduction path between the control terminal of the fourth transistor and the second node according to a control signal, so that the sensing result can be obtained from the first node.

[0009] The testing apparatus of the present invention generates test results based on the read voltage of a non-transitory memory. The testing apparatus includes a non-transitory memory, the aforementioned sensing circuit, and a test controller, wherein the non-transitory memory is programmed with a voltage value corresponding to a bit value. The test controller generates a control signal to cause a switch group to disconnect the conduction path according to the control signal to enter a first test mode, and when the sensing result obtained from executing the first test mode is the aforementioned bit value, causes the switch group to connect the conduction path according to the control signal to enter a second test mode. The test controller is also used to generate a test result indicating the presence of a high-impedance leakage current path in the non-transitory memory when the sensing result obtained from executing the second sensing mode is not the aforementioned bit value.

[0010] The testing apparatus of the present invention generates test results based on the read voltage of a non-transitory memory. The testing apparatus includes a non-transitory memory, the aforementioned sensing circuit, and a test controller, wherein the non-transitory memory is erased with a voltage value corresponding to a bit value. The test controller generates a control signal to cause a switch group to disconnect the conduction path according to the control signal to enter a first test mode, and when the sensing result obtained from executing the first test mode is not the aforementioned bit value, causes the switch group to reconnect the conduction path according to the control signal to enter a second test mode. The testing apparatus also generates a test result indicating that the sensing result has been corrected for read bit value errors caused by a high-impedance read path in the non-transitory memory when the sensing result obtained from executing the second sensing mode is the aforementioned bit value. In the application terminal product stage, the sensing circuit is switched to the second test mode to sense and correct the result, thereby improving yield.

[0011] The sensing circuit of the present invention generates a sensing result based on a read voltage of a non-transitory memory. The sensing circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a switching group. The first transistor is coupled between a first node and a second node, wherein the control terminal of the first transistor receives the read voltage. The second transistor is coupled between the second node and a reference ground voltage. The third transistor is coupled between an operating voltage and the first node, wherein the control terminal of the third transistor is coupled to the control terminal of the second transistor and receives the read voltage. The fourth transistor is coupled between the second node and the reference ground voltage. The switching group forms or disconnects a conduction path between the first node and the control terminal of the fourth transistor according to a control signal, so that the sensing result is acquired by the second node.

[0012] The testing apparatus of the present invention generates test results based on the read voltage of a non-transitory memory. The testing apparatus includes a non-transitory memory, the aforementioned sensing circuit, and a test controller, wherein the non-transitory memory is erased with a voltage value corresponding to a bit value. The test controller generates a control signal to cause a switch group to disconnect the conduction path according to the control signal to enter a first test mode, and when the sensing result obtained by executing the first test mode is the aforementioned bit value, causes the switch group to connect the conduction path according to the control signal to enter a second test mode. The test controller also generates a test result indicating the presence of a high-impedance leakage current path in the non-transitory memory when the sensing result obtained by executing the second sensing mode is not the aforementioned bit value.

[0013] The testing apparatus of the present invention generates test results based on the read voltage of a non-transitory memory. The testing apparatus includes a non-transitory memory, the aforementioned sensing circuit, and a test controller, wherein the non-transitory memory is programmed with a voltage value corresponding to a bit value. The test controller generates a control signal to cause a switch group to disconnect the conduction path according to the control signal to enter a first test mode, and when the sensing result obtained from executing the first test mode is not the aforementioned bit value, causes the switch group to connect the conduction path according to the control signal to enter a second test mode. The test controller also generates a test result indicating that the sensing result has been corrected for read bit value errors caused by a high-impedance read path in the non-transitory memory when the sensing result obtained from executing the second sensing mode is the aforementioned bit value. In the application end product stage, the sensing circuit is switched to the second test mode to sense and correct the result, thereby improving yield.

[0014] Based on the above, this invention enables the execution of a first test mode and a second test mode by controlling the operation of a switch within the sensing circuit. By sequentially executing the first and second test modes, this invention can detect the presence of a leakage current path with high impedance characteristics in non-transitory memory. This avoids the problem of non-transitory memory with high impedance leakage current paths passing the detection but subsequently experiencing general failures. Therefore, product reliability is improved. Furthermore, to address misjudgments caused by high-impedance read paths, the sensing circuit can switch to the second test mode and maintain this mode in the end product, thereby correcting the sensing results and improving yield. Attached Figure Description

[0015] Figure 1 The diagram shows the basic circuit structure of an OTP memory (or MTP memory).

[0016] Figure 2A and Figure 2B The diagram illustrates the circuit structure of the sensing circuit according to the first embodiment of the present invention.

[0017] Figure 3 The diagram is a block diagram illustrating the test circuit of the present invention.

[0018] Figure 4 The diagram illustrates the steps of detecting the presence of a leakage current path with high impedance characteristics in the first embodiment of the present invention.

[0019] Figure 5 The diagram shows the basic circuit structure of an OTP memory (or MTP memory).

[0020] Figure 6 The diagram illustrates the steps of detecting the existence of a read path with high impedance characteristics in the first embodiment of the present invention.

[0021] Figure 7 The diagram shows a block diagram of the test circuit according to a second embodiment of the present invention.

[0022] Figure 8 The diagram illustrates the steps for detecting the presence of a leakage current path with high impedance characteristics under the second embodiment of the present invention.

[0023] Figure 9 The diagram illustrates the steps of detecting the existence of a read path with high impedance characteristics under the second embodiment of the present invention. Detailed Implementation

[0024] Figure 2A and Figure 2B The diagram illustrates the circuit structure of the sensing circuit according to the first embodiment of the present invention. Figure 2AThe circuit structure of the sensor circuit shown is the same as Figure 2B The circuit structures of the sensing circuits shown are exactly the same; the only difference lies in the operating mode of the switch groups (switch SW1 and switch SW2). Please also refer to... Figure 2A and Figure 2B The OTP memory (or MTP memory) 100 may include a transistor Ms, a load 102, a transistor Msel, and a transistor Mc. The transistor Ms acts as a current source, equivalent to... Figure 1 The current source 101. The functions of the load 102 and the transistor Mc can be referred to. Figure 1 The descriptions of the components with the same name in the code will not be repeated here. When transistor Msel is turned on, OTP memory (or MTP memory) 100 can be written to and read from; therefore, transistor Msel is also called a selection transistor. In this embodiment, transistor Ms can be a P-type metal-oxide-semiconductor field-effect transistor, and transistors Msel and Mc can be N-type metal-oxide-semiconductor field-effect transistors.

[0025] Sensing circuit 200 generates sensing result Dout based on the read voltage Vsen of OTP memory (or MTP memory) 100. Sensing circuit 200 includes transistors M1-M4, switch SW1, switch SW2, and buffer B. The first terminal of transistor M1 receives the operating voltage VDD. The second terminal of transistor M1 is coupled to node N1. The control terminal of transistor M1 receives the read voltage Vsen (i.e., the operation of transistor M1 is controlled by the read voltage Vsen). The first terminal of transistor M2 is coupled to node N1. The second terminal of transistor M2 is coupled to node N2. The control terminal of transistor M2 receives the read voltage Vsen (i.e., the operation of transistor M2 is controlled by the read voltage Vsen). In this embodiment, transistors M1 and M2 form an inverter. The first terminal of transistor M3 is coupled to node N2. The second terminal of transistor M3 is coupled to a reference ground voltage. The control terminal of transistor M3 receives the read voltage Vsen (i.e., the operation of transistor M3 is controlled by the read voltage Vsen). The first terminal of transistor M4 is coupled to the operating voltage VDD. The second terminal of transistor M4 is coupled to node N1. The control terminal of transistor M4 is coupled to the first terminal of switch SW1. In this embodiment, transistors M1 and M4 can be P-type metal-oxide-semiconductor field-effect transistors, and transistors M2 and M3 can be N-type metal-oxide-semiconductor field-effect transistors.

[0026] The first terminal of switch SW1 is coupled to the control terminal of transistor M4. The second terminal of switch SW1 is selectively coupled to either the operating voltage VDD or node N3, depending on the control signal. The first terminal of switch SW2 is coupled to node N2. The second terminal of switch SW2 is selectively coupled to either the reference ground voltage or node N3, depending on the control signal. Switches SW1 and SW2 are controlled by the control signal to operate synchronously, thereby forming a switch group. This switch group forms or disconnects the conduction path between the control terminal of transistor M4 and node N2 according to the control signal. For example, when the control signal is at a first voltage level (e.g., a high voltage level), switches SW1 and SW2 operate synchronously to form the aforementioned conduction path. When the control signal is at a second voltage level (e.g., a low voltage level), switches SW1 and SW2 operate synchronously to disconnect the aforementioned conduction path. The input terminal of buffer B is coupled to node N1 to receive the voltage signal of node N1. The function of buffer B is to digitize the analog voltage signal of node N1 to output the digital sensing result Dout. In one embodiment, buffer B can be implemented by connecting two inverters in series.

[0027] Please see Figure 2A When the switching group of sensing circuit 200 disconnects the conduction path between the control terminal of transistor M4 and node N2 according to the control signal, transistors M3 and M4 are inactive. Specifically, since transistor M2 is directly grounded via switch SW2, transistor M3 is bypassed, effectively inactive. Furthermore, since the control terminal of transistor M4 is connected to the operating voltage VDD via switch SW1, transistor M4 is not turned on, also effectively inactive. With neither transistors M3 nor M4 active, sensing circuit 200 effectively obtains the sensing result Dout through an inverter (only transistors M1 and M2 are active) and buffer B.

[0028] Please see Figure 2BWhen the switching group of the sensing circuit 200 forms a conduction path between the control terminal of transistor M4 and node N2 according to the control signal, transistors M1 to M4 all function. Transistors M1 and M2 still function as inverters. Transistors M2 and M3 are connected in series, and transistors M1 and M4 are connected in parallel. When the read voltage Vsen is at a relatively high voltage, the presence of transistor M3 can increase the threshold voltage of transistor M2. At this time, transistor M3 may be fully turned on, while transistor M2 is partially turned on. In this way, the conduction path of transistor M2 to ground will not be fully open, and the voltage of node N1 will be maintained at a voltage level equivalent to the operating voltage VDD. In other words, the role of transistor M3 is to improve the tolerance (tolerance) of the sensing circuit 200 to the high read voltage Vsen, and it can act as the first line of defense to maintain the voltage level of N1 at a high voltage level.

[0029] When the read voltage Vsen is very high, both transistors M2 and M3 may be fully turned on. At this time, nodes N2 and N3 are at or near the reference ground voltage, causing transistor M4 to turn on. The operating voltage VDD flows through transistor M4 to compensate for current at node N1, pulling up the voltage level of node N1 and maintaining it at a level equivalent to the operating voltage VDD. Therefore, transistor M4 acts as a second line of defense to maintain the voltage level of N1 at a high level. In short, under high read voltage Vsen conditions, transistors M3 and M4 can compensate for voltage drops at node N1 to a high voltage level.

[0030] Figure 3 The diagram is a block diagram illustrating the test circuit of the present invention. Figure 3 The test circuit shown can be applied, for example, during the CP phase, to detect whether transistors in non-transitory memory have leakage current paths with low impedance or high impedance characteristics. Please also refer to... Figure 2A , Figure 2B and Figure 3 The test circuit includes a non-temporary memory 100' to be tested, a sensing circuit 200, and a test controller 300. The non-temporary memory 100' can be as follows: Figure 1 and Figures 2A-2B The OTP memory (or MTP memory) 100 is shown. The architecture of the sensing circuit 200 can be referenced. Figures 2A-2BThe description of the sensing circuit 200 shown will not be repeated here. The test controller 300 is used to generate a control signal S. The sensing circuit 200 forms or disconnects the conduction path between the control terminal of transistor M4 and node N2 according to the control signal S. The test controller 300 is, for example, a microprocessor, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices.

[0031] Figure 3 The test apparatus shown can operate in either a first test mode or a second test mode. The first test mode is also known as the normal test mode, and the second test mode is also known as the high-impedance path test mode. When the test apparatus operates in the first test mode, the test controller 300 disconnects the conduction path between the control terminal of transistor M4 and node N2 in the sensing circuit 200 via the control signal S. Transistors M3 and M4 are inactive due to the disconnection of the aforementioned conduction path. At this time, the sensing circuit 200 effectively obtains the sensing result Dout through an inverter (composed of transistors M1 and M2) and a buffer B.

[0032] In the first test mode, when the non-transitory memory 100' is programmed with a write voltage equivalent to bit value "0", if a sensing result Dout equivalent to bit value "0" is obtained, it indicates that the non-transitory memory 100' does not have a leakage current path with low impedance characteristics. However, if a sensing result Dout equivalent to bit value "1" is obtained, it indicates that the non-transitory memory 100' has a leakage current path with low impedance characteristics. In the second test mode, when the non-transitory memory 100' is programmed with a write voltage equivalent to bit value "0", if a sensing result Dout equivalent to bit value "0" is obtained, it indicates that the non-transitory memory 100' does not have a leakage current path with high impedance characteristics. However, if a sensing result Dout equivalent to bit value "1" is obtained, it indicates that the non-transitory memory 100' has a leakage current path with high impedance characteristics.

[0033] Figure 4 The diagram illustrates the steps for detecting the presence of a leakage current path with high impedance characteristics according to the first embodiment of the present invention. Please also refer to... Figure 2A , Figure 2B , Figure 3 and Figure 4 The process begins at step S410. In step S420, all memory cells of the non-transitory memory 100' are programmed with a voltage value equivalent to a bit value "0", and execution is performed for each memory cell. Figure 4 The remaining steps. In step S430, the test device is operated in the first test mode (transistors M3 and M4 are not active due to the open conduction path), and step S440 is executed. In step S440, it is confirmed whether the sensing result Dout is a bit value "0". If not (the sensing result Dout is a bit value "1"), it indicates that the non-transitory memory 100' has failed to program due to the presence of a leakage current path with low impedance characteristics (step S450). If yes (the sensing result Dout is a bit value "0"), it indicates that the non-transitory memory 100' does not have a leakage current path with low impedance characteristics, but the possibility that the non-transitory memory 100' has incorrectly obtained the same sensing result as the ideal state (the sensing result Dout is a bit value "0") due to the presence of a leakage current path with high impedance characteristics cannot be ruled out. Therefore, step S460 needs to be executed.

[0034] In step S460, the test device is switched to the second test mode (transistors M3 and M4 function due to the conduction path), and step S470 is executed. In step S470, it is confirmed whether the sensing result Dout is a bit value "0". If the sensing result Dout obtained in the second test mode is still a bit value "0", it indicates that the non-transitory memory 100' has been successfully programmed (step S480). If the sensing result Dout obtained in the second test mode is a bit value "1", it indicates that the non-transitory memory 100' has a leakage current path with high impedance characteristics (step S490). By executing the first test mode, it can be confirmed whether the non-transitory memory 100' has a leakage current path with low impedance characteristics. By executing the second test mode, it can be further confirmed whether the non-transitory memory 100' has a leakage current path with high impedance characteristics. In this way, defective products with leakage current paths with high impedance characteristics can be prevented from passing the CP test. This avoids the possibility that the non-transitory memory 100' may experience general failure (read error) in subsequent product applications due to leakage current paths potentially changing from high sensing voltage characteristics to low sensing voltage characteristics under low system voltage operation.

[0035] Furthermore, even without leakage current paths exhibiting high / low impedance characteristics, read errors can still occur if the non-transitory memory 100' has a read path with high impedance characteristics (e.g., high impedance signal noise caused by process variations such as narrow line width). During the CP detection stage, the non-transitory memory 100' with a read path exhibiting high impedance characteristics will be detected as a defective product due to read errors. However, this read error is caused by the high impedance read path, not by a problem with the non-transitory memory 100' itself. In reality, the non-transitory memory 100' is usable. Therefore, this situation will result in additional product yield losses.

[0036] Figure 5 The diagram shows the basic circuit structure of an OTP memory (or MTP memory). Figure 5 The circuit structure shown is similar to Figure 1 The circuit structures shown are basically the same, with the only difference being... Figure 5 The OTP memory (or MTP memory) 100 shown has a high-impedance read path, rather than a high / low impedance leakage current path.

[0037] Please see Figure 5 When transistor Mc is erased by a write voltage equivalent to a bit value "1" (transistor Mc is turned on, pulling the read voltage Vsen low), the OTP memory (or MTP memory) 100 should ideally obtain a sensed bit value "1". However, due to the existence of a high-impedance read path (see...), Figure 5 When the reading voltage Vsen is at a relatively high level (greater than half the operating voltage), as shown by the dashed line, the sensing amplifier 103 will incorrectly obtain a sensing result of bit value "0", resulting in a reading error.

[0038] In this invention, it can also be achieved by... Figure 2A and Figure 2B The sensing circuit 200 shown is used to further detect whether there is a read path with high impedance characteristics in the non-transitory memory. Furthermore, during the application end-product stage, the sensing circuit can be switched to a second test mode to correct the results, thereby improving yield. Figure 6 The diagram illustrates the steps of detecting the presence of a readout path with high impedance characteristics according to the first embodiment of the present invention. Please also refer to... Figure 2A , Figure 2B , Figure 3 and Figure 6 The process begins at step S610. In step S620, all memory cells of the non-transitory memory 100' are erased, making their storage state equivalent to the bit value "1", and the following steps are performed on each memory cell: Figure 6 The remaining steps are as follows. In step S630, the test device is operated in the first test mode (transistors M3 and M4 are not active due to the disconnection of the conduction path), and step S640 is executed. In step S640, it is confirmed whether the sensing result Dout is a bit value "1". If yes, it indicates that the erasure was successful (step S650). If no (the sensing result Dout is a bit value "0"), it indicates that there is a possibility of a read error due to the existence of a read path with high impedance characteristics, so step S660 needs to be executed further. In step S660, the test device is operated in the second test mode (transistors M3 and M4 are active due to the formation of the conduction path) to confirm whether the non-temporary memory 100' failed to read due to the existence of a read path with high impedance characteristics or because of a structural problem of the non-temporary memory 100' itself. In step S670, it is confirmed whether the sensing result Dout is a bit value "1". If yes (the sensing result Dout has been corrected / compensated), it indicates that the erasure was successful (step S650). If not (the sensing result Dout is a bit value "0"), then the erasure failed (step S680).

[0039] In this way, even if the non-temporary memory 100' has a high-impedance read path, it can still be accessed through methods such as... Figure 2A and Figure 2B The architecture shown modifies / compensates the sensing result Dout to prevent the non-transitory memory 100' from failing the CP detection stage and being treated as a defective product. Furthermore, by applying the second test mode and maintaining this mode in the end product, the product yield can be improved.

[0040] Table (a) records the sensing results of the non-temporary memory 100' in various states in the first sensing mode and the second sensing mode.

[0041] Table (1)

[0042]

[0043] Please also see Figure 2A , Figure 2BAccording to Table (I), in the erase state, the non-transitory memory 100' is written with a bit value "1" and transistor Mc is turned on. At this time, the sensing result Dout obtained via the first test mode is a bit value "1". Furthermore, in the second test mode, since transistor M1 is turned on and transistors M2 and M3 are both turned off, the obtained sensing result Dout will also be a bit value "1" (corresponding to a voltage value of 3.3V). In the case of a path with high impedance characteristics (whether a leakage current path or a read path), the sensing result Dout obtained via the first test mode will instead be a bit value "0". Furthermore, in the second test mode, since transistor M1 is turned off, transistor M2 is partially turned on (or fully turned on), and transistors M3 and M4 are both turned on, the obtained sensing result Dout will be a bit value "1" (corresponding to a voltage value of 3.3V). In the programming state, the non-transitory memory 100' is written with a bit value "0" and transistor Mc is turned off. At this time, the sensing result Dout obtained via the first test mode is a bit value "0". Furthermore, in the second test mode, since transistor M1 is off and both transistors M2 and M3 are on, the resulting sensing value Dout will also be a bit value "0" (corresponding to a voltage value of 0V). When the programming margin is insufficient, the non-transitory memory 100' is written with a bit value "0" but transistor Mc is not turned off. In this case, the sensing result Dout obtained via the first test mode will be a bit value "1". Additionally, in the second test mode, since transistor M1 is on and both transistors M2 and M3 are off, the resulting sensing result Dout will also be a bit value "1" (corresponding to a voltage value of 3.3V).

[0044] Therefore, except in cases where a path with high impedance characteristics exists (whether it's a leakage current path or a read path), the sensing result Dout obtained through the first test mode and the second test mode will be the same in all other states. Thus, the presence of a path with high impedance characteristics (whether it's a leakage current path or a read path) in the non-transitory memory 100' can be confirmed by sequentially executing the first test mode and the second test mode.

[0045] Figure 2A and Figure 2B The sensing circuit 200 shown is designed for a non-transitory memory where the transistor Mc is an N-type metal-oxide-semiconductor field-effect transistor. Under the same concept, this invention also designs another sensing circuit for a case where the transistor Mc is a P-type metal-oxide-semiconductor field-effect transistor.

[0046] Figure 7 The diagram shows a block diagram of the test circuit according to a second embodiment of the present invention. Figure 7The sensing circuit 200' shown is designed for the case where the transistor Mc is a P-type metal-oxide-semiconductor field-effect transistor. Please see... Figure 7 The sensing circuit 200' generates a sensing result Dout based on the read voltage Vsen of the non-transitory memory. The sensing circuit 200' includes transistors M5-M8, switches SW3 and SW4, and a buffer B. The first terminal of transistor M5 is coupled to node N4. The second terminal of transistor M5 is coupled to node N5. The control terminal of transistor M5 receives the read voltage Vsen (i.e., the operation of transistor M5 is controlled by the read voltage Vsen). The first terminal of transistor M6 is coupled to the second terminal of transistor M5 (i.e., node N5). The second terminal of transistor M6 is coupled to a reference ground voltage. The first terminal of transistor M7 receives the operating voltage VDD. The second terminal of transistor M7 is coupled to node N4. Furthermore, the control terminals of transistors M7, M6, and M5 are coupled together. Transistors M5 and M6 form an inverter. The first terminal of transistor M8 is coupled to node N5. The second terminal of transistor M8 is coupled to a reference ground voltage. Furthermore, the control terminal of transistor M8 is coupled to node N4 through a conduction path. In this embodiment, transistors M5 and M7 can be P-type metal-oxide-semiconductor field-effect transistors, and transistors M6 and M8 can be N-type metal-oxide-semiconductor field-effect transistors.

[0047] The first terminal of switch SW3 is coupled to node N4. The second terminal of switch SW3 is selectively coupled to either the operating voltage VDD or node N6, depending on a control signal. The first terminal of switch SW4 is coupled to the control terminal of transistor M8. The second terminal of switch SW4 is selectively coupled to either the reference ground voltage or node N6, depending on a control signal. Switches SW3 and SW4 are controlled by a control signal to operate synchronously, thereby forming a switch group. This switch group forms or disconnects a conduction path between the control terminal of transistor M8 and node N4 according to the control signal. For example, when the control signal is at a first voltage level (e.g., a high voltage level), switches SW3 and SW4 operate synchronously to form the aforementioned conduction path. When the control signal is at a second voltage level (e.g., a low voltage level), switches SW3 and SW4 operate synchronously to disconnect the aforementioned conduction path. The input terminal of buffer B is coupled to node N5 to receive the voltage signal of node N5. The function of buffer B is to digitize the analog voltage signal of node N5 to output a digital sensing result Dout. In one embodiment, buffer B can be implemented by connecting two inverters in series.

[0048] because Figure 7 The sensor circuit 200' shown can be considered as Figure 2A and Figure 2B The complementary circuit architecture of the sensing circuit 200 shown is omitted here. Figure 7 A detailed explanation of the circuit operation. In short, in the case of non-transitory memory with a high-impedance leakage current path / read path, Figure 2A and Figure 2B The function of the sensing circuit 200 shown is to maintain a high voltage level at node N1 through transistors M3 and M4 and the negative feedback path between them. Conversely, Figure 2A and Figure 2B The function of the sensing circuit 200 shown is to maintain the voltage of node N5 at a low voltage level through transistors M7 and M8 and the negative feedback path between them.

[0049] Figure 7 The sensor circuit 200' shown can be applied to Figure 3 The test circuit is shown. In other words, Figure 3 The architecture of the sensing circuit 200 can be as follows Figure 7 The sensing circuit 200' is shown. Similarly, when Figure 3 When the test circuit shown operates in the first test mode, the test controller 300 generates a control signal S to control the sensing circuit 200' to disconnect the conduction path between the control terminal of transistor M8 and node N4. When... Figure 3 When the test circuit shown operates in the second test mode, the test controller 300 generates a control signal S to control the sensing circuit 200' to form a conduction path between the control terminal of transistor M8 and node N4.

[0050] Figure 8 The diagram illustrates the steps for detecting the presence of a leakage current path with high impedance characteristics according to the second embodiment of the present invention. Please also refer to Figure [Figure Number]. Figure 3 , Figure 7 and Figure 8 The process begins at step S810. In step S820, all memory cells of the non-temporary memory 100' are erased to a bit value of "1", and each memory cell is processed... Figure 8The remaining steps. In step S830, the test device is operated in the first test mode (transistors M7 and M8 are not active due to the open conduction path), and step S840 is executed. In step S840, it is confirmed whether the sensing result Dout is a bit value "1". If not (the sensing result Dout is a bit value "0"), it indicates that the non-transitory memory 100' has failed to erase (step S850). If yes (the sensing result Dout is a bit value "1"), it indicates that the non-transitory memory 100' does not have a leakage current path with low impedance characteristics, but the possibility that the non-transitory memory 100' has incorrectly obtained the same sensing result as the ideal state (the sensing result Dout is a bit value "1") because of the existence of a leakage current path with high impedance characteristics cannot be ruled out. Therefore, step S860 needs to be executed.

[0051] In step S860, the test device is switched to the second test mode (transistors M7 and M8 function due to the conduction path), and step S870 is executed. In step S870, it is confirmed whether the sensing result Dout is a bit value "1". If the sensing result Dout obtained in the second test mode is still a bit value "1", it indicates that the non-transitory memory 100' has been successfully erased (step S880). If the sensing result Dout obtained in the second test mode is a bit value "0", it indicates that the non-transitory memory 100' has a leakage current path with high impedance characteristics (step S890). By executing the first test mode, it can be confirmed whether the non-transitory memory 100' has a leakage current path with low impedance characteristics. By executing the second test mode, it can be further confirmed whether the non-transitory memory 100' has a leakage current path with high impedance characteristics. In this way, defective products with leakage current paths with high impedance characteristics can be prevented from passing the CP test. This avoids the possibility that the non-transitory memory 100' may experience general failure (read error) in subsequent product applications due to leakage current paths potentially changing from high sensing voltage characteristics to low sensing voltage characteristics under low system voltage operation.

[0052] Furthermore, during the CP detection phase, non-transitory memory 100' with a read path exhibiting high impedance characteristics will be detected as a defective product due to read errors. To avoid this problem, it is also possible to... Figure 7 The sensing circuit 200' shown is used to further detect whether there is a read path with high impedance characteristics in the non-transitory memory, and in the application terminal product stage, the sensing circuit is switched to the second test mode to sense and correct the results, thereby improving the yield.

[0053] Figure 9 The diagram illustrates the steps of detecting the presence of a readout path with high impedance characteristics according to the second embodiment of the present invention. Please also refer to... Figure 3 , Figure 7 and Figure 9 The process begins at step S910. In step S920, all memory cells of the non-transitory memory 100' are programmed with a voltage equivalent to a bit value "0", and execution is performed for each memory cell. Figure 9 The remaining steps are as follows. In step S930, the test device is operated in the first test mode (transistors M7 and M8 are not active due to the disconnection of the conduction path), and step S940 is executed. In step S940, it is confirmed whether the sensing result Dout is a bit value "0". If yes, the programming is successful (step S950). If no (the sensing result Dout is a bit value "1"), it indicates that there is a possibility of a read error due to the existence of a read path with high impedance characteristics, so step S960 needs to be executed further. In step S960, the test device is operated in the second test mode (transistors M7 and M8 are active due to the formation of the conduction path) to confirm whether the non-temporary memory 100' failed to read due to the existence of a read path with high impedance characteristics or failed to erase due to a structural problem of the non-temporary memory 100' itself. In step S970, it is confirmed whether the sensing result Dout is a bit value "0". If yes (the sensing result Dout has been corrected / compensated), the programming is successful (step S950). If not (the sensing result Dout is a bit value "1"), then programming has failed (step S980).

[0054] In this way, even if the non-temporary memory 100' has a high-impedance read path, it can still be accessed through methods such as... Figure 7 The architecture shown is used to modify / compensate the sensing result Dout to prevent the non-temporary memory 100' from failing the CP detection stage and being treated as a defective product. The second test mode is directly applied to the end product, thereby improving the product yield.

[0055] It should be noted that although the above embodiments are all based on OTP memory (or MTP memory) as examples, the present invention is not limited thereto. In other embodiments, the sensing circuit and testing device of the present invention can be applied to any non-transitory memory, including read-only memory (ROM), flash memory, and non-volatile random access memory (NVRAM). Among them, read-only memory includes programmable read-only memory (PROM), electrically alterable read-only memory (EAROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), mask-programmed read-only memory (Mask ROM), and fuse-programmed read-only memory (Fuse ROM).

[0056] In summary, this invention controls the sensing circuit (such as...) Figure 2A , Figure 2B as well as Figure 7 The operation of the switch within (as shown) allows for both a first test mode and a second test mode. This invention can detect the presence of a leakage current path with high impedance characteristics in a non-transitory memory by sequentially performing the first and second test modes. Furthermore, this invention can also detect the presence of a read path with high impedance characteristics in a non-transitory memory by sequentially performing the first and second test modes and automatically compensate for the sensing results.

[0057] This avoids the problem of non-transitory memory with high-impedance leakage current paths passing through the sensor but subsequently failing (read errors) during use. Furthermore, it allows for improved product yield by compensating for the presence of high-impedance read paths. Therefore, both product reliability and yield can be improved.

[0058] [Symbol Explanation]

[0059] 100, 100': OTP memory (or MTP memory)

[0060] 101: Current Source

[0061] 102: Load

[0062] 103: Sensing Amplifier

[0063] 200: Sensing Circuit

[0064] 300: Test Controller

[0065] B: Buffer

[0066] Dout: Sensing result

[0067] M1~M8: Transistors

[0068] Mc: Transistor

[0069] Ms: Transistor

[0070] Msel: Transistor

[0071] N1~N6: Nodes

[0072] S: Control signal

[0073] S410~S490, S610~S680, S810~S890, S910~980: Steps

[0074] SW1~SW4: Switches

[0075] VDD: Operating voltage

[0076] Vsen: Read voltage

Claims

1. A sensing circuit for generating a sensing result based on a read voltage of a non-transitory memory, comprising: The first transistor is coupled between the operating voltage and the first node; The second transistor is coupled between the first node and the second node; The third transistor is coupled between the second node and the reference ground voltage, wherein the control terminals of the first transistor, the second transistor, and the third transistor all receive the read voltage; The fourth transistor is coupled between the operating voltage and the first node; as well as The switching group disconnects the conduction path between the control terminal of the fourth transistor and the second node according to the control signal, so that the first node can obtain the first sensing result, and forms a conduction path between the control terminal of the fourth transistor and the second node according to the control signal, so that the first node can obtain the second sensing result.

2. The sensing circuit according to claim 1, wherein the switch group comprises: The first switch is positioned between the control terminal of the fourth transistor and the third node; as well as The second switch is located between the second node and the third node. Specifically, when the control signal is at the first voltage level, the first switch and the second switch form the conduction path. When the control signal is at the second voltage level, the first switch and the second switch operate to be coupled to the operating voltage and the reference ground voltage respectively, so as to disconnect the conduction path.

3. The sensing circuit according to claim 1, wherein the first transistor and the fourth transistor are P-type metal-oxide-semiconductor field-effect transistors, and the second transistor and the third transistor are N-type metal-oxide-semiconductor field-effect transistors.

4. The sensing circuit according to claim 1 further includes: A buffer, coupled to the first node, is used to digitize the simulated sensing result.

5. The sensing circuit of claim 4, wherein the buffer comprises two inverters connected in series.

6. The sensing circuit according to claim 1, wherein the non-temporary memory is a one-time programmable memory or a multiple-time programmable memory.

7. A testing apparatus for generating a test result based on the read voltage of a non-transitory memory, comprising: Non-transitory memory, programmed with voltage values ​​corresponding to bit values; The sensing circuit according to claim 1; as well as Test controller, used to: The control signal is generated so that the switch group disconnects the conduction path according to the control signal to enter the first test mode, and when the sensing result obtained by executing the first test mode is the bit value, the switch group is turned on the conduction path according to the control signal to enter the second test mode. as well as When the sensing result obtained by performing the second test mode is not the bit value, the test result is generated to indicate that there is a high-impedance leakage current path in the non-transitory memory.

8. The testing apparatus according to claim 7, wherein the test controller is further configured to: When the sensing result obtained by executing the first test mode is not the bit value, the test result is generated to indicate that the programming result failed because there is a low impedance leakage current path in the non-transitory memory.

9. The testing apparatus according to claim 7, wherein the test controller is further configured to: When the sensing result obtained by executing the second test mode is the bit value, the test result is generated to indicate that the programming result is successful.

10. A testing apparatus for generating a test result based on a read voltage of a non-transitory memory, comprising: Non-transitory memory is erased with a voltage value corresponding to the bit value; The sensing circuit according to claim 1; as well as Test controller, used to: The control signal is generated so that the switch group disconnects the conduction path according to the control signal to enter the first test mode, and when the sensing result obtained by executing the first test mode is not the bit value, the switch group is turned on the conduction path according to the control signal to enter the second test mode. as well as When the sensing result obtained by executing the second test mode is the bit value, the test result is generated to indicate that the sensing result has been corrected for the read bit value error caused by the high impedance read path of the non-transitory memory.

11. The testing apparatus according to claim 10, wherein the test controller is further configured to: When the sensing result obtained by executing the first test mode is the bit value, the test result is generated to indicate that the erasure result was successful.

12. The testing apparatus according to claim 10, wherein the test controller is further configured to: If the sensing result obtained by executing the second test mode is not the bit value, the test result is generated to indicate that the erasure result has failed.

13. A sensing circuit for generating a sensing result based on a read voltage of a non-transitory memory, comprising: A first transistor is coupled between a first node and a second node, wherein the control terminal of the first transistor receives the read voltage; The second transistor is coupled between the second node and the reference ground voltage; The third transistor is coupled between the operating voltage and the first node, wherein the control terminal of the third transistor is coupled to the control terminal of the second transistor and receives the read voltage; The fourth transistor is coupled between the second node and the reference ground voltage; as well as The switching group disconnects the conduction path between the first node and the control terminal of the fourth transistor according to the control signal, so that the second node can obtain the first sensing result, and forms a conduction path between the first node and the control terminal of the fourth transistor according to the control signal, so that the second node can obtain the second sensing result.

14. The sensing circuit of claim 13, wherein the switch group comprises: The first switch is set between the first node and the third node; as well as The second switch is positioned between the third node and the control terminal of the fourth transistor. Specifically, when the control signal is at the first voltage level, the first switch and the second switch form the conduction path. When the control signal is at the second voltage level, the first switch and the second switch operate to be coupled to the operating voltage and the reference ground voltage respectively, so as to disconnect the conduction path.

15. The sensing circuit of claim 13, wherein the first transistor and the third transistor are P-type metal-oxide-semiconductor field-effect transistors, and the second transistor and the fourth transistor are N-type metal-oxide-semiconductor field-effect transistors.

16. The sensing circuit according to claim 13, further comprising: A buffer, coupled to the second node, is used to digitize the simulated sensing result.

17. The sensing circuit of claim 16, wherein the buffer comprises two inverters connected in series.

18. The sensing circuit according to claim 13, wherein the non-temporary memory is a one-time programmable memory or a multiple-time programmable memory.

19. A testing apparatus for generating a test result based on a read voltage of a non-transitory memory, comprising: Non-transitory memory is erased with a voltage value corresponding to the bit value; The sensing circuit according to claim 13; as well as Test controller, used to: The control signal is generated so that the switch group disconnects the conduction path according to the control signal to enter the first test mode, and when the sensing result obtained by executing the first test mode is the bit value, the switch group is turned on the conduction path according to the control signal to enter the second test mode. as well as When the sensing result obtained by performing the second test mode is not the bit value, the test result is generated to indicate that there is a high-impedance leakage current path in the non-transitory memory.

20. The testing apparatus according to claim 19, wherein the test controller is further configured to: If the sensing result obtained by executing the first test mode is not the bit value, the test result is generated to indicate that the erasure result has failed.

21. The testing apparatus according to claim 19, wherein the test controller is further configured to: When the sensing result obtained by executing the second test mode is the bit value, the test result is generated to indicate that the erasure result was successful.

22. A testing apparatus for generating a test result based on a read voltage of a non-transitory memory, comprising: Non-transitory memory, programmed with voltage values ​​corresponding to bit values; The sensing circuit according to claim 13; as well as Test controller, used to: The control signal is generated so that the switch group disconnects the conduction path according to the control signal to enter the first test mode, and when the sensing result obtained by executing the first test mode is not the bit value, the switch group is turned on the conduction path according to the control signal to enter the second test mode. as well as When the sensing result obtained by executing the second test mode is the bit value, the test result is generated to indicate that the sensing result has been corrected for the read bit value error caused by the high impedance read path of the non-transitory memory.

23. The testing apparatus according to claim 22, wherein the test controller is further configured to: When the sensing result obtained by executing the first test mode is the bit value, the test result is generated to indicate that the programming result is successful.

24. The testing apparatus according to claim 22, wherein the test controller is further configured to: If the sensing result obtained by executing the second test mode is not the bit value, the test result is generated to indicate that the programming result has failed.

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