Memory testing method, device, equipment and medium

Abstract

The present disclosure provides a memory test method, device, equipment and medium, and relates to the technical field of semiconductors. The method comprises: performing at least one read-write operation test on a test storage array in a memory, wherein in each read-write operation test, the following steps are performed: obtaining a read-write timing diagram corresponding to the read-write operation test, wherein the read-write timing diagram is a timing diagram of a control signal sequence corresponding to the read-write operation, and an actual pre-charge duration of a pre-charge stage in each stage is a test pre-charge duration corresponding to the read-write operation test; determining a test result of the read-write operation test according to the read-write timing diagram and a preset abnormality determination condition, and the test result is used to represent whether the memory has a read-write abnormality caused by a standby mode under the test pre-charge duration. According to the embodiment of the present disclosure, the influence of the standby mode on the read-write of the memory can be accurately tested.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory testing method, apparatus, device, and medium. Background Art

[0002] In the field of semiconductor technology, with the iterative upgrade of memory products, issues such as memory power consumption have also become an important consideration in product design.

[0003] In order to optimize the power consumption of the memory, the memory can reduce the power consumption of the memory by entering the standby mode. At present, there is a lack of a solution for testing the impact of the standby mode on the read and write test of the memory.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The present disclosure provides a memory testing method, apparatus, device, and medium, which accurately test the impact of a standby mode on memory reading and writing, at least to a certain extent.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a memory testing method is provided, the method comprising:

[0008] Perform at least one read and write operation test on the test storage array in the memory, wherein each read and write function test corresponds to a test precharge duration.

[0009] In each read and write operation test, the following steps are performed:

[0010] Obtaining a read / write timing diagram corresponding to the current read / write operation test, wherein the read / write timing diagram is a timing diagram of a control signal sequence corresponding to the current read / write operation, the control signal sequence including a pulse signal corresponding to each stage in the current read / write test, the pulse signal of each stage being used to instruct the test memory array to enter that stage, and the actual pre-charge duration of the pre-charge stage in each stage being the test pre-charge duration corresponding to the current read / write operation test;

[0011] According to the read and write timing diagram and the preset abnormality judgment conditions, the test results of this read and write operation test are determined. The test results are used to indicate whether the memory has read and write abnormalities caused by the standby mode during the test precharge time.

[0012] In one embodiment, the abnormality determination condition includes the presence of an interference signal in the read / write timing diagram,

[0013] According to the read and write timing diagram and the preset abnormality judgment conditions, the test results of this read and write operation test are determined, including:

[0014] When there is an interference signal in the read / write timing diagram, the test result of this read / write operation test is determined to be the first test result. The first test result is used to characterize the read / write anomaly caused by the standby mode during the test pre-charge time of the memory.

[0015] In one embodiment, the phases include an activation phase, a read / write phase, and a precharge phase.

[0016] In the case where an interference signal exists in the read / write timing diagram, determining the test result of the current read / write operation test as the first test result includes:

[0017] When an interference signal exists in the timing segment of at least one of the activation phase, the read / write phase, and the precharge phase, the test result of the current read / write operation test is determined to be the first test result.

[0018] In one embodiment, before obtaining the read / write timing diagram corresponding to the current read / write operation test, the method further includes:

[0019] Obtaining the control signal sequence corresponding to the current read and write operation test generated in real time;

[0020] Using the control signal sequence generated in real time, the test storage array is read and written in a preset read and write mode to simulate the impact of the actual read and write process on the read and write timing diagram.

[0021] In one embodiment, the test memory array includes multiple memory arrays of a memory, the control signal sequence includes a control signal sequence for each memory array, and the preset read and write mode includes controlling at least one memory array of the multiple memory arrays to perform a write operation and controlling other memory arrays except the at least one memory array to perform a read operation;

[0022] Using real-time generated control signal sequences, the test memory array is read and written in a preset read and write mode to simulate the impact of the actual read and write process on the read and write timing diagram, including:

[0023] At least one storage array is controlled to perform a write operation and the other storage arrays are controlled to perform a read operation by utilizing respective control signal sequences of the plurality of storage arrays.

[0024] In one embodiment, the preset read / write mode includes controlling one of any two adjacent storage arrays in the plurality of storage arrays to perform a write operation and controlling the other of any two adjacent storage arrays to perform a read operation;

[0025] Using control signal sequences of the plurality of storage arrays to control at least one storage array to perform a write operation and to control the other storage arrays to perform a read operation, comprising:

[0026] For one of any two adjacent storage arrays, a write operation is performed on the one using a control signal sequence of the one generated in real time;

[0027] Furthermore, for the other of any two adjacent storage arrays, a read operation is performed on the other using the control signal sequence of the other generated in real time.

[0028] In one embodiment, for the other of any two adjacent storage arrays, using the control signal sequence of the other generated in real time, before performing a read operation on the other, the method further includes:

[0029] During the previous read / write operation test, a write operation is performed on the other of any two adjacent storage arrays, so that during the current operation test, a read operation is performed on the other.

[0030] In one embodiment, the preset read and write mode includes: at least one of a preset operation mode and a preset write operation mode;

[0031] The preset read operation mode is used to select the word line or bit line to be turned on and the length of the read data;

[0032] The preset write operation mode is used to select whether to open a word line or a bit line and the length of the written data.

[0033] In one embodiment, the preset read and write mode includes reading and writing the test memory array according to a preset test pattern;

[0034] Before reading and writing the test storage array in a preset read and write mode using the control signal sequence generated in real time, the method further includes:

[0035] Obtaining a preset test pattern corresponding to the test storage array;

[0036] Using real-time generated control signal sequences, the test memory array is read and written in a preset manner, including:

[0037] The test memory array is read and written according to a preset test pattern using a control signal sequence generated in real time.

[0038] In one embodiment, the preset test pattern includes:

[0039] Checkerboard, striped, or diagonal patterns.

[0040] In one embodiment, before obtaining the read / write timing diagram corresponding to the current read / write operation test, the method further includes:

[0041] According to the preset time generation method, the test pre-charging time corresponding to this read and write operation test is selected within the pre-charging time range specified by the preset specification protocol.

[0042] In one embodiment, the method further comprises:

[0043] Determining a target value range for the precharge duration based on the test results of the at least one read and write operation test and the test precharge duration corresponding to the at least one read and write operation test, wherein the target value range is a precharge duration value range within which an actual precharge duration of the memory does not cause a read or write anomaly due to the standby mode;

[0044] The actual read and write operations of the memory are controlled according to the target value range.

[0045] According to another aspect of the present disclosure, a memory testing device is provided, comprising:

[0046] The test module is used to perform at least one read and write operation test on the test storage array in the memory, wherein each read and write function test corresponds to a test precharge time.

[0047] Wherein, the test module includes:

[0048] a timing diagram acquisition unit, configured to acquire, during each read / write operation test, a read / write timing diagram corresponding to the current read / write operation test, wherein the read / write timing diagram is a timing diagram of a control signal sequence corresponding to the current read / write operation, the control signal sequence including a pulse signal corresponding to each stage in the current read / write test, the pulse signal in each stage being used to instruct the test memory array to enter that stage, and the actual pre-charge duration of the pre-charge stage in each stage being the test pre-charge duration corresponding to the current read / write operation stage;

[0049] The test unit is used to determine the test result of the read and write operation test according to the read and write timing diagram and the preset abnormality judgment condition during each read and write operation test. The test result is used to characterize whether the memory has a read and write abnormality caused by the standby mode during the test pre-charging time.

[0050] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-mentioned memory testing method by executing the executable instructions.

[0051] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the computer program implements the above-mentioned memory testing method.

[0052] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, which implements the above-mentioned memory testing method when executed by a processor.

[0053] The memory test method, device, equipment and medium provided by the embodiments of the present disclosure can perform at least one read and write operation test on the test storage array of the memory, and in each read and write operation test, the actual pre-charge duration of the test read and write operation test can be controlled to be the test pre-charge duration corresponding to the current read and write operation test. Since the standby time of the standby mode is affected by the actual pre-charge duration, and when the memory causes read and write anomalies due to the standby mode, it will affect the read and write timing diagram, therefore, the embodiments of the present disclosure can accurately test the read and write functions of the memory under each test pre-charge duration through at least one read and write operation test, and according to the read and write timing diagram and the preset abnormality judgment conditions, so as to accurately test the impact of the standby mode on the reading and writing of the memory.

[0054] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0056] Figure 1 A schematic diagram of a read and write process of a memory provided by an embodiment of the present disclosure is shown;

[0057] Figure 2 A partial structural diagram of an exemplary memory provided by an embodiment of the present disclosure is shown;

[0058] Figure 3 FIG2 shows an exemplary potential change diagram of normally reading data “0” from a memory provided by an embodiment of the present disclosure;

[0059] Figure 4 A flow chart of a memory testing method according to an embodiment of the present disclosure is shown;

[0060] Figure 5 A schematic diagram showing a flow chart of a memory testing method provided by an embodiment of the present disclosure is shown;

[0061] Figure 6 A schematic diagram showing an exemplary read and write timing diagram provided by an embodiment of the present disclosure is shown;

[0062] Figure 7 A schematic diagram showing a flow chart of another memory testing method provided by an embodiment of the present disclosure;

[0063] Figure 8 A schematic diagram illustrating a flow chart of another memory testing method provided by an embodiment of the present disclosure is shown;

[0064] Figure 9 A schematic diagram of a memory testing device according to an embodiment of the present disclosure is shown;

[0065] Figure 10 A structural block diagram showing an electronic device according to an embodiment of the present disclosure; and

[0066] Figure 11 A schematic diagram of a computer-readable storage medium in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0067] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0068] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0069] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0070] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0071] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0072] With the development of semiconductor technology, in the research and development of memory products such as Dynamic Random Access Memory (DRAM), the power consumption characteristics of the memory during the reading and writing process have become one of the important performance indicators of the memory.

[0073] Figure 1 FIG. 1 shows a schematic diagram of a read and write process of a memory provided by an embodiment of the present disclosure. Figure 1 As shown, the memory may sequentially enter the activation (ACT) phase 11, the read / write (WR / RD) phase 12, and the precharge phase 13 during each read / write operation. Then, after a preset time (Timer), the memory enters the activation (ACT) phase 11 for the next read / write operation.

[0074] In the above read / write process, to reduce the power consumption of the memory, the memory can enter the standby mode between the precharge phase 13 of the current read / write process and the activation (ACT) phase 11 of the next read / write process. For example, the memory can save power by turning off the local power supply in the standby mode.

[0075] However, the inventors discovered through research that standby mode often causes abnormal read and write behavior in memory. For example, when the local power supply is off, circuit noise and other factors can cause abnormal read and write behavior. Furthermore, if this issue cannot be effectively detected in advance, it can extend the memory product development cycle and affect product competitiveness. Furthermore, it can affect the reliability and yield of semiconductor products.

[0076] Therefore, how to test the impact of the standby mode on memory read and write tests has become an urgent problem to be solved.

[0077] Based on this, embodiments of the present disclosure provide a memory testing method, apparatus, device, and medium that can be applied in the field of semiconductor technology, and illustratively, can be applied in the product development of memories such as dynamic random access memory (DRAM). Embodiments of the present disclosure accurately test the read and write functions of the memory under various test precharge durations by performing at least one read and write operation test, and in each read and write operation test, based on a read and write timing diagram and preset abnormality determination conditions, thereby accurately testing the impact of standby mode on memory read and write tests.

[0078] The following will describe the technical solutions provided by the embodiments of the present disclosure in conjunction with the accompanying drawings. Before describing the technical solutions provided by the embodiments of the present disclosure, for ease of understanding, the following part of the present disclosure will first describe the memory.

[0079] Figure 2 FIG. 1 shows a partial structural diagram of an exemplary memory provided by an embodiment of the present disclosure. Figure 2 As shown, the memory may include a word line WL, a bit line BL, a reference bit line / BL, a memory cell 210, a sense amplifier (SA) 220, an equalizer 230, and a bit line selector 240. The memory cell 210 is used to store data "0" or "1." The SA 220 is used to detect and amplify the voltage difference between the bit line BL and the reference bit line / BL. The equalizer 230 is used to provide an equalization voltage VEQ (Voltage of Equalizer, VEQ) to restore the bit line BL and the reference bit line / BL to the same potential. The bit line selector module 240 is used to control whether the bit line BL is turned on or off, that is, whether the memory cell 210 is read or written through this bit line, and output the read data through the LIO terminal.

[0080] SA220 may include four transistors M1 - M4 to amplify small voltage changes on the bit line BL during the process of reading data stored in the memory cell 210 .

[0081] After briefly introducing the structure of the memory, the reading and writing process of the memory will be described with reference to the accompanying drawings.

[0082] Figure 3 A schematic diagram of potential changes when data "0" is normally read from a memory is shown, which is an exemplary embodiment of the present disclosure.

[0083] Please also see Figure 2 and Figure 3Upon receiving the wordline activation signal (i.e., entering the ACT phase), the equalizer 230 is turned off by controlling VEQ to be off, and the wordline WL is turned on. During the charge sharing phase, after the voltage difference between the bitline and the reference bitline reaches ΔV, the first transistor M1 and the second transistor M2 are turned on, with the first transistor M1 being turned on to a greater degree than the second transistor M2. At this point, the potential of the bitline BL is rapidly pulled down to the voltage Vss at the node NCS. Simultaneously, as the bitline BL is pulled down, the second transistor M2 is turned off, the fourth transistor M4 is turned on, and the voltage Vary at the node PCS is applied to the reference bitline / BL. During this process, the SA operates to detect and amplify the voltage difference between the bitline BL and the reference bitline / BL. At this point, the normal data read (RD) phase can begin for data reading. After the data reading is completed, the precharge (PRE) stage can be entered. In the precharge stage, the word line WL can be turned off, and the SA 220 can be turned off. The equalizer 130 is turned on by turning on VEQ to restore the bit line BL and the reference bit line / BL to the same potential under the control of the equalizer controller 130.

[0084] Among them, Figure 3 As shown in FIG, the time from the start of the current pre-charging phase to the arrival of the next activation phase is actually the pre-charging time tRP.

[0085] In passing Figure 2 and Figure 3 After introducing the memory and the memory reading and writing process, this exemplary implementation is described in detail with reference to the accompanying drawings and embodiments.

[0086] An embodiment of the present disclosure provides a memory testing method, which can be executed by any electronic device with data processing capabilities.

[0087] Figure 4 A flow chart of a memory testing method according to an embodiment of the present disclosure is shown. Figure 4 As shown, the memory testing method provided in the embodiment of the present disclosure includes the following step S410.

[0088] S410: Perform at least one read / write operation test on a test memory array in a memory, wherein each read / write function test corresponds to a test pre-charging time.

[0089] For the memory, it can be a memory that performs read and write function verification. For example, the memory can be any one of the dynamic random access memories such as the fourth-generation double data rate synchronous dynamic random access memory (DDR4 SDRAM), the fourth-generation low-power double data rate synchronous dynamic random access memory (LPDDR4 SDRAM), the fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM), and the fifth-generation low-power double data rate synchronous dynamic random access memory (LPDDR4 SDRAM), without specific limitation. It should be noted that the memory can also be other memories besides dynamic random access memory, without specific limitation.

[0090] The test memory array may refer to a test memory array among multiple memory arrays of a memory that needs to be tested for read and write operations, and specifically, may be one or more memory arrays in the memory, which is not specifically limited.

[0091] The read / write operation test may refer to a test of the read / write functions of the test memory array for reading and / or writing data. For example, in each read / write operation test, the test memory array may be controlled by corresponding control instructions to enter an activation (ACT) phase, a read / write phase, and a precharge (PRE) phase.

[0092] The test precharge duration may be the precharge duration required for performing a read / write test. For each test precharge duration, the duration between the current activation phase and the next precharge phase in the corresponding read / write test function test may be controlled to be equal to the test precharge duration. For example, the test precharge durations corresponding to any two read / write operation tests may be the same or different, and this is not specifically limited.

[0093] In some embodiments, the test pre-charging duration of each read / write operation test may be determined according to a preset specification protocol. Accordingly, before S411, the memory test method may further include step A1.

[0094] Step A1: According to a preset time generation method, a test pre-charging time corresponding to the current read / write operation test is selected within the pre-charging time range specified in a preset specification protocol.

[0095] The preset specification protocol may be a protocol that specifies a precharge time tRP for reading and writing memory. For example, the preset specification protocol may be a Joint Electron Device Engineering Council (JEDEC) standard protocol.

[0096] The pre-charge duration range may be within the allowable value range of the pre-charge duration tRP specified in a preset specification protocol. For example, the pre-charge duration range may be 20 ns (nanoseconds) to 8000 ns.

[0097] After introducing the preset standard protocol and the pre-charging time range, the specific implementation of step A1 will be described next.

[0098] In one example, step A1 may include the following step A11.

[0099] Step A11, randomly selecting a test pre-charging duration for this read / write operation test within the pre-charging duration range. It should be noted that by randomly selecting a pre-charging duration for each test, comprehensive testing can be achieved within the pre-charging duration range.

[0100] In another example, step A1 may include the following step A12.

[0101] Step A12, within the pre-charge duration range, increase or decrease the test pre-charge duration of each read-write operation test according to a preset step. For example, the preset time threshold can be increased or decreased on the basis of the test pre-charge duration of the previous read-write operation test to obtain the test pre-charge duration of this read-write operation test. Among them, the preset time threshold can be a preset empirical value, or a value set according to the actual test scenario and specific test requirements, and is not specifically limited to this. Through this example, the test pre-charge duration can be increased or decreased within the range of the preset step, thereby achieving standardized testing within the pre-charge duration range, thereby improving the accuracy and comprehensiveness of the test.

[0102] It should be noted that the test pre-charging time can also be selected within the pre-charging time range specified in the preset specification protocol through other methods according to the actual test scenario and specific test requirements, and there is no specific restriction on this.

[0103] Through this embodiment, since the pre-charging time tRP in the actual reading and writing process needs to meet the requirements of the preset specification protocol, by selecting the test pre-charging time within the pre-charging time range specified by the preset specification protocol, the test results can meet the requirements of the actual reading and writing process, thereby improving the effectiveness and practicality of the test.

[0104] After introducing the above concepts, the specific implementation of the read and write operation test will be described next.

[0105] Specifically, Figure 5 FIG. 1 shows a flow chart of a memory testing method provided by an embodiment of the present disclosure. Figure 5As shown, in each read and write operation test, the following steps S411 and S412 are performed.

[0106] S411, obtaining a read / write timing diagram corresponding to this read / write operation test.

[0107] For the read and write timing diagram, it can be a timing diagram of the control signal sequence corresponding to this read and write operation. The control signal sequence includes the pulse signals corresponding to each stage in this read and write test. The pulse signals of each stage are used to indicate that the test storage array enters this stage. The actual pre-charging duration of the pre-charging stage in each stage is the test pre-charging duration corresponding to the current read and write operation stage.

[0108] In one example, Figure 6 FIG. 1 shows a schematic diagram of an exemplary read and write timing diagram provided by an embodiment of the present disclosure. Figure 6 As shown, the read and write timing Figure 1-4 Including the pulse signals of the activation phase, read / write phase, and pre-charge phase during each read / write operation. Taking the activation phase as an example, when the pulse signal of this phase jumps from a low level to a high level, it enters the activation phase accordingly.

[0109] And, continue to see Figure 6 In the embodiment of the present disclosure, by controlling the actual pre-charge time to the test pre-charge time corresponding to each read and write operation test, Figure 6 The preset time in the standby mode is controlled to achieve control of the standby time.

[0110] After introducing the read and write timing diagram, the specific implementation of S411 is described next.

[0111] In an example, S411 may include: acquiring, from the command generation module, a control signal sequence corresponding to each read and write operation test generated by the command generation module, and generating a corresponding read and write timing diagram based on the control signal sequence.

[0112] It should be noted that the read and write timing diagram may also be obtained or generated in other ways, and there is no specific limitation to this.

[0113] S412: Determine the test result of the read / write operation test based on the read / write timing diagram and the preset abnormality determination condition, wherein the test result is used to indicate whether the memory has a read / write abnormality caused by the standby mode during the test precharge time.

[0114] The preset abnormality determination condition may refer to the condition that needs to be met when determining that the memory has a read / write abnormality caused by the standby mode. In one example, the abnormality determination condition may include the presence of an interference signal in the read / write timing diagram of this read / write operation test. The interference signal may refer to a signal waveform that is more than the normal read / write timing diagram in the actual read / write timing diagram. For example, continue to refer to Figure 6 , Figure 6 The signal waveform shown by the dotted line is the interference signal G1. It should be noted that other abnormality judgment conditions, such as the signal duty cycle being greater than a preset duty cycle threshold, can be set according to actual test conditions and specific test requirements to determine whether the read and write operation is abnormal based on the read and write timing diagram, and there is no specific limitation on this.

[0115] In some embodiments, when the preset abnormality determination condition includes the presence of an interference signal in the read / write timing diagram, S412 may include the following step B1.

[0116] Step B1: If there is an interference signal in the read / write timing diagram, determine the test result of the read / write operation test as a first test result, wherein the first test result is used to indicate that the memory has a read / write abnormality caused by the standby mode during the corresponding test precharge duration.

[0117] In one embodiment, a judgment step may be included before step B1. Accordingly, the memory testing method may further include the following step B2.

[0118] Step B2: Determine whether there is an interference signal in the read / write timing diagram. Exemplarily, whether there is an interference signal in the read / write timing diagram can be determined by graphical analysis, timing diagram data processing, etc., and the specific determination method is not specifically limited.

[0119] For example, see Figure 6 , when the interference signal G1 is found in the read / write timing diagram, it can be determined that the test structure of this read / write operation test is the first test result.

[0120] In one embodiment, after step B2, the memory testing method may further include the following step B3.

[0121] Step B3: If there is no interference signal in the read / write timing diagram, determine that the test structure of the current read / write operation test is a second test result, wherein the second test result is used to indicate that the memory can read and write normally under the test precharge duration.

[0122] Through this embodiment, since the memory may generate circuit noise due to the local power switch in standby mode, and the circuit noise will cause certain fluctuations in the waveform of the read and write timing diagram, therefore, through the read and write timing diagram and the preset abnormality judgment conditions, it is possible to accurately judge whether the memory has read and write abnormalities caused by standby mode during the test pre-charge time, thereby improving the accuracy of the test.

[0123] In one example, since the stages of the read / write test may include an activation stage, a read / write stage, and a pre-charge stage, step B1 may include the following step B11 .

[0124] Step B11 : when an interference signal exists in the timing segment of at least one of the activation phase, the read / write phase, and the pre-charge phase, determining the test result of the current read / write operation test as the first test result.

[0125] For example, see Figure 6 , read and write timing Figure 1 The figure shows the situation where the interference signal G1 exists in the timing segment of the signal writing (WR) phase. Figure 2 The figure shows the situation where the interference signal G1 exists in the timing segment of the signal writing (WR) phase. Figure 3 The following shows the situation where the interference signal G1 exists in the timing segment of the activation (ACT) phase, the read and write timing Figure 4 The figure shows the situation where the interference signal G1 exists in the timing segment of the precharge (PRE) phase. Figure 1-4 , it can be determined that the test result of this read and write operation test is the first test result.

[0126] The memory test method provided by the embodiment of the present disclosure can perform at least one read and write operation test on the test storage array of the memory, and in each read and write operation test, the actual pre-charge duration of the test read and write operation test can be controlled to be the test pre-charge duration corresponding to the current read and write operation test. Since the standby time of the standby mode is affected by the actual pre-charge duration, and when the memory causes read and write anomalies due to the standby mode, it will affect the read and write timing diagram, therefore, the embodiment of the present disclosure can accurately test the read and write function of the memory under each test pre-charge duration through at least one read and write operation test, and according to the read and write timing diagram and the preset abnormality judgment conditions, so as to accurately test the impact of the standby mode on the read and write of the memory.

[0127] Figure 7 The flowchart of another memory testing method provided by the embodiment of the present disclosure is shown. The embodiment of the present disclosure is optimized based on the above embodiment, and the embodiment of the present disclosure can be combined with various optional solutions in one or more of the above embodiments.

[0128] like Figure 7 As shown, the memory testing method may include the following step S710.

[0129] S710: Perform at least one read / write operation test on a test storage array in a memory, wherein each read / write function test corresponds to a test pre-charging time.

[0130] In each read / write operation test, the following steps S711 to S714 are performed.

[0131] S711: Obtain a control signal sequence corresponding to the current read / write operation test, which is generated in real time. The control signal sequence may refer to a control signal sequence for a single read / write operation. For example, when the test storage array includes multiple storage arrays of a memory, the control signal sequence may include a control signal sequence for each storage array.

[0132] Exemplarily, the control signal sequence generated in real time by the command generation module can be obtained from the command generation module.

[0133] S712 , using the control signal sequence generated in real time, performing reading and writing on the test storage array in a preset reading and writing mode to simulate the influence of the actual reading and writing process on the reading and writing timing diagram.

[0134] The preset read / write mode is used to cause the test memory array to be read and written in a certain manner. For example, the preset read / write mode may be a mode for reading and / or writing multiple test memory arrays, a pattern for a single test memory array, or a read / write mode for a single test memory array, etc., without specific limitation.

[0135] In some embodiments, the preset read and write mode includes at least one of a preset operation mode and a preset write operation mode.

[0136] The preset read operation mode is used to select the word line or bit line to be turned on and / or the length of the read data;

[0137] The preset write operation mode is used to select the word line or bit line to be turned on and / or the length of the written data.

[0138] Illustratively, the preset read operation mode may include any one of the following read modes 1-3.

[0139] Read mode 1: X-Fast Read, also known as an X-direction read operation. Before each read operation, all word lines on the same bit line are sequentially enabled. Specifically, a word line is enabled and the contents of a burst-length (8-bit) unit are sequentially read from it. This word line is then disabled, and the next word line is enabled and the contents of the next burst-length unit are sequentially read from it.

[0140] Read mode 2: Y-Fast Read, also known as a Y-direction read operation. Before each read operation, a word line is turned on. After sequentially reading one burst-length cell on this word line, the word line is turned off. The word line is then turned on again and read one burst-length cell sequentially. This process of turning the word line on and off repeatedly continues until all the corresponding memory cells on this word line have been read. The next word line is then turned on and the same process is repeated.

[0141] Read mode 3: diagonal readout (diagonal), that is, each time a diagonal line is opened, after the data on the diagonal line is read, the read operation of the next diagonal line is opened.

[0142] Illustratively, the preset write operation mode may include any one of the following write modes 1-4.

[0143] Write mode 1: Y-Page Write, a Y-direction write operation. Before each write operation, a word line is turned on. After all the corresponding memory cells on this word line are written sequentially, this word line is turned off. Then, the next word line is turned on and all the memory cells are written sequentially.

[0144] Write mode 2: X-Fast Write, also known as an X-direction write mode. Before each write operation, all word lines on the same bit line are sequentially enabled. After a word line is enabled and the contents of one burst length unit are sequentially written to it, the word line is then disabled, and the next word line is enabled and the contents of one burst length unit are sequentially written to it.

[0145] Write method 3: Y-Fast Write, a Y-direction write method. Before each write operation, a word line is turned on. After writing a burst length unit on this word line, the word line is turned off. Then, the word line is turned on again and a burst length unit is written. This process of turning the word line on and off is repeated until all the corresponding storage cells on this word line are written. Then, the next word line is turned on and the same process is repeated.

[0146] Write mode 4, diagonal write (diagonal), that is, each time a diagonal line is opened, after the data on the diagonal line is written, the next diagonal line is opened.

[0147] It should be noted that you can also choose a suitable reading and writing method for testing according to actual conditions and specific scenarios, and there is no specific limitation on this.

[0148] By using the above preset reading and writing methods, the influence of different reading and writing methods on the test results can be tested, thereby improving the test accuracy.

[0149] Next, S712 will be described in detail in conjunction with the preset reading and writing method.

[0150] In some embodiments, the preset read and write mode includes controlling at least one storage array among the plurality of storage arrays to perform a write operation and controlling other storage arrays except the at least one storage array to perform a read operation.

[0151] Accordingly, S712 includes the following step C1.

[0152] In step C1, the control signal sequences of the plurality of storage arrays are used to control at least one storage array to perform a write operation and to control the other storage arrays to perform a read operation. The plurality of storage arrays may be part of or all of the storage arrays of the memory, without specific limitation.

[0153] For example, for a plurality of memory arrays 1-6 of a memory, memory array 1 and memory array 6 may be controlled to perform write operations, and the remaining memory arrays, ie, memory arrays 2-5, may be controlled to perform read operations.

[0154] Since the actual operation of the memory may involve simultaneous read and write operations, this embodiment can simulate the impact of the standby mode on the actual read and write process when the read and write operations are performed simultaneously, thereby improving the comprehensiveness and accuracy of the test and making the test results more consistent with the requirements of the actual read and write process.

[0155] In one embodiment, the preset read / write mode includes controlling one of any two adjacent storage arrays in the plurality of storage arrays to perform a write operation and controlling the other of any two adjacent storage arrays to perform a read operation. For example, for storage arrays 1-6, storage arrays 1, 3, and 5 can be controlled to perform a write operation, while storage arrays 2, 4, and 6 can be controlled to perform a read operation.

[0156] Accordingly, step C1 may include the following steps C11 and C12.

[0157] Step C11 : performing a write operation on one of any two adjacent storage arrays using a control signal sequence generated in real time.

[0158] Specifically, in this embodiment, one of any two adjacent storage arrays may refer to the storage array that needs to perform a write operation. For example, for storage array 3 and storage array 4, if storage array 3 needs to perform a write operation, then one of any two adjacent storage arrays may refer to storage array 3.

[0159] Step C12 : performing a read operation on the other of any two adjacent storage arrays using the control signal sequence of the other generated in real time.

[0160] Continuing with the previous example, for storage array 3 and storage array 4, if storage array 3 needs to perform a write operation, the other of any two adjacent storage arrays may be storage array 4.

[0161] Through steps C11 and C12, multiple storage arrays of the memory can be controlled to perform cross-reading and writing, thereby fully simulating the impact of the standby mode on the actual reading and writing process when performing read and write operations simultaneously, thereby improving test accuracy.

[0162] In one example, before step C12, step C1 may further include the following step C13.

[0163] Step C13: During the previous read / write operation test, a write operation is performed on the other of any two adjacent storage arrays so that a read operation can be performed on the other during the current operation test.

[0164] For example, in order to fully test the impact of the same test pre-charge duration on the read and write test, the write operation of the previous read and write operation test can correspond to the same test pre-charge duration as the current read and write operation test. It should be noted that, depending on the actual scenario and specific needs, the write operation of the previous read and write operation test can correspond to a different test pre-charge duration than the current read and write operation test, and there is no specific limitation on this.

[0165] Through step C13, data can be written to the test storage array in advance in the previous read and write operation test, thereby facilitating the read operation in this read and write operation test, thereby comprehensively testing the impact of the standby mode on the read and write operations, thereby improving the comprehensiveness and accuracy of the test.

[0166] In some embodiments, before S712 , the memory testing method may further include the following step D1 .

[0167] Step D1, obtaining a preset test pattern corresponding to the test memory array.

[0168] The preset test pattern may be a pattern composed of preset data stored in each storage unit on the memory array to be tested.

[0169] Exemplarily, the preset test pattern includes: a checkerboard pattern, a stripe pattern, or a diagonal pattern. It should be noted that the preset test pattern may also be other patterns, which is not specifically limited.

[0170] The checkerboard pattern is a test pattern in which when a certain memory cell stores data "1", its upper, lower, left, and right adjacent memory cells store data "0". Alternatively, when a certain memory cell stores data "0", its upper, lower, left, and right adjacent memory cells store data "1".

[0171] The stripe pattern can be a row stripe pattern, i.e., a test pattern that controls the storage cells in a certain row to store data "1" and the storage cells in an adjacent row to store data "0." It should be noted that column stripes can also be selected based on actual needs, and this is not specifically limited.

[0172] The diagonal pattern may refer to a test pattern for writing data into memory cells located on the diagonal of the memory array.

[0173] In one example, in order to balance test accuracy and test rate, the preset test pattern may be a diagonal pattern.

[0174] Since the diagonal pattern can increase the write / read rate and simulate the impact of capacitor leakage behavior during actual read / write processes on test results, both test accuracy and test efficiency can be taken into account.

[0175] In another example, in order to improve the accuracy of the test, the preset test pattern may be a checkerboard pattern.

[0176] Since the checkerboard pattern can make any two adjacent storage cells in the row and column directions in different data writing states, it can fully simulate the impact of capacitor leakage behavior in the actual reading and writing process on the test results, thereby improving the accuracy of the test.

[0177] By using checkerboard patterns, stripe patterns, and diagonal patterns, two adjacent storage cells can be controlled to be in different data states, thereby improving test efficiency while simulating the impact of behaviors such as capacitor leakage on test results, thereby improving the comprehensiveness of the test.

[0178] Accordingly, in the case where the method further includes step D1, S712 may include the following step D2.

[0179] Step D2: Using the control signal sequence generated in real time, read and write the test memory array according to the preset test pattern.

[0180] For example, when the preset test pattern is a diagonal pattern, data may be written into or read from memory cells located on a diagonal line of the test memory array.

[0181] Through steps D1 and D2, a read and write test can be performed according to a preset test pattern, thereby testing the impact of the standby mode on the memory read and written according to the preset test pattern, thereby improving the comprehensiveness of the test. Furthermore, the impact of the preset test pattern on the test results can be tested, thereby improving the test accuracy.

[0182] S713, obtaining a read / write timing diagram corresponding to the current read / write operation test, wherein the read / write timing diagram is a timing diagram of a control signal sequence corresponding to the current read / write operation, the control signal sequence includes a pulse signal corresponding to each stage in the current read / write test, the pulse signal of each stage is used to instruct the test storage array to enter that stage, and the actual pre-charge duration of the pre-charge stage in each stage is the test pre-charge duration corresponding to the current read / write operation test.

[0183] Among them, S713 is similar to S411. Please refer to the specific content of S411 and will not be repeated here.

[0184] S714 , determining a test result of this read / write operation test based on the read / write timing diagram and preset abnormality determination conditions. The test result is used to indicate whether a read / write abnormality caused by the standby mode occurs during the test precharge time of the memory.

[0185] Among them, S714 is similar to S412. Please refer to the specific content of S412 and will not be repeated here.

[0186] The memory test method provided by the embodiment of the present disclosure can perform at least one read and write operation test on the test storage array of the memory, and in each read and write operation test, the actual pre-charge duration of the test read and write operation test can be controlled to be the test pre-charge duration corresponding to the current read and write operation test. Since the standby time of the standby mode is affected by the actual pre-charge duration, and when the memory causes read and write anomalies due to the standby mode, it will affect the read and write timing diagram, therefore, the embodiment of the present disclosure can accurately test the read and write function of the memory under each test pre-charge duration through at least one read and write operation test, and according to the read and write timing diagram and the preset abnormality judgment conditions, so as to accurately test the impact of the standby mode on the read and write of the memory.

[0187] Furthermore, by controlling the storage array to read and write according to a preset read and write method, the impact of the actual read and write process in the standby mode on the test results can be simulated, thereby improving the comprehensiveness and accuracy of the test.

[0188] Figure 8 The flowchart of another memory testing method provided by the embodiment of the present disclosure is shown. The embodiment of the present disclosure is optimized based on the above embodiment, and the embodiment of the present disclosure can be combined with various optional solutions in one or more of the above embodiments.

[0189] like Figure 8 As shown, the memory testing method may include the following steps S810 to S830.

[0190] S810, performing at least one read and write operation test on the test storage array in the memory, wherein each read and write function test corresponds to a test precharge duration. S810 is similar to S410, and the details of S410 may be referred to, which will not be repeated here.

[0191] In each read and write operation test, the following steps S811 and S812 are executed:

[0192] S811, obtaining a read / write timing diagram corresponding to the current read / write operation test, wherein the read / write timing diagram is a timing diagram of a control signal sequence corresponding to the current read / write operation, the control signal sequence includes a pulse signal corresponding to each stage in the current read / write test, the pulse signal of each stage is used to instruct the test storage array to enter that stage, and the actual pre-charge duration of the pre-charge stage in each stage is the test pre-charge duration corresponding to the current read / write operation test.

[0193] Among them, S811 is similar to S411. Please refer to the specific content of S411 and will not be repeated here.

[0194] S812, determining the test result of this read / write operation test according to the read / write timing diagram and the preset abnormality judgment condition, wherein the test result is used to indicate whether the memory has a read / write abnormality caused by the standby mode during the test precharge time.

[0195] Among them, S812 is similar to S412. Please refer to the specific content of S412 and will not be repeated here.

[0196] S820: Determine a target value range for the pre-charge duration based on the test results of the at least one read and write operation test and the test pre-charge duration corresponding to the at least one read and write operation test. The target value range is a pre-charge duration value range that ensures that the actual pre-charge duration of the memory does not cause read and write anomalies due to the standby mode.

[0197] For example, after obtaining the test results of multiple read and write operations, the multiple read and write operations corresponding to the second test result (for example, there is no interference signal in the read and write timing diagram) can be screened out, and the test pre-charging time can be determined based on the test pre-charging time corresponding to the multiple read and write operations corresponding to the second test result.

[0198] For example, if multiple read and write operation tests determine that the test pre-charging time lengths of 20ns, 60ns, 80ns, and 95ns correspond to the second test result, the target value range can be determined to be 20ns to 95ns.

[0199] S830: Control the actual read and write operations of the memory according to the target value range.

[0200] Exemplarily, a data may be selected within the target value range as the value of the pre-charge time tRP during the actual read and write operations.

[0201] The memory test method provided by the embodiment of the present disclosure can perform at least one read and write operation test on the test storage array of the memory, and in each read and write operation test, the actual pre-charge duration of the test read and write operation test can be controlled to be the test pre-charge duration corresponding to the current read and write operation test. Since the standby time of the standby mode is affected by the actual pre-charge duration, and when the memory causes read and write anomalies due to the standby mode, it will affect the read and write timing diagram, therefore, the embodiment of the present disclosure can accurately test the read and write function of the memory under each test pre-charge duration through at least one read and write operation test, and according to the read and write timing diagram and the preset abnormality judgment conditions, so as to accurately test the impact of the standby mode on the read and write of the memory.

[0202] The disclosed embodiments can ensure that a suitable pre-charge time tRP can be selected during the actual reading and writing process, thereby ensuring the reading and writing quality while reducing power consumption through the standby mode, thereby improving the yield and performance of the memory.

[0203] Based on the same inventive concept, an embodiment of the present disclosure further provides a memory testing device, such as the following embodiment.

[0204] Figure 9 A schematic diagram of a memory test device according to an embodiment of the present disclosure is shown. Figure 9 As shown, the memory test device 900 includes:

[0205] The test module 910 is used to perform at least one read and write operation test on the test storage array in the memory, wherein each read and write function test corresponds to a test precharge time.

[0206] The testing module 910 includes a timing diagram acquiring unit 911 and a testing unit 912 .

[0207] The timing diagram acquisition unit 911 is used to obtain the read / write timing diagram corresponding to each read / write operation test during each read / write operation test, wherein the read / write timing diagram is a timing diagram of the control signal sequence corresponding to the read / write operation. The control signal sequence includes pulse signals corresponding to each stage in the read / write test. The pulse signal of each stage is used to indicate that the test storage array enters that stage. The actual pre-charging duration of the pre-charging stage in each stage is the test pre-charging duration corresponding to the read / write operation stage.

[0208] The test unit 912 is used to determine the test result of each read and write operation test according to the read and write timing diagram and the preset abnormality judgment conditions. The test result is used to indicate whether the memory has a read and write abnormality caused by the standby mode during the test pre-charge time.

[0209] The memory test device provided by the embodiment of the present disclosure can perform at least one read and write operation test on the test storage array of the memory, and in each read and write operation test, the actual pre-charge duration of the test read and write operation test can be controlled to be the test pre-charge duration corresponding to the current read and write operation test. Since the standby time of the standby mode is affected by the actual pre-charge duration, and when the memory causes read and write anomalies due to the standby mode, it will affect the read and write timing diagram, therefore, the embodiment of the present disclosure can accurately test the read and write functions of the memory under each test pre-charge duration through at least one read and write operation test, and according to the read and write timing diagram and the preset abnormality judgment conditions, so as to accurately test the impact of the standby mode on the reading and writing of the memory.

[0210] In one embodiment, the abnormality determination condition includes the presence of an interference signal in the read / write timing diagram,

[0211] Accordingly, the testing unit 912 may be specifically configured as follows:

[0212] When there is an interference signal in the read / write timing diagram, the test result of this read / write operation test is determined to be the first test result. The first test result is used to characterize the read / write anomaly caused by the standby mode during the test pre-charge time of the memory.

[0213] In one embodiment, the phases include an activation phase, a read / write phase, and a precharge phase.

[0214] Accordingly, the testing unit 912 may be specifically configured as follows:

[0215] When an interference signal exists in the timing segment of at least one of the activation phase, the read / write phase, and the precharge phase, the test result of the current read / write operation test is determined to be the first test result.

[0216] In one embodiment, the memory testing device 900 further includes: a signal sequence acquisition module and a read / write module.

[0217] A signal sequence acquisition module is used to obtain the control signal sequence corresponding to the current read and write operation test generated in real time;

[0218] The read / write module is used to read and write the test storage array in a preset read / write mode using a real-time generated control signal sequence to simulate the impact of the actual read / write process on the read / write timing diagram.

[0219] In one embodiment, the test storage array includes multiple storage arrays of a memory, the control signal sequence includes a control signal sequence for each storage array, and the preset read and write mode includes controlling at least one storage array of the multiple storage arrays to perform a write operation and controlling other storage arrays except the at least one storage array to perform a read operation.

[0220] The read-write module includes a read-write control unit.

[0221] The read / write control unit is used to control at least one storage array to perform a write operation and to control other storage arrays to perform a read operation using respective control signal sequences of the plurality of storage arrays.

[0222] In one embodiment, the preset read / write mode includes controlling one of any two adjacent storage arrays in the plurality of storage arrays to perform a write operation and controlling the other of any two adjacent storage arrays to perform a read operation;

[0223] The read-write control unit is specifically configured as follows:

[0224] For one of any two adjacent storage arrays, a write operation is performed on the one using a control signal sequence of the one generated in real time;

[0225] Furthermore, for the other of any two adjacent storage arrays, a read operation is performed on the other using the control signal sequence of the other generated in real time.

[0226] In one embodiment, the read / write control unit is specifically configured as follows:

[0227] During the previous read / write operation test, a write operation is performed on the other of any two adjacent storage arrays, so that during the current operation test, a read operation is performed on the other.

[0228] In one embodiment, the preset read and write mode includes: at least one of a preset operation mode and a preset write operation mode;

[0229] The preset read operation mode is used to select the word line or bit line to be turned on and the length of the read data;

[0230] The preset write operation mode is used to select whether to open a word line or a bit line and the length of the written data.

[0231] In one embodiment, the preset read and write mode includes reading and writing the test memory array according to a preset test pattern;

[0232] The memory testing device 900 further includes a pattern acquisition module.

[0233] A pattern acquisition module, configured to acquire a preset test pattern corresponding to the test storage array;

[0234] Accordingly, the read / write module is specifically configured as follows:

[0235] The test memory array is read and written according to a preset test pattern using a control signal sequence generated in real time.

[0236] In one embodiment, the preset test pattern includes a checkerboard pattern, a stripe pattern, or a diagonal pattern.

[0237] In one embodiment, the memory testing device 900 further includes a duration selection module.

[0238] The duration selection module is used to select the test pre-charging duration corresponding to the current read and write operation test within the pre-charging duration range specified by the preset specification protocol according to the preset time generation method.

[0239] In one embodiment, the memory testing device 900 further includes: a range determination module and a read / write control module.

[0240] a range determination module, configured to determine a target value range for the pre-charge duration based on the test results of at least one read and write operation test and the test pre-charge duration corresponding to the at least one read and write operation test, wherein the target value range is a pre-charge duration value range within which the actual pre-charge duration of the memory does not suffer from read and write anomalies caused by the standby mode;

[0241] The read / write control module is used to control the actual read and write operations of the memory according to the target value range.

[0242] It should be noted that Figure 9 The memory test apparatus 900 shown can perform Figures 4 to 8 The various steps in the method embodiment shown are implemented Figures 4 to 8 The various processes and effects in the illustrated method embodiment are not described in detail here.

[0243] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods, or program products. Therefore, various aspects of the present disclosure may be implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which may be collectively referred to herein as "circuits," "modules," or "systems."

[0244] Refer to the following Figure 10 1000 according to this embodiment of the present disclosure will be described. Figure 10 The electronic device 1000 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0245] like Figure 10 As shown, electronic device 1000 is implemented as a general-purpose computing device. Components of electronic device 1000 may include, but are not limited to, the aforementioned at least one processing unit 1010, the aforementioned at least one storage unit 1020, and a bus 1030 connecting various system components (including storage unit 1020 and processing unit 1010).

[0246] The storage unit stores program codes, which can be executed by the processing unit 1010, so that the processing unit 1010 executes the steps according to various exemplary embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0247] The storage unit 1020 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 10201 and / or a cache memory unit 10202 , and may further include a read-only memory unit (ROM) 10203 .

[0248] The storage unit 1020 may also include a program / utility 10204 having a set (at least one) of program modules 10205, such program modules 10205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0249] Bus 1030 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0250] The electronic device 1000 may also communicate with one or more external devices 1040 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 1000, and / or any device that enables the electronic device 1000 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication may be performed through an input / output (I / O) interface 1050.

[0251] Furthermore, the electronic device 1000 can also communicate with one or more networks (eg, a local area network (LAN), a wide area network (WAN) and / or a public network, such as the Internet) through the network adapter 1060 .

[0252] like Figure 10 As shown, the network adapter 1060 communicates with other modules of the electronic device 1000 via the bus 1030 .

[0253] It should be understood that although not shown in the figures, other hardware and / or software modules may be used in conjunction with the electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0254] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0255] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is further provided. The computer-readable storage medium may be a readable signal medium or a readable storage medium. Figure 11 A schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure is shown. Figure 11 As shown, the computer-readable storage medium 1100 stores a program product capable of implementing the above-mentioned method of the present disclosure.

[0256] In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps described in the above "Exemplary Method" section of this specification according to various exemplary implementations of the present disclosure.

[0257] More specific examples of computer-readable storage media in the present disclosure may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0258] In the present disclosure, a computer-readable storage medium may include a data signal transmitted in baseband or as part of a carrier wave, wherein the computer-readable program code is carried. Such a transmitted data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0259] A readable signal medium may also be any readable medium other than a readable storage medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0260] In some examples, program code embodied on a computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0261] In a specific implementation, the program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0262] Where a remote computing device is involved, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0263] The present disclosure provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the memory testing method provided in any of the various optional embodiments of the present disclosure.

[0264] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0265] Furthermore, although the steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0266] Through the description of the above embodiments, those skilled in the art will readily understand that the example embodiments described herein may be implemented by software, or by combining software with necessary hardware.

[0267] Therefore, the technical solution according to the embodiment of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiment of the present disclosure.

[0268] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein.

[0269] This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A memory testing method, characterized in that: The method comprises: Perform at least one read and write operation test on the test storage array in the memory, wherein each read and write function test corresponds to a test precharge duration. In each read and write operation test, the following steps are performed: Obtaining a read / write timing diagram corresponding to the current read / write operation test, wherein the read / write timing diagram is a timing diagram of a control signal sequence corresponding to the current read / write operation, the control signal sequence including a pulse signal corresponding to each stage in the current read / write test, the pulse signal in each stage being used to instruct the test memory array to enter that stage, and the actual pre-charge duration of the pre-charge stage in each stage being the test pre-charge duration corresponding to the current read / write operation test; According to the read / write timing diagram and the preset abnormality judgment condition, the test result of this read / write operation test is determined, and the test result is used to indicate whether the memory has a read / write abnormality caused by the standby mode during the test pre-charging time.

2. The method according to claim 1, characterized in that The abnormality determination condition includes the presence of an interference signal in the read / write timing diagram, The step of determining the test result of the read / write operation test according to the read / write timing diagram and the preset abnormality determination condition includes: When there is an interference signal in the read / write timing diagram, the test result of this read / write operation test is determined to be the first test result, and the first test result is used to characterize the read / write anomaly of the memory caused by the standby mode during the test pre-charging time.

3. The method according to claim 2, characterized in that The stages include activation stage, read / write stage and pre-charge stage. When an interference signal exists in the read / write timing diagram, determining that a test result of the current read / write operation test is a first test result includes: When an interference signal exists in a timing segment of at least one of the activation phase, the read / write phase, and the precharge phase, the test result of the current read / write operation test is determined to be a first test result.

4. The method according to claim 1, wherein Before obtaining the read / write timing diagram corresponding to the current read / write operation test, the method further includes: Obtaining the control signal sequence corresponding to the current read and write operation test generated in real time; The test storage array is read and written in a preset read and write manner using a control signal sequence generated in real time, so as to simulate the influence of an actual read and write process on the read and write timing diagram.

5. The method according to claim 4, characterized in that The test memory array includes multiple memory arrays of the memory, the control signal sequence includes a control signal sequence for each memory array, and the preset read and write mode includes controlling at least one memory array of the multiple memory arrays to perform a write operation and controlling other memory arrays except the at least one memory array to perform a read operation; The method of using the real-time generated control signal sequence to read and write the test storage array in a preset read and write manner to simulate the influence of the actual read and write process on the read and write timing diagram includes: The control signal sequences of the plurality of storage arrays are used to control at least one storage array to perform a write operation and to control the other storage arrays to perform a read operation.

6. The method according to claim 5, characterized in that The preset read / write mode includes controlling one of any two adjacent storage arrays in the plurality of storage arrays to perform a write operation and controlling the other of the any two adjacent storage arrays to perform a read operation; The controlling the at least one storage array to perform a write operation and the controlling the other storage arrays to perform a read operation by using respective control signal sequences of the plurality of storage arrays comprises: For one of the two adjacent storage arrays, performing a write operation on the one using a control signal sequence of the one generated in real time; And, for the other one of the any two adjacent storage arrays, a read operation is performed on the other one using a control signal sequence of the other one generated in real time.

7. The method according to claim 6, characterized in that Before performing a read operation on the other of the two adjacent storage arrays using the control signal sequence of the other generated in real time, the method further includes: During the previous read / write operation test, a write operation is performed on the other of the two adjacent storage arrays, so that during the current operation test, a read operation is performed on the other.

8. The method according to claim 4, characterized in that The preset read and write mode includes: at least one of a preset read operation mode and a preset write operation mode; The preset read operation mode is used to select the word line or bit line to be turned on and the length of the read data; The preset write operation mode is used to select the opening of a word line or a bit line and the length of the written data.

9. The method according to claim 4, characterized in that The preset reading and writing mode includes reading and writing the test storage array according to a preset test pattern; Before reading and writing the test storage array in a preset read and write manner using the control signal sequence generated in real time, the method further includes: Obtaining a preset test pattern corresponding to the test storage array; The method of using the control signal sequence generated in real time to test the storage array in a preset reading and writing mode includes: The control signal sequence generated in real time is used to read and write the test storage array according to the preset test pattern.

10. The method according to claim 9, characterized in that The preset test pattern includes: Checkerboard, striped, or diagonal patterns.

11. The method according to claim 1, wherein Before obtaining the read / write timing diagram corresponding to the current read / write operation test, the method further includes: According to the preset time generation method, the test pre-charging time corresponding to this read and write operation test is selected within the pre-charging time range specified by the preset specification protocol.

12. The method according to claim 1, characterized in that The method further comprises: Determining a target value range for the precharge duration based on the test results of the at least one read and write operation test and the test precharge duration corresponding to the at least one read and write operation test, wherein the target value range is a precharge duration value range within which an actual precharge duration of the memory does not cause a read or write anomaly caused by the standby mode; The actual read and write operations of the memory are controlled according to the target value range.

13. A memory testing device, characterized in that: include: The test module is used to perform at least one read and write operation test on the test storage array in the memory, wherein each read and write function test corresponds to a test precharge time. Wherein, the test module includes: a timing diagram acquisition unit, configured to acquire, during each read / write operation test, a read / write timing diagram corresponding to the current read / write operation test, wherein the read / write timing diagram is a timing diagram of a control signal sequence corresponding to the current read / write operation, the control signal sequence including a pulse signal corresponding to each stage in the current read / write test, the pulse signal in each stage being used to instruct the test memory array to enter that stage, and the actual pre-charge duration of the pre-charge stage in each stage being the test pre-charge duration corresponding to the current read / write operation test; The test unit is used to determine the test result of the read and write operation test according to the read and write timing diagram and the preset abnormality judgment condition during each read and write operation test. The test result is used to characterize whether the memory has a read and write abnormality caused by the standby mode during the test pre-charging time.

14. An electronic device, characterized in that: include: processor; as well as a memory for storing executable instructions of the processor; The processor is configured to execute the memory testing method according to any one of claims 1 to 12 by executing the executable instructions.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the memory testing method according to any one of claims 1 to 12 is implemented.

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