Methods for testing flash memory modules and related system chips

Abstract

This invention provides a method for detecting flash memory modules and a related system-on-a-chip (SoC). The method reads data with a specific data format from the flash memory module and then decodes and verifies the data to determine multiple characteristic parameters and data page size of the flash memory module. Therefore, the SoC does not require one-time programmable memory or pin-bound components, thus reducing manufacturing costs.

Description

TECHNICAL FIELD

[0001] The present application relates to a flash memory. BACKGROUND

[0002] Due to its fast access speed and low manufacturing cost, flash memory has gradually become the mainstream storage device for embedded systems. However, since flash memory is still in the stage of vigorous development, flash memories from different manufacturers or different models can have different characteristic parameters, such as data page size, spare size, address cycle, error correction code (ECC) requirement, etc. These differences not only make different flash memories have different access methods, but also require different data formats. Therefore, in order to read the data stored on the flash memory, the system chip needs to obtain the correct characteristic parameters and data format through one-time programmable (OTP) memory or a strap pin, so as to correctly read the data stored on the flash memory.

[0003] Specifically, in the setting of a general flash memory and related system chip, the engineer first needs to correctly set the one-time programmable memory or the strap pin according to the characteristic parameters of the flash memory used, and then encapsulate the data into an appropriate format according to the ECC requirement and the spare size of the flash memory used, and then pre-write it into the flash memory. After booting, the system chip will operate the flash memory controller according to the information brought in by the strap pin to read the data on the flash memory. However, once a flash memory from a different manufacturer or a different model is replaced, the strap pin and the data format also need to be adjusted so that the system chip can correctly read the data on the flash memory, thereby increasing the complexity of the setting of the flash memory and the related system chip. SUMMARY

[0004] Therefore, one of the purposes of the present application is to provide a method for detecting the characteristic parameters of a flash memory, which can obtain the characteristic parameters of the flash memory by reading the flash memory and analyzing its content without the need of one-time writing memory or strap pin, so as to solve the problems in the prior art.

[0005] In one embodiment of the present application, a method for detecting a flash memory module is provided, comprising the steps of: (a) selecting one of a plurality of combinations of characteristic parameters to set a flash memory controller; (b) using the flash memory controller to read a P-byte data from the flash memory module according to a column address and a row address, wherein the P-byte data comprises data of a data interval, a volume tag interval and an error correction code interval of a data page of a block in the flash memory module; (c) decoding the P-byte data, if decoding fails, adjusting the column address and returning to step (b) to read a next P-byte data from the flash memory module; (d) if decoding the P-byte data succeeds, checking whether the decoded data of step (c) is correct according to a check code in the volume tag interval, if the checking is correct, adjusting the row address and returning to step (b) to read a next P-byte data from the flash memory module; and (e) if the checking in step (d) fails, determining a plurality of characteristic parameters of the flash memory module according to the currently used combination of characteristic parameters and the current row address.

[0006] In another embodiment of the present application, a system chip is disclosed, comprising a central processing unit to execute a program code to perform the following operations: (a) selecting one of a plurality of combinations of characteristic parameters to set a flash memory controller; (b) using the flash memory controller to read a P-byte data from the flash memory module according to a column address and a row address, wherein the P-byte data comprises data of a data interval, a volume tag interval and an error correction code interval of a data page of a block in the flash memory module; (c) decoding the P-byte data, if decoding fails, adjusting the column address and returning to step (b) to read a next P-byte data from the flash memory module; (d) if decoding the P-byte data succeeds, checking whether the decoded data of step (c) is correct according to a check code in the volume tag interval, if the checking is correct, adjusting the row address and returning to step (b) to read a next P-byte data from the flash memory module; and (e) if the checking in step (d) fails, determining a plurality of characteristic parameters of the flash memory module according to the currently used combination of characteristic parameters and the current row address. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A schematic diagram of a system chip and a flash memory module according to an embodiment of the present application.

[0008] Figure 2 A schematic diagram of an architecture of a flash memory module.

[0009] Figure 3 A schematic diagram of a data format written to a flash memory module.

[0010] Figure 4A flowchart of determining characteristic parameters of a flash memory module according to an embodiment of the present application. DETAILED DESCRIPTION

[0011] Figure 1 A schematic diagram of a system on chip (SoC) 110 and a flash memory module 120 according to an embodiment of the present application. As shown, the SoC 110 includes a central processing unit (CPU) 112, a flash memory controller 114, and a read only memory (ROM) 116, wherein the ROM 116 includes a program code 118. In this embodiment, the SoC 110 and the flash memory module 120 can be disposed in any electronic device, such as a network switch or the like. Figure 1

[0012] A schematic diagram of the flash memory module 120. As shown, the flash memory module 120 includes at least one flash memory chip (in this embodiment, flash memory chips 210_1, 210_2 are shown), and each flash memory chip includes a plurality of blocks 220_1-220_K, wherein each block is a minimum erasing unit, i.e., data in a block needs to be erased together and cannot be partially erased. In addition, each block includes a plurality of pages P1-PN, wherein each page is a minimum writing unit. Figure 2 Figure 2

[0013] ​​In this embodiment, some data are pre-written in the flash memory module 120 for the system chip 110 to read after power-up to perform related operations. For example, the data required by the system chip 110 can be pre-written in the flash memory module 120 at the factory before the flash memory module 120 is linked with the system chip 110, and then when the system chip 110 and the flash memory module 120 are set in an electronic device, the system chip 110 can read the flash memory module 120 to perform related operations. However, as described in the prior art, because the flash memory module 120 can have different characteristic parameters, such as data page size, spare area size, address cycle, error correction code requirement, etc., due to different manufacturers or different models, the prior art needs to set the correct characteristic parameters and data format through a one-time write memory or a binding pin in the system chip to correctly set the flash memory controller 114, but this increases the design complexity of the system chip. To solve this problem, the system chip 110 of this embodiment does not need the one-time write memory or the binding pin described above, but designs an algorithm in the program code 118 that can actively detect the characteristic parameters of the flash memory module 120, which can accurately and quickly detect at least part of the characteristic parameters of the flash memory module 120 when the system chip 110 is powered on for the first time, to set the flash memory controller 114 to perform subsequent operations of accessing the flash memory module 120.

[0014] Specifically, the flash memory module 120 can use a fixed data format to write data when pre-writing data at the factory. Referring to Figure 3As shown, the data to be written into the flash module 120 can be divided into a plurality of data intervals, each of which has a size of D bytes; for each group of data intervals, a tag interval with a length of T bytes is added, wherein the content of the tag interval can include the serial number of the corresponding data interval and a related check code, which can be a cyclic redundancy check (CRC) code of the corresponding data interval. In addition, for each group of data intervals and the successive tag interval, an error correction code (ECC) interval with a length of E bytes is added, which is used to correct errors in the data intervals and the tag interval. In an embodiment, since the data page sizes of flash modules 120 of different manufacturers or different models usually have a multiple relationship, it is assumed that the data page sizes of flash modules 120 of different manufacturers or different models are 512 bytes, 1024 bytes, and 2048 bytes, and the sum of the data sizes of the above-mentioned data intervals, tag intervals, and ECC intervals is designed to be the greatest common divisor P of the data page sizes of flash modules 120 of different manufacturers or different models, i.e., P = D + T + E, but the present application is not limited thereto. In an embodiment, P can be 512 bytes.

[0015] Next, when the system chip 110 and the flash module 120 are arranged in an electronic device, and the electronic device is powered on, the central processing unit 112 reads the program code 118 from the read-only memory 116 and executes the program code 118 to perform the operations shown in FIG. 2 to detect the characteristic parameters of the flash module 120. Figure 4 In the following description, it is assumed that the number of data pages included in each block of flash modules 120 of different manufacturers or different models has a greatest common divisor Pnum, the number of reference columns Rmax corresponding to the number of bad blocks allowed by the flash module 120, and a part of the set of to-be-detected characteristic parameters is R, wherein R includes a plurality of subsets r1, r2, …, and each subset is a combination of characteristic parameters, but the combination of characteristic parameters does not include the size of the data page. The reference column Rmax is determined according to the following equation: Figure 4the flowchart, at step 400, the flowchart begins and the central processing unit 112 starts executing the program code 118. At step 402, the central processing unit 112 determines whether the set of characteristic parameters R still contains a subset that has not been tested, if yes, the flowchart proceeds to step 404; if no, the flowchart proceeds to step 430 and determines that the system chip 110 does not support the flash memory module 120, and ends the flowchart. At step 404, the central processing unit 112 selects a subset r from the set of characteristic parameters R that has not been tested, and uses the characteristic parameters in the subset r to configure the flash memory controller 114. At step 408, the flash memory controller 114 selects a set of memory addresses R_addr and C_addr, where R_addr is a row address representing a column of data pages, and different column addresses represent different data pages, and C_addr is a column address. Initially, the column address R_addr and the column address C_addr are both 0, i.e., the flash memory controller 114 selects the starting address of the first data page in the first block of the flash memory module 120.

[0016] At step 410, the central processing unit 112 determines whether the column address R_addr is less than the reference column number Rmax, if yes, the flowchart proceeds to step 412; if no, the flowchart proceeds to step 402.

[0017] At step 412, the flash memory controller 114 reads P bytes of data from the flash memory module 120 starting from the column address R_addr and the column address C_addr, where the P bytes of data read includes Figure 3 the data interval, the volume tag interval, and the ECC interval. At step 414, the central processing unit 112 or the flash memory controller 114 performs a decoding operation on the data interval, the volume tag interval, and the ECC interval, i.e., uses the ECC interval to correct errors in the data interval and the volume tag interval. At step 416, the central processing unit 112 or the flash memory controller 114 determines whether the decoding operation is successful, if yes, the flowchart proceeds to step 418; if no, the flowchart proceeds to step 426. The possible reasons for the decoding failure can be that the block is a bad block, the data read encounters a certain boundary (e.g., the end of a data page), or the characteristic parameters in the subset r used to configure the flash memory controller 114 are not suitable for the flash memory module 120.

[0018] At step 418, the central processing unit 112 determines whether the data decoded at step 414 is correct according to the check code in the volume tag interval, e.g., performs a cyclic redundancy check operation on the data decoded at step 414 to generate a calculation result, and determines whether the calculation result is consistent with the check code in the volume tag interval to determine whether the check is successful, if yes, the flowchart proceeds to step 422; if no, the flowchart proceeds to step 426.

[0019] In step 422, the central processing unit 112 adds the row address C_addr to the address offset of P bytes, and the process returns to step 412 to read P bytes of data from the flash memory module 120 starting with the column address R_addr and the row address (C_addr+P), that is, to read... Figure 3 The second data range, label range, and ECC range are shown.

[0020] In step 424, the central processing unit 112 determines that the block currently being read may be a bad block, meaning that some of the data in it has been corrupted. Therefore, in order to avoid wasting too much time reading the bad block content, the flash memory controller 114 adds Pnum to the column address R_addr and sets the row address C_addr to 0, and the process returns to step 408, that is, the flash memory controller 114 starts reading P bytes of data from the flash memory module 120 with the column address (R_addr+Pnum) and the row address C_addr.

[0021] In step 426, the flash memory controller 114 determines whether the row address C_addr is not equal to 0. If yes, the process proceeds to step 428; if no, since the content of the data page read at the beginning was incorrect, it can be determined that the currently read block may be a bad block, and the process proceeds to step 424. In step 428, since the row address C_addr is not equal to 0, it means that the read data may have encountered some boundary, such as the end of the data page. The main reason is that the previously read P bytes could be successfully verified by the checksum in the volume label interval, but the current data cannot be successfully verified by the checksum in the volume label interval. Therefore, it can be determined that the current row address C_addr is the size of the data page, and at this time, the characteristic parameters in the subset r used to set the flash memory controller 114 can be applied to the flash memory module 120.

[0022] As mentioned above, in Figure 4 In the process shown, by using different subsets r and the relevant data page size determination mechanism, at least some characteristic parameters of the flash memory module 120 can be accurately and quickly detected when the system chip 110 is powered on for the first time without the need for one-time programmable memory or pin binding, thereby reducing the design and manufacturing cost of the system chip 110.

[0023] In one embodiment, Figure 4 The process only needs to be executed when the system chip 110 is powered on for the first time. After the characteristic parameters of the flash memory module 120 are determined, the flash memory controller 114 can use these characteristic parameters to set them for subsequent access to the flash memory module 120.

[0024] It should be noted that,Figure 4 The values of Pnum and Rmax are merely illustrative and not limiting to the present application. In particular, the purpose of using Pnum in step 424 to adjust the column address R_addr is to avoid the flash controller 114 to read the contents in the bad block multiple times, and the purpose of using Rmax in step 410 is to avoid the flash controller 114 to continuously use the inappropriate subset of characteristic parameters to read the flash memory module 120. Therefore, since Pnum and Rmax are used to speed up the algorithm performance, they can be arbitrarily set by the designer.

[0025] Briefly summarized Figure 4 The method for detecting the flash memory module 120 can sequentially include the following steps: (a) selecting one of a plurality of characteristic parameter combinations to set a flash controller; (b) using the flash controller to read a P-byte data from the flash memory module according to a column address and a row address, wherein the P-byte data includes data of a data interval, a volume label interval and an error correction code interval of a data page in a block of the flash memory module; (c) decoding the P-byte data, if the decoding fails, adjusting the column address and returning to step (b) to read a next P-byte data from the flash memory module; (d) if the decoding of the P-byte data succeeds, checking whether the decoded data of step (c) is correct according to a check code in the volume label interval, if the checking is correct, adjusting the row address and returning to step (b) to read a next P-byte data from the flash memory module; and (e) if the checking in step (d) fails, judging whether the current row address is a start address of the data page; if the row address is the start address of the data page, adjusting the column address and returning to step (b) to read a next P-byte data from the flash memory module; and if the row address is not the start address of the data page, judging that the currently used characteristic parameter combination is the plurality of characteristic parameters of the flash memory module, and judging that the current row address is the size of the data page.

[0026] The above descriptions are only the preferred embodiments of the present application, and any equivalent changes and modifications made within the scope of the present application should be covered by the present application.

[0027]

Symbolic Description

[0028] 110: system chip

[0029] 112: central processing unit

[0030] 114: flash controller

[0031] 116: read only memory

[0032] 118: program code

[0033] 120: flash memory module

[0034] 210_1, 210_2: flash memory chip

[0035] 220_1 ~ 220_K: block

[0036] P1 ~ PN: data page

[0037] 400 ~ 430: step

Claims

1. A method for detecting a flash memory module, comprising: (a) selecting one of a plurality of parameter sets to configure a flash memory controller; (b) using the flash memory controller to read a P-byte data from the flash memory module according to a column address and a row address, wherein the P-byte data includes data of a data interval, a volume tag interval and an error correction code interval of a data page of a block in the flash memory module; (c) decoding the P-byte data, if the decoding fails, adjusting the column address and returning to step (b) to read a next P-byte data from the flash memory module; (d) if the decoding of the P-byte data succeeds, checking whether the decoded data of step (c) is correct according to a check code in the volume tag interval, if the checking is correct, adjusting the row address and returning to step (b) to read a next P-byte data from the flash memory module; and (e) if the checking of step (d) fails, determining a plurality of parameters of the flash memory module according to the parameter set currently used and the row address currently used.

2. The method of claim 1, wherein a size of the data page is a positive integer multiple of P bytes.

3. The method of claim 1, wherein the volume tag interval includes a cyclic redundancy check code of data of the data interval, and the error correction code interval includes an error correction code used for decoding operation of data in the data interval and the volume tag interval.

4. The method of claim 1, wherein step (e) includes: (e1) if the checking of step (d) fails, determining whether the row address currently used is a start address of the data page; (e2) if the row address is the start address of the data page, adjusting the column address and returning to step (b) to read a next P-byte data from the flash memory module; and (e3) if the row address is not the start address of the data page, determining that the parameter set currently used is the plurality of parameters of the flash memory module, and determining that the row address currently used is the size of the data page.

5. The method of claim 1, wherein step (c) includes: (c1) decoding the P-byte data, if the decoding fails, determining whether the row address currently used is a start address of the data page; (c2) if the row address is the start address of the data page, adjusting the column address and returning to step (b) to read a next P-byte data from the flash memory module; and (c3) if the row address is not the start address of the data page, determining that the parameter set currently used is the plurality of parameters of the flash memory module, and determining that the row address currently used is the size of the data page.

6. The method of claim 1, wherein step (c) includes: decoding the P-byte data, if decoding fails, adjusting the column address to correspond to another data page different from the data page, setting the row address as a start address of the another data page, and returning to step (b) to read a next P-byte data from the flash memory module.

7. The method of claim 1, further comprising: determining whether the column address in step (b) is greater than a reference column number; if the column address in step (b) is greater than the reference column number, returning to step (a) and selecting another characteristic parameter combination from the plurality of characteristic parameter combinations to set the flash memory controller; and if the column address in step (b) is not greater than the reference column number, using the flash memory controller to read the P-byte data from the flash memory module according to the column address and the row address.

8. A system chip, comprising: a central processing unit to execute a program code to: (a) select a characteristic parameter combination from a plurality of characteristic parameter combinations to set a flash memory controller; (b) use the flash memory controller to read a P-byte data from a flash memory module according to a column address and a row address, wherein the P-byte data includes data of a data interval, a volume tag interval, and an error correction code interval of a data page of a block in the flash memory module; (c) decode the P-byte data, if decoding fails, adjust the column address and return to step (b) to read a next P-byte data from the flash memory module; (d) if decoding the P-byte data succeeds, verify whether the decoded data in step (c) is correct according to a check code in the volume tag interval, if the verification is correct, adjust the row address and return to step (b) to read a next P-byte data from the flash memory module; and (e) if the verification in step (d) fails, determine a plurality of characteristic parameters of the flash memory module according to a currently used characteristic parameter combination and the row address.

9. The system chip of claim 8, wherein the volume tag interval includes a cyclic redundancy check code of data of the data interval, and the error correction code interval includes an error correction code used to decode data in the data interval and the volume tag interval.

10. The system chip of claim 8, wherein step (e) comprises: (e1) if the verification in step (d) fails, determining whether the row address is a start address of the data page; (e2) if the row address is the start address of the data page, adjusting the column address and returning to step (b) to read a next P-byte data from the flash memory module; and (e3) if the row address is not the start address of the data page, determining that the currently used characteristic parameter combination is the plurality of characteristic parameters of the flash memory module, and determining that the row address is a size of the data page. ​

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