Method, device, equipment and storage medium for determining chip position in power module

Abstract

The present invention relates to a method, device, equipment and storage medium for determining the position of a chip in a power module. The method comprises: obtaining wafer test data of a plurality of chips, the wafer test data comprising at least one electrical performance parameter corresponding to each of the chips; obtaining a thermal simulation result of a packaging module, the thermal simulation result comprising a temperature value corresponding to each of a plurality of mounting positions, the mounting position being a position for mounting the chip in the packaging module, the packaging module being used to package a plurality of the chips to form a power module; and determining the correspondence between the chip and the mounting position according to the wafer test data and the thermal simulation result. The method, device, equipment and storage medium for determining the position of a chip in a power module provided by the present invention can reduce the temperature difference of the chips in the packaging module, improve the electrical performance of the power module, and have low cost.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and in particular to a method, device, equipment and storage medium for determining a chip position in a power module. Background Art

[0002] For the packaging of multi-chip power modules in parallel, high consistency requirements are placed on the parallel chips, especially for automotive applications. If the consistency of the parallel chips in the power module is poor, it may cause a large temperature difference between the chips in the power module, resulting in thermal runaway, which will affect the electrical output waveform and reliability life. However, the existing technology often directly mixes the chips on the wafer indiscriminately in the power module without considering the consistency of each chip. Once the consistency is poor, it is easy for a single chip to bear the entire current at the moment of switching, and it is also easy to cause uneven temperature distribution of the chip, affecting the life of the chip and module.

[0003] In order to overcome the above problems, the related technology proposes a method of packaging chips in single-parameter bins through a known good die (KGD) machine, and then using each bin to package them into power modules separately. However, KGD machines are not commonly used by chip packaging manufacturers and have high usage costs. In addition, when using a single parameter for binning packaging, there are certain accidental errors in the accuracy of binning; for multiple chips in each bin, directly packaging them into the power module reduces the problem of chip consistency within the bin, but there is still room for optimization in how to arrange the chips in the power module.

[0004] It can be seen that how to better solve the problem of temperature difference between chips in a power module during the packaging process of the power module has always been an important topic that technical personnel in this field have devoted themselves to studying. Summary of the invention

[0005] In view of this, embodiments of the present application provide a method, device, equipment and storage medium for determining a chip position in a power module to solve at least one problem existing in the background technology.

[0006] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0007] In a first aspect, an embodiment of the present application provides a method for determining a chip position in a power module, the method comprising:

[0008] Acquire wafer test data of a plurality of chips, wherein the wafer test data includes at least one electrical performance parameter corresponding to each of the chips;

[0009] Obtaining a thermal simulation result of the packaging module, wherein the thermal simulation result includes a temperature value corresponding to each of a plurality of mounting positions, wherein the mounting position is a position in the packaging module for mounting the chip, and the packaging module is used to package the plurality of chips to form a power module;

[0010] The corresponding relationship between the chip and the mounting position is determined according to the wafer test data and the thermal simulation result.

[0011] Optionally, before determining the correspondence between the chip and the installation position, the method further includes:

[0012] According to at least one electrical performance parameter of each chip in the wafer test data, sorting the chips according to a first preset rule;

[0013] The plurality of installation positions are sorted according to the temperature values ​​corresponding to the installation positions in the thermal simulation results.

[0014] Optionally, the sorting of the chips according to a first preset rule based on at least one electrical performance parameter of each chip in the wafer test data includes:

[0015] According to the values ​​of at least two electrical performance parameters in the wafer test data that respectively characterize at least two different performances of the chip, the chips are batched and sorted according to the quality of the chip performance.

[0016] Optionally, the at least two electrical performance parameters include a first electrical performance parameter for characterizing the quality of a first preset performance of the chip and a second electrical performance parameter for characterizing the quality of a second preset performance of the chip;

[0017] The step of batching and sorting the chips according to the performance of the chips based on the values ​​of at least two electrical performance parameters in the wafer test data that respectively characterize at least two different performances of the chips includes:

[0018] According to the first electrical performance parameter, dividing the chips into multiple batches;

[0019] The chips are sorted according to the following sorting rules:

[0020] The chips in the same batch are sorted in descending order according to the second preset performance, and the chips between the batches are sorted in descending order according to the first preset performance.

[0021] Optionally, determining the correspondence between the chip and the installation position according to the wafer test data and the thermal simulation result includes:

[0022] According to the number of mounting positions in the packaging module, the sorted chips are divided into a plurality of chip groups in order, and the number of chips in each chip group is the same as the number of mounting positions in each packaging module;

[0023] According to the third electrical performance parameter in the wafer test data characterizing the quality of the third preset performance of the chip, the chips in each of the chipsets are sorted in descending order according to the third preset performance;

[0024] The chips in the sorted chipset and the sorted installation positions are respectively and sequentially determined in their respective orders to determine the corresponding relationship between the chips and the installation positions.

[0025] Optionally, the method further includes:

[0026] A first position of the chip in the wafer is associated with a second position of the chip corresponding to a mounting position in the packaging module, and the associations are stored in a file of a preset format.

[0027] Optionally, before sorting the chips according to a first preset rule based on at least one electrical performance parameter of each chip in the wafer test data, the method further comprises: determining the chips that meet preset requirements based on the wafer test data and the value of the at least one electrical performance parameter;

[0028] The sorting of the chips according to a first preset rule includes: sorting the chips meeting the preset requirements according to the first preset rule.

[0029] In a second aspect, an embodiment of the present application provides a device for determining a chip position in a power module, the device comprising:

[0030] A first acquisition unit, configured to acquire wafer test data of a plurality of chips, wherein the wafer test data includes at least one electrical performance parameter corresponding to each of the chips;

[0031] A second acquisition unit is used to acquire a thermal simulation result of the packaging module, wherein the thermal simulation result includes a temperature value corresponding to each of a plurality of mounting positions, wherein the mounting position is a position in the packaging module for mounting the chip, and the packaging module is used to package a plurality of the chips to form a power module;

[0032] A determination unit is used to determine the corresponding relationship between the chip and the installation position according to the wafer test data and the thermal simulation result.

[0033] In a third aspect, an embodiment of the present application provides a computing device, the computing device comprising: a memory, a communication bus, and a processor, wherein:

[0034] The memory is used to store a method program for determining the position of a chip in a power module;

[0035] The communication bus is used to realize the connection and communication between the memory and the processor;

[0036] The processor is used to execute the method program for determining the chip position in the power module to implement the steps of any one of the methods described above.

[0037] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which an executable program is stored, and when the executable program is executed by a processor, the steps of any one of the methods described above are implemented.

[0038] The method, device, equipment and storage medium for determining the position of a chip in a power module provided in the embodiment of the present application include: obtaining wafer test data of multiple chips; obtaining thermal simulation results of a packaging module; determining the corresponding relationship between the chip and the installation position according to the wafer test data and the thermal simulation results. Among them, obtaining wafer test data not only saves the use fee of an additional KGD machine, but also can obtain the parameter value of at least one electrical performance parameter that affects the operating temperature of the chip through the wafer test data; through the thermal simulation results, the heat dissipation condition of the installation position in the packaging module and other factors that affect the operating temperature of the chip can be obtained. Combining the above two takes into account both electrical balance and thermal balance, which is conducive to reducing the temperature difference of the chip in the packaging module and improving the electrical performance of the power module. Compared with the method of using a KGD machine, this scheme not only reduces the cost, but also optimizes the arrangement of each chip in the power module. In this way, the method, device, equipment and storage medium for determining the position of a chip in a power module provided in the embodiment of the present application are conducive to reducing the temperature difference of the chip in the packaging module, improving the electrical performance of the power module, and the cost is low.

[0039] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0041] Figure 1 A schematic diagram of a flow chart of a method for determining a chip position in a power module provided in an embodiment of the present application;

[0042] Figure 2A schematic diagram of a specific process of a method for determining a chip position in a power module provided in an embodiment of the present application;

[0043] Figure 3 A schematic diagram of the structure of a device for determining a chip position in a power module provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of a computing device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0045] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0046] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0047] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0048] In view of the technical problems in the related art, the embodiment of the present application provides a method for determining the position of a chip in a power module, which can be implemented by a computing device, such as a computer, which can be a server or a client, wherein the server can be a local server or a cloud server. Figure 1 As shown, the method includes:

[0049] Step 101: Acquire wafer test data of a plurality of chips, wherein the wafer test data includes at least one electrical performance parameter corresponding to each of the chips;

[0050] Step 102: Obtain thermal simulation results of the packaging module, the thermal simulation results including a temperature value corresponding to each of a plurality of installation positions, the installation position being a position in the packaging module for installing the chip, and the packaging module being used to package a plurality of the chips to form a power module.

[0051] Step 103: Determine the correspondence between the chip and the installation position according to the wafer test data and the thermal simulation result.

[0052] Exemplarily, in step 101, the chip may be a die or chip on a wafer. The wafer test data may be the test result of the intermediate test (CP, Chip Probing), which is used to detect the electrical performance and circuit function of each die. After the test is completed, the unqualified dies are removed and the qualified dies are packaged into the power module. The packaging step is implemented by a packaging machine, not a testing machine. After obtaining the wafer, the packaging machine can cut the wafer, and then use a robot to grab the chip for packaging. The robot uses the coordinates of the chip, for example (x i ,y j ) Identify the location of the chip and grab it accurately. Exemplarily, the wafer test data may include many parameters related to the electrical performance and circuit functions of the chip.

[0053] In this embodiment, taking a metal-oxide-semiconductor field-effect transistor (MOSFET) as an example, the threshold voltage (V th , Threshold Voltage), DS conduction equivalent resistance (R dson ), saturation drain-source current (I DSS , Zero Gate Voltage Drain Current) and other electrical performance parameters mainly related to the operating temperature of the chip. The electrical performance parameters of each chip may be different, or even very different, which may cause the operating temperatures of each chip to be different. Therefore, there will be a large temperature difference between chips, and thermal runaway and other situations that affect the electrical performance of the power module. It can be understood that the above-mentioned electrical performance parameters also affect other performance of the chip and other performance of the power module. It can be understood that other electrical performance parameters can also be obtained to improve other performance of the power module. It can be understood that for chips other than MOSFET, other electrical performance parameters can be obtained to control the temperature difference between chips.

[0054] Exemplarily, in step 102, the thermal simulation result refers to the result of a virtual experiment simulating the actual working condition of the packaging module. Thermal simulation can also be called a thermal simulation experiment. Thermal simulation calculates the heat dissipation condition of the product under different operating scenarios by inputting a series of information data, and obtains the operating temperature of the chip at each installation position according to the heat dissipation condition, and then obtains the heat dissipation condition of each installation position. Furthermore, if the simulation results show that the heat dissipation condition of one or several installation positions is particularly poor, the heat dissipation scheme or power module structure can also be improved, thereby saving research and development time and proofing costs. The embodiments of the present application do not involve improving the heat dissipation scheme or power module structure and will not be repeated. Exemplarily, in addition to reflecting the heat dissipation condition of each installation position, the thermal simulation results can also reflect other conditions such as the structure or circuit of the packaging module. For example, the resistance of the circuit between the installation position and the input power supply can also affect the operating temperature of the chip.

[0055] Exemplarily, in step 103, the corresponding relationship between the chip and the installation position can be determined based on the wafer test data obtained in step 101 and the thermal simulation result obtained in step 102. For example, a chip with a high parameter value among the electrical performance parameters that affect the operating temperature is arranged at an installation position with good heat dissipation in the packaging module, and a chip with a low parameter value among the electrical performance parameters that affect the operating temperature is arranged at an installation position with poor heat dissipation in the packaging module. dson It is an electrical performance parameter that mainly affects the operating temperature of the chip. dson The chip with a small parameter value is arranged at an installation position in the packaging module where the heat dissipation condition is poor. The determination of the correspondence between the chip and the installation position in this embodiment only determines the correspondence and does not involve actual packaging. The actual packaging process may be that after the packaging machine obtains the determined correspondence, it grabs the chip from the wafer according to the correspondence to the corresponding installation position of the packaging module and performs packaging.

[0056] The method for determining the chip position in the power module provided in the embodiment of the present application can obtain the parameter value of at least one electrical performance parameter that affects the chip operating temperature through the wafer test data; through the thermal simulation results, the factors affecting the chip operating temperature, such as the heat dissipation conditions of the installation position in the packaging module, can be known; combining the above two takes into account both electrical balance and thermal balance, which is beneficial to reducing the temperature difference of the chip in the packaging module and improving the electrical performance of the power module, and does not require the use of a KGD machine, so the cost is low.

[0057] Furthermore, the method for determining the position of a chip in a power module provided in the embodiment of the present application can also determine the corresponding relationship with the installation position in the power module through other electrical performance parameters that affect the working performance of the chip, so as to improve the performance of the power module. For example, by determining the corresponding relationship with the installation position in the power module through the electrical performance parameters that affect the chip conduction time, it is possible to avoid a single chip from bearing all the current at the moment of switching, thereby improving the reliability of the power module. For example, V th It is related to the conduction speed. In the same power module, the V th The smaller the difference, the higher the reliability of the power module. For the sake of clarity, the following description mainly introduces the method for determining the chip position in the power module of the embodiment of the present application by taking the example of reducing the temperature difference of the chip in the package module to improve the performance of the power module. It can be understood that the method for determining the chip position in the power module of the embodiment of the present application is also conducive to reducing other performance gaps of the chip in the package module, thereby improving the performance of the power module.

[0058] In some embodiments, in step 103, before determining the correspondence between the chip and the installation position, the method may further include:

[0059] According to at least one electrical performance parameter of each chip in the wafer test data, sorting the chips according to a first preset rule;

[0060] The plurality of installation positions are sorted according to the temperature values ​​corresponding to the installation positions in the thermal simulation results.

[0061] Exemplarily, the chips are sorted and the installation positions are sorted, and the corresponding relationship can be determined according to the sorted order, which makes the determination process simpler. For example, the corresponding relationship between the chip ranked first and the installation position ranked first is determined, and the corresponding relationship between the chip ranked second and the installation position ranked second is determined. Among them, the chip ranked first can be the chip with the best performance in the sorting, and the installation position ranked first can be the installation position with the highest temperature in the thermal simulation experiment. Generally speaking, the chip with the best performance in the sorting can be the chip with the lowest heat generation. Because when sorting, if only one electrical performance parameter is used, the electrical performance parameter generally selects the parameter that most affects the heat generation of the chip; if multiple electrical performance parameters are used, the parameter that most affects the heat generation of the chip can be used as the main basis.

[0062] In some embodiments, sorting the chips according to a first preset rule based on at least one electrical performance parameter of each chip in the wafer test data may include:

[0063] According to the values ​​of at least two electrical performance parameters in the wafer test data that respectively characterize at least two different performances of the chip, the chips are batched and sorted according to the quality of the chip performance.

[0064] Exemplarily, since there may be multiple electrical performance parameters that affect the operating temperature of the chip, at least two electrical performance parameters that respectively characterize at least two different performances of the chip are obtained from the wafer test data, and the chips are batched and sorted according to the at least two electrical performance parameters, which is conducive to better control of the temperature difference of the chip components in the packaging module, thereby facilitating the improvement of the performance of the packaging module. Exemplarily, although some electrical performance parameters do not directly affect the operating temperature of the chip, they may indirectly affect the operating temperature of the chip. Therefore, the chips are batched and sorted according to at least two electrical performance parameters. Even if there may be only one electrical performance parameter that directly affects the operating temperature of the chip, it is also conducive to better control of the temperature difference of the chip components in the packaging module.

[0065] Exemplarily, the quality of the chip performance refers to a direct relationship with the operating temperature of the chip. For example, if the chip performance is good, the operating temperature of the chip will be lower, otherwise, the operating temperature of the chip will be higher. The quality of chip performance is characterized by the parameter value of the electrical performance parameter. Exemplarily, the relationship between the quality of chip performance and the parameter value is sometimes a positive correlation, that is, the larger or smaller the parameter value, the better the performance of the chip. Some may not be a positive correlation, for example, when the parameter value is at a preset value, the performance of the chip is optimal, the parameter value is lower or higher than the parameter value, the performance of the chip is worse than the optimal, and the larger the value below or above, the worse the performance of the chip. Therefore, batching and sorting the chips in the order of the quality of the chip performance can better adapt to the installation position in the packaging module.

[0066] For example, the chips are divided into batches and sorted according to at least two electrical performance parameters, which may be divided into batches and sorted according to one electrical performance parameter, and then divided into sub-batches and sorted according to another electrical performance parameter within the divided batches, and so on. The chips may also be sorted once by combining parameter values ​​of multiple electrical performance parameters, wherein the multiple electrical performance parameters may be combined to give different electrical performance parameters the same weight or different weights.

[0067] In some embodiments, the at least two electrical performance parameters include a first electrical performance parameter for characterizing the quality of a first preset performance of the chip and a second electrical performance parameter for characterizing the quality of a second preset performance of the chip;

[0068] The step of batching and sorting the chips according to the performance of the chips based on the values ​​of at least two electrical performance parameters in the wafer test data that respectively characterize at least two different performances of the chips includes:

[0069] According to the first electrical performance parameter, the chips are divided into multiple batches; the chips are sorted according to the following sorting rules: the chips in the same batch are sorted in descending order according to the second preset performance, and the chips between the batches are sorted in descending order according to the first preset performance.

[0070] For example, the chips can be divided into M batches according to the first electrical performance parameter; wherein M is a positive integer greater than or equal to 2, and the serial number of each batch is represented by English letters such as A, B, etc.; then, the chips in each batch are sorted in the order of the second preset performance from best to worst according to the second electrical performance parameter, and there are n chips in each batch; finally, the batches are sorted in the order of the first preset performance from best to worst according to the first electrical performance parameter. In this way, all the chips are arranged in the same direction or in the same column, which facilitates the establishment of a corresponding relationship with the installation position of the packaging module later. The sorted chips are as follows:

[0071] A1, A2..., An, B1, B2...Bn...M1, M2...Mn.

[0072] For example, the above n is not a fixed value, because the number of chips in different batches may be different. Since in normal wafer processing, the electrical performance parameters of most chips conform to the normal distribution, this may result in a larger number of chips in batches with medium performance, and a smaller number of chips in batches with better or worse performance.

[0073] In some embodiments, M can be 2, which simplifies the sorting process and avoids the situation where the number of chips in some batches is small, so that the corresponding relationship with the installation position of the packaging module can be better established. When M is 2, the sorted chips are as follows:

[0074] A1, A2..., An, M1, M2...Mn.

[0075] In some embodiments, the first electrical performance parameter may be R dson , the second electrical performance parameter may be V th .

[0076] In some embodiments, determining the correspondence between the chip and the installation position according to the wafer test data and the thermal simulation result may include:

[0077] According to the number of mounting positions in the packaging module, the sorted chips are divided into a plurality of chip groups in order, and the number of chips in each chip group is the same as the number of mounting positions in each packaging module;

[0078] According to the third electrical performance parameter in the wafer test data characterizing the quality of the third preset performance of the chip, the chips in each of the chipsets are sorted in descending order according to the third preset performance;

[0079] The chips in the sorted chipset and the sorted installation positions are respectively and sequentially determined in their respective orders to determine the corresponding relationship between the chips and the installation positions.

[0080] Exemplarily, the chips after sorting may be sorted by one electrical performance parameter or by multiple electrical performance parameters, without limitation. Exemplarily, since the chips in the chipset are sorted and divided into the chipset, the parameter values ​​of one or more electrical performance parameters of the chips in the same chipset are relatively close, or the performance of the chips in the same chipset is relatively close, for example, the operating temperature may be relatively close. In this way, on the one hand, the performance difference between the chips in the chipset is small, so that the electrical performance of the power module is better. On the other hand, the number of chips in the chipset is consistent with the number of installation positions of the packaging module, which is also convenient for determining the correspondence between the chips and the installation positions.

[0081] For example, although the performance differences of the chips in the chipset are relatively small, the effects of various installation positions in the packaging module on the working state of the chips are different. Therefore, it is necessary to sort the chips in the chipset again in order from best to worst according to the third preset performance. In other words, the sorting of the chips before they are divided into the chipset is to make the performance of the chips in the chipset closer, and it may be that multiple performances are relatively close. The sorting of the chips after they are divided into the chipset is to make the chips more compatible with the installation position in the packaging module. The third preset performance is the performance of a chip related to the installation position in the packaging module. For example, the installation position in the packaging module is mainly due to large differences in heat dissipation conditions, then the third preset performance can be a performance that affects the operating temperature of the chip.

[0082] For example, the third electrical performance parameter may be the first electrical performance parameter, the second electrical performance parameter, etc. that appeared before, or a new electrical performance parameter that did not appear before. In some embodiments, the third electrical performance parameter is R dson , that is, the same as the first electrical performance parameter.

[0083] In some embodiments, the method may further include:

[0084] A first position of the chip in the wafer is associated with a second position of the chip corresponding to a mounting position in the packaging module, and the associations are stored in a file of a preset format.

[0085] Exemplarily, as mentioned above, since during the chip packaging process, the chip is grabbed from the wafer by the packaging machine through a robot. Therefore, associating the first position and the second position can facilitate the operation of the robot. For example, the robot obtains an instruction: put the chip in the xth installation position in the packaging module, then the robot can know from which position of the wafer to grab it through the above-mentioned association relationship. Or the robot obtains an instruction: grab the chip at the yth position on the wafer, then the robot can know from which installation position of the packaging module to put the grabbed chip through the above-mentioned association relationship. Exemplarily, the file in the preset format can be a file format that can be read by the packaging machine, for example, it can be a notepad format, that is, a file format with the suffix .Txt.

[0086] In some embodiments, before sorting the chips according to a first preset rule based on at least one electrical performance parameter of each chip in the wafer test data, the method may further include:

[0087] Determining the chip that meets the preset requirements according to the wafer test data and the value of the at least one electrical performance parameter;

[0088] The sorting of the chips according to a first preset rule includes: sorting the chips meeting the preset requirements according to the first preset rule.

[0089] For example, since the power module has high requirements for chips, before sorting the chips, it is necessary to determine the chips that meet the preset requirements according to the preset requirements of the electrical performance parameters, that is, remove some of the chips that do not meet the preset requirements.

[0090] In some embodiments, determining the chip that meets the preset requirements according to the wafer test data and the value of the at least one electrical performance parameter may include:

[0091] According to the wafer test data and the preset parameter value range of the electrical performance parameter, chips whose parameter values ​​do not conform to the preset parameter value range are removed, and the remaining chips are determined as chips that conform to the preset requirements.

[0092] Exemplarily, the preset parameter value range can be set according to the requirements of the power module, and the requirements of the power module can be determined according to the specific application industry. For example, the requirements for vehicle-mounted applications are relatively high, and the general preset parameter value range can be determined according to the Six Sigma principle.

[0093] Alternatively, multiple parameter values ​​of the same electrical performance parameter of the chip in the wafer test data are obtained, and based on the distribution of the multiple parameter values, chips with abnormal parameter value distribution are removed, and the remaining chips are determined as chips that meet preset requirements.

[0094] That is, not only the absolute value of the parameter value is examined, but also the distribution of multiple parameter values ​​is considered. Sometimes a relatively discrete distribution or an abnormal distribution form is also a defect. In some embodiments, the first-order difference method can be used to determine the abnormal distribution, and then remove chips with abnormal value distribution.

[0095] In order to more clearly understand the embodiments of the present application, more specific embodiments are given below for illustration: Figure 2 As shown, the method for determining the chip position in the power module may include the following steps: This method may be executed by an ordinary computer, and the computer may be an independent computer or a computer configured in a testing machine or a packaging machine.

[0096] Step 201: Start. In this embodiment, the method for determining the chip position in the power module is a program, and this step is to start executing the program.

[0097] Step 202: Initialize parameters. The initialized parameters may include: program intrinsic parameters, which are generally automatically loaded; algorithm parameters, such as which electrical performance parameters to use for step 204; product traceability parameters, such as wafer quantity, product model and batch number, which generally need to be manually entered.

[0098] Step 203: Acquire the test data of the test in progress. The test data of the test in progress can be read through the communication interface, and the computer of the method can read the file format output by the test equipment of the test in progress.

[0099] Step 204: Multi-factor screening and batching. There are actually two steps here. The first is screening, that is, based on the mid-test, further determining qualified chips, that is, removing some chips with unsatisfactory test data based on the test data. The second is batching. The batching method is described above.

[0100] Step 205: Obtaining the thermal simulation result of the packaging module, that is, obtaining the result of the thermal simulation experiment of the packaging module, which may include the operating temperature of the chip at each installation position in each virtual experiment.

[0101] Step 206: Sorting the chips in the chipset. That is, the chips are divided into batches based on step 204, and the chips after batching are divided into chipsets, and then the chips are sorted in the chipset. For specific steps, please refer to the above description.

[0102] Step 207: Output the file associated with the first position of the chip in the wafer and the second position of the chip in the packaging module. That is, the file associated with the first position and the second position is stored in a preset format and output so that the packaging machine can read it. In this embodiment, the preset format can be a notepad format, that is, a file format with a suffix of .txt.

[0103] Step 208: End. The program ends and stops running.

[0104] The present application also provides a device for determining the position of a chip in a power module. Figure 3 As shown, the device 300 includes: a first acquisition unit 301, a second acquisition unit 302 and a determination unit 303. Among them:

[0105] A first acquisition unit 301 is used to acquire wafer test data of a plurality of chips, wherein the wafer test data includes at least one electrical performance parameter corresponding to each of the chips;

[0106] A second acquisition unit 302 is used to acquire a thermal simulation result of the packaging module, wherein the thermal simulation result includes a temperature value corresponding to each of a plurality of mounting positions, wherein the mounting position is a position in the packaging module for mounting the chip, and the packaging module is used to package a plurality of the chips to form a power module;

[0107] The determination unit 303 is used to determine the correspondence between the chip and the installation position according to the wafer test data and the thermal simulation result.

[0108] In some embodiments, the determining unit 303 may also be used to:

[0109] According to at least one electrical performance parameter of each chip in the wafer test data, sorting the chips according to a first preset rule;

[0110] The plurality of installation positions are sorted according to the temperature values ​​corresponding to the installation positions in the thermal simulation results.

[0111] Exemplarily, the chips are sorted and the installation positions are sorted, and the corresponding relationship can be determined according to the sorted order, which makes the determination process simpler. For example, the corresponding relationship between the chip ranked first and the installation position ranked first is determined, and the corresponding relationship between the chip ranked second and the installation position ranked second is determined. Among them, the chip ranked first can be the chip with the best performance in the sorting, and the installation position ranked first can be the installation position with the highest temperature in the thermal simulation experiment. Generally speaking, the chip with the best performance in the sorting can be the chip with the lowest heat generation. Because when sorting, if only one electrical performance parameter is used, the electrical performance parameter generally selects the parameter that most affects the heat generation of the chip; if multiple electrical performance parameters are used, the parameter that most affects the heat generation of the chip can be used as the main basis.

[0112] In some embodiments, the determining unit 303 may also be used to:

[0113] According to the values ​​of at least two electrical performance parameters in the wafer test data that respectively characterize at least two different performances of the chip, the chips are batched and sorted according to the quality of the chip performance.

[0114] Exemplarily, since there may be multiple electrical performance parameters that affect the operating temperature of the chip, at least two electrical performance parameters that respectively characterize at least two different performances of the chip are obtained from the wafer test data, and the chips are batched and sorted according to the at least two electrical performance parameters, which is conducive to better control of the temperature difference of the chip components in the packaging module, thereby facilitating the improvement of the performance of the packaging module. Exemplarily, although some electrical performance parameters do not directly affect the operating temperature of the chip, they may indirectly affect the operating temperature of the chip. Therefore, the chips are batched and sorted according to at least two electrical performance parameters. Even if there may be only one electrical performance parameter that directly affects the operating temperature of the chip, it is also conducive to better control of the temperature difference of the chip components in the packaging module.

[0115] Exemplarily, the quality of the chip performance refers to a direct relationship with the operating temperature of the chip. For example, if the chip performance is good, the operating temperature of the chip will be lower, otherwise, the operating temperature of the chip will be higher. The quality of chip performance is characterized by the parameter value of the electrical performance parameter. Exemplarily, the relationship between the quality of chip performance and the parameter value is sometimes a positive correlation, that is, the larger or smaller the parameter value, the better the performance of the chip. Some may not be a positive correlation, for example, when the parameter value is at a preset value, the performance of the chip is optimal, the parameter value is lower or higher than the parameter value, the performance of the chip is worse than the optimal, and the larger the value below or above, the worse the performance of the chip. Therefore, batching and sorting the chips in the order of the quality of the chip performance can better adapt to the installation position in the packaging module.

[0116] For example, the chips are divided into batches and sorted according to at least two electrical performance parameters, which may be divided into batches and sorted according to one electrical performance parameter, and then divided into sub-batches and sorted according to another electrical performance parameter within the divided batches, and so on. The chips may also be sorted once by combining parameter values ​​of multiple electrical performance parameters, wherein the multiple electrical performance parameters may be combined to give different electrical performance parameters the same weight or different weights.

[0117] In some embodiments, the determining unit 303 may also be used to:

[0118] According to the first electrical performance parameter, the chips are divided into multiple batches; the chips are sorted according to the following sorting rules: the chips in the same batch are sorted in descending order according to the second preset performance, and the chips between the batches are sorted in descending order according to the first preset performance.

[0119] For example, the chips can be divided into M batches according to the first electrical performance parameter; wherein M is a positive integer greater than or equal to 2, and the serial number of each batch is represented by English letters such as A, B, etc.; then, the chips in each batch are sorted in the order of the second preset performance from best to worst according to the second electrical performance parameter, and there are n chips in each batch; finally, the batches are sorted in the order of the first preset performance from best to worst according to the first electrical performance parameter. In this way, all the chips are arranged in the same direction or in the same column, which facilitates the establishment of a corresponding relationship with the installation position of the packaging module later. The sorted chips are as follows:

[0120] A1, A2..., An, B1, B2...Bn...M1, M2...Mn.

[0121] For example, the above n is not a fixed value, because the number of chips in different batches may be different. Since in normal wafer processing, the electrical performance parameters of most chips conform to the normal distribution, this may result in a larger number of chips in batches with medium performance, and a smaller number of chips in batches with better or worse performance.

[0122] In some embodiments, M can be 2, which simplifies the sorting process and avoids the situation where the number of chips in some batches is small, so that the corresponding relationship with the installation position of the packaging module can be better established. When M is 2, the sorted chips are as follows:

[0123] A1, A2..., An, M1, M2...Mn.

[0124] In some embodiments, the first electrical performance parameter may be R dson , the second electrical performance parameter may be V th .

[0125] In some embodiments, the determining unit 303 may also be used to:

[0126] According to the number of mounting positions in the packaging module, the sorted chips are divided into a plurality of chip groups in order, and the number of chips in each chip group is the same as the number of mounting positions in each packaging module;

[0127] According to the third electrical performance parameter in the wafer test data characterizing the quality of the third preset performance of the chip, the chips in each of the chipsets are sorted in descending order according to the third preset performance;

[0128] The chips in the sorted chipset and the sorted installation positions are respectively and sequentially determined in their respective orders to determine the corresponding relationship between the chips and the installation positions.

[0129] Exemplarily, the chips after sorting may be sorted by one electrical performance parameter or by multiple electrical performance parameters, without limitation. Exemplarily, since the chips in the chipset are sorted and divided into the chipset, the parameter values ​​of one or more electrical performance parameters of the chips in the same chipset are relatively close, or the performance of the chips in the same chipset is relatively close, for example, the operating temperature may be relatively close. In this way, on the one hand, the performance difference between the chips in the chipset is small, so that the electrical performance of the power module is better. On the other hand, the number of chips in the chipset is consistent with the number of installation positions of the packaging module, which is also convenient for determining the correspondence between the chips and the installation positions.

[0130] For example, although the performance differences of the chips in the chipset are relatively small, the effects of various installation positions in the packaging module on the working state of the chips are different. Therefore, it is necessary to sort the chips in the chipset again in order from best to worst according to the third preset performance. In other words, the sorting of the chips before they are divided into the chipset is to make the performance of the chips in the chipset closer, and it may be that multiple performances are relatively close. The sorting of the chips after they are divided into the chipset is to make the chips more compatible with the installation position in the packaging module. The third preset performance is the performance of a chip related to the installation position in the packaging module. For example, the installation position in the packaging module is mainly due to large differences in heat dissipation conditions, then the third preset performance can be a performance that affects the operating temperature of the chip.

[0131] For example, the third electrical performance parameter may be the first electrical performance parameter, the second electrical performance parameter, etc. that appeared before, or a new electrical performance parameter that did not appear before. In some embodiments, the third electrical performance parameter is R dson , that is, the same as the first electrical performance parameter.

[0132] In some embodiments, the determining unit 303 may also be used to:

[0133] A first position of the chip in the wafer is associated with a second position of the chip corresponding to a mounting position in the packaging module, and the associations are stored in a file of a preset format.

[0134] Exemplarily, as mentioned above, since during the chip packaging process, the chip is grabbed from the wafer by the packaging machine through a robot. Therefore, associating the first position and the second position can facilitate the operation of the robot. For example, the robot obtains an instruction: put the chip in the xth installation position in the packaging module, then the robot can know from which position of the wafer to grab it through the above-mentioned association relationship. Or the robot obtains an instruction: grab the chip at the yth position on the wafer, then the robot can know from which installation position of the packaging module to put the grabbed chip through the above-mentioned association relationship. Exemplarily, the file in the preset format can be a file format that can be read by the packaging machine, for example, it can be a notepad format, that is, a file format with the suffix .Txt.

[0135] In some embodiments, the first acquisition unit 301 may also be used to:

[0136] Determining the chip that meets the preset requirements according to the wafer test data and the value of the at least one electrical performance parameter;

[0137] The sorting of the chips according to a first preset rule includes: sorting the chips meeting the preset requirements according to the first preset rule.

[0138] For example, since the power module has high requirements for chips, before sorting the chips, it is necessary to determine the chips that meet the preset requirements according to the preset requirements of the electrical performance parameters, that is, remove some of the chips that do not meet the preset requirements.

[0139] In some embodiments, the first acquisition unit 301 may also be used to:

[0140] According to the wafer test data and the preset parameter value range of the electrical performance parameter, chips whose parameter values ​​do not conform to the preset parameter value range are removed, and the remaining chips are determined as chips that conform to the preset requirements.

[0141] Exemplarily, the preset parameter value range can be set according to the requirements of the power module, and the requirements of the power module can be determined according to the specific application industry. For example, the requirements for vehicle-mounted applications are relatively high, and the general preset parameter value range can be determined according to the Six Sigma principle.

[0142] Alternatively, multiple parameter values ​​of the same electrical performance parameter of the chip in the wafer test data are obtained, and based on the distribution of the multiple parameter values, chips with abnormal parameter value distribution are removed, and the remaining chips are determined as chips that meet preset requirements.

[0143] That is, not only the absolute value of the parameter value is examined, but also the distribution of multiple parameter values ​​is considered. Sometimes a relatively discrete distribution or an abnormal distribution form is also a defect. In some embodiments, the first-order difference method can be used to determine the abnormal distribution, and then remove chips with abnormal value distribution.

[0144] The device 300 in the embodiment of the present invention may be a device disposed in a test device, or may be an independent device connected to and communicating with the test device.

[0145] In some embodiments, the device 300 of the embodiment of the present invention can be used to execute the method for determining the misalignment of the wafer test mapping image described in the above embodiments. Of course, it can also include a module for executing any process and / or step in the method for determining the misalignment of the wafer test mapping image described in the above embodiments. For the sake of brevity, it will not be repeated.

[0146] The description of the above device 300 embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device 300 of this embodiment, please refer to the description of the method embodiment of the present invention for understanding.

[0147] Each module included in the embodiment of the present invention can be implemented by a processor in a computing device; of course, it can also be implemented by a logic circuit in a computing device; in the implementation process, the processor can be a general-purpose processor, a digital signal processor (DSP), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a central processing unit (CPU), a microprocessor (MPU) or any other conventional processor.

[0148] The present application also provides a computing device, such as Figure 4 As shown, the computing device 400 includes: a memory 401, a communication bus 402 and a processor 403, wherein:

[0149] The memory 401 is used to store a method program for determining the position of a chip in a power module;

[0150] The communication bus 402 is used to realize the connection and communication between the memory and the processor;

[0151] The processor 403 is used to execute the method program for determining the position of a chip in a power module to implement any one or any multiple steps of the method for determining the position of a chip in a power module as described above.

[0152] Specifically, the processor 403 may be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.; the memory 401 may be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, mobile memory, etc., or any combination thereof.

[0153] Specifically, the computing device 400 may further include: an external communication interface 404 and a display 405, wherein:

[0154] The external communication interface 404 may be used for communicating with the outside, where the external terminal includes a server or a client, and the external communication interface 404 may include a wired interface and a wireless interface;

[0155] The display 405 may be used to display a wafer map and the corresponding relationship between the chip and the installation position.

[0156] The description of the computing device 400 embodiment is similar to the description of the method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the computing device 400 of this embodiment, please refer to the description of the method embodiment of the present invention for understanding.

[0157] The embodiment of the present application also provides a computer-readable storage medium, on which an executable program is stored, and when the executable program is executed by the processor, any one or more steps in the method for determining the chip position in the power module as described above are implemented. The computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device, or a combination thereof. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a read-only optical disc (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. Volatile memory can be random access memory (RAM), which acts as external cache.By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), direct memory bus random access memory (DRRAM). The storage medium described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memory.

[0158] The description of the above computer-readable storage medium embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the computer-readable storage medium of this embodiment, please refer to the description of the method embodiment of the present invention for understanding.

[0159] In the following description, the terms "first\second\..." are only used to distinguish similar objects and do not represent a specific order of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted.

[0160] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0161] It should be understood that "one embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present invention, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention. The serial numbers of the above-mentioned embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

[0162] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as: multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or modules can be electrical, mechanical or other forms.

[0163] The modules described above as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules; they may be located in one place or distributed on multiple network modules; some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0164] In addition, all functional modules in the embodiments of the present invention may be integrated into one processing module, or each functional module may be a separate module, or two or more functional modules may be integrated into one module; the above-mentioned integrated modules may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0165] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiment.

[0166] Alternatively, if the above-mentioned integrated module of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for enabling an electronic device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. In this way, the embodiment of the present invention is not limited to any specific combination of hardware and software.

[0167] The methods disclosed in several method embodiments provided in this application can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided in this application can be combined arbitrarily without conflict to obtain new product embodiments.

[0168] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0169] In the description of the embodiments of the present invention, unless otherwise specified and limited, the term "connection" should be understood in a broad sense. For example, it can be an electrical connection or a connection between two components. It can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0170] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present invention that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present invention and do not limit the scope of protection of the patent of the present invention.

Claims

1. A method for determining the position of a chip in a power module, characterized in that: The method comprises: Acquire wafer test data of a plurality of chips, wherein the wafer test data includes at least one electrical performance parameter corresponding to each of the chips; Obtaining a thermal simulation result of the packaging module, wherein the thermal simulation result includes a temperature value corresponding to each of a plurality of mounting positions, wherein the mounting position is a position in the packaging module for mounting the chip, and the packaging module is used to package the plurality of chips to form a power module; According to at least one electrical performance parameter of each chip in the wafer test data, the chips are sorted according to a first preset rule, and when sorting, the electrical performance parameter is selected as the parameter that most affects the heat generation of the chip; the first preset rule is to sort by the performance of the chips; the chip with the best performance in the sorting is the chip with the smallest heat generation; sorting the plurality of installation positions according to the temperature values ​​corresponding to the installation positions in the thermal simulation results; According to the order of the chips and the order of the installation positions, the corresponding relationship between the chips and the installation positions is determined.

2. The method for determining the chip position in a power module according to claim 1, characterized in that: The step of sorting the chips according to a first preset rule based on at least one electrical performance parameter of each chip in the wafer test data comprises: According to the values ​​of at least two electrical performance parameters in the wafer test data that respectively characterize at least two different performances of the chip, the chips are batched and sorted according to the quality of the chip performance.

3. The method for determining the chip position in a power module according to claim 2, characterized in that: The at least two electrical performance parameters include a first electrical performance parameter for characterizing the quality of a first preset performance of the chip and a second electrical performance parameter for characterizing the quality of a second preset performance of the chip; The step of batching and sorting the chips according to the performance of the chips based on the values ​​of at least two electrical performance parameters in the wafer test data that respectively characterize at least two different performances of the chips includes: According to the first electrical performance parameter, dividing the chips into multiple batches; The chips are sorted according to the following sorting rules: The chips in the same batch are sorted in descending order according to the second preset performance, and the chips between the batches are sorted in descending order according to the first preset performance.

4. The method for determining the chip position in a power module according to claim 1 or 2, characterized in that: Determining the correspondence between the chips and the installation positions according to the order of the chips and the order of the installation positions includes: According to the number of mounting positions in the packaging module, the sorted chips are divided into a plurality of chip groups in order, and the number of chips in each chip group is the same as the number of mounting positions in each packaging module; According to the third electrical performance parameter in the wafer test data characterizing the quality of the third preset performance of the chip, the chips in each of the chipsets are sorted in descending order according to the third preset performance; The chips in the sorted chipset and the sorted installation positions are respectively and sequentially determined in their respective orders to determine the corresponding relationship between the chips and the installation positions.

5. The method for determining the chip position in a power module according to claim 3, characterized in that: The method further comprises: The first position of the chip in the wafer is associated with the second position of the chip corresponding to the mounting position in the packaging module, and the association is stored in a file of a preset format.

6. The method for determining chip position in a power module according to claim 1, characterized in that: Before sorting the chips according to a first preset rule based on at least one electrical performance parameter of each chip in the wafer test data, the method further includes: determining the chips that meet preset requirements based on the wafer test data and the value of the at least one electrical performance parameter; The sorting of the chips according to a first preset rule includes: sorting the chips meeting the preset requirements according to the first preset rule.

7. A device for executing the method for determining the chip position in the power module according to claim 1, characterized in that: The device comprises: A first acquisition unit, configured to acquire wafer test data of a plurality of chips, wherein the wafer test data includes at least one electrical performance parameter corresponding to each of the chips; A second acquisition unit is used to acquire a thermal simulation result of the packaging module, wherein the thermal simulation result includes a temperature value corresponding to each of a plurality of mounting positions, wherein the mounting position is a position in the packaging module for mounting the chip, and the packaging module is used to package a plurality of the chips to form a power module; A determination unit is used to determine the corresponding relationship between the chip and the installation position according to the wafer test data and the thermal simulation result.

8. A computing device, characterized in that The computing device comprises: a memory, a communication bus and a processor, wherein: The memory is used to store a method program for determining the position of a chip in a power module; The communication bus is used to realize the connection and communication between the memory and the processor; The processor is used to execute a method program for determining a chip position in a power module to implement the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores an executable program, and when the executable program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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