A chip with fully enclosed isolation for signal lines, a method thereof, and a chip manufacturing method.

Abstract

A chip, method, and chip manufacturing method with fully enclosed isolation for signal lines are disclosed. The chip 100 includes at least three stacked metal layers and a plurality of functional vias disposed at corresponding positions in the at least three metal layers. Classified signal line clusters are disposed in the middle metal layer and isolated from other signal lines in the chip based on an isolation layer. By arranging noisy, normal, and sensitive signal line clusters at different positions in the chip, and wrapping noisy signal lines with high-level metal lines and sensitive signal lines with zero-level metal lines, the noisy, normal, and sensitive signal line clusters are isolated, thereby achieving isolation of noisy signals and protection of sensitive signals.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits and chip manufacturing, and more specifically, to a chip, method, and chip manufacturing method with fully enclosed isolation of signal lines. Background Technology

[0002] In the prior art, because different signal lines in an analog chip have different signal transmission functions, the signals transmitted in some signal lines are relatively noisy, which causes serious electromagnetic interference to other signal lines that are close to each other, thereby affecting the transmission quality of signals in other signal lines and further affecting the performance of the analog chip.

[0003] Specifically, based on the different functions of various signal lines in an analog chip, they can be classified into noisy signal lines and sensitive signal lines. Noisy signal lines typically have large signal amplitudes or frequent signal movements with significant amplitude variations, easily interfering with other adjacent signal lines. Sensitive signal lines usually require high precision, as even minor changes can significantly impact chip performance. Interference with these lines can easily lead to signal transmission errors. Therefore, these signal lines should be protected from external interference as much as possible, and their signal values ​​should be kept relatively constant during transmission.

[0004] Currently, in the process of integrated circuit layout, noisy signal lines are typically placed at intervals from sensitive signal lines to prevent interference. However, as chip manufacturing size and circuit complexity increase, this existing method increases the complexity of integrated circuits, increases circuit length, prevents further reduction in chip area, and reduces the degree of chip integration.

[0005] Therefore, there is an urgent need for a new method to isolate sensitive signal lines in chips to prevent interference from noisy signals. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a chip, method, and chip manufacturing method with fully enclosed isolation of signal lines. By arranging noisy, normal, and sensitive signal line clusters at different locations within the chip, and enclosing the noisy signal lines with high-level metal lines and the sensitive signal lines with zero-level metal lines, isolation of noisy signals and protection of sensitive signals are achieved.

[0007] The present invention adopts the following technical solution.

[0008] In a first aspect, the present invention relates to a chip with full-wrap isolation of signal lines, wherein the chip 100 includes at least three stacked metal layers and a plurality of functional vias disposed at corresponding positions in the at least three metal layers; wherein a cluster of classified signal lines is disposed in an intermediate metal layer and is isolated from other signal lines in the chip based on an isolation layer.

[0009] Preferably, the isolation layer includes metal layers on both sides of the area where the classification signal line cluster is located in the middle metal layer, an upper metal layer area corresponding to the area where the classification signal line cluster is located and the areas on both sides, and a lower metal layer area corresponding to the area where the classification signal line cluster is located and the areas on both sides; wherein, each metal layer area inside the isolation layer is not connected to other metal layer areas outside the isolation layer; and, each metal layer area inside the isolation layer is interconnected through signal lines to isolate the classification signal line cluster.

[0010] Preferably, the classification method of the classification signal line cluster is noisy signal line 101, ordinary signal line 102 and sensitive signal line 103.

[0011] Preferably, the metal layer regions in the isolation layer are connected by signal lines and metal lines, which is achieved by connecting different metal layers based on multiple functional vias 204 and 205 at corresponding positions in at least three metal layers.

[0012] Preferably, the noisy signal line cluster is isolated by metal wires 104, 106 located in the isolation layer corresponding to the noisy signal line cluster and connected to the power supply potential.

[0013] Preferably, the sensitive signal line cluster is isolated by a metal wire 105 located in the isolation layer corresponding to the sensitive signal line cluster and connected to ground potential.

[0014] Preferably, the noisy signal line cluster and its isolation layer are located at one end of the chip, the sensitive signal line cluster and its isolation layer are located at the other end of the chip, and the ordinary signal line cluster is located in the middle of the chip to achieve isolation between the noisy signal line cluster and the sensitive signal line cluster.

[0015] Preferably, a plurality of first functional vias 204 are provided between the upper metal layer 201 and the middle metal layer 202, and a plurality of second functional vias 205 are provided between the middle metal layer 202 and the lower metal layer 203; and the metal lines in the upper metal layer 201 in the isolation layer are connected to the metal lines on both sides of the area where the classification signal line cluster is located in the middle metal layer 202 through the first functional vias 204; the metal lines on both sides of the area where the classification signal line cluster is located in the isolation layer are connected to the metal lines in the lower metal layer 203 located in the area where the classification signal line cluster is located and the areas on both sides through the second functional vias 205.

[0016] A second aspect of the present invention relates to a method for full-wrap isolation of signal lines, wherein the method is implemented using a chip for full-wrap isolation of signal lines as described in the first aspect of the present invention.

[0017] A third aspect of the present invention relates to a method for manufacturing a chip with fully enclosed isolation of signal lines, wherein the chip manufacturing method employs the chip wiring method described in the first aspect of the present invention for manufacturing the chip.

[0018] The beneficial effect of the present invention is that, compared with the prior art, the chip, method and chip manufacturing method of the present invention with signal line full-wrap isolation can arrange noisy, normal and sensitive signal line clusters in different positions in the chip, and wrap high-level metal lines around the noisy signal lines and zero-level metal lines around the sensitive signal lines, so as to achieve isolation of noisy signals and protection of sensitive signals.

[0019] The beneficial effects of the present invention also include:

[0020] 1. By fully enclosing the circuit to isolate noisy signals, the external circuit can have better noise immunity; by fully enclosing the circuit to isolate sensitive signals, sensitive signals can be protected in all aspects to prevent noise interference.

[0021] 2. Since both sensitive signal lines and noisy signal lines are equipped with isolation layers, the isolation distance between them can be reduced to a large extent while achieving the same isolation effect. This reduces the length of the effective circuit, supports a smaller chip area, and improves the integration of the circuit.

[0022] 3. The isolation method for noisy signal lines and sensitive signal lines in this invention has a simple structure, is easy to implement, can support a variety of different types of chips and circuit types that are common in the prior art, and can achieve a wide range of applications. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a signal line arrangement in a chip with fully enclosed isolation of signal lines according to the present invention;

[0024] Figure 2 This is a schematic diagram of the connection method of different metal layers in a chip with fully enclosed isolation of signal lines according to the present invention.

[0025] Figure label:

[0026] 100-chip,

[0027] 101 - Noisy Signal Line

[0028] 102-Sensitive signal line,

[0029] 103 - Standard Signal Cable

[0030] 104 - Metal wire connected to power supply potential.

[0031] 105 - Metal wire connected to ground potential,

[0032] 106-Metallic Wire

[0033] 201 - Upper metal layer

[0034] 202 - Intermediate Metal Layer

[0035] 203 - Lower metal layer

[0036] 204 - First functional via,

[0037] 205 - Second functional via. Detailed Implementation

[0038] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0039] Figure 1 This is a schematic diagram of a signal line arrangement in a chip with fully enclosed isolation of signal lines according to the present invention. Figure 2 This is a schematic diagram illustrating the connection method of different metal layers in a chip with fully enclosed isolation of signal lines, as described in this invention. Figure 1-2 As shown, in a first aspect, the present invention relates to a chip 100 with full signal line isolation, wherein the chip 100 includes at least three stacked metal layers and a plurality of functional vias disposed at corresponding positions in the at least three metal layers; wherein, a cluster of classified signal lines is disposed in the middle metal layer and is isolated from other signal lines in the chip based on the isolation layer.

[0040] Specifically, in integrated circuit chips, the design layout of the integrated circuit can be achieved by various material layers formed on a semiconductor substrate, such as a silicon wafer. These various material layers on the semiconductor substrate can be formed from various metals, metal oxides, and thin semiconductor layers. Different portions of these thin layers, formed from different materials, can be used to realize, for example, gate electrodes, source and drain regions, metal interconnects such as metal lines or vias, openings for bonding pads, and so on.

[0041] It is understandable that the substrate can include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, various field-effect transistors, various transistors, or combinations of components. To connect these different components to the circuit in a suitable manner and to further reduce the chip area, existing technologies typically employ a wiring method that places multiple metal layers on top of the substrate to connect multiple different components. For example, patent application CN112558407A discloses a method for manufacturing a semiconductor device, which discloses a layout after routing that includes an interconnect structure, and the interconnect structure includes multiple metal layers such as a first, second, and third metal layer.

[0042] Based on existing technologies, the technical solution of this invention places different types of signal line clusters at different positions on multiple metal layers and fully wraps them from top to bottom and left to right, thereby achieving good signal isolation.

[0043] The multiple metal layers can be at least three, with the number of metal layers appropriately increased based on the actual wiring method of the integrated circuit in the chip and the limits permitted by the chip manufacturing process. Correspondingly, the classification signal line cluster can be placed in one or more intermediate metal layers excluding the top and bottom metal layers. Since the classification signal line cluster needs to be wrapped with an isolation layer, at least one upper metal layer and one lower metal layer need to be reserved for isolation.

[0044] Similarly, functional vias of the metal layer can be set on the left and right sides of the classification signal line cluster, and the metal layer at the corresponding position of the functional via can be reserved for isolation.

[0045] Preferably, the isolation layer includes two metal layer regions 202 on both sides of the metal layer where the classification signal line cluster is located in the middle metal layer, an upper metal layer region 104 or 105 corresponding to the region where the classification signal line cluster is located and the two side regions, and a lower metal layer region 106 corresponding to the region where the classification signal line cluster is located and the two side regions; each metal layer region in the isolation layer is not connected to other metal layer regions in the non-isolation layer part of the chip, and each metal layer region in the isolation layer is interconnected to isolate the classification signal line cluster; wherein, each metal layer region is a metal line inside the chip used to realize the connection of internal components.

[0046] Understandably, based on the specific location of the classification signal line cluster, the adjacent metal lines above, below, left, and right are selected, and these metal lines are interconnected to form an isolation layer. For example... Figure 1As shown, the isolation layer includes the metal layer regions on both sides of the layer where the classified signal line clusters are located, as well as the top and bottom metal layers of the aforementioned regions. This configuration method achieves comprehensive encapsulation and isolation of the signal lines, effectively preventing mutual interference between signals. Compared to commonly used isolation methods in the prior art, the method in this invention offers significantly superior performance.

[0047] Preferably, the classification method of the classification signal line cluster is noisy signal line 101, ordinary signal line 103 and sensitive signal line 102; wherein, noisy signal line 101 includes at least signal lines for connecting high-power devices that perform chip functions; sensitive signal line 102 includes at least signal lines for connecting control circuits required to perform chip functions; and ordinary signal line 103 refers to other signal lines in the chip besides noisy signal line 101 and sensitive signal line 102.

[0048] Specifically, signal lines can be classified according to their function, circuit principle, and the characteristics of the signals transmitted in them. For example, signal lines transmitting signals with large amplitude can be classified as noisy signal lines, while signal lines carrying small amplitude signals that are easily interfered with and whose interference severely affects chip function can be classified as sensitive signal lines. In one embodiment, high-power input / output signals used as high-power devices, or signals such as the on-state voltage and current of devices like MOSFETs and transistors, can be classified as noisy signals, and the signal lines carrying these signals can also be classified as noisy signal lines accordingly. In another embodiment, signals used as auxiliary functions of the aforementioned high-power devices, such as some commonly used control signals, can be classified as sensitive signals. Signal lines can be classified according to the above at the chip circuit layout design stage. In summary, neither the prior art nor this application has a fixed or completely explicit definition for noisy signal lines and sensitive signal lines. The signal line classification method in this application can be defined according to the specific chip required to achieve isolation.

[0049] Preferably, the metal layer regions in the isolation layer are connected by signal lines and metal lines 106 to realize the connection of different metal layer regions based on multiple functional vias 204, 205 at corresponding positions in at least three metal layers.

[0050] Specifically, each metal layer region represents a metal line pre-installed inside the chip, for example... Figure 2The metal lines 201, 202, and 203 described herein. Since the areas containing these metal lines are adjacent to the noisy signal lines on all sides, they are used as isolation layers. To achieve isolation, these metal lines should be connected end-to-end and have an appropriate potential applied to them to isolate the noisy signal lines located within them. Because the various metal layer regions, i.e., the various metal lines, are located in different layers, connecting the metal lines in different layers requires multiple functional vias 204 and 205.

[0051] Preferably, the noisy signal line clusters are isolated by metal line regions 104, 106 located in the isolation layer corresponding to the noisy signal line clusters and then connected to the power potential bus.

[0052] Specifically, for noisy signal lines, because the signals they carry typically have high power, fluctuate frequently, and can vary significantly in amplitude, isolation with a metal wire possessing a high internal voltage is necessary. This is because when the metal wire has a stable high voltage inside, the high voltage shields most of the electromagnetic interference caused by the noisy signal, reducing its susceptibility to the noise. Therefore, signal lines outside the high-voltage isolation layer receive little or no interference from the noisy signal line.

[0053] Preferably, the sensitive signal line cluster is isolated by a metal wire 105 located in the isolation layer corresponding to the sensitive signal line cluster and connected to ground potential.

[0054] Specifically, sensitive signal line clusters, because they carry relatively small signals, do not exhibit excessive outward radiated interference. Conversely, these signal lines are susceptible to external interference. Based on this characteristic, their isolation layer can be connected to a clean ground line to achieve isolation. Specifically, within a chip, for easier and more standardized routing, there may be multiple power supply buses and multiple ground buses.

[0055] Preferably, the noisy signal line cluster and its isolation layer are located at one end of the chip, the sensitive signal line cluster and its isolation layer are located at the other end of the chip, and the ordinary signal line cluster is located in the middle of the chip to achieve isolation between the noisy signal line cluster and the sensitive signal line cluster.

[0056] Since noisy and sensitive signal lines already have a fully enclosed isolation layer, there is no need to add an extra isolation layer outside ordinary signal lines.

[0057] Preferably, a plurality of first functional vias 204 are provided between the upper metal layer 201 and the middle metal layer 202, and a plurality of second functional vias 205 are provided between the middle metal layer 202 and the lower metal layer 203; and the metal lines in the upper metal layer 201 in the isolation layer are connected to the metal lines on both sides of the area where the classification signal line cluster is located in the middle metal layer 202 through the first functional vias 204; the metal lines on both sides of the area where the classification signal line cluster is located in the isolation layer are connected to the metal lines in the lower metal layer 203 located in the area where the classification signal line cluster is located and the areas on both sides through the second functional vias 205.

[0058] Specifically, the functional vias described in this invention are no different from the functional vias between multiple metal layers commonly used in the prior art; both are used to connect metal wires in multiple different metal layers.

[0059] A second aspect of the present invention relates to a method for full-wrap isolation of signal lines, wherein the method is implemented using a chip for full-wrap isolation of signal lines as described in the first aspect of the present invention.

[0060] A third aspect of the present invention relates to a chip manufacturing method with fully enclosed isolation of signal lines, wherein the chip manufacturing method employs the chip wiring method in a chip with fully enclosed isolation of signal lines as described in the first aspect of the present invention to achieve chip manufacturing.

[0061] The beneficial effect of the present invention is that, compared with the prior art, the chip, method and chip manufacturing method of the present invention with signal line full-wrap isolation can arrange noisy, normal and sensitive signal line clusters in different positions in the chip, and wrap high-level metal lines around the noisy signal lines and zero-level metal lines around the sensitive signal lines, so as to achieve isolation of noisy signals and protection of sensitive signals.

[0062] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A chip with fully enclosed isolation for signal lines, characterized in that: The chip (100) includes at least three stacked metal layers and a plurality of functional vias disposed at corresponding positions in the at least three metal layers; The classification signal line cluster is located in the middle metal layer and is isolated from other signal lines in the chip based on the isolation layer; The isolation layer includes the metal layer regions on both sides of the metal layer where the classification signal line cluster is located in the middle metal layer, the upper metal layer region corresponding to the region where the classification signal line cluster is located and the regions on both sides, and the lower metal layer region corresponding to the region where the classification signal line cluster is located and the regions on both sides. Each metal layer region in the isolation layer is not connected to other metal layer regions in the non-isolation layer part of the chip, and each metal layer region in the isolation layer is interconnected to isolate the classification signal line cluster. The classification method for the signal line clusters is as follows: noisy signal line cluster (101), ordinary signal line cluster (103), and sensitive signal line cluster (102); among which, The noisy signal line cluster (101) includes at least signal lines for connecting high-power devices that perform chip functions; The sensitive signal line cluster (102) includes at least signal lines for connecting control circuitry required to perform chip functions. The common signal line cluster (103) refers to the other signal lines in the chip besides the noisy signal line cluster (101) and the sensitive signal line cluster (102); The noisy signal line clusters are isolated by connecting the power potential bus to the metal layer regions (104, 106) located in the isolation layer corresponding to the noisy signal line clusters; The sensitive signal line clusters are isolated by connecting a ground potential bus to a metal layer region (105, 106) located in the isolation layer corresponding to the sensitive signal line clusters; The noisy signal line cluster and its isolation layer are located at one end of the chip, the sensitive signal line cluster and its isolation layer are located at the other end of the chip, and the ordinary signal line cluster is located in the middle of the chip to achieve isolation between the noisy signal line cluster and the sensitive signal line cluster.

2. The chip with fully enclosed isolation of signal lines according to claim 1, characterized in that: Each of the aforementioned metal layer regions is a metal line inside the chip used to connect internal components.

3. A chip with fully enclosed isolation of signal lines as described in claim 1, characterized in that: The metal layer regions in the isolation layer are connected by signal lines and metal lines, which are based on multiple functional vias (204, 205) at corresponding positions in the at least three metal layers to achieve the connection of different metal layer regions.

4. A chip with fully enclosed isolation of signal lines as described in claim 1, characterized in that: A plurality of first functional vias (204) are provided between the upper metal layer (201) and the middle metal layer (202), and a plurality of second functional vias (205) are provided between the middle metal layer (202) and the lower metal layer (203); and, The metal lines in the upper metal layer (201) of the isolation layer are connected to the metal lines on both sides of the area where the classification signal line cluster is located in the middle metal layer (202) through the first functional via (204); The metal lines located on both sides of the region where the classification signal line cluster is located in the isolation layer are connected to the metal lines located in the region where the classification signal line cluster is located and the regions on both sides in the lower metal layer (203) through the second functional via (205).

5. A method for full-wrap isolation of signal lines, characterized in that: The method is implemented using a chip with full signal line isolation as described in any one of claims 1-4.

6. A chip manufacturing method with fully enclosed isolation of signal lines, characterized in that, The chip manufacturing method employs a chip wiring method in a chip with fully enclosed isolation of signal lines as described in any one of claims 1-4, in order to manufacture the chip.

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