A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, which comprises a first voltage trace, a second voltage trace and a plurality of dummy traces, wherein the first voltage trace is a high-voltage trace, the second voltage trace is a low-voltage trace, the first voltage trace and the second voltage trace are located on the same line, the plurality of dummy traces are distributed on both sides of the first voltage trace and the second voltage trace, and any dummy trace adjacent to the first voltage trace and the second voltage trace has a relative part with only one of the first voltage trace and the second voltage trace in a second direction or has no relative part with the first voltage trace and the second voltage trace in the second direction. The application improves the layout of the traces, so that the dummy traces adjacent to the high-voltage trace and the low-voltage trace do not face the high-voltage trace and the low-voltage trace at the same time, thereby effectively improving the line-to-line breakdown voltage between the high-voltage / low-voltage trace and the dummy trace without increasing the trace spacing, effectively controlling the chip area, and not affecting the original high-voltage trace and low-voltage trace.

Description

[0001] This application is a divisional application of the patent application filed on September 3, 2019, with application number 201910826314.X and entitled "A Three-Dimensional Storage Device and a Method for Manufacturing the Same". Technical Field

[0002] This invention belongs to the field of semiconductor integrated circuits and relates to a semiconductor device and its fabrication method. Background Technology

[0003] In 3D NAND technology, the metal traces on the upper layer of the high-voltage metal-oxide-semiconductor (HV MOS) in the complementary metal-oxide-semiconductor page buffer circuit, apart from the high-voltage metal line (HV) and the low-voltage metal line (LV), are all very long floating dummy traces. These floating dummy traces are affected by the coupling effect of the high-voltage metal line, which can easily cause a decrease in the line-to-line breakdown voltage (Vbd) between the two metal lines (HV / Dummy) or between the two metal lines (Dummy / LV), thus leading to the problem of time-dependent dielectric breakdown (TDDB).

[0004] Current solutions mainly involve increasing the spacing between traces, but as the number of layers in 3D NAND technology increases and the number of traces in the back end of the device increases significantly, increasing the spacing is no longer possible.

[0005] Therefore, how to design a new three-dimensional storage device and its fabrication method to improve the above problems has become an important technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a three-dimensional storage device and its manufacturing method, which solves the problem of time-dependent dielectric breakdown (TDDB) caused by the reduced line-to-line breakdown voltage (Vbd) of floating dummy traces due to the coupling effect of high-voltage metal lines.

[0007] To achieve the above and other related objectives, the present invention provides a three-dimensional storage device, comprising:

[0008] A first voltage trace extends along a first direction;

[0009] The second voltage trace is located on the same straight line as the first voltage trace, and the voltage of the second voltage trace is lower than the voltage of the first voltage trace.

[0010] Multiple dummy traces are distributed on both sides of the first voltage trace and the second voltage trace. Among them, any dummy trace adjacent to the first voltage trace and the second voltage trace has a relative portion with only one of the first voltage trace and the second voltage trace in the second direction, or has no relative portion with either the first voltage trace or the second voltage trace in the second direction. The second direction is perpendicular to the first direction.

[0011] Optionally, the plurality of dummy traces include a first dummy trace, a second dummy trace, a third dummy trace, and a fourth dummy trace adjacent to the first voltage trace and the second voltage trace. The first dummy trace and the second dummy trace are located on the same straight line, the third dummy trace and the fourth dummy trace are located on the same straight line, the first dummy trace and the third dummy trace are respectively located on opposite sides of the first voltage trace and have opposite portions with the first voltage trace in the second direction, and the second dummy trace and the fourth dummy trace are respectively located on opposite sides of the second voltage trace and have opposite portions with the second voltage trace in the second direction.

[0012] Optionally, the three-dimensional storage device further includes at least one central dummy trace, which is located on the same straight line as the first voltage trace and the second voltage trace, and is located between the first voltage trace and the second voltage trace.

[0013] Optionally, the first dummy trace, the second dummy trace, the third dummy trace, and the fourth dummy trace all have a relative portion with the central dummy trace in the second direction.

[0014] Optionally, the plurality of dummy traces may further include a fifth dummy trace, wherein the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.

[0015] Optionally, the first dummy trace and the fourth dummy trace have no opposite portion to the central dummy trace in the second direction, while the second dummy trace and the third dummy trace have opposite portions to the central dummy trace in the second direction.

[0016] Optionally, the plurality of dummy traces may further include a fifth dummy trace, wherein the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.

[0017] Optionally, the three-dimensional memory device includes a page-buffered high-voltage NMOS transistor, the drain of which is connected to the lower side of the first voltage line via a first contact portion, and the source of which is connected to the lower side of the second voltage line via a second contact portion.

[0018] Optionally, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.

[0019] Optionally, the three-dimensional storage device further includes a third voltage trace, the voltage of which is equal to the voltage of the second voltage trace, the third voltage trace is parallel to the second voltage trace, and the third voltage trace and the second voltage trace are separated by at least one of the dummy trace intervals.

[0020] Optionally, the third voltage trace is connected to the second voltage trace through at least one dummy trace and at least two connecting portions, and the two sides of the at least one connecting portion are respectively connected to the second voltage trace and one dummy trace, and the two sides of the at least one connecting portion are respectively connected to one dummy trace and the third voltage trace.

[0021] This invention also provides a method for manufacturing a three-dimensional storage device, comprising the following steps:

[0022] Provide a substrate;

[0023] A wiring layer is formed above the substrate. The wiring layer includes a first voltage line, a second voltage line, and a plurality of dummy lines. The second voltage line and the first voltage line are located on the same straight line, and the voltage of the second voltage line is lower than that of the first voltage line. The plurality of dummy lines are distributed on both sides of the first voltage line and the second voltage line. Any dummy line adjacent to the first voltage line and the second voltage line has a relative portion with only one of the first voltage line and the second voltage line in a second direction, or has no relative portion with either the first voltage line or the second voltage line in a second direction. The second direction is perpendicular to the first direction.

[0024] Alternatively, the wiring layer can be obtained by forming a conductive layer over the substrate and patterning the conductive layer.

[0025] Optionally, the wiring layer is obtained by forming a mask layer with an opening pattern over the substrate and forming a conductive material in the opening pattern.

[0026] Optionally, the plurality of dummy traces include a first dummy trace, a second dummy trace, a third dummy trace, and a fourth dummy trace adjacent to the first voltage trace and the second voltage trace. The first dummy trace and the second dummy trace are located on the same straight line, the third dummy trace and the fourth dummy trace are located on the same straight line, the first dummy trace and the third dummy trace are respectively located on opposite sides of the first voltage trace and have opposite portions with the first voltage trace in the second direction, and the second dummy trace and the fourth dummy trace are respectively located on opposite sides of the second voltage trace and have opposite portions with the second voltage trace in the second direction.

[0027] Optionally, the three-dimensional storage device further includes at least one central dummy trace, which is located on the same straight line as the first voltage trace and the second voltage trace, and is located between the first voltage trace and the second voltage trace.

[0028] Optionally, the first dummy trace, the second dummy trace, the third dummy trace, and the fourth dummy trace all have a relative portion with the central dummy trace in the second direction.

[0029] Optionally, the plurality of dummy traces may further include a fifth dummy trace, wherein the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.

[0030] Optionally, the first dummy trace and the fourth dummy trace have no opposite portion to the central dummy trace in the second direction, while the second dummy trace and the third dummy trace have opposite portions to the central dummy trace in the second direction.

[0031] Optionally, the plurality of dummy traces may further include a fifth dummy trace, wherein the fifth dummy trace is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.

[0032] Optionally, the substrate is provided with a page-buffered high-voltage NMOS transistor, the first voltage trace is connected to the drain of the transistor through a first contact portion, and the second voltage trace is connected to the source of the transistor through a second contact portion.

[0033] As described above, the three-dimensional memory device and its fabrication method of the present invention improve the layout of the traces so that the dummy traces adjacent to the high-voltage traces or low-voltage traces do not simultaneously face the high-voltage traces and low-voltage traces. This can effectively increase the line-to-line breakdown voltage (Vbd) between the high-voltage traces and dummy traces, or between the dummy traces and low-voltage traces, without increasing the spacing between the traces. This not only effectively controls the chip area, but also does not affect the original high-voltage traces and low-voltage traces. Attached Figure Description

[0034] Figure 1 This is shown as a schematic diagram of the routing layout of an example three-dimensional storage device.

[0035] Figure 2 Displayed as Figure 1 The diagram shows the simulation results of the three-dimensional storage device.

[0036] Figure 3 The diagram shows the wiring plan layout of the three-dimensional storage device of the present invention in Embodiment 1.

[0037] Figure 4 The diagram shows the wiring plan layout of the three-dimensional storage device of the present invention in Embodiment 2.

[0038] Figure 5 The diagram shows the wiring plan layout of the three-dimensional storage device of the present invention in Embodiment 3.

[0039] Figure 6 Displayed as Figure 5 The diagram shows the simulation results of the three-dimensional storage device.

[0040] Figure 7 The diagram shows the wiring plan layout of the three-dimensional storage device of the present invention in Embodiment 4.

[0041] Component designation explanation

[0042] 101 First Voltage Line

[0043] 102 Second Voltage Line

[0044] 103 First Contact Section

[0045] 104 Second Contact Section

[0046] 105, 106, 107, 108, 109, 110, 111 (Dummy wiring)

[0047] 112 Third Voltage Routing

[0048] 113, 114, 115 Connecting parts

[0049] W trace width

[0050] D. Trace Spacing

[0051] 201 First Voltage Trajectory

[0052] 202 Second Voltage Line

[0053] 203 First Contact Section

[0054] 204 Second Contact Section

[0055] 205 First Dummy Wiring

[0056] 206 Second Dummy Wiring

[0057] 207 Third Dummy Wiring

[0058] 208 Fourth Dummy Wiring

[0059] 209, 210, 211, 212 Dummy wiring

[0060] 213 Third Voltage Routing

[0061] 301 First Voltage Trajectory

[0062] 302 Second Voltage Trajectory

[0063] 303 First Contact Section

[0064] 304 Second Contact Section

[0065] 305 Dummy wiring in the middle

[0066] 306 First Dummy Wiring

[0067] 307 Second Dummy Wiring

[0068] 308 Third Dummy Wiring

[0069] 309 Fourth Dummy Wiring

[0070] 310, 311, 312, 313 Dummy wiring

[0071] 314 Third Voltage Trajectory

[0072] 401 First Voltage Trajectory

[0073] 402 Second Voltage Line

[0074] 403 First Contact Section

[0075] 404 Second Contact Section

[0076] 405 Dummy wiring in the middle

[0077] 406 First Dummy Wiring

[0078] 407 Second Dummy Wiring

[0079] 408 Third Dummy Wiring

[0080] 409 Fourth Dummy Wiring

[0081] 410, 411, 412, 413 Dummy wiring

[0082] 414 Third Voltage Trajectory

[0083] 415 Fifth Dummy Wiring

[0084] 416, 417, 418 Connecting parts

[0085] 501 First Voltage Trajectory

[0086] 502 Second Voltage Trajectory

[0087] 503 First Contact Section

[0088] 504 Second Contact Section

[0089] 505 Dummy wiring in the middle

[0090] 506 First Dummy Wiring

[0091] 507 Second Dummy Wiring

[0092] 508 Third Dummy Wiring

[0093] 509 Fourth Dummy Wiring

[0094] 510, 511, 512, 513 Dummy wiring

[0095] 514 Third Voltage Tracing

[0096] 515 Fifth Dummy Wiring

[0097] X Second Direction

[0098] Y First direction Detailed Implementation

[0099] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0100] Please see Figures 1 to 7It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the component layout is also different.

[0101] like Figure 1 The diagram shows a routing planar layout of an example three-dimensional memory device. The three-dimensional memory device includes a first voltage trace 101 and a second voltage trace 102 located on the same straight line. The first voltage trace 101 is a high-voltage trace, and the second voltage trace 102 is a low-voltage trace. The first voltage trace 101 and the second voltage trace 102 respectively provide high voltage and low voltage to the semiconductor element below them through a first contact portion 103 and a second contact portion 104 below them.

[0102] As an example, Figure 1 The diagram shows the trace width W and trace spacing D.

[0103] As an example, the three-dimensional storage device further includes multiple dummy traces distributed on opposite sides of the first voltage trace 101 and the second voltage trace 102. Dummy trace 105 is adjacent to the left side of the first voltage trace 101 and the second voltage trace 102 and faces the first voltage trace 101 and the second voltage trace 102. Dummy trace 106 and dummy trace 107 are adjacent to the right side of the first voltage trace 101 and the second voltage trace 102, and dummy trace 107 faces the first voltage trace 101 and the second voltage trace 102. Dummy traces 108, dummy trace 109, dummy trace 111 and dummy trace 111 are all separated from the first voltage trace 101 or the second voltage trace 102 by other traces.

[0104] As an example, the three-dimensional storage device further includes a third voltage trace 112 distributed to the right of the first voltage trace 101 and the second voltage trace 102. The third voltage trace 112 also serves as a low-voltage trace, and there are other traces between the third voltage trace 112 and the first voltage trace 101 or the second voltage trace 102.

[0105] like Figure 2 As shown, it is displayed as Figure 1The diagram shows the simulation results of the three-dimensional storage device. A high voltage HV = 22V is applied to the first voltage trace 101, and a low voltage LV = 0V is applied to the second voltage trace 102. The second voltage trace 102 and the third voltage trace 112 are connected via a connector 113, a dummy trace 107, a connector 114, a dummy trace 111, and a connector 115. The simulation results show that, due to the coupling effect, the voltage of the dummy trace 105 is 6.5V, the voltage of the dummy trace 106 is 11.27V, and the voltage of the dummy trace 110 is 4.7V.

[0106] Because the breakdown point of the metal TDDB (the point of strongest electric field) is between the two traces with the largest voltage difference, Figure 2 In the simulation results, the maximum voltage difference between the two traces is ΔV = (22-6.5)V = 15.5V. Therefore, the device is prone to breakdown between the first voltage trace 101 and the dummy trace 105. The dummy trace 105 is characterized by being adjacent to the first voltage trace 101 and having a relatively long length, while also being opposite to both the first voltage trace 101 and the second voltage trace 102.

[0107] Based on simulations of the aforementioned devices and analysis of the simulation results, this invention concludes that the dummy traces adjacent to both high-voltage and low-voltage traces are most affected by coupling effects. Therefore, this invention employs a cutting method to eliminate adjacent dummy traces that simultaneously face both high-voltage and low-voltage traces. The technical solution of this invention will be illustrated below with more specific embodiments.

[0108] Example 1

[0109] This embodiment provides a three-dimensional storage device; please refer to [link / reference]. Figure 3 The diagram shows the routing plan layout of the three-dimensional storage device, which includes a first voltage trace 201, a second voltage trace 202, and multiple dummy traces. The first voltage trace 201 extends along a first direction Y, the second voltage trace 202 is located on the same straight line as the first voltage trace 201, and the multiple dummy traces are distributed on both sides of the first voltage trace 201 and the second voltage trace 202.

[0110] Specifically, the voltage of the second voltage trace is lower than the voltage of the first voltage trace. The first voltage trace 201 is a high-voltage trace, and the second voltage trace 202 is a low-voltage trace.

[0111] As an example, the three-dimensional memory device includes a page-buffered high-voltage NMOS transistor. The drain of the transistor is connected to the lower part of the first voltage line 201 through a first contact portion 203, and the source of the transistor is connected to the lower part of the second voltage line 202 through a second contact portion 204.

[0112] As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.

[0113] Specifically, any dummy trace adjacent to the first voltage trace 201 and the second voltage trace 202 has a relative portion with one of the first voltage trace and the second voltage trace in the second direction X, or has no relative portion with either the first voltage trace or the second voltage trace in the second direction, wherein the second direction X is perpendicular to the first direction Y.

[0114] In this embodiment, the multiple dummy traces include a first dummy trace 205, a second dummy trace 206, a third dummy trace 207, and a fourth dummy trace 208 adjacent to the first voltage trace and the second voltage trace. The first dummy trace 205 and the second dummy trace 206 are located on the same straight line. The third dummy trace 207 and the fourth dummy trace 208 are located on the same straight line. The first dummy trace 205 and the third dummy trace 207 are located on opposite sides of the first voltage trace 201 and have opposite portions with the first voltage trace 201 in the second direction X. The second dummy trace 206 and the fourth dummy trace 208 are located on opposite sides of the second voltage trace 202 and have opposite portions with the second voltage trace 202 in the second direction X.

[0115] As an example, the plurality of dummy traces also include dummy traces 209, dummy trace 210, dummy trace 211, and dummy trace 212 that are not directly adjacent to the first voltage trace 201 or the second voltage trace 202.

[0116] As an example, the three-dimensional storage device further includes a third voltage trace 213, which is a low-voltage trace, and the voltage of the third voltage trace is equal to the voltage of the second voltage trace. The third voltage trace 213 is parallel to the second voltage trace 202, and the third voltage trace 213 and the second voltage trace 202 are separated by at least one of the aforementioned dummy trace intervals.

[0117] Of course, the dummy lines that are not adjacent to the high-voltage lines and low-voltage lines that are on the same straight line can also adopt other layouts, and the low-voltage lines that are not on the same straight line as the high-voltage lines can also adopt other layouts. The scope of protection of this invention should not be overly limited here.

[0118] In the three-dimensional memory device of this embodiment, the dummy traces adjacent to the high-voltage traces or low-voltage traces do not simultaneously face the high-voltage traces and low-voltage traces. This can effectively improve the line-to-line breakdown voltage (Vbd) between the high-voltage traces and dummy traces, or between the dummy traces and low-voltage traces, without increasing the spacing between the traces. This is beneficial for effectively controlling the chip area. Moreover, the new trace layout is only equivalent to setting small cut points in some traces, without affecting the original high-voltage traces and low-voltage traces.

[0119] Example 2

[0120] This embodiment uses the same technical solution as Embodiment 1. The difference is that in Embodiment 1, there is no dummy routing interval between the high-voltage routing and the low-voltage routing on the same straight line, while in this embodiment, there is a dummy routing between the high-voltage routing and the low-voltage routing on the same straight line. In other words, it is equivalent to setting a cut-off point in the original low-voltage routing.

[0121] Please see Figure 4 The diagram shows the routing planar layout of the three-dimensional storage device in this embodiment. The three-dimensional storage device includes a first voltage trace 301, a second voltage trace 302, at least one central dummy trace 305, and multiple dummy traces. The first voltage trace 301 extends along a first direction Y. The first voltage trace 301, the second voltage trace 302, and the central dummy trace 305 are located on the same straight line, and the central dummy trace 305 is located between the first voltage trace 301 and the second voltage trace 302. The multiple dummy traces are distributed on both sides of the first voltage trace 301 and the second voltage trace 302.

[0122] Specifically, the voltage of the second voltage trace is lower than the voltage of the first voltage trace. The first voltage trace 301 is a high-voltage trace, and the second voltage trace 302 is a low-voltage trace.

[0123] As an example, the three-dimensional memory device includes a page-buffered high-voltage NMOS transistor. The drain of the transistor is connected to the lower part of the first voltage line 301 through a first contact portion 303, and the source of the transistor is connected to the lower part of the second voltage line 302 through a second contact portion 304.

[0124] As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.

[0125] Specifically, any dummy trace adjacent to the first voltage trace and the second voltage trace has a relative portion with only one of the first voltage trace and the second voltage trace in the second direction X, or has no relative portion with either the first voltage trace or the second voltage trace in the second direction X, wherein the second direction X is perpendicular to the first direction Y.

[0126] In this embodiment, the multiple dummy traces include a first dummy trace 306, a second dummy trace 307, a third dummy trace 308, and a fourth dummy trace 309. The first dummy trace 306 and the second dummy trace 307 are located on the same straight line, the third dummy trace 308 and the fourth dummy trace 309 are located on the same straight line, the first dummy trace 306 and the third dummy trace 308 are located on opposite sides of the first voltage trace 301, and the second dummy trace 307 and the fourth dummy trace 309 are located on opposite sides of the second voltage trace 302.

[0127] Furthermore, the first dummy trace 306, the second dummy trace 307, the third dummy trace 308, and the fourth dummy trace 309 all have a relative portion with the central dummy trace 305 in the second direction X.

[0128] As an example, the plurality of dummy traces also include dummy traces 310, 311, 312, and 313 that are not directly adjacent to the first voltage trace 301 or the second voltage trace 302.

[0129] As an example, the three-dimensional storage device further includes a third voltage trace 314, which is a low-voltage trace, and the voltage of the third voltage trace is equal to the voltage of the second voltage trace. The third voltage trace 314 is parallel to the second voltage trace 302, and the third voltage trace 314 and the second voltage trace 302 are separated by at least one of the aforementioned dummy trace intervals.

[0130] Of course, the dummy lines that are not adjacent to the high-voltage lines and low-voltage lines that are on the same straight line can also adopt other layouts, and the low-voltage lines that are not on the same straight line as the high-voltage lines can also adopt other layouts. The scope of protection of this invention should not be overly limited here.

[0131] The routing plane layout of the three-dimensional storage device in this embodiment is relative to... Figure 1The routing planar layout shown is equivalent to cutting off the dummy routing 105 and the second voltage routing 102. Cutting off the dummy routing 105 can disrupt the original relationship between the dummy routing 105 and the high-voltage routing and the low-voltage routing. Cutting off the second voltage routing 102 is equivalent to turning a part of the original low-voltage routing into a dummy routing, which can disrupt the original relationship between the dummy routing 106 and the high-voltage routing and the low-voltage routing. Therefore, the line-to-line breakdown voltage (Vbd) between the high-voltage routing and the dummy routing, or between the dummy routing and the low-voltage routing, can be effectively improved without increasing the spacing between the routings. This is beneficial for effectively controlling the chip area. Moreover, the new routing layout is only equivalent to setting small cut points in some routings, and will not affect the original high-voltage routing and low-voltage routing.

[0132] Example 3

[0133] This embodiment uses the same technical solution as Embodiment 2. The difference is that in Embodiment 2, the fourth dummy trace directly adjacent to the low-voltage trace is longer, while in this embodiment, the multiple dummy traces also include a fifth dummy trace. The fifth dummy trace, the third dummy trace, and the fourth dummy trace are located on the same straight line, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace. This is equivalent to setting a breakpoint in the original fourth dummy trace, dividing the longer fourth dummy trace into two segments of dummy traces.

[0134] Please see Figure 5 The diagram shows the routing planar layout of the three-dimensional storage device in this embodiment. The three-dimensional storage device includes a first voltage trace 401, a second voltage trace 402, at least one central dummy trace 405, and multiple dummy traces. The first voltage trace 401 extends along a first direction Y. The first voltage trace 401, the second voltage trace 402, and the central dummy trace 405 are located on the same straight line, and the central dummy trace 405 is located between the first voltage trace 401 and the second voltage trace 402. The multiple dummy traces are distributed on both sides of the first voltage trace 401 and the second voltage trace 402.

[0135] Specifically, the voltage of the second voltage trace is lower than the voltage of the first voltage trace. The first voltage trace 401 is a high-voltage trace, and the second voltage trace 402 is a low-voltage trace.

[0136] As an example, the three-dimensional memory device includes a page-buffered high-voltage NMOS transistor. The drain of the transistor is connected to the lower part of the first voltage line 401 through a first contact portion 403, and the source of the transistor is connected to the lower part of the second voltage line 402 through a second contact portion 404.

[0137] As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.

[0138] Specifically, any dummy trace adjacent to the first voltage trace and the second voltage trace has a relative portion with only one of the first voltage trace and the second voltage trace in the second direction X, or has no relative portion with either the first voltage trace or the second voltage trace in the second direction X, wherein the second direction X is perpendicular to the first direction Y.

[0139] In this embodiment, the multiple dummy traces include a first dummy trace 406, a second dummy trace 407, a third dummy trace 408, a fourth dummy trace 409, and a fifth dummy trace 415. The first dummy trace 406 and the second dummy trace 407 are located on the same straight line. The third dummy trace 408, the fourth dummy trace 409, and the fifth dummy trace 415 are also located on the same straight line, with the fifth dummy trace 415 located between the third dummy trace 408 and the fourth dummy trace 409. The first dummy trace 406 and the third dummy trace 408 are located on opposite sides of the first voltage trace 401, and the second dummy trace 407 and the fourth dummy trace 409 are located on opposite sides of the second voltage trace 402.

[0140] Furthermore, the first dummy trace 406 and the third dummy trace 408 each have a corresponding portion in the second direction X with the first voltage trace 401 and the central dummy trace 405. Similarly, the second dummy trace 407 and the fourth dummy trace 409 each have a corresponding portion in the second direction X with the second voltage trace 402 and the central dummy trace 405. The dummy trace 515 has no corresponding portion in the second direction X with either the first voltage trace or the second voltage trace.

[0141] As an example, the plurality of dummy traces also include dummy traces 410, 411, 412, and 413 that are not directly adjacent to the first voltage trace 401 or the second voltage trace 402.

[0142] As an example, the three-dimensional storage device further includes a third voltage trace 414, which is a low-voltage trace, and the voltage of the third voltage trace is equal to the voltage of the second voltage trace. The third voltage trace 414 is parallel to the second voltage trace 402, and the third voltage trace 414 and the second voltage trace 402 are separated by at least one of the aforementioned dummy trace intervals.

[0143] Of course, the dummy lines that are not adjacent to the high-voltage lines and low-voltage lines that are on the same straight line can also adopt other layouts, and the low-voltage lines that are not on the same straight line as the high-voltage lines can also adopt other layouts. The scope of protection of this invention should not be overly limited here.

[0144] Please see Figure 6 Displayed as Figure 5 The diagram shows the simulation results of the three-dimensional storage device. A high voltage HV = 22V is applied to the first voltage trace 401, and a low voltage LV = 0V is applied to the second voltage trace 402. The second voltage trace 402 and the third voltage trace 414 are connected by a connector 416, a dummy trace 107, a connector 114, a dummy trace 111, and a connector 115. The simulation results show that, due to the coupling effect, the voltage of the first dummy trace 406 is 13.14V, the voltage of the second dummy trace 407 is 5.8V, the voltage of the central dummy trace 405 is 7.8V, the voltage of the third dummy trace 408 is 13.08V, and the voltage of the dummy trace 412 is 5.9V. It can be seen that the maximum voltage difference occurs between the first voltage trace 401 and the third dummy trace 408, with a maximum voltage difference ΔV = (22 - 13.08)V = 8.92V. Compared to Figure 1 The maximum voltage difference of the routing layout shown is 15.5V. The routing layout of this embodiment greatly reduces the voltage difference between the routing lines, thereby effectively suppressing the TDDB effect.

[0145] The routing plane layout of the three-dimensional storage device in this embodiment is relative to... Figure 1 The routing planar layout shown is equivalent to cutting off the dummy routing 105, the second voltage routing 102, and the dummy routing 107. Cutting off the dummy routing 105 can disrupt the original relationship between the dummy routing 105 and the high-voltage and low-voltage routing. Cutting off the second voltage routing 102 is equivalent to turning a part of the original low-voltage routing into a dummy routing, which can disrupt the original relationship between the dummy routing 106 and the high-voltage and low-voltage routing. Cutting off the dummy routing 107 can reduce the length of the dummy routing 107 and further optimize the distribution of coupling voltage. Thus, the line-to-line breakdown voltage (Vbd) between the high-voltage routing and the dummy routing, or between the dummy routing and the low-voltage routing, can be effectively improved without increasing the spacing between the routing lines. This is beneficial for effectively controlling the chip area. Moreover, the new routing layout is only equivalent to setting small cut points in some routing lines and will not affect the original high-voltage and low-voltage routing lines.

[0146] Example 4

[0147] This embodiment uses essentially the same technical solution as Embodiment 3. The difference lies in that, in Embodiment 3, the first dummy trace has a relative portion with both the first voltage trace and the central dummy trace in the second direction X, and the fourth dummy trace has a relative portion with both the second voltage trace and the central dummy trace in the second direction X. In this embodiment, the first dummy trace has a relative portion with the first voltage trace in the second direction X but no relative portion with the central dummy trace in the second direction X, and the fourth dummy trace has a relative portion with the second voltage trace in the second direction X but no relative portion with the central dummy trace in the second direction X.

[0148] Please see Figure 7 The diagram shows the routing planar layout of the three-dimensional storage device in this embodiment. The three-dimensional storage device includes a first voltage trace 201, a second voltage trace 502, at least one central dummy trace 505, and multiple dummy traces. The first voltage trace 201 extends along a first direction Y. The first voltage trace 501, the second voltage trace 502, and the central dummy trace 505 are located on the same straight line, and the central dummy trace 505 is located between the first voltage trace 501 and the second voltage trace 502. The multiple dummy traces are distributed on both sides of the first voltage trace 501 and the second voltage trace 502.

[0149] Specifically, the voltage of the second voltage trace is lower than the voltage of the first voltage trace. The first voltage trace 501 is a high-voltage trace, and the second voltage trace 502 is a low-voltage trace.

[0150] As an example, the three-dimensional memory device includes a page-buffered high-voltage NMOS transistor. The drain of the transistor is connected to the lower part of the first voltage line 501 through a first contact portion 503, and the source of the transistor is connected to the lower part of the second voltage line 502 through a second contact portion 504.

[0151] As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.

[0152] Specifically, any dummy trace adjacent to the first voltage trace and the second voltage trace has a relative portion with only one of the first voltage trace and the second voltage trace in the second direction X, or has no relative portion with either the first voltage trace or the second voltage trace in the second direction X, wherein the second direction X is perpendicular to the first direction Y.

[0153] In this embodiment, the multiple dummy traces include a first dummy trace 506, a second dummy trace 507, a third dummy trace 508, a fourth dummy trace 509, and a fifth dummy trace 515. The first dummy trace 506 and the second dummy trace 507 are located on the same straight line. The third dummy trace 508, the fourth dummy trace 509, and the fifth dummy trace 515 are located on the same straight line, and the fifth dummy trace 515 is located between the third dummy trace 508 and the fourth dummy trace 509. The first dummy trace 506 and the third dummy trace 508 are located on opposite sides of the first voltage trace 501, and the second dummy trace 507 and the fourth dummy trace 509 are located on opposite sides of the second voltage trace 502.

[0154] Furthermore, the first dummy trace 506 and the first voltage trace 501 have opposing portions in the second direction X, but are not adjacent to the central dummy trace 505 and the second voltage trace 502 in the second direction X. The second dummy trace 507 has opposing portions in the second direction X with both the central dummy trace 505 and the second voltage trace 502. The third dummy trace 508 has opposing portions in the second direction X with both the first voltage trace 501 and the central dummy trace 505, but is not adjacent to the second voltage trace 502 in the second direction X. The fourth dummy trace 509 has opposing portions in the second direction X with the second voltage trace 502, but is not adjacent to the central dummy trace 505 in the second direction X. The dummy trace 515 has no opposing portions in the second direction X with either the first voltage trace or the second voltage trace.

[0155] As an example, the plurality of dummy traces also include dummy traces 510, 511, 512, and 513 that are not directly adjacent to the first voltage trace 501 or the second voltage trace 502.

[0156] As an example, the three-dimensional storage device further includes a third voltage trace 514, which is a low-voltage trace, and the voltage of the third voltage trace is equal to the voltage of the second voltage trace. The third voltage trace 514 is parallel to the second voltage trace 502, and the third voltage trace 514 and the second voltage trace 502 are separated by at least one of the aforementioned dummy trace intervals.

[0157] Of course, the dummy lines that are not adjacent to the high-voltage lines and low-voltage lines that are on the same straight line can also adopt other layouts, and the low-voltage lines that are not on the same straight line as the high-voltage lines can also adopt other layouts. The scope of protection of this invention should not be overly limited here.

[0158] The routing plane layout of the three-dimensional memory device in this embodiment optimizes the position of the breakpoints compared to the routing plane layout of the three-dimensional memory device in Embodiment 3. It further cuts off the coupling path between the first dummy trace and the central dummy trace, and further cuts off the coupling path between the central dummy trace and the fourth dummy trace. This can more effectively improve the line-to-line breakdown voltage (Vbd) between high-voltage traces and dummy traces, or between dummy traces and low-voltage traces, without increasing the spacing between traces. This is beneficial for effectively controlling the chip area. Moreover, the new routing layout is only equivalent to setting small breakpoints in some traces, and will not affect the original high-voltage traces and low-voltage traces.

[0159] Example 5

[0160] This embodiment provides a method for manufacturing a three-dimensional storage device, used to manufacture the three-dimensional storage device described in any one of Embodiments 1 to 4, comprising the following steps:

[0161] S1: Provide a substrate;

[0162] S2: A wiring layer is formed above the substrate. The wiring layer includes a first voltage line, a second voltage line, and multiple dummy lines. The second voltage line and the first voltage line are located on the same straight line, and the voltage of the second voltage line is lower than the voltage of the first voltage line. The multiple dummy lines are distributed on both sides of the first voltage line and the second voltage line. All dummy lines directly adjacent to the first voltage line are not directly adjacent to the second voltage line, and all dummy lines directly adjacent to the second voltage line are not directly adjacent to the first voltage line.

[0163] As an example, the wiring layer can be obtained by forming a conductive layer over the substrate and patterning the conductive layer.

[0164] As an example, the wiring layer can also be obtained by forming a mask layer with an opening pattern over the substrate and forming a conductive material in the opening pattern.

[0165] As an example, the plurality of dummy traces include a first dummy trace, a second dummy trace, a third dummy trace, and a fourth dummy trace adjacent to the first voltage trace and the second voltage trace. The first dummy trace and the second dummy trace are located on the same straight line. The third dummy trace and the fourth dummy trace are located on the same straight line. The first dummy trace and the third dummy trace are located on opposite sides of the first voltage trace and have opposite portions with the first voltage trace in the second direction X. The second dummy trace and the fourth dummy trace are located on opposite sides of the second voltage trace and have opposite portions with the second voltage trace in the second direction X.

[0166] As an example, the three-dimensional storage device further includes at least one central dummy trace, which is located on the same straight line as the first voltage trace and the second voltage trace, and is located between the first voltage trace and the second voltage trace.

[0167] As an example, the first dummy trace, the second dummy trace, the third dummy trace, and the fourth dummy trace all have a portion opposite to the center dummy trace in the second direction X. Alternatively, the first dummy trace and the fourth dummy trace do not have a portion opposite to the center dummy trace in the second direction X, but the second dummy trace and the third dummy trace all have a portion opposite to the center dummy trace in the second direction X.

[0168] As an example, the plurality of dummy traces also include a fifth dummy trace, which is located on the same straight line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.

[0169] As an example, the three-dimensional memory device includes a page-buffered high-voltage NMOS transistor, the drain of which is connected to the lower part of the first voltage line through a first contact portion, and the source of which is connected to the lower part of the second voltage line through a second contact portion.

[0170] As an example, the voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.

[0171] As an example, the routing layer further includes a third voltage trace, the voltage of which is equal to the voltage of the second voltage trace, the third voltage trace is parallel to the second voltage trace, and the third voltage trace and the second voltage trace are separated by at least one of the dummy trace intervals.

[0172] As an example, the third voltage trace is connected to the second voltage trace through at least one dummy trace and at least two connecting portions, and the two sides of the at least one connecting portion are respectively connected to the second voltage trace and one dummy trace, and the two sides of the at least one connecting portion are respectively connected to one dummy trace and the third voltage trace.

[0173] The fabrication method of the device in this embodiment can be used to fabricate any of the three-dimensional storage devices described in Embodiments 1 to 4. Different wiring layer designs can be achieved by simply changing the photolithography pattern. It has the advantages of simple process and no increase in manufacturing cost.

[0174] In summary, the three-dimensional memory device and its fabrication method of the present invention improve the layout of the traces so that dummy traces adjacent to high-voltage or low-voltage traces do not simultaneously face the high-voltage or low-voltage traces. This effectively increases the line-to-line breakdown voltage (Vbd) between high-voltage traces and dummy traces, or between dummy traces and low-voltage traces, without increasing the spacing between traces. This not only effectively controls the chip area but also does not affect the original high-voltage and low-voltage traces. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0175] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a first voltage trace extending in a first direction; a second voltage trace located on the same line as the first voltage trace, and the voltage of the second voltage trace is lower than the voltage of the first voltage trace; a plurality of dummy traces distributed on both sides of the first voltage trace and the second voltage trace and extending in the first direction, wherein any dummy trace adjacent to the first voltage trace or the second voltage trace satisfies that the dummy trace only has a relative part with one of the first voltage trace and the second voltage trace in a second direction perpendicular to the first direction; wherein the semiconductor device is provided with a page buffer high-voltage NMOS transistor, the drain of the transistor is connected to the lower side of the first voltage trace through a first contact, and the source of the transistor is connected to the lower side of the second voltage trace through a second contact; The semiconductor device further comprises at least one center dummy trace located on the same line as the first voltage trace and the second voltage trace and between the first voltage trace and the second voltage trace.

2. The semiconductor device of claim 1, wherein: The plurality of dummy traces comprises a first dummy trace, a second dummy trace, a third dummy trace and a fourth dummy trace adjacent to the first voltage trace and the second voltage trace, the first dummy trace and the second dummy trace are located on the same line, the third dummy trace and the fourth dummy trace are located on the same line, the first dummy trace and the third dummy trace are respectively located on the opposite sides of the first voltage trace and have a relative part with the first voltage trace in the second direction, and the second dummy trace and the fourth dummy trace are respectively located on the opposite sides of the second voltage trace and have a relative part with the second voltage trace in the second direction.

3. The semiconductor device of claim 2, wherein: The first dummy trace, the second dummy trace, the third dummy trace and the fourth dummy trace all have a relative part with the center dummy trace in the second direction.

4. The semiconductor device of claim 3, wherein: The plurality of dummy traces further comprises a fifth dummy trace, the fifth dummy trace is located on the same line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.

5. The semiconductor device of claim 2, wherein: The first dummy trace and the fourth dummy trace do not have a relative part with the center dummy trace in the second direction, and the second dummy trace and the third dummy trace have a relative part with the center dummy trace in the second direction.

6. The semiconductor device of claim 5, wherein: The plurality of dummy traces further comprises a fifth dummy trace, the fifth dummy trace is located on the same line as the third dummy trace and the fourth dummy trace, and the fifth dummy trace is located between the third dummy trace and the fourth dummy trace.

7. The semiconductor device of claim 1, wherein: The voltage of the first voltage trace is greater than or equal to 20V, and the voltage of the second voltage trace is less than or equal to 10V.

8. The semiconductor device of claim 1, wherein: The semiconductor device further comprises a third voltage trace, a voltage of the third voltage trace is equal to a voltage of the second voltage trace, the third voltage trace is parallel to the second voltage trace, and the third voltage trace is spaced from the second voltage trace by at least one dummy trace.

9. The semiconductor device of claim 8, wherein: The third voltage trace is connected to the second voltage trace by at least one dummy trace and at least two connection portions, two sides of at least one connection portion are connected to the second voltage trace and a dummy trace respectively, and two sides of at least one connection portion are connected to a dummy trace and the third voltage trace respectively.

10. A method of fabricating a semiconductor device, characterized by, The method comprises the following steps: providing a substrate; forming a trace layer above the substrate, the trace layer comprising a first voltage trace, a second voltage trace and a plurality of dummy traces, wherein the second voltage trace and the first voltage trace are located on the same line, the second voltage trace and the first voltage trace extend in a first direction, and a voltage of the second voltage trace is lower than a voltage of the first voltage trace, the plurality of dummy traces are distributed on both sides of the first voltage trace and the second voltage trace and extend in the first direction, and any dummy trace adjacent to the first voltage trace or the second voltage trace satisfies that the dummy trace has a relative part to only one of the first voltage trace and the second voltage trace in a second direction, the second direction being perpendicular to the first direction; wherein a page buffer high-voltage NMOS transistor is provided in the substrate, the first voltage trace is connected above a drain of the transistor by a first contact portion, and the second voltage trace is connected above a source of the transistor by a second contact portion; The semiconductor device further comprises at least one center dummy trace, the center dummy trace is located on the same line with the first voltage trace and the second voltage trace, and between the first voltage trace and the second voltage trace.

11. The method of fabricating a semiconductor device according to claim 10, wherein: The trace layer is obtained by forming a conductive layer above the substrate and patterning the conductive layer.

12. The method of fabricating a semiconductor device of claim 10, wherein: The trace layer is obtained by forming a mask layer with an opening pattern above the substrate and forming a conductive material in the opening pattern.

13. The method of fabricating a semiconductor device of claim 10, wherein: The plurality of dummy traces comprises a first dummy trace, a second dummy trace, a third dummy trace and a fourth dummy trace adjacent to the first voltage trace and the second voltage trace, the first dummy trace and the second dummy trace are located on the same line, the third dummy trace and the fourth dummy trace are located on the same line, the first dummy trace and the third dummy trace are respectively located on opposite sides of the first voltage trace and have a relative part to the first voltage trace in the second direction, and the second dummy trace and the fourth dummy trace are respectively located on opposite sides of the second voltage trace and have a relative part to the second voltage trace in the second direction.

14. The method of fabricating a semiconductor device according to Claim 13, wherein: The first dummy trace, the second dummy trace, the third dummy trace and the fourth dummy trace all have a relative part to the center dummy trace in the second direction.

15. The method of fabricating a semiconductor device according to claim 14, wherein: The plurality of dummy wires further include a fifth dummy wire, the fifth dummy wire is located on the same line with the third dummy wire and the fourth dummy wire, and the fifth dummy wire is located between the third dummy wire and the fourth dummy wire.

16. The method of fabricating a semiconductor device of claim 13, wherein: The first dummy wire and the fourth dummy wire have no relative parts with the center dummy wire in the second direction, and the second dummy wire and the third dummy wire have relative parts with the center dummy wire in the second direction.

17. The method of fabricating a semiconductor device according to claim 16, wherein: The plurality of dummy wires further include a fifth dummy wire, the fifth dummy wire is located on the same line with the third dummy wire and the fourth dummy wire, and the fifth dummy wire is located between the third dummy wire and the fourth dummy wire.

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