Display substrate, display module and display device

Abstract

The present disclosure provides a display substrate, a display module, and a display device, belonging to the field of display technology. The display substrate of the present disclosure includes a silicon-based substrate and a pixel unit arranged on the silicon-based substrate; the pixel unit includes a pixel driving circuit and a light-emitting device; the pixel driving circuit includes a first thin film transistor, a second thin film transistor, and a third thin film transistor arranged on the silicon-based substrate; the silicon-based substrate includes a first well and a second well arranged along a first direction; a first deep well is included between the silicon-based substrate and the second well; the first deep well is arranged around the second well; the second well is provided with a first active layer of the first thin film transistor; a first conductive layer is provided on the silicon-based substrate; the first conductive layer includes a first source electrode and a first transfer electrode of the first thin film transistor; the first source electrode is connected to the source contact area of ​​the first active layer through a first connecting via hole; the first transfer electrode is connected to the second well contact area of ​​the second well through a second connecting via hole; and the first source electrode is electrically connected to the first transfer electrode.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate, a display module, and a display device. Background Art

[0002] With the development of organic light-emitting diodes (OLEDs), OLEDs are increasingly being used in various display devices due to their advantages such as self-luminescence, wide viewing angle, almost infinite contrast, low power consumption, and extremely high response speed. With market demand and a growing number of application scenarios, the requirements for OLED devices are becoming increasingly stringent, with greater brightness, higher contrast, and higher pixel density (PPI) becoming one of the main requirements. How to achieve high brightness, high contrast, and high pixel density in display substrates has become an urgent problem to be solved. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provide a display substrate, a display module and a display device with high brightness, high contrast and high pixel density.

[0004] In a first aspect, an embodiment of the present disclosure includes a display substrate comprising a silicon-based substrate and a plurality of pixel units disposed on the silicon-based substrate; the pixel units comprising a pixel driving circuit and a light-emitting device;

[0005] The pixel driving circuit includes a first thin film transistor, a second thin film transistor and a third thin film transistor provided on a silicon substrate; the first thin film transistor includes a first source electrode, a first drain electrode, a first gate electrode and a first active layer; the second thin film transistor includes a second active layer; and the third thin film transistor includes a third active layer;

[0006] The silicon-based substrate includes a first well and a second well arranged along a first direction; a first deep well is further included between the silicon-based substrate and the second well; the first deep well is arranged around the second well;

[0007] The first active layer is provided in the second well; the second active layer and the third active layer are provided in the first well;

[0008] A first conductive layer is also provided on the silicon-based substrate; the first conductive layer includes a first source and a first transfer electrode; the first source is connected to the source contact area of ​​the first active layer through a first connecting via; the first transfer electrode is connected to the second well contact area of ​​the second well through a second connecting via; the first source is electrically connected to the first transfer electrode.

[0009] The third active layer and the second active layer are arranged in the same first well.

[0010] Among them, two first wells and one second well are arranged along the first direction on the silicon-based substrate; the third active layer and the second active layer are arranged in different first wells; the second well surrounds the first well in which the third active layer is arranged; and the first deep well surrounds the second well.

[0011] Wherein, the display substrate further comprises a plurality of repeating units arranged in an array on a silicon-based substrate;

[0012] The repeating unit includes two pixel units arranged side by side along a first direction;

[0013] The repeating unit is provided with two second wells along a first direction on the silicon-based substrate and a first well is sandwiched between the two second wells; a first deep well is provided between the second well and the silicon-based substrate, and the first deep well is provided around one of the second wells;

[0014] In the first direction, two third active layers in the first well sandwich two second active layers.

[0015] The repeating units arranged along the second direction share the first well.

[0016] Wherein, the display substrate further comprises a plurality of repeating units arranged in an array on the base substrate;

[0017] The repeating unit includes two pixel units arranged side by side along a first direction;

[0018] The repeating unit is provided with two second wells in the silicon substrate along a first direction and three first wells are sandwiched between the two second wells;

[0019] The third active layer is arranged in the first well close to the second well; two second active layers are arranged in the middle first well along the first direction;

[0020] The second well surrounds the first well of the third active layer; the first deep well is arranged around one of the second wells;

[0021] In the first direction, two of the first deep wells sandwich one of the first wells.

[0022] The repeating units arranged along the second direction share the first well located in the middle.

[0023] Wherein, the first conductive layer further includes a first drain electrode; the first drain electrode is electrically connected to the drain contact region of the first active layer through a third connecting via hole;

[0024] The first drain electrodes of adjacent first thin film transistors are electrically connected in the first conductive layer.

[0025] The first conductive layer further includes a first conductive pattern; the first conductive pattern at least partially includes a first power signal line; and the first drain is electrically connected to the first conductive pattern.

[0026] In which, the display substrate also includes a third conductive layer on the side away from the first conductive layer; the third thin film transistor includes a third drain; the third drain is arranged in the third conductive layer; the third drain is electrically connected to the drain contact area of ​​the third active layer through a fourth connecting via; the light-emitting device includes a first electrode, a light-emitting layer and a second electrode; the first electrode is electrically connected to the third drain.

[0027] Wherein, the display substrate further includes:

[0028] a second conductive layer located between the silicon-based substrate and the first conductive layer; the second conductive layer comprising the first gate, the second gate of the second thin film transistor, and the third gate of the third thin film transistor;

[0029] a first gate insulating layer, located between the silicon-based substrate and the second conductive layer;

[0030] a first interlayer insulating layer, located between the first conductive layer and the second conductive layer;

[0031] a second interlayer insulating layer, located on a side of the first conductive layer facing away from the silicon-based substrate;

[0032] The first connection via, the second connection via, and the third connection via penetrate the first interlayer insulating layer and the first gate insulating layer; and the fourth connection via penetrates the second interlayer insulating layer, the first interlayer insulating layer, and the first gate insulating layer.

[0033] The display substrate further includes a first encapsulation layer, a color filter layer, and a second encapsulation layer which are sequentially arranged away from the second electrode of the light-emitting device.

[0034] In a second aspect, the embodiments of the present disclosure further include a display module, which includes any of the display substrates described above.

[0035] Wherein, the display module also includes a flexible printed circuit board and a cover glass.

[0036] In a third aspect, an embodiment of the present disclosure further includes a display device, which includes any of the display modules described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A circuit diagram provided in an embodiment of the present disclosure;

[0038] Figure 2 for Figure 1 A driving timing diagram of the pixel circuit shown;

[0039] Figure 3 A schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure;

[0040] Figure 4 A schematic cross-sectional view of another display substrate provided in an embodiment of the present disclosure;

[0041] Figure 5 A schematic diagram of a transistor arrangement provided in an embodiment of the present disclosure;

[0042] Figure 6 This is a schematic diagram of another transistor arrangement provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0045] Figure 1 A circuit diagram is provided in an embodiment of the present disclosure, such as Figure 1 As shown, the pixel driving circuit in the embodiment of the present disclosure includes a first thin film transistor N1, a second thin film transistor P1, a third thin film transistor P2, a storage capacitor C and a light-emitting device D; the first thin film transistor N1 includes a first source N11, a first drain N12 and a first gate N13; the second thin film transistor P1 includes a second source, a second drain and a second gate; the third thin film transistor P2 includes a third source, a third drain P22 and a third gate P23; the storage capacitor C includes a first plate and a second plate; the light-emitting device D includes a first electrode.

[0046] It should be noted that the transistors used in the embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In addition, according to the characteristics of the transistors, transistors can be divided into N-type and P-type. When a P-type transistor is used, the source and drain are conductive when a low-level signal is input to the gate; when an N-type transistor is used, the source and drain are conductive when a high-level signal is input to the gate. In the embodiments of the present disclosure and the subsequent description, the first thin-film transistor N1 in the pixel circuit is an N-type transistor, and the second thin-film transistor P1 and the third thin-film transistor P2 are P-type transistors. However, the transistors in the embodiments of the present disclosure are not limited to using an N-type transistor for the first thin-film transistor N1 and a P-type transistor for the second thin-film transistor P1 and the third thin-film transistor P2. Those skilled in the art can also make adjustments according to actual needs, for example, using a P-type thin-film transistor for the first thin-film transistor N1 and an N-type transistor for the second thin-film transistor P1 and the third thin-film transistor P2 to implement the functions of one or more transistors in the embodiments of the present disclosure.

[0047] like Figure 1 As shown, the first thin-film transistor N1 is used as a driving transistor in the circuit, the second thin-film transistor P1 is used as a data writing transistor in the circuit, and the third thin-film transistor P2 is used as a light-emitting control transistor in the circuit. The connection point between the first gate electrode N13 of the first thin-film transistor N1, the second drain electrode of the second thin-film transistor P1, and the first plate of the storage capacitor C is a first node; the first drain electrode N12 of the first thin-film transistor N1 is connected to the first power supply voltage signal terminal VDD; the second source electrode of the second thin-film transistor P1 is connected to the data signal terminal VData, and the second gate electrode is connected to the scan signal terminal Gate; the third gate electrode P23 of the third thin-film transistor P2 is connected to the first reference voltage signal terminal VSS1, and the third drain electrode P22 is connected to the first electrode of the light-emitting device D; the second plate of the storage capacitor C is connected to the second reference voltage signal terminal VSS2; and the second electrode of the light-emitting device D is connected to the third reference voltage signal terminal VSS3.

[0048] Figure 2 for Figure 1 A driving timing diagram of the pixel circuit shown in FIG. Figure 2As shown, the pixel circuit operates as follows: a data signal is input to the data signal terminal VData, while a low-level signal is input to the scan signal terminal Gate. The second thin-film transistor P1, controlled by the low-level signal, turns on and transmits the data signal to the storage capacitor C, which stores the data signal. The first thin-film transistor N1, controlled by the data signal stored in the storage capacitor C, turns on, connecting the gate and drain of the first thin-film transistor N1. The third gate P23 of the third thin-film transistor P2 is connected to the first reference voltage signal terminal VSS1, which can be a reference ground. Therefore, the gate voltage of the third thin-film transistor P2 remains low, and the third thin-film transistor P2 is always on. During this time, the first thin-film transistor N1 converts the voltage of the first power supply voltage signal into a driving current, forming a current loop for the light-emitting device D between the first power supply voltage terminal and the third reference voltage signal terminal VSS3, driving the light-emitting device D to emit light. The voltage applied to the first electrode of the light-emitting device D is the voltage input to the data signal terminal VData minus the threshold voltage of the first thin-film transistor N1.

[0049] Furthermore, when the first and second electrodes of the OLED device are short-circuited, a latch-up effect may occur, causing circuit failure or damage. When the first and second electrodes of the OLED device are short-circuited, the parasitic PN junction at the drain of the third thin-film transistor P2 becomes reverse biased, thereby preventing the latch-up effect. Therefore, the design of the pixel driver circuit in the disclosed embodiment can prevent defects in the entire display area caused by a short circuit between the anode and cathode of the OLED device in an individual pixel unit 1.

[0050] In the disclosed embodiment, the first source electrode N11 of the first thin-film transistor N1 is connected to the substrate where the first active layer of the first thin-film transistor N1 is located to eliminate the offset effect. Experimental testing has shown that before connecting the first source electrode N11 to the substrate, the threshold voltage of the first thin-film transistor N1 increases to approximately 2.8V. When the data signal voltage is 8V, the maximum voltage applied to the first electrode of the light-emitting device D is approximately 5.2V (8V-2.8V). Connecting the first source electrode N11 to the substrate eliminates the offset effect, so the threshold voltage of the first thin-film transistor N1 drops to approximately 1.1V. When the data signal voltage is 8V, the maximum voltage applied to the first electrode of the light-emitting device D is approximately 6.9V (8V-1.1V). Therefore, connecting the first source electrode N11 to the substrate eliminates the offset effect and increases the maximum voltage that can be applied to the first electrode of the light-emitting device D. Due to the increase in the maximum voltage that can be applied to the first electrode, the voltage span range of the first electrode is also expanded, and the voltage range that can be applied to the first electrode is 0.58V to 6.9V. By expanding the range of the voltage that can be applied to the first electrode, the display contrast is improved.

[0051] With the development of organic light-emitting diodes (OLEDs), OLEDs have been increasingly used in various display devices due to their advantages such as self-luminescence, wide viewing angle, almost infinite contrast, low power consumption, and extremely high response speed. With market demand and a growing number of application scenarios, the requirements for OLED devices are becoming increasingly higher, among which a larger brightness range and a higher pixel density (PPI) have become one of the main requirements. How to increase the span range of the anode voltage provided by the pixel drive circuit to the OLED device to achieve high-brightness display and high-brightness range display, and how to reduce the area of ​​the pixel unit 1 and improve the PPI have become urgent problems to be solved.

[0052] The bias effect mainly comes from the influence of the bias voltage between the substrate and the source of the thin film transistor on the threshold voltage of the thin film transistor: taking NMOS as an example, when the source potential of the transistor is higher than the substrate potential, more holes in the surface layer below the gate will be attracted to the substrate, which will increase the number of immobile negative ions left in the depletion layer, increase the width of the depletion layer, and increase the surface charge density Qdep in the depletion layer, thereby increasing the threshold voltage of the thin film transistor and causing the maximum value of the driving voltage provided to the first electrode of the light-emitting device D in the pixel driving circuit to become lower.

[0053] In light of this, the present disclosure provides a display substrate. During the manufacture of the display substrate, the source electrode of a first thin-film transistor N1 used for driving the light is connected to the substrate and maintained at the same potential. This method eliminates the offset effect, prevents the threshold voltage of the thin-film transistor from rising, and reduces the voltage loss of the data signal in the pixel driving circuit. This increases the maximum voltage supplied by the pixel driving circuit to the anode of the light-emitting device D, and increases the voltage span applied to the anode, thereby improving the maximum brightness of the light-emitting device D and expanding the brightness range.

[0054] The display substrate of the embodiment of the present disclosure is described below with reference to the accompanying drawings and specific embodiments.

[0055] In a first aspect, the present disclosure provides a display substrate. Figure 3 A schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure; Figure 4 FIG. 1 is a schematic cross-sectional view of another display substrate provided in an embodiment of the present disclosure; FIG. Figure 3 、 4As shown, the display substrate includes a silicon-based substrate P_SUB and a plurality of pixel units 1 arranged on the silicon-based substrate P_SUB; the pixel unit 1 includes a pixel driving circuit and a light-emitting device D; the pixel driving circuit includes a first thin film transistor N1, a second thin film transistor P1 and a third thin film transistor P2 arranged on the silicon-based substrate P_SUB; the first thin film transistor N1 includes a first source N11, a first drain N12, a first gate N13 and a first active layer; the second thin film transistor P1 includes a second active layer; the third thin film transistor P2 includes a third active layer; the silicon-based substrate P_SUB includes a first well NW and a second well PW arranged along a first direction; a first deep well DNW is further included between the silicon-based substrate P_SUB and the second well PW; the first deep well DNW is arranged around the second well PW; a first active layer is arranged in the second well PW; and the first well NW is provided with a second active layer and a third active layer.

[0056] It should be noted that the active layer of the P-type transistor needs to be made in the N-well, and the active layer of the N-type transistor needs to be made in the P-well. In the embodiment of the present disclosure, the first thin-film transistor N1 is an N-type thin-film transistor, and the second thin-film transistor P1 and the third thin-film transistor P2 are P-type thin-film transistors. Therefore, the first well NW in the embodiment of the present disclosure is an N-well, the second well PW is a P-well, and the first deep well DNW is a deep N-well. The first well NW is an N-well, which is made of a low-concentration doped N-type material; the second well PW is a P-well, which is made of a low-concentration doped P-type material. The first deep well DNW is a deep N-well, which is made of a low-concentration doped N-type material. The silicon-based substrate P_SUB can be a P-type substrate or an N-type substrate. In the present disclosure, the silicon-based substrate P_SUB adopts a P-type substrate. The active layer of the N-type transistor can be directly set on the P-type substrate. The first active layer of the corresponding first thin-film transistor N1 of the present application can be directly set on the silicon-based substrate P_SUB. However, since the first source N11 of the first thin-film transistor N1 needs to be connected to its substrate, that is, electrically connected to the second well PW where the first active layer is set, it is necessary to set a first deep well DNW between the second well PW and the substrate for isolation. When multiple N-type transistors are made on the same P-type silicon-based substrate P_SUB, connecting the source and substrate of the N-type transistor will affect each other. Therefore, it is necessary to make the N-type transistor separately in a P-well and surround it with a deep N-well to isolate it from the P-type silicon-based substrate P_SUB, thereby preventing noise interference caused by the common substrate.

[0057] Furthermore, a first conductive layer 21 is provided on the silicon substrate P_SUB. The first conductive layer 21 includes a first source electrode N11 and a first transfer electrode 31. The first source electrode N11 is connected to the source contact region of the first active layer via a first connection via Via1. The first transfer electrode 31 is connected to the second well contact region of the second well PW via a second connection via Via2. The first source electrode N11 is electrically connected to the first transfer electrode 31. The first transfer electrode 31 is directly electrically connected to the second well PW (i.e., a region of lightly doped P-type material) via the second connection via Via2. By connecting the first source electrode N11 of the first thin-film transistor N1, which serves as a driver transistor, to the substrate, the offset effect can be completely eliminated, preventing the threshold voltage of the thin-film transistor from rising. This reduces data signal voltage loss in the pixel driver circuit, thereby increasing the maximum voltage supplied to the anode of the light-emitting device D by the pixel driver circuit and broadening the voltage span applied to the anode. This improves the maximum brightness of the light-emitting device D, expands the brightness range, and enhances the display contrast.

[0058] In some examples, the third active layer and the second active layer are disposed in the same first well NW. In the disclosed embodiments, the second thin-film transistor P1 and the third thin-film transistor P2 are both P-type transistors, and their sources do not need to be electrically connected to the substrate during fabrication. Therefore, the second active layer of the second thin-film transistor P1 and the third active layer of the third thin-film transistor P2 can be disposed in the same first well NW.

[0059] In some examples, two first wells NW are disposed along a first direction on a silicon substrate P_SUB; the third active layer and the second active layer are disposed in different first wells NW; the second well PW surrounds the first well NW in which the third active layer is disposed; and the first deep well DNW surrounds the second well PW. When the power supply voltage connected to the pixel driver circuit is high, such as 8V, coupling noise may be generated between adjacent and separate N-type and P-type transistors on the silicon substrate P_SUB. Therefore, the active layers of the second thin-film transistor P1 and the third thin-film transistor P2 are disposed in separate first wells NW, respectively. Furthermore, a first well NW and a second well PW are disposed in the first deep well DNW, and the third active layer is disposed in the first well NW of the first deep well DNW. Because both the first well NW and the first deep well DNW are doped with N-type material, to separate them, during fabrication, the second well PW surrounds the first well NW, and the first deep well DNW surrounds the second well PW.

[0060] Furthermore, analog voltages must be connected to the silicon substrate P_SUB, the first deep well DNW, and the first well NW. The first deep well DNW and the first well NW are connected to the same potential, which can be an analog voltage input from the outside to the pixel driver circuit. The potential in the P-type doped region must be lower than that in the N-type doped region. Therefore, the silicon substrate P_SUB must be connected to a lower potential than the first deep well DNW. For example, when the external input voltage is 8V, the silicon substrate P_SUB must be connected to an analog voltage of -8V. Similarly, when the external input voltage is 6V, the silicon substrate P_SUB must be connected to an analog voltage of -6V. Alternatively, the silicon substrate P_SUB can be connected to a reference ground.

[0061] In some examples, Figure 5 A schematic diagram of a transistor arrangement provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the display substrate also includes a plurality of repeating units 11 arranged in an array on a silicon-based substrate P_SUB; the repeating unit 11 includes two pixel units 1 arranged along a first direction; the repeating unit 11 sets two second wells PW on the silicon-based substrate P_SUB along the first direction and sandwiches a first well NW between the two second wells PW; a first deep well DNW is set between the second well PW and the silicon-based substrate P_SUB, and the first deep well DNW is set around a second well PW; in the first direction, two second active layers are sandwiched between two third active layers in the first well NW. In order to improve the pixel density (PPI) of the display substrate, the first thin film transistor N1 is arranged together, and the second thin film transistor P1 and the third thin film transistor P2 are arranged together; in the first direction, the repeating unit 11 is provided with second wells PW surrounding the first deep well DNW on both sides, and the first well NW is provided in the middle, and the second wells PW of adjacent repeating units 11 are provided adjacently; therefore, the first thin film transistor N1 which is an N-type transistor is provided in a concentrated area on the display substrate, and the active layers of the second thin film transistor P1 and the third thin film transistor P2 which are both P-type transistors can be made in a first well NW which is an N-well. In this way, some N-type transistors and some P-type transistors are provided in a concentrated manner, and multiple areas where N-type transistors are provided and multiple areas where P-type transistors are provided are alternately provided on the display substrate. This method optimizes the arrangement of transistors on the silicon-based substrate P_SUB, and also realizes a more reasonable arrangement of pixel units 1 on the display substrate.

[0062] Furthermore, the repeating units 11 arranged along the second direction share a common first well NW. The second active layer and third active layer of the second thin-film transistor P1 and the third thin-film transistor P2 of the repeating units 11 arranged along the second direction, which are P-type transistors, are arranged in the same first well NW, further optimizing the arrangement of the transistors in the pixel drive circuit and achieving a more reasonable arrangement of the pixel units 1 on the display substrate. The transistors in the pixel drive circuit of the pixel unit 1 adopt the above arrangement, which can achieve a pixel spacing of 6.3μm in the pixel unit 1. The size of the first electrode of the light-emitting device D connected to the pixel drive circuit is 4.2μm x 3.15μm, and the area of ​​the first electrode is approximately 13.23 square microns, thereby improving the pixel density of the display substrate.

[0063] In some examples, Figure 6 This is another transistor arrangement diagram provided in an embodiment of the present disclosure, such as Figure 6As shown, the display substrate also includes a plurality of repeating units 11 arranged in an array on the base substrate; the repeating unit 11 includes two pixel units 1 arranged side by side along the first direction; the repeating unit 11 sets two second wells PW on the silicon-based substrate P_SUB along the first direction and sandwiches three first wells NW between the two second wells PW; the third active layer is set in the first well NW close to the second well PW; in the first well NW located in the middle, two second active layers are set along the first direction; the second well PW surrounds the first well NW in which the third active layer is set; the first deep well DNW is set around a second well PW; in the first direction, two first deep wells DNW sandwich a first well NW. When the power supply voltage connected to the pixel driver circuit is high, for example, when an 8V voltage is connected to the pixel driver circuit, coupling noise may be generated by adjacent and separately arranged N-type transistors and P-type transistors on the silicon substrate P_SUB. Therefore, the active layer of the second thin-film transistor P1 and the active layer of the third thin-film transistor P2 are respectively arranged in different first wells NW, and a first well NW and a second well PW are arranged in the first deep well DNW, and the third active layer is arranged in the first well NW arranged in the first deep well DNW. Because the first well NW and the first deep well DNW are both N-type material doped regions, in order to separate the two, during fabrication, the second well PW is fabricated around the first well NW, and the first deep well DNW is fabricated around the second well PW. In order to improve the pixel density (PPI) of the display substrate, the first thin film transistor N1 is arranged adjacent to each other, and the second thin film transistor P1 and the third thin film transistor P2 are arranged adjacent to each other; first deep wells DNW surrounding the second well PW are arranged on both sides of the repeating unit 11 in the first direction, wherein the second well PW also surrounds a first well NW in which a third active layer is arranged, and the first well NW sandwiched by the two first deep wells DNW is provided with two second active layers along the first direction; the second wells PW of adjacent repeating units 11 are arranged adjacent to each other; therefore, the first thin film transistors N1, which are N-type transistors, are arranged in a concentrated area on the display substrate, and the active layers of the multiple second thin film transistors P1, which are all P-type transistors, can be fabricated in a first well NW, which is an N-well. In this way, some N-type transistors and some P-type transistors are arranged in a concentrated manner, and multiple areas for N-type transistors and multiple areas for P-type transistors are alternately arranged on the display substrate. This method optimizes the arrangement of transistors on the silicon-based substrate P_SUB and also achieves a more reasonable arrangement of pixel units 1 on the display substrate.

[0064] In some examples, the repeating units 11 arranged along the second direction share a common first well NW sandwiched between two first deep wells DNW. The second active layer of the second thin-film transistor P1, which is a P-type transistor in the repeating units 11 arranged along the second direction, is arranged in the same first well NW, further optimizing the arrangement of transistors in the pixel drive circuit and achieving a more reasonable arrangement of the pixel units 1 on the display substrate. The transistors in the pixel drive circuit of the pixel unit 1 adopt the above arrangement, which can make the pixel spacing of the pixel unit 1 6.3μm. The size of the first electrode of the light-emitting device D connected to the pixel drive circuit is 4.2μm x 3.15μm, and the area of ​​the first electrode is approximately 13.23 square microns, thereby improving the pixel density of the display substrate.

[0065] In some examples, the first conductive layer 21 further includes a first drain electrode N12; the first drain electrode N12 is electrically connected to the drain contact region of the first active layer through a third connection via Via3; and the first drain electrodes N12 of adjacent first thin-film transistors N1 are electrically connected in the first conductive layer 21. Adjacent repeating units 11 have adjacent first thin-film transistors N1; therefore, during fabrication, the drain electrodes of adjacent first thin-film transistors N1 used for driving can be connected to the same power signal line.

[0066] In some examples, the first conductive layer 21 further includes a first conductive pattern 32; the first conductive pattern 32 at least partially includes a first power signal line; and the first drain electrode N12 is electrically connected to the first conductive pattern 32. The first conductive pattern 32 is formed on the first conductive layer 21, and a portion of the first conductive pattern 32 serves as a first power signal line for providing a driving voltage to the pixel driving circuit. Two adjacent first drain electrodes N12 are connected to the same first power signal line.

[0067] In some examples, the display substrate further includes a third conductive layer 23 on a side facing away from the first conductive layer 21; the third thin-film transistor P2 includes a third drain electrode P22; the third drain electrode P22 is disposed in the third conductive layer 23; the third drain electrode P22 is electrically connected to the drain contact region of the third active layer through a fourth connection via Via4; the light-emitting device D includes a first electrode, a light-emitting layer, and a second electrode; the first electrode is electrically connected to the third drain electrode P22. The third drain electrode P22 of the third thin-film transistor P2 is used as an output terminal, so the third drain electrode P22 is connected to the first electrode of the light-emitting device D to drive the light-emitting device D to emit light. The stacked structure in the embodiment of the present disclosure is merely an exemplary structure, and those skilled in the art may also make adjustments according to actual needs, such as adding other conductive layers, insulating layers, or other functional layers (not shown in the figure) to the third conductive layer 23 and the silicon-based substrate P_SUB.

[0068] In some examples, such as Figure 3 、 Figure 4As shown, the display substrate also includes: a second conductive layer 22, located between the silicon-based substrate P_SUB and the first conductive layer 21; the second conductive layer 22 includes a first gate N13, a second gate of the second thin film transistor P1 and a third gate P23 of the third thin film transistor P2; a first gate insulating layer GI1, located between the silicon-based substrate P_SUB and the second conductive layer 22; a first interlayer insulating layer ILD1, located between the first conductive layer 21 and the second conductive layer 22; a second interlayer insulating layer ILD2, located on the side of the first conductive layer 21 away from the silicon-based substrate P_SUB; a first connecting via Via1, a second connecting via Via2 and a third connecting via Via3 penetrate the first interlayer insulating layer ILD1 and the first gate insulating layer GI1; a fourth connecting via Via4 penetrates the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1 and the first gate insulating layer GI1. The stacked structure in the embodiment of the present disclosure is only an exemplary structure, and those skilled in the art can also adjust it according to actual needs, such as adding other conductive layers, insulating layers or other functional layers (not shown in the figure) to the first conductive layer 21 and the silicon-based substrate P_SUB.

[0069] In some examples, the display substrate further includes a first encapsulation layer, a color filter layer, and a second encapsulation layer, arranged in sequence, facing away from the second electrode of the light-emitting device D. The first electrode of the light-emitting device D is generally made of ITO, which has high transmittance and a high work function. The light-emitting layer of the light-emitting device D is typically made of an organic material. Leveraging the luminescent properties of organic materials, voltage or current excites holes and electrons to form excitons, resulting in luminescence. A second electrode is disposed above the light-emitting layer. The second electrode is a transparent structure and located below the first encapsulation layer. The second electrode can be made of one or more alloys selected from Mg and Ag. A color filter layer is also disposed on the side of the first encapsulation layer facing away from the second electrode. The second encapsulation layer is disposed between the second encapsulation layer and the first encapsulation layer, corresponding to the light-emitting layer, to achieve a colored display of the emitted light. The second encapsulation layer, in conjunction with the first encapsulation layer, effectively encapsulates the OLED device, effectively blocking moisture and oxygen, thereby protecting the device and extending its life. The color filter layer complements the light-emitting layer and, disposed above the color filter layer, protects the color filter layer. The first encapsulation layer and the second encapsulation layer can be made of one or more combinations of organic materials and inorganic materials with good sealing properties, such as silicon oxide, silicon nitride, etc., to protect the OLED device structure and achieve a good sealing effect.

[0070] It should be noted that the present disclosure does not further limit the materials of the first electrode, light-emitting layer and second electrode of the light-emitting device D and the first packaging layer, color filter layer and second packaging layer of the display substrate. Those skilled in the art can select appropriate materials according to actual needs.

[0071] In a second aspect, the embodiments of the present disclosure further include a display module, which includes any of the above-mentioned display substrates.

[0072] In some examples, the display module also includes a flexible printed circuit board (FPCB) and cover glass. The cover glass effectively encapsulates the OLED device, effectively blocking moisture and oxygen, thereby protecting the device and extending its lifespan. The cover glass is a transparent material, for example, a high-transmittance plain glass. The FPCB is electrically connected to the display substrate, enabling the transmission of external signals and transferring external voltage to the pixel driver circuit, providing driving voltage for the pixel driver circuit.

[0073] In a third aspect, embodiments of the present disclosure further include a display device comprising any of the above-mentioned display modules. The display device can be a small display device such as a mobile phone or a watch, or a large display device such as a television or a computer.

[0074] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate comprising a silicon-based substrate and a plurality of pixel units disposed on the silicon-based substrate; the pixel units comprising a pixel driving circuit and a light-emitting device; The pixel driving circuit includes a first thin film transistor, a second thin film transistor and a third thin film transistor provided on a silicon substrate; the first thin film transistor includes a first source electrode, a first drain electrode, a first gate electrode and a first active layer; The second thin film transistor includes a second active layer; the third thin film transistor includes a third active layer; The silicon-based substrate includes a first well and a second well arranged along a first direction; a first deep well is further included between the silicon-based substrate and the second well; the first deep well is arranged around the second well; The first active layer is provided in the second well; the second active layer and the third active layer are provided in the first well; A first conductive layer is further provided on the silicon-based substrate; the first conductive layer includes a first source electrode and a first transfer electrode; The first source electrode is connected to the source contact area of ​​the first active layer through a first connecting via hole; the first transfer electrode is connected to the second well contact area of ​​the second well through a second connecting via hole; the first source electrode is electrically connected to the first transfer electrode; Two first wells and one second well are arranged along a first direction on the silicon-based substrate; The third active layer and the second active layer are arranged in different first wells; The second well surrounds the first well where the third active layer is disposed; The first deep well surrounds the second well.

2. The display substrate according to claim 1, wherein: The display substrate further comprises a plurality of repeating units arranged in an array on a silicon-based substrate; The repeating unit includes two pixel units arranged side by side along a first direction; The repeating unit is provided with two second wells along a first direction on the silicon-based substrate and a first well is sandwiched between the two second wells; a first deep well is provided between the second well and the silicon-based substrate, and the first deep well is provided around one of the second wells; In the first direction, two third active layers in the first well sandwich two second active layers.

3. The display substrate according to claim 2, wherein: The repeating units arranged along the second direction share the first well.

4. The display substrate according to claim 1, wherein The display substrate further comprises a plurality of repeating units arranged in an array on the base substrate; The repeating unit includes two pixel units arranged side by side along a first direction; The repeating unit is configured to arrange two second wells on the silicon substrate along a first direction and to sandwich three first wells between the two second wells; The third active layer is disposed in the first well adjacent to the second well; Two second active layers are arranged in the first well in the middle along the first direction; The second well surrounds the first well where the third active layer is disposed; The first deep well is arranged around one of the second wells; In the first direction, two of the first deep wells sandwich one of the first wells.

5. The display substrate according to claim 4, wherein: The repeating units arranged along the second direction share the first well located in the middle.

6. The display substrate according to claim 1, wherein: The first conductive layer further includes a first drain electrode; the first drain electrode is electrically connected to the drain contact region of the first active layer through a third connecting via hole; The first drain electrodes of adjacent first thin film transistors are electrically connected in the first conductive layer.

7. The display substrate according to claim 1, wherein: The first conductive layer further includes a first conductive pattern; the first conductive pattern at least partially includes a first power signal line; and the first drain is electrically connected to the first conductive pattern.

8. The display substrate according to claim 1, wherein: The display substrate also includes a third conductive layer on the side facing away from the first conductive layer; the third thin film transistor includes a third drain electrode; the third drain electrode is arranged in the third conductive layer; the third drain electrode is electrically connected to the drain contact area of ​​the third active layer through a fourth connecting via; the light-emitting device includes a first electrode, a light-emitting layer and a second electrode; the first electrode is electrically connected to the third drain electrode.

9. The display substrate according to claim 1, wherein: The display substrate further includes: a second conductive layer located between the silicon-based substrate and the first conductive layer; the second conductive layer comprising the first gate, the second gate of the second thin film transistor, and the third gate of the third thin film transistor; a first gate insulating layer, located between the silicon-based substrate and the second conductive layer; a first interlayer insulating layer, located between the first conductive layer and the second conductive layer; a second interlayer insulating layer, located on a side of the first conductive layer facing away from the silicon-based substrate; The first connection via, the second connection via, and the third connection via penetrate the first interlayer insulating layer and the first gate insulating layer; and the fourth connection via penetrates the second interlayer insulating layer, the first interlayer insulating layer, and the first gate insulating layer.

10. The display substrate according to claim 8, wherein The display substrate further includes a first encapsulation layer, a color filter layer, and a second encapsulation layer which are sequentially arranged away from the second electrode of the light-emitting device.

11. A display module, characterized in that: The display module includes the display substrate according to any one of claims 1-10.

12. The display module according to claim 11, wherein: The display module also includes a flexible printed circuit board and a cover glass.

13. A display device, characterized in that: The display device includes the display module according to any one of claims 11 and 12.

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