Enhancement-mode III-V semiconductor device and manufacturing method thereof

Abstract

An enhancement-mode III-V semiconductor device and a manufacturing method thereof, comprising: a substrate; a buffer layer formed on the substrate; a GaN channel layer formed on the buffer layer; an AlGaN barrier layer formed on the channel layer; an AlGaN etch stop layer formed on the barrier layer, the chemical composition of which is AlGaN. x Ga (1‑x) N, where 0.4 <= x <= 0.7, and the thickness of the AlGaN etch stop layer corresponding to the source and drain regions is less than the thickness of the AlGaN etch stop layer corresponding to the gate region; a pGaN layer formed in the gate region of the AlGaN etch stop layer; and a source and drain formed on the source and drain regions of the AlGaN etch stop layer, respectively. Embodiments of the present invention provide enhancement-mode III-V semiconductor devices having advantages such as good lattice matching, high device breakdown voltage, and excellent dynamic resistance transistor characteristics.

Description

Technical Field

[0001] The present invention relates to an enhancement-mode III-V semiconductor device, and more particularly to an enhancement-mode III-V semiconductor device with good lattice matching, high device breakdown voltage and excellent dynamic resistance transistor characteristics and a manufacturing method thereof. Background Art

[0002] Aluminum gallium nitride / gallium nitride high electron mobility field-effect transistors (AlGaN / GaNHEMTs) with silicon substrates are commonly used in microwave and radio frequency applications, as well as in power conversion, due to GaN's inherent material advantages and excellent carrier transport properties. Traditional AlGaN / GaN transistors primarily utilize their material properties to generate polarized charges at the heterojunction. These polarized charges attract electron pairs, forming a high-density two-dimensional electron gas at the junction, lowering the conduction band below the Fermi level. This results in a normally-on device, meaning current conducts when the gate is at zero bias. Therefore, circuit design requires an additional negative bias on the gate metal to operate the device in the off state.

[0003] P-type gallium nitride (pGaN) transistors are formed by doping magnesium (Mg) into the gallium nitride layer during epitaxial growth and then activating it at high temperature. This pGaN layer forms a PN depletion region with the aluminum gallium nitride (AlGaN). A P-type gate is then formed by etching the non-gate areas of the pGaN layer to prevent excessive two-dimensional electron gas (2DEG) depletion, thereby achieving the effect of an enhancement-mode device. Etching accuracy is crucial for the pGaN layer. Using an inductively coupled plasma etcher with a BCl3 / Cl2 gas mixture, etching the pGaN layer too deep into the AlGaN layer can reduce the polarization effect at the heterojunction and lower the 2DEG concentration. Conversely, if any pGaN remains outside the gate region, holes can be injected into the channel layer, reducing the 2DEG concentration and adversely affecting device performance. Simply put, etching the pGaN layer at a computerized etching rate can lead to under- or over-etching of the pGaN layer due to tool instability.

[0004] Please refer to Figure 1 , Figure 1This is a schematic vertical cross-section of a conventional III-V semiconductor device. To improve etching accuracy, a proposal has been made to add an epitaxial layer of aluminum nitride (AlN) between the pGaN layer 103 and the AlGaN layer (barrier layer 105) as an etch stop layer 104. When a BCl3 / Cl2 / SF6 gas mixture is introduced to etch from the pGaN layer 103 to the AlN layer (etch stop layer 104), the high concentration of aluminum ions bonds with the fluoride ions in the SF6 to form aluminum fluoride (AlF3), which is hard and non-volatile. This prevents the BCl3 / Cl2 gas from further etching, effectively stopping the etching. However, the addition of the AlN etch stop layer 104 results in lattice mismatch due to the significant lattice difference between aluminum nitride and gallium nitride, affecting the reliability of the gate 102 and the characteristics of the enhancement-mode III-V semiconductor device. Summary of the Invention

[0005] According to the purpose of the present invention, an enhancement mode III-V semiconductor device is provided, which comprises: a substrate; a buffer layer formed on the substrate; a GaN channel layer formed on the buffer layer; an AlGaN barrier layer formed on the channel layer; an AlGaN etch stop layer formed on the barrier layer, the chemical composition of which is AlGaN x Ga (1-x) N, wherein 0.4<=x<=0.7, and the thickness of the AlGaN etch stop layer corresponding to the source and drain regions is less than the thickness of the AlGaN etch stop layer corresponding to the gate region; a pGaN layer formed in the gate region of the AlGaN etch stop layer; and a source and a drain formed on the source region and the drain region, respectively, of the AlGaN etch stop layer.

[0006] According to the purpose of the present invention, a method for manufacturing an enhancement-mode III-V semiconductor device is provided, which comprises: providing an enhancement-mode III-V semiconductor structure having no source, drain, or gate formed therein and having a two-dimensional electron gas, wherein the channel layer and the barrier layer of the enhancement-mode III-V semiconductor structure are respectively a GaN channel layer and an AlGaN barrier layer; forming an AlGaN etch stop layer on the barrier layer of the enhancement-mode III-V semiconductor structure, wherein the AlGaN etch stop layer has a chemical composition of AlGaN. x Ga (1-x)N, where 0.4<=x<=0.7; forming a pGaN layer on the AlGaN etch stop layer, and forming a mask layer on the pGaN layer to define a gate region, a source region, and a drain region; performing gas plasma etching to etch all of the pGaN layer on the source region and the drain region and partially etch the AlGaN etch stop layer on the source region and the drain region, removing the mask layer and performing surface treatment by removing residual aluminum fluoride using a silicon dioxide etchant; and forming a gate, a source, and a drain on the gate region, the source region, and the drain region.

[0007] Optionally, the thickness of the AlGaN etch stop layer in the gate region is 2 to 10 nm, and the etching loss of the AlGaN etch stop layer is 10% to 90% of the original thickness.

[0008] Optionally, the chemical composition formula of the AlGaN barrier layer is Al z Ga 1-z N, 0.1<=z<=0.3, and its thickness is 5 to 30 nm.

[0009] Optionally, the pGaN layer is doped with Mg at a concentration of 10 -18 to 10 -20 , and the thickness of the pGaN layer is 60 to 150 nm.

[0010] Optionally, the enhancement-mode III-V semiconductor device further includes: a nucleation layer formed between the substrate and the buffer layer; and a capping layer formed between the barrier layer and the AlGaN etch stop layer.

[0011] Optionally, an inductively coupled plasma (ICP) etcher is used, with the gas flow rates of BCl3 / Cl2 / SF6 set to 1-50sccm / 1-50sccm / 1-50sccm, the RF bias power to 10-100 watts, the ICP power to 100-500W, and the chamber pressure to 7.5-75mTorr for etching, wherein the etching rate is measured to be less than 0.65nm / s, and the etching time is at least 120 seconds.

[0012] In summary, compared to the prior art, the enhancement-mode III-V semiconductor device provided by the embodiments of the present invention has advantages such as good lattice matching, high device breakdown voltage, and excellent dynamic resistance transistor characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The various drawings of the present invention are intended only to facilitate understanding of the present invention by persons having ordinary skill in the art. The dimensions and configurations thereof are for illustrative purposes only and are not intended to limit the present invention. A brief description of each of the drawings is as follows:

[0014] Figure 1 It is a vertical cross-sectional diagram of a traditional III-V semiconductor device;

[0015] Figure 2 is a flow chart of a method for manufacturing an enhancement-mode III-V semiconductor device with good lattice matching according to an embodiment of the present invention; and

[0016] Figures 3A to 3E It is a cross-sectional schematic diagram of the finished products of each step of the method for manufacturing an enhancement-mode III-V semiconductor device with good lattice matching according to an embodiment of the present invention.

[0017] The description of the accompanying drawings is as follows:

[0018] 100: Source

[0019] 101: Drain

[0020] 102: Gate

[0021] 103, 103A: pGaN layer

[0022] 104, 104A, 104B: Etching stop layer

[0023] 105: Barrier layer

[0024] 106: Channel layer

[0025] 107: Buffer layer

[0026] 108: Substrate

[0027] 109: Mask layer

[0028] S21~S25:Steps DETAILED DESCRIPTION

[0029] To help examiners understand the technical features, content, advantages, and achievable effects of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and in the form of embodiments. The drawings used therein are intended only for illustration and to assist in the description, and may not reflect the actual proportions and precise configurations of the present invention after implementation. Therefore, the proportions and configurations of the attached drawings should not be interpreted to limit the scope of the present invention in actual implementation. This is to be noted in advance.

[0030] In order to solve the technical problem of poor lattice matching in the prior art, the present invention uses an AlGaN layer as an etch stop layer, wherein the chemical composition is Al x Ga (1-x)N, and x is between 0.4 and 0.7 (inclusive), primarily to reduce the moiré concentration of aluminum for better lattice matching. Subsequently, when a BCl3 / Cl2 / SF6 gas mixture is introduced to etch the p-type GaN to the AlGaN etch stop layer, the high concentration of aluminum ions bonds with the fluoride ions in SF6 to form hard, non-volatile aluminum fluoride (AlF3), which blocks further etching by the BCl3 / Cl2 gas. A silicon dioxide etchant then removes the remaining AlF3, ensuring that device characteristics are not affected by the AlF3. In addition to improving transistor lattice matching and enhancing gate reliability, this approach also achieves high etch selectivity due to the epitaxial extension of the AlGaN etch stop layer between the p-type GaN layer and the AlGaN barrier layer, thereby enhancing transistor characteristics such as device breakdown voltage and dynamic resistance.

[0031] First, please refer to Figure 3E The final product of the method for manufacturing an enhanced III-V semiconductor device with good lattice matching according to an embodiment of the present invention is as follows: Figure 3E The enhancement-mode III-V semiconductor device includes a source 100, a drain 101, a gate 102, a P-type gallium nitride layer 103, an aluminum gallium nitride etch stop layer 104A, an aluminum gallium nitride barrier layer 105, a gallium nitride channel layer 106, a buffer layer 107, and a substrate 108. The chemical composition of the aluminum gallium nitride in the aluminum gallium nitride etch stop layer 104A is Al x Ga (1-x) N, where 0.4<=x<=0.7, the thickness on the gate region is 2 to 10 nm (including both endpoints of 2 nm and 10 nm), and the etching loss is 10% to 90% of the original thickness (including both endpoints of 10% and 90%).

[0032] A buffer layer 107 is formed on a substrate 108. Optionally, a nucleation layer (not shown) may be further provided vertically between the buffer layer 107 and the substrate 108. A gallium nitride channel layer 106 is formed on the buffer layer 107, and an aluminum gallium nitride barrier layer 105 is formed on the gallium nitride channel layer 106. An AlGaN etch stop layer 104A is formed on the AlGaN barrier layer 105, with the left, middle, and right horizontal portions corresponding to the source, gate, and drain regions, respectively. The thicknesses of the left and right AlGaN etch stop layer 104A are thinner than the thickness of the middle portion of the AlGaN etch stop layer 104A. The thickness ratio is related to the original thickness of the etching loss. The thickness of the middle portion of the AlGaN etch stop layer 104A relative to the thickness of the left and right AlGaN etch stop layer 104A is approximately 1:0.9 to 1:0.1 (inclusive). Optionally, the AlGaN etch stop layer 104A and the AlGaN barrier layer 105 may be capped with a cap layer (not shown) in the vertical direction. The source 100 and the drain 101 are respectively located on the left and right portions of the AlGaN etch stop layer 104A. The P-type GaN layer 103 is located on the middle portion of the AlGaN etch stop layer 104A. The gate 102 is located on the P-type GaN layer 103.

[0033] The substrate 108 can be, for example, silicon, silicon on insulator (SOI), silicon carbide (SiC), sapphire substrate or other substrate that can allow enhancement mode III-V semiconductor epitaxy, and the present invention is not limited thereto. If a nucleation layer is selected for design, the nucleation layer can be, for example, a low-temperature GaN layer, a low-temperature AlN layer, a high-temperature GaN layer or a high-temperature AlN layer, and the present invention is not limited thereto. The buffer layer 107 can be, for example, an AlN layer, an AlGaN layer, an InGaN layer, a super lattice AlN / GaN layer, a super crystalline AlGaN / GaN layer, a super crystalline AlN / AlGaN, a carbon-doped GaN layer, an iron-doped GaN layer or an undoped GaN layer, and the present invention is not limited thereto. When the buffer layer 107 is an AlGaN layer, the chemical composition formula of AlGaN is AlGaN. y Ga 1-y N, 0.05<=y. The chemical composition formula of AlGaN in the barrier layer 105 is Al z Ga 1-z N, 0.1<=z<=0.3, and a thickness of 5 to 30 nm (including both endpoints). If a capping layer is selected, the capping layer may be, for example, a GaN layer, a GaN layer, an AlN layer, an AlGaN layer, or an InGaN layer.

[0034] Each of the source 100 and the drain 101 is a metal stack layer forming an ohmic contact electrode, which includes, for example, a first structure layer and a second structure layer arranged from bottom to top. The first structure layer can be a Ti / Al double-layer structure, and the second structure layer can be a Ni / Au double-layer structure, a Ti / Ta double-layer structure, a Ti layer, a TiN layer, a Cu layer or a W layer, and the present invention is not limited thereto. The gate 102 is a Schottky electrode for controlling the channel, which is a metal stack layer formed by at least one of Ti, Al, N and Au, such as a Ni / Au double-layer structure, and the present invention is not limited thereto. The P-type gallium nitride layer 103 is doped with Mg at a concentration of 10 -18 to 10 -20 (Including 10 -18 with 10 -20 and the thickness of the P-type GaN layer 103 is 60 to 150 nm (including the two endpoints of 60 nm and 150 nm).

[0035] Next, please refer to Figure 2 and Figures 3A to 3E , Figure 2 is a flow chart of a method for manufacturing an enhancement-mode III-V semiconductor device with good lattice matching according to an embodiment of the present invention, and Figures 3A to 3E Schematic cross-sectional view of the finished product of each step of the method for manufacturing a well-lattice-matched enhancement-mode III-V semiconductor device according to an embodiment of the present invention. First, in step S21, an enhancement-mode III-V semiconductor structure having a two-dimensional electron gas and without a source, a drain, and a gate is provided, such as Figure 3A As shown, the enhancement-mode III-V semiconductor structure includes a substrate 108, a buffer layer 107, a GaN channel layer 106, and an AlGaN barrier layer 105 stacked in order from top to bottom. Next, in step S22, an AlGaN etch stop layer 104B is formed on the AlGaN barrier layer 105 of the enhancement-mode III-V semiconductor structure. Figure 3B As shown, the chemical composition formula of the aluminum gallium nitride etching stop layer 104A is Al x Ga (1-x) N, 0.4<=x<=0.7, and its thickness is 2 to 10 nm (including both endpoints of 2 nm and 10 nm). Then, in step S23, a P-type GaN layer 103A and a mask layer 109 (for example, but not limited to, made of a photoresist material) are sequentially formed on the aluminum gallium nitride etching stop layer 104A to define the gate, source, and drain regions, as shown in FIG. Figure 3C As shown, the P-type gallium nitride layer 103A is doped with Mg at a concentration of 10 -18 to 10 -20 (Including 10 -18 with 10-20 and the thickness of the P-type GaN layer 103A is 60 to 150 nm (including the two endpoints of 60 nm and 150 nm).

[0036] Then, in step S24, gas plasma etching is performed, and the mask layer 109 is removed. Surface treatment is performed by removing the residual aluminum fluoride using a silicon dioxide etchant, wherein the left and right portions of the P-type GaN layer 103A corresponding to the source and drain regions are completely etched, leaving only the P-type GaN layer 103 corresponding to the gate region, and approximately 10% to 90% of the left and right portions of the aluminum gallium nitride etch stop layer 104A corresponding to the source and drain regions are etched (etching loss is 10% to 90% of the original thickness), thereby forming the etched aluminum gallium nitride etch stop layer 104. Figure 3D . Further, in step S24, an inductively coupled plasma (ICP) etcher is used, and the gas flow rate BCl3 / Cl2 / SF6 is set to 1-50sccm / 1-50sccm / 1-50sccm, the RF bias power is 10-100 watts, the ICP power is 100-500W, and the chamber pressure is 7.5-75mTorr to perform etching, wherein the etching rate is measured to be less than 0.65nm / s, and the etching is stopped when the etching period is 120 seconds, and the etching is continued to 240 seconds (that is, the actual etching time is at least 120 seconds) to confirm that the aluminum gallium nitride etching stop layer can solve the problem of excessive etching, and the calculated etching selectivity is as high as 37.5:1. Then, in step S25, a source 100, a drain 101, and a gate 102 are formed in the source region, the drain region, and the gate region, respectively, as shown in FIG. Figure 3E shown.

[0037] In summary, the embodiments of the present invention provide an enhancement-mode III-V semiconductor device with good lattice matching, high device breakdown voltage, and excellent dynamic resistance transistor characteristics, and a method for manufacturing the same. Furthermore, after X-ray diffraction measurement (XRD), the screw dislocations and edge dislocations of the enhancement-mode III-V semiconductor device of the embodiment of the present invention are lower than those of conventional III-V semiconductor devices (indicating good lattice matching); through electrical measurement, the threshold voltage, leakage current, and source-drain on-resistance (R DS_ON ) to dynamic resistance ratio is lower than the threshold voltage, leakage current, and source-drain turn-on resistance to dynamic resistance ratio of conventional III-V semiconductor devices. The saturation current and breakdown voltage of the enhancement-mode III-V semiconductor device of the present invention are higher than those of conventional III-V semiconductor devices.

[0038] In summary, it can be seen that the present invention has indeed achieved the desired enhanced effect while breaking through the previous technology.

[0039] The embodiments described above are merely for illustrating the technical concepts and features of the present invention. Their purpose is to enable persons skilled in the art to understand the contents of the present invention and implement them accordingly. They cannot be used to limit the patent scope of the present invention. In other words, any equivalent changes or modifications made according to the spirit disclosed by the present invention should still be covered by the patent scope of the present invention.

Claims

1. An enhancement-mode III-V semiconductor device, comprising: a substrate (108); a buffer layer (107) formed on the substrate (108); a GaN channel layer (106) formed on the buffer layer (107); an AlGaN barrier layer (105) formed on the channel layer (106); An AlGaN etching stop layer (104A) is formed on the barrier layer (105), and its chemical composition is Al x Ga (1-x) N, wherein 0.4<=x<=0.7, and the thickness of the AlGaN etch stop layer (104A) corresponding to the source and drain regions is less than the thickness of the AlGaN etch stop layer (104A) corresponding to the gate region, and the etching loss of the AlGaN etch stop layer (104A) is 10% to 90% of the original thickness; A pGaN layer (103) is formed in the gate region of the AlGaN etch stop layer (104A), wherein the thickness of the AlGaN etch stop layer (104A) corresponding to the pGaN layer (103) is greater than the thickness of the AlGaN etch stop layer (104A) corresponding to the pGaN layer (103) to the source region and greater than the thickness of the AlGaN etch stop layer (104A) corresponding to the pGaN layer (103) to the drain region; and A source (100) and a drain (101) are respectively formed on the source region and the drain region of the AlGaN etching stop layer (104A).

2. The enhancement-mode III-V semiconductor device according to claim 1, wherein the thickness of the AlGaN etch stop layer (104A) in the gate region is 2 to 10 nm.

3. The enhancement mode III-V semiconductor device according to claim 2, wherein the chemical composition formula of the AlGaN barrier layer (105) is Al z Ga 1-z N, 0.1<=z<=0.3, and its thickness is 5 to 30 nm.

4. The enhancement-mode III-V semiconductor device according to claim 3, wherein the pGaN layer (103) is doped with Mg at a concentration of 10 -18 to 10 -20 , and the thickness of the pGaN layer (103) is 60 to 150 nm.

5. The enhancement-mode III-V semiconductor device according to any one of claims 1 to 4, further comprising: a nucleation layer formed between the substrate (108) and the buffer layer (107); as well as A capping layer is formed between the barrier layer (105) and the AlGaN etching stop layer (104A).

6. A method for manufacturing an enhancement-mode III-V semiconductor device, comprising: An enhanced III-V semiconductor structure having a two-dimensional electron gas and without forming a source, a drain and a gate is provided, wherein a channel layer (106) and a barrier layer (105) of the enhanced III-V semiconductor structure are respectively a GaN channel layer (106) and an AlGaN barrier layer (105); An AlGaN etching stop layer (104A) is formed on the barrier layer (105) of the enhanced III-V semiconductor structure, and its chemical composition formula is Al x Ga (1-x) N, where 0.4 <= x <= 0.7; forming a pGaN layer (103) on the AlGaN etching stop layer (104A), and forming a mask layer (109) on the pGaN layer (103) to define a gate region, a source region, and a drain region; Performing gas plasma etching to etch all of the pGaN layer (103) on the source region and the drain region and partially etch the AlGaN etching stop layer (104A) on the source region and the drain region, removing the mask layer (109) and using a silicon dioxide etching solution to remove residual aluminum fluoride for surface treatment, wherein the etching loss of the AlGaN etching stop layer (104A) is 10% to 90% of the original thickness, and the thickness of the AlGaN etching stop layer (104A) corresponding to the pGaN layer (103) is greater than the thickness of the AlGaN etching stop layer (104A) corresponding to the pGaN layer (103) to the source region and greater than the thickness of the AlGaN etching stop layer (104A) corresponding to the pGaN layer (103) to the drain region; and A gate (102), a source (100) and a drain (101) are formed on the gate region, the source region and the drain region.

7. The method for manufacturing an enhancement-mode III-V semiconductor device as claimed in claim 6, wherein the thickness of the AlGaN etch stop layer (104A) in the gate region is 2 to 10 nm.

8. The method for manufacturing an enhancement mode III-V semiconductor device according to claim 7, wherein the chemical composition formula of the AlGaN barrier layer (105) is Al z Ga 1-z N, 0.1<=z<=0.3, and its thickness is 5 to 30 nm.

9. The method for manufacturing an enhancement mode III-V semiconductor device according to claim 8, wherein the pGaN layer (103) is doped with Mg at a concentration of 10 -18 to 10 -20 , and the thickness of the pGaN layer (103) is 60 to 150 nm.

10. A method for manufacturing an enhancement-mode III-V semiconductor device as claimed in any one of claims 6 to 9, wherein etching is performed using an inductively coupled plasma etcher, with gas flow rates of BCl3 / Cl2 / SF6 set to 1-50 sccm / 1-50 sccm / 1-50 sccm, RF bias power to 10-100 watts, inductively coupled plasma power to 100-500 W, and chamber pressure to 7.5-75 mTorr, wherein an etching rate is measured to be less than 0.65 nm / s, and the etching time is at least 120 seconds.

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