Densely packaged VCSEL arrays, semiconductor devices including VCSEL arrays, and methods for manufacturing the same.

Abstract

This disclosure relates to the field of vertical-cavity surface-emitting lasers (VCSELs), and particularly to a semiconductor device (1) comprising a VCSEL array and a method for manufacturing the semiconductor device comprising the VCSEL array, wherein the semiconductor device comprises: a first VCSEL having a first active region; a second VCSEL having a second active region; a bridge connecting the first VCSEL and the second VCSEL; wherein the first active region of the first VCSEL and the second active region of the second VCSEL are arranged along a first crystal axis; and a blocking structure disposed between the first VCSEL and the second VCSEL, wherein the blocking structure is adapted to block defects from propagating along the first crystal axis between the first VCSEL and the second VCSEL.

Description

Technical Field

[0001] This invention relates to a semiconductor device comprising a vertical-cavity surface-emitting laser (VCSEL) array. The invention further relates to a corresponding method for manufacturing such a semiconductor device comprising a VCSEL array. Background Technology

[0002] A vertical-cavity surface-emitting laser, or VCSEL, is a semiconductor laser diode whose laser beam is emitted vertically from its top surface. Due to the high efficiency, flexible packaging options, reliability, and various other advantages offered by these semiconductor light sources, VCSELs can be used as visible light and infrared illumination devices in a wide range of applications. Exemplary applications include, but are not limited to, computer mice, fiber optic communications, laser printers, and optical sensors.

[0003] In some applications, it may be desirable to provide VCSEL arrays comprising multiple VCSELs. For sensors in mass production, it is desirable to provide VCSEL arrays that can be manufactured at low cost. Since manufacturing costs are proportional to chip area, densely packaged VCSEL arrays are desirable.

[0004] US 2020 / 0144792 A1 discloses a small-pitch VCSEL array. It provides a vertical-cavity surface-emitting laser (VCSEL) and a VCSEL array with small size and small pitch. Methods for reducing the area consumed by the VCSEL structure are described to enable higher density VCSEL devices. As described in US 2020 / 0144792 A1, the proposed VCSEL array includes: a plurality of VCSEL elements, each VCSEL element including: an oxide via; a mesa concentrically surrounding the oxide via, the mesa including a circular mesa portion and a mesa tab extending outward from the circular mesa portion, wherein ohmic metal is provided on the mesa tab; and nitride vias positioned on the mesa tabs, wherein adjacent VCSEL elements have overlapping mesa tabs. Summary of the Invention

[0005] The object of this invention is to provide a further improved VCSEL array. In particular, it would be advantageous to provide a VCSEL array suitable for large-scale production at low cost and high yield. It is desirable to provide a VCSEL array that can be manufactured at low cost and high yield while providing high device reliability.

[0006] According to a first aspect of this disclosure, a semiconductor device comprising a vertical-cavity surface-emitting laser (VCSEL) array is proposed. The semiconductor device includes: a first VCSEL having a first active region; a second VCSEL having a second active region; wherein the first active region of the first VCSEL and the second active region of the second VCSEL are arranged along a first crystal axis; and a blocking structure disposed between the first VCSEL and the second VCSEL, wherein the blocking structure is adapted to block the propagation of defects along the first crystal axis between the first VCSEL and the second VCSEL. A bridge may connect the first VCSEL and the second VCSEL. The blocking structure is particularly adapted to block the propagation of defects along the first crystal axis between the active regions of the first VCSEL and the second VCSEL.

[0007] In another aspect of this disclosure, a method for fabricating a semiconductor device including a vertical-cavity surface-emitting laser (VCSEL) array is provided. The method includes the steps of: providing a semiconductor die including a vertical layer stack suitable for fabricating VCSELs; determining a crystal axis of the semiconductor die in a direction parallel to the surface of the semiconductor die and perpendicular to the vertical layer stack; and processing the semiconductor die into a semiconductor device including: a first VCSEL having a first active region; a second VCSEL having a second active region; wherein the first active region of the first VCSEL and the second active region of the second VCSEL are arranged along the first crystal axis; and a blocking structure disposed between the first VCSEL and the second VCSEL, wherein the blocking structure is adapted to block defects from propagating along the first crystal axis between the first VCSEL (its active region) and the second VCSEL (its active region).

[0008] Preferred embodiments of the invention are described below. It should be understood that the claimed method may have similar and / or identical preferred embodiments to the claimed semiconductor device, particularly the preferred embodiments disclosed herein.

[0009] The solution proposed in this paper offers the possibility of providing further improved VCSEL arrays that can be manufactured at low cost and high yield while providing high device reliability.

[0010] The inventors recognized that in densely packaged VCSEL arrays, particularly in densely packaged VCSEL arrays with ultra-low pitch of 20 to 30 μm or less, several mesas are at risk of developing defects. As a characteristic, the inventors recognized that such defects can affect adjacent VCSELs. While a limited number of defects in individual VCSELs may be tolerable in some applications, defects in several adjacent VCSELs can be considered device failures due to non-uniform brightness patterns.

[0011] The inventors recognized that adjacent VCSELs arranged along the crystal axis are more likely to suffer from multi-mesa defects than adjacent VCSELs not arranged along the crystal axis. Therefore, this invention is based on the idea of ​​providing, specifically, a barrier structure arranged between adjacent first and second VCSELs, adapted to prevent defects from propagating along the first crystal axis between the first VCSEL (its active region) and the second VCSEL (its active region). The first VCSEL, the barrier structure, and the second VCSEL can thus be arranged sequentially along the crystal axis from front to back such that the barrier structure protects the second VCSEL from defects originating from the first VCSEL that are likely to propagate along the crystal axis with a higher probability. The bridge connecting the first and second VCSELs can still be provided along a path that does not coincide with the straight line along the crystal axis. Therefore, a very dense package with small pitch can be achieved using only a portion of the etched area and the remaining bridge between adjacent VCSELs.

[0012] The characteristic of the first and second VCSELs being connected by a bridge (also called a ridge or mesh) means that the material around the emitter is not completely removed; that is, the first and second VCSELs are not provided as independent mesa, as this does not allow for the realization of a densely packed array. For example, the material around the emitter will not be completely removed; only, for example, four regions around the emitter can be etched, and on the one hand, used for oxidation, and given that these regions are advantageously and purposefully aligned about the crystal axis, they can be used as barrier structures. Thus, advantageous synergies in manufacturing can be achieved. The first and second VCSELs can at least partially share a common top surface contact. The first and second VCSELs are adjacent VCSELs; particularly the adjacent VCSELs closest to each other, especially in the direction of the first crystal axis. As used herein, the active region of a VCSEL refers to the region of the VCSEL suitable for emitting light during operation, typically the central portion of the VCSEL.

[0013] The inventors recognized that, to further reduce the spacing of VCSEL arrays, an obvious idea would be to place oxide trenches at the corners of the rows and columns of the VCSEL array grid. This could provide even more compact designs. Smaller chip sizes allow for more chips per wafer, and smaller chips can be placed in smaller packages, thus reducing the overall cost of the chips and packages.

[0014] However, it has been found that utilizing a specific arrangement of barrier structures, as described in this paper, to mitigate the beneficial effects of multi-mesa defects can improve product yield. This is achieved by allowing some of the increased chip area and consequently higher manufacturing costs to be outcompensated by the higher manufacturing yield. Furthermore, it reduces the reliance on multiple additional backup VCSELs for redundancy in the event of a single VCSEL failure. This further reduces the required device area and can further contribute to lower power consumption.

[0015] VCSEL arrays can be arrays, particularly densely packaged arrays, having a pitch of no more than 30 μm, particularly no more than 20 μm, particularly no more than 17.5 μm, particularly no more than 15 μm, and particularly no more than 10 μm. As used herein, the term "pitch" can refer to the (shortest) center-to-center distance between adjacent VCSELs. The proposed solution is particularly advantageous at small pitches because completely separating the mesa and providing separate electrical connections is no longer feasible. Furthermore, the risk of multi-mesa defects increases with increasing VCSEL density.

[0016] The width (or length) of the barrier structure in the direction perpendicular to the first crystal axis can be wider than the width of the first active region and / or the second active region in the direction perpendicular to the first crystal axis. For example, if the barrier structure is provided as a trench between adjacent VCSELs along the first crystal axis, the trench can be wider than the diameter of the active region. Given this orientation, the width of the barrier structure in the direction perpendicular to the first crystal axis can refer to the length of the trench. As used herein, perpendicular to the crystal axis means perpendicular to the crystal axis but parallel to the top surface of the semiconductor die. The first active region, the barrier structure, and the second active region can be centered relative to the first crystal axis such that the barrier structure, which is wider than the first active region, blocks defects originating from the first active region and propagating along the first crystal axis from reaching the second active region.

[0017] The width (or thickness) of the barrier structure in the direction parallel to the first crystal axis can be less than 30% of the VCSEL pitch, particularly less than 20% of the VCSEL pitch, particularly less than 10% of the VCSEL pitch, and particularly less than 5% of the VCSEL pitch. Alternatively or alternatively, the width of the barrier structure in the direction parallel to the first crystal axis can be less than 10 μm, particularly less than 5 μm, particularly less than 3 μm, and particularly less than 2 μm. Therefore, even relatively narrow trenches or barrier structures can effectively reduce multi-mesa defects. Given this orientation, the width of the barrier structure in the direction parallel to the first crystal axis can refer to the width of the trench. For example, a trench or other barrier structure can be 3 μm wide and 10 μm long. As used herein, parallel to the crystal axis means parallel to the crystal axis and parallel to the top surface of the semiconductor wafer.

[0018] As noted above, the barrier structure may include or be formed from etched regions. In particular, the barrier structure may include or be formed from trenches for oxidation, especially trenches for oxidizing corresponding oxide orifices of the first VCSEL and / or the second VCSEL. An advantage of this embodiment is the synergistic effect, as the formation of the barrier structure and the formation of the oxide orifices can occur simultaneously.

[0019] It should be understood that the depth of the etched region can exceed the depth of the active layer of the first VCSEL and / or the second VCSEL. Therefore, the risk of defect propagation can be significantly reduced.

[0020] The etched area may be separated from the top surface contact portion of the first VCSEL and / or the second VCSEL. Specifically, the barrier structure may include a portion of the etched area that may be separated from the top surface contact portion surrounding the active region of the first VCSEL. This top surface contact portion may be a p-type contact portion or an n-type contact portion.

[0021] The bridge connecting the first VCSEL and the second VCSEL can advantageously bend around one side of the barrier structure. Therefore, the bridge preferably does not establish a path between the first and second VCSELs that coincides with the first crystal axis or optionally any crystal axis. In a further improvement, a second bridge connecting the first and second VCSELs can be provided, which bends around a second side of the barrier structure different from the first side. The advantage of this embodiment is that less material needs to be removed and additional structural support can be provided.

[0022] The bridge connecting the first VCSEL and the second VCSEL may optionally be a bridge connecting the first VCSEL, the second VCSEL, and an adjacent third VCSEL. In a further improvement, the bridge may also connect an adjacent fourth VCSEL. As used herein, connecting VCSELs means directly connecting VCSELs, i.e., without passing through any other intermediate VCSELs or portions thereof.

[0023] Referring again to the device geometry, the distance between the first VCSEL and the second VCSEL can be less than the diameter of the first active region and / or the second active region. This further highlights the aspect of providing a densely packed array where the VCSELs of the array are very close to each other. The distance between adjacent VCSELs can refer to the width of the barrier structure arranged between the first VCSEL and the second VCSEL.

[0024] The first and second VCSELs of the array may have a common electrical top surface contact and / or a common electrical bottom surface contact. The top surface contact may be a p-type contact. The bottom surface contact may be an n-type contact, or vice versa. Optionally, a first top surface contact portion surrounding the active region of the first VCSEL and a second top surface contact portion surrounding the active region of the second VCSEL may be provided. The first and second top surface contact portions may be connected via a first bypass contact portion surrounding a first side of the barrier structure and via a second bypass contact portion surrounding a second side of the barrier structure. This provides different electrical paths between adjacent VCSELs. Such bypass contacts may refer to electrical connections that are adjacent to each other on both sides and bypass the barrier structure.

[0025] The VCSEL array of the semiconductor device can, of course, provide more than two VCSELs. The semiconductor device may further include a third VCSEL having a third active region. A second bridge connecting the first and third VCSELs can be provided. The first active region of the first VCSEL and the third active region of the third VCSEL can be arranged along a second crystal axis. A second blocking structure can be arranged between the first and third VCSELs. This blocking structure can be adapted to block defects from propagating along the second crystal axis between the active regions of the first and third VCSELs. This further reduces multi-mesa defects. The first crystal axis can intersect the second crystal axis at angles between 45° and 135°, particularly between 60° and 120°, particularly between 75° and 105°, and particularly between 85° and 95°.

[0026] The first VCSEL can have a rectangular, particularly square, active region, wherein a barrier structure is provided on each side of the active region. For example, four barrier structures can be provided around the active region, one on each side. This effectively protects the VCSEL from external defects and also protects adjacent VCSELs.

[0027] Semiconductor devices may include multiple VCSELs arranged in rows and columns on a rectangular grid, particularly a square grid. A separate blocking structure is provided between each pair of adjacent VCSELs on the grid. Each blocking structure is adapted to prevent defects from propagating between the corresponding pair of adjacent VCSELs. The rows of the grid may be aligned with a first crystal axis. Blocking structures along the rows are adapted to prevent defects from propagating between adjacent VCSELs along the corresponding row. The columns of the grid may be aligned with a second crystal axis different from the first crystal axis. Blocking structures along the columns are adapted to prevent defects from propagating between adjacent VCSELs along the corresponding column.

[0028] It should be understood that, without departing from the scope of the invention, the features mentioned above and the features to be explained below can be used not only in the combinations indicated, but also in other combinations or individually. Attached Figure Description

[0029] These and other aspects of the invention will become apparent from and be elucidated with reference to the embodiments described below. In the following figures:

[0030] Figure 1 A schematic diagram of an embodiment of a semiconductor device including a vertical-cavity surface-emitting laser (VCSEL) array according to one aspect of this disclosure is shown.

[0031] Figure 2 An image of an exemplary semiconductor device according to one aspect of this disclosure is shown;

[0032] Figures 3A to 3L It demonstrates the different processing steps in the manufacturing process;

[0033] Figures 4A to 4D Measurement results of an exemplary semiconductor device according to one aspect of this disclosure are shown;

[0034] Figure 5 A schematic diagram of defect propagation is shown;

[0035] Figure 6 A flowchart of a method according to one aspect of the present invention is shown. Detailed Implementation

[0036] Figure 1A schematic diagram of an embodiment of a semiconductor device including a vertical-cavity surface-emitting laser (VCSEL) array is shown. The system is generally indicated by reference numeral 1. The first crystal axis of the semiconductor device is indicated by reference numeral 2. An optional second crystal axis is indicated by reference numeral 3. In a given example, the first and second crystal axes may intersect at a 90° angle. The semiconductor device 1 includes a first VCSEL 10 having a first active region 20 and a second VCSEL 11 having a second active region 21. Bridges 31 and 31' connecting the first VCSEL 10 and the second VCSEL 11 are provided. These bridges may be unetched portions of the semiconductor material. The first active region 20 of the first VCSEL 10 and the second active region 21 of the second VCSEL 11 are arranged behind each other along the first crystal axis 2. A barrier structure 41, in the form of a trench, is arranged between the first VCSEL 10 and the second VCSEL 11, particularly between the first active region 20 and the second active region 21. The barrier structure is adapted to prevent defect 101 from propagating along the first crystal axis 2 between the first VCSEL 10 and the second VCSEL 11. This is in Figure 1 Arrow 101 is shown as an example, which is blocked as a groove of the blocking structure 41.

[0037] Semiconductor device 1 may optionally include an additional VCSEL, such as Figure 1 As exemplarily shown above, a third VCSEL 12 with a third active region 22 can be provided. Second bridges 32, 32' connect the first VCSEL 10 and the third VCSEL 12. The first active region 20 of the first VCSEL 10 and the third active region 22 of the third VCSEL 12 are arranged along the second crystal axis 2. A second blocking structure 42 is arranged between the first VCSEL 10 and the third VCSEL 12, wherein the blocking structure is adapted to block the propagation of defect 102 along the second crystal axis 2 between the first VCSEL 10 and the third VCSEL 12. This is in Figure 1 Arrow 102 is exemplarily shown in the diagram, and this arrow is blocked by a trench serving as a blocking structure 42. It should be noted that no blocking structure is provided between the first VCSEL 10 and the fourth VCSEL 13, which is arranged diagonally opposite to the first VCSEL 10. However, the probability of a defect propagating along arrow 103 is limited, and therefore this path is tolerable even for densely packaged arrays. Furthermore, due to the longer diagonal path length, the probability that a defect originating from the first VCSEL 10 will not reach the second VCSEL 20 is relatively high.

[0038] In other words, if a defect is present in an emitter, it will in most cases propagate along one of the crystal axes 2 and 3. A blocking structure arranged in this direction (provided here as an etched area) will prevent the defect from propagating. This will significantly reduce the risk of multi-mesa failures. Therefore, device reliability and manufacturing yield can be further improved.

[0039] Advantageously, the semiconductor device 1 may include a plurality of unit cells 60, which can be flexibly combined to provide a VCSEL array with a desired size and shape. The number of rows and / or columns of the VCSEL array can be flexibly adjusted as needed.

[0040] Regarding exemplary geometries, the VCSEL array can be an array of densely packed packages with a pitch between 8 and 30 μm (e.g., 16 μm). A narrow trench with a width d1 can be provided as a barrier structure. The width d1 of the barrier structure in the direction parallel to the first crystal axis 2 can be less than 30% of the VCSEL pitch p, particularly less than 20% of the VCSEL pitch, particularly less than 10% of the VCSEL pitch, and particularly less than 5% of the VCSEL pitch. In a given example, the trench can be approximately 3 μm narrow. On the other hand, the width w2 of the barrier structure 31 in the direction perpendicular to the first crystal axis 2 is preferably wider than the width w1 of the first active region 20 and / or the second active region 21 in the direction perpendicular to the first crystal axis 2. Therefore, any defects originating from one of the two active regions can be effectively prevented from reaching the corresponding other active region. For example, the width w1 of the active region can be between 3 μm and 20 μm. The width w2 of the barrier structure can typically be at least approximately 10 μm. However, for active region widths exceeding 10 μm, the width of the barrier structure can be increased accordingly. The distance d2 between the inner edges of the top surface contacts of adjacent VCSELs can be at least 5 μm, and particularly at least 8 μm, to provide sufficient space for forming a barrier structure. However, as an upper limit, the distance d2 can be less than 20 μm, and particularly less than 15 μm. This allows for a compact array. Figure 1 In the example shown, the center-to-center distance between the first VCSEL 10 and the second VCSEL 11 can be approximately 16 μm. Defect propagation along this short distance is effectively blocked by the blocking structure. In an embodiment, the blocking structure can be positioned at the center of the line connecting the centers of the first VCSEL 10 and the second VCSEL 11. Figure 1 In the example shown, the center-to-center distance between the first VCSEL 10 and the fourth VCSEL 13 (i.e., along the diagonal 103) can be approximately 22.8 μm.

[0041] like Figure 1As shown, the bridge 31 connecting the first VCSEL 10 and the second VCSEL 11 can be bent around the upper side of the blocking structure 41. Therefore, a common electrical connection is established while bypassing the direct path along the crystal axis 2. Optionally, a second bridge 31' connecting the first VCSEL 10 and the second VCSEL 11 can be bent around the lower side of the blocking structure 41. These bridges can be shared by multiple adjacent VCSELs. Figure 1 As shown, the bridge 31 connecting the first VCSEL 10 and the second VCSEL 11 can also be connected to the adjacent third VCSEL 12 and preferably also to the adjacent fourth VCSEL 13. Although different reference numerals 31 and 32 are shown, they will be understood as a common bridge structure shared between at least three adjacent VCSELs.

[0042] Figure 2 An image of an exemplary semiconductor device 1 according to one aspect of this disclosure is shown. In the given example, 12 VCSELs are provided, arranged in two rows of four VCSELs, followed by two rows of two VCSELs. First VCSEL 10 and second VCSEL 11 are again separated by a barrier structure 31 adapted to prevent defects from propagating between first VCSEL 10 and second VCSEL 12 along a first crystal axis aligned with the respective centers of the active regions of first VCSEL 10 and second VCSEL 11. Bonding pads 201 for providing first electrical contacts for the VCSELs can be seen on the top surface. A back electrode (not shown) may be used as a second electrical contact. Optionally, production markings 202 may be shown on the surface. Additional details regarding the device will be further explained below with reference to FIG4.

[0043] Figures 3A to 3L The different processing steps in the manufacturing process are illustrated. Unfinished semiconductor devices are indicated by reference numeral 1'. (See attached figure.) Figure 3A As shown, a semiconductor die 300 is provided in the first step, the semiconductor die including a vertical layer stack suitable for fabricating a VCSEL. The semiconductor die is arranged such that during fabrication, the die crystal axis 2 of the die in a direction parallel to the surface of the semiconductor die and perpendicular to the vertical layer stack is aligned with the active region of the adjacent VCSEL. Figure 3B It shows the use of, for example Figure 3B The step of photolithography 301 on the p-contact portion of the mask 301 shown is performed. Figure 3C The steps for depositing p-contact 302 are shown. Figure 3D The steps for depositing the SiNx layer 303 are shown. Figure 3E It shows the use of, for example Figure 3E The mask 305 shown is used for photolithography 304 to achieve the mesa etching step. Figure 3F The steps of performing mesa dry etching to form trenches 306 are shown, which can be used as oxide trenches to provide, on the one hand, the surface of the trenches as well as ... Figure 3G The oxide hole 306 shown can also be used as a barrier structure between the active regions of adjacent VCSELs along the crystal axis 2. Figure 3H The steps for depositing the SiNx layer 308 are shown. Figure 3I The results of through-hole etching lithography and seed layer 309 deposition are shown. Figure 3J The photolithography 310 used to achieve gold plating was demonstrated. Figure 3K The steps for gold plating 311 are shown. Figure 3L The final results are shown after additional steps such as seed layer removal, street etching in SiNx, bow-shaped compensation layer removal and wafer thinning, back n-type contact and bow-shaped compensation metal deposition and annealing. The back contact is indicated by reference numeral 322. Figure 3L The first VCSEL 11 and the second VCSEL 12 are now separated by the blocking structure 41. Therefore, it can effectively prevent... Figure 3L Defects in the active region 21 of the first VCSEL 11 propagate along the direction of the first crystal axis 2 to the adjacent second VCSEL.

[0044] Refer again Figure 2 And refer to Figures 4A to 4D Exemplary, non-limiting embodiments are described. A VCSEL array with 12 emitters emitting at 940 nm is presented for achieving high optical output power. The output characteristics are adapted to exhibit spectral single-mode behavior and a Gaussian-shaped far-field profile. The densely packaged emitter design per mm... 2 Up to 3850 emitters can be measured and is easily expanded for high-power applications. The basic architecture of the exemplary vertical-cavity surface-emitting laser (VCSEL) allows for densely packaged multi-emitter arrays to achieve high optical output power. As noted above, an oxide 940nm single-mode emitting VCSEL array with 12 output surfaces and a stable Gaussian far-field beam profile can be provided for various driving conditions and temperatures. Peak single-mode output power up to 300mW (>25mW per emitter) has been demonstrated under short-pulse conditions. Advantageously, excellent device reliability allows for industrial time-of-flight (ToF) applications over a wide temperature range.

[0045] In an embodiment, a GaAs-based epitaxial layer structure can be provided, comprising a GaAsP active region to achieve ultraviolet 940nm output characteristics, using oxide confinement to maintain spectral single-mode behavior. Chip design as follows... Figure 2As depicted, 12 emission windows are clearly visible as openings in the gold-plated electrical top surface contact, which includes the bonding pad 201 in the lower left of the image. The exemplary diced chip size is 187 × 187 μm. The back side of the chip may undergo wafer thinning and gold plating and serve as the electrical bottom surface contact (see [link]). Figure 3L (322 in the middle).

[0046] Light-current-voltage (LIV) measurement of an exemplary VCSEL array chip in Figure 4A As shown in the diagram, thermal roll-over of output power has not yet been achieved at currents above 30mA. The slope efficiency at 50°C is 0.90 W / A, with the threshold current ranging from 3mA to 6mA, depending on the ambient temperature. The optical output power of the oxide 12-emitter VCSEL array can be even higher than that of a single-mode VCSEL with a similar optical aperture using epitaxial regener. High-power concepts such as multi-junction VCSELs require higher forward voltages and do not provide single-mode emission.

[0047] like Figure 4B As shown, using short pulse conditions in the nanosecond range, the peak output power can be increased to over 300 mW (>25 mW per transmitter) while maintaining a slope efficiency of 0.75 W / A at room temperature. The output power can be further increased by scaling up to larger chips with the same transmitter density. For 0.97 mm... 2 With its small chip size and 2352 transmitters, a slope efficiency of approximately 1 W / A can be achieved by using pulse operation with a 200 μs pulse width and a 10% duty cycle. This can generate 4 W of output power at a current of 5 A.

[0048] like Figure 4C As shown, the spectral measurements of the 12-emitter VCSEL array exhibit single-mode behavior at 75°C, with an FWHM bandwidth of 300 GHz and a peak wavelength of approximately 937 nm. Narrow bandwidth spectra for each emitter are expected to emerge with increased spectral resolution. (See right side). Figure 4D As the images show, interference from all emitters produces a Gaussian-shaped far-field characteristic. In the given example, the divergence angle at 50°C is approximately 17°, with a small temperature drift of only -0.015° / °C in the range of 25 and 105°C. It should be noted that even in short-pulse operating modes in the ns range, the transverse mode behavior consistently maintains a Gaussian shape.

[0049] Reliability measurements of a set of exemplary devices implementing the proposed solution demonstrate outstanding results. No failures occurred after 3300 hours of continuous wave operation at currents below 32.5 mA and temperatures of 120°C. Under more extreme conditions such as 40 mA at 120°C and 25 mA at 150°C, the first failures occurred only after 600 hours and 1200 hours, respectively. Calculations for the time to 1% failure under pressure conditions such as 25 mA at 105°C provide a device lifetime exceeding 16,000 hours, setting a benchmark for high-power single-mode devices. In particular, multi-mesa defects can be significantly reduced. This is especially advantageous in application scenarios where a single VCSEL failure can be tolerated.

[0050] therefore, Figure 2 Show and reference in Figures 4A to 4D The exemplary device described in the experimental results provides a single-mode VCSEL array with 12 top-surface emitters to achieve high single-mode optical output power of up to 25mW at 30mA under low forward voltage without thermal flip-flop. Output power can be further increased by utilizing short pulses to achieve up to 25mW per emitter or by scaling up the emitter area of ​​a dense package, thus enabling power values ​​in the watt range. Even under short-pulse conditions, this 12-emitter device convincingly exhibits a low divergence angle without a higher lateral mode. The device's excellent reliability characteristics meet the requirements of long-life industrial applications.

[0051] refer to Figure 5 The thickness of the barrier structure can optionally vary based on the probability of a defect propagating from the first VCSEL 10 to the active region of the second VCSEL 11. Multiple sets of arrows 501 and 502 illustrate several potential propagation paths. For a defect originating from the upper edge of the first VCSEL 10, a narrow tip at the top of the barrier structure 41 may be sufficient, as the probability of a defect impacting this portion of the barrier structure is limited. However, a wider barrier region can be implemented towards the center of the barrier structure 41, as the probability of a defect reaching this portion of the barrier structure is higher.

[0052] Figure 6 A flowchart of a method 600 according to one aspect of the present invention is shown. In a first step S601, a semiconductor die is provided, the semiconductor die comprising a vertical layer stack suitable for fabricating a VCSEL. In a second step S602, the crystal axis of the semiconductor die in a direction parallel to the surface of the semiconductor die and perpendicular to the vertical layer stack is determined. In a third step S603, such as, for example, referring to... Figures 3A to 3LThe semiconductor device is fabricated from a semiconductor die as described above, the semiconductor device comprising: a first VCSEL having a first active region; a second VCSEL having a second active region; wherein the first active region of the first VCSEL and the second active region of the second VCSEL are arranged along a first crystal axis; and a barrier structure disposed between the first VCSEL and the second VCSEL, wherein the barrier structure is adapted to block defects from propagating along the first crystal axis between the first VCSEL and the second VCSEL.

[0053] While the invention has been shown and described in detail in the accompanying drawings and foregoing description, such showing and description is to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention from a study of the drawings, disclosure, and appended claims.

[0054] In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "an" or "a" do not exclude multiple. A single element or other unit can perform the function of several items listed in the claims. The simple fact that certain measures are listed in different dependent claims does not indicate that a combination of these measures cannot be used advantageously.

[0055] Computer programs can be stored / distributed on suitable non-transitory media (such as optical storage media or solid-state media provided with or as part of other hardware), but can also be distributed in other forms (such as via the Internet or other wired or wireless telecommunications systems).

[0056] Any reference numerals in the claims should not be construed as limiting the scope.

Claims

1. A semiconductor device (1) comprising a vertical cavity surface emitting laser (10, 11, 12, 13) VCSEL array, wherein, The semiconductor device comprises: - a first VCSEL (10) having a first active region (20); - a second VCSEL (11) having a second active region (21); - a bridge (31, 31') connecting the first and the second VCSEL; wherein the first active region of the first VCSEL and the second active region of the second VCSEL are arranged along a first crystal axis (2); and - a barrier structure (41) arranged between the first (10) and the second (11) VCSEL, wherein the barrier structure is adapted to block propagation of defects between the first and the second VCSEL along the first crystal axis (2), wherein the bridge (31) connecting the first (10) and the second (11) VCSEL is bent around one side of the barrier structure (41), thereby forming a narrow tip at the top end of the barrier structure (41) in a direction perpendicular to the first crystal axis (2).

2. The semiconductor device of claim 1, wherein, The VCSEL array is a dense package array having a pitch (p) of not more than 30 pm.

3. The semiconductor device according to claim 1 or 2, wherein The barrier structure (41) has a width (w2) in a direction perpendicular to the first crystal axis (2) which is wider than a width (w1) of the first and / or second active region in a direction perpendicular to the first crystal axis (2).

4. The semiconductor device according to claim 1 or 2, wherein The barrier structure (41) has a width (d1) in a direction parallel to the first crystal axis which is less than 30% of the VCSEL pitch.

5. The semiconductor device according to claim 1 or 2, wherein The barrier structure (41) comprises an etched region.

6. The semiconductor device of claim 5, wherein, The etched region has a depth which exceeds a depth of an active layer of the first and / or second VCSEL (10, 11).

7. The semiconductor device of claim 5, wherein, The etched region is separated from a top side contact (71, 72) of the first and / or second VCSEL.

8. The semiconductor device of claim 1 or 2, wherein, A second bridge (31') connecting the first (10) and the second (11) VCSEL is bent around a second side of the barrier structure (41) different from the one side.

9. The semiconductor device according to claim 1 or 2, wherein The bridge (31) connecting the first (10) and the second (11) VCSEL is a bridge connecting the first (10), the second (11) and an adjacent third (12) VCSEL.

10. The semiconductor device according to claim 1 or 2, wherein The first and second VCSEL (10, 11) of the array have a common top side contact and / or a common bottom side contact.

11. The semiconductor device according to claim 1 or 2, further comprising: - a third VCSEL (12) having a third active region (22); - a second bridge (32, 32') connecting the first and the third VCSEL; - a third bridge (33, 33') connecting the second and the third VCSEL. wherein a first active region (20) of the first VCSEL and a third active region (22) of the third VCSEL are arranged along a second crystal axis (3); and - a second barrier structure (42) arranged between the first VCSEL (10) and the third VCSEL (12), wherein the barrier structure is adapted to block propagation of defects between the first and third VCSEL along the second crystal axis (3).

12. The semiconductor device according to claim 1 or 2, wherein, The first VCSEL (10) has a rectangular active region, wherein a barrier structure is provided on each side of the active region.

13. The semiconductor device according to claim 1 or 2, wherein The semiconductor device (1) comprises a plurality of VCSELs (10, 11, 12, 13) arranged in rows and columns on a rectangular grid, wherein a separate barrier structure (41, 42) is provided between each pair of adjacent VCSELs on the grid.

14. The semiconductor device of claim 2, wherein, The array has a pitch (p) of no more than 20 pm.

15. The semiconductor device of claim 14, wherein, The array has a pitch (p) of no more than 17.5 pm.

16. The semiconductor device of claim 15, wherein, The array has a pitch (p) of no more than 15 pm.

17. The semiconductor device of claim 16, wherein, The array has a pitch (p) of no more than 10 pm.

18. The semiconductor device of claim 4, wherein, The barrier structure (41) has a width (dl) in a direction parallel to the first crystal axis which is less than 20% of the VCSEL pitch (p).

19. The semiconductor device of claim 18, wherein, The barrier structure (41) has a width (dl) in a direction parallel to the first crystal axis which is less than 10% of the VCSEL pitch.

20. The semiconductor device of claim 19, wherein, The barrier structure (41) has a width (dl) in a direction parallel to the first crystal axis which is less than 5% of the VCSEL pitch.

21. The semiconductor device of claim 5, wherein, The barrier structure comprises a trench for oxidizing the first and / or second VCSEL (10, 11).

22. The semiconductor device of claim 9, wherein, The bridge (31) connecting the first (10) and second (11) VCSELs is a bridge connecting the first (10), second (11), third (12) and also fourth (13) VCSELs.

23. The semiconductor device of claim 12, wherein, The first VCSEL (10) has a square active region.

24. The semiconductor device of claim 13, wherein, The semiconductor device (1) comprises a plurality of VCSELs (10, 11, 12, 13) arranged in rows and columns on a square grid.

25. A method (600) for manufacturing a semiconductor device comprising a vertical cavity surface emitting laser (10, 11, 12, 13), VCSEL array, the method comprising the steps of: - providing a semiconductor die comprising a vertical layer stack (S601) adapted to manufacture a VCSEL; - determining a crystal axis of the semiconductor die in a direction parallel to a surface of the semiconductor die and perpendicular to the vertical layer stack (S602); - processing the semiconductor die into a semiconductor device (S603), the semiconductor device comprising: - a first VCSEL having a first active region; - a second VCSEL having a second active region; - a bridge (31, 31') connecting the first and the second VCSEL; wherein a first active region of the first VCSEL and a second active region of the second VCSEL are arranged along a first crystal axis; and - a barrier structure arranged between the first and the second VCSEL, wherein the barrier structure is adapted to block propagation of defects between the first and the second VCSEL along the first crystal axis, wherein the bridge (31) connecting the first (10) and the second (11) VCSEL is bent around one side of the barrier structure (41), thereby forming a narrow tip at the top end of the barrier structure (41) in a direction perpendicular to the first crystal axis (2).

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