A seven-level hybrid clamped inverter topology and voltage balance modulation method thereof

Abstract

The present invention relates to a seven-level hybrid clamped inverter topology and a voltage balancing modulation method thereof, comprising a DC input source Udc, two series-connected DC bus capacitors C1 and C2, and a three-phase circuit whose input is connected in parallel with the DC bus capacitors C1 and C2 of the three-phase circuit. The present invention has the following advantages: 1. The present invention discloses a seven-level hybrid clamped inverter topology, and the combination of IGBT devices and wide bandgap devices is conducive to further reducing the cost of the seven-level hybrid clamped inverter topology. 2. The present invention discloses a voltage balancing modulation strategy suitable for a seven-level hybrid clamped inverter, which can effectively balance the flying capacitor voltage and the DC bus capacitor voltage.

Description

Technical Field

[0001] The invention relates to a seven-level hybrid clamped inverter topology and a voltage balance modulation method thereof. Background Art

[0002] As an important part of energy-efficient power electronic conversion technology, multi-level inverters have advantages such as lower switching losses and less output voltage harmonic content compared to traditional two-level inverters, and are therefore widely used in medium-voltage and high-power applications such as industrial power supplies, new energy power generation, rail transit, and large ships. In medium-voltage and high-power applications, the increase in the number of output levels of multi-level inverters is conducive to further reducing the voltage stress of each switching device, reducing dv / dt, reducing switching losses, and improving power quality. Summary of the invention

[0003] The technical solution of the present invention provides a seven-level hybrid clamped inverter topology, including a DC input source U dc 、Two series DC bus capacitors C 1 and C 2 , and the input and three-phase circuit DC bus capacitor C 1 and C 2 Three-phase circuits in parallel.

[0004] In the above-mentioned seven-level hybrid clamped inverter topology, the three-phase circuit has the same structure, including switch tubes T connected in series in sequence. x1 To switch tube T x4 ; and the switch tubes S connected in series x1 To switch tube S x6 ; Switch tubes S connected in series x1 To switch tube S x6 One end is connected to the switch tube T x1 And switch tube T x2 In parallel, the other end is connected to the switch tube T x3 And switch tube T x4 Parallel; switch tube S x7 , switch tube S x8 and the flying capacitor C fx1 、Flying capacitor C fx2 The H bridge is connected across the switch tube S x1 To switch tube S x6 Upper: Switching tube S x3 And switch tube S x4 The connection node is the output u x ; Where x is the three phases a, b, and c.

[0005] In the above-mentioned seven-level hybrid clamped inverter topology, the switch tube T x1 , switch tube Tx2 , switch tube T x3 , switch tube T x4 Working at fundamental frequency, IGBT device is selected; switch tube S x1 , switch tube S x2 , switch tube S x3 , switch tube S x4 , switch tube S x5 , switch tube S x6 , switch tube S x7 , switch tube S x8 When operating at high switching frequencies, wide bandgap devices can be used, specifically SiC MOSFET or GaN devices.

[0006] In the above-mentioned seven-level hybrid clamped inverter topology, in the A phase circuit, the switch tube T a1 The collector of is connected to the DC input source U dc The positive terminal and capacitor C 1 The positive pole of the switch tube T a1 The emitter is connected to the switch tube T a2 The collector and switch tube S a1 The drain of the switch tube T a2 The emitter is connected to the switch tube T a3 The collector and bus capacitance C 1 , C 2 The center point N, the switch tube T a3 The emitter is connected to the switch tube T a4 The collector and switch tube S a6 The source of the switch tube S a6 The drain of fa2 The negative electrode and the switch tube S a5 The source of the switch tube S a5 The drain of the switch tube S a8 The source and switch tube S a4 The source of the switch tube S a4 The drain of the switch tube S a3 The source of the A phase circuit is used as the output terminal, and the switch tube S a3 The drain of the switch tube S a7 The drain and switch S a2 The source of the switch tube S a7 The source of the switch S a8 The drain and flying capacitor C fa1 The negative electrode and flying capacitor C fa2 The positive electrode of the switch tube S a2 The drain of the switch tube S a1 The source and flying capacitor C fa1 The positive electrode of the switch tube S a1The drain of the switch tube T a1 The emitter and switch tube T a2 The collector.

[0007] In the above-mentioned seven-level hybrid clamped inverter topology, in the B-phase circuit, the switch tube T b1 The collector of is connected to the DC input source U dc The positive terminal and capacitor C 1 The positive pole of the switch tube T b1 The emitter is connected to the switch tube T b2 The collector and switch tube S b1 The drain of the switch tube T b2 The emitter is connected to the switch tube T b3 The collector and bus capacitance C 1 , C 2 The center point N, the switch tube T b3 The emitter is connected to the switch tube T b4 The collector and switch tube S b6 The source of the switch tube S b6 The drain of fb2 The negative electrode and the switch tube S b5 The source of the switch tube S b5 The drain of the switch tube S b8 The source and switch tube S b4 The source of the switch tube S b4 The drain of the switch tube S b3 The source of the B-phase circuit is used as the output terminal, and the switch tube S b3 The drain of the switch tube S b7 The drain and switch S b2 The source of the switch tube S b7 The source of the switch S b8 The drain and flying capacitor C fb1 The negative electrode and flying capacitor C fb2 The positive electrode of the switch tube S b2 The drain of the switch tube S b1 The source and flying capacitor C fb1 The positive electrode of the switch tube S b1 The drain of the switch tube T b1 The emitter and switch tube T b2 The collector.

[0008] In the above-mentioned seven-level hybrid clamped inverter topology, in the B-phase circuit, the switch tube T c1 The collector of is connected to the DC input source U dc The positive terminal and capacitor C 1 The positive pole of the switch tube T c1 The emitter is connected to the switch tube Tc2 The collector and switch tube S c1 The drain of the switch tube T c2 The emitter is connected to the switch tube T c3 The collector and bus capacitance C 1 , C 2 The center point N, the switch tube T c3 The emitter is connected to the switch tube T c4 The collector and switch tube S c6 The source of the switch tube S a6 The drain of fc2 The negative electrode and the switch tube S c5 The source of the switch tube S c5 The drain of the switch tube S c8 The source and switch tube S c4 The source of the switch tube S c4 The drain of the switch tube S c3 The source of the C phase circuit is used as the output terminal of the switch tube S c3 The drain of the switch tube S c7 The drain and switch S c2 The source of the switch tube S c7 The source of the switch S c8 The drain and flying capacitor C fc1 The negative electrode and flying capacitor C fc2 The positive electrode of the switch tube S c2 The drain of the switch tube S c1 The source and flying capacitor C fc1 The positive electrode of the switch tube S c1 The drain of the switch tube T c1 The emitter and switch tube T c2 The collector.

[0009] A voltage balancing modulation method using a seven-level hybrid clamped inverter topology, characterized in that:

[0010] The modulation signal of the seven-level hybrid clamped inverter is defined as:

[0011]

[0012] Among them, u refa is the modulation signal of phase A circuit, u refb is the modulation signal of the B phase circuit, u refc is the modulation signal of the C phase circuit; m is the modulation ratio, f m is the fundamental frequency.

[0013] In the A phase circuit, based on the modulation signal u refa The modulated signal u can be obtained refa1 、urefa2 、u refa3 for:

[0014]

[0015]

[0016] Similarly, for the B phase circuit, based on the modulation signal u refb The modulated signal u can be obtained refb1 、u refb2 、u refb3 for:

[0017]

[0018]

[0019] For the C phase circuit, based on the modulation signal u refc The modulated signal u can be obtained refc1 、u refc2 、u refc3 for:

[0020]

[0021]

[0022] The deviation between the flying capacitor voltage and the reference voltage is defined as:

[0023]

[0024] Among them, ΔU fa1 , ΔU fa2 They are respectively the flying capacitor C of phase A circuit fa1 , C fa2 Voltage deviation, ΔU fb1 , ΔU fb2 They are respectively the flying capacitor C of phase B circuit fb1 , C fb2 Voltage deviation, ΔU fc1 , ΔU fc2 They are respectively the flying capacitor C of the C phase circuit fc1 , C fc2 voltage deviation.

[0025] Taking the A phase circuit as an example, the voltage balance modulation strategy is as follows: Figure 3 As shown, the waveforms of the modulation logic comparison and key switch tube signals are as follows Figure 4 The effect of the switching state of the A phase circuit on the flying capacitor voltage is shown in Figure 5 As shown, based on this figure, the flying capacitor voltage balance control strategy of the A phase circuit is described as follows:

[0026] 1) In order to output phase voltage u a =1 / 2U dc , select switch state A1.

[0027] 2) In order to output phase voltage u a =1 / 3U dc , when the output phase current i a ≥0 and satisfy: ①ΔU fa1 ≥0 or ②ΔU fa1 <0, ΔU fa2 >0,|ΔU fa1 |<|ΔU fa2 |, select switch state B1, otherwise select switch state B2; when the output phase current i a <0 and satisfies: ①ΔU fa1 <0 or ②ΔU fa1 ≥0, ΔU fa2 ≤0,|ΔU fa1 |≤|ΔU fa2 |, select switch state B1, otherwise select switch state B2.

[0028] 3) For output voltage u a =1 / 6U dc , when the output phase current i a ≥0 and satisfy: ①ΔU fa2 ≤0 or ②ΔU fa1 <0, ΔU fa2 >0,|ΔU fa1 |>|ΔU fa2 |, select switch state C2, otherwise select switch state C1; when the output phase current i a <0 and satisfies: ①ΔU fa2 >0 or ②ΔU fa1 ≥0, ΔU fa2 ≤0,|ΔU fa1 |≥|ΔU fa2 |, select switch state C2, otherwise select switch state C1.

[0029] 4) In order to output phase voltage u a =0, select switch state D1 or D2.

[0030] 5) In order to output phase voltage u a =-1 / 6U dc , when the output phase current i a ≥0 and satisfy: ①ΔU fa1 ≥0 or ②ΔU fa1 <0, ΔU fa2 >0,|ΔU fa1 |<|ΔU fa2|, select switch state E1, otherwise select switch state E2; when the output phase current i a <0 and satisfies: ①ΔU fa1 <0 or ②ΔU fa1 ≥0, ΔU fa2 ≤0,|ΔU fa1 |≤|ΔU fa2 |, select switch state E1, otherwise select switch state E2.

[0031] 6) For output voltage u a =-1 / 3U dc , when the output phase current i a ≥0 and satisfy: ①ΔU fa2 ≤0 or ②ΔU fa1 <0, ΔU fa2 >0,|ΔU fa1 |>|ΔU fa2 |, select switch state F2, otherwise select switch state F1; when the output phase current i a <0 and satisfies: ①ΔU fa2 >0 or ②ΔU fa1 ≥0, ΔU fa2 ≤0,|ΔU fa1 |≥|ΔU fa2 |, select switch state F2, otherwise select switch state F1.

[0032] 7) In order to output phase voltage u a =-1 / 2U dc , select switch state G1.

[0033] Through the proposed voltage balance modulation strategy, the output voltage u of each phase can be x The size is 1 / 2U dc , or 1 / 3U dc , or 1 / 6U dc , or 0, or -1 / 6U dc , or -1 / 3U dc , or -1 / 2U dc .

[0034] The present invention has the following advantages:

[0035] 1. The present invention discloses a seven-level hybrid clamped inverter topology, which combines IGBT devices and wide bandgap devices, thereby further reducing the cost of the seven-level hybrid clamped inverter topology.

[0036] 2. The present invention discloses a voltage balancing modulation strategy suitable for a seven-level hybrid clamped inverter, which can effectively balance the flying capacitor voltage and the DC bus capacitor voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The seven-level hybrid clamped inverter topology provided by the present invention;

[0038] FIG2(a) is an equivalent circuit diagram of the provided seven-level hybrid clamped inverter (output 1 / 2U dc );

[0039] FIG2(b) is an equivalent circuit diagram of the provided seven-level hybrid clamped inverter (output 1 / 3U dc );

[0040] FIG2(c) is an equivalent circuit diagram of the seven-level hybrid clamped inverter (output 1 / 3U dc );

[0041] FIG2(d) is an equivalent circuit of the provided seven-level hybrid clamped inverter (output 1 / 6U dc );

[0042] FIG2(e) is an equivalent circuit of the provided seven-level hybrid clamped inverter (output 1 / 6U dc );

[0043] FIG2( f ) is an equivalent circuit of the provided seven-level hybrid clamped inverter (output 0);

[0044] FIG2( g ) is an equivalent circuit of the provided seven-level hybrid clamped inverter (output 0);

[0045] FIG2(h) is an equivalent circuit diagram of the provided seven-level hybrid clamped inverter (output -1 / 6U dc );

[0046] FIG2(i) is an equivalent circuit diagram of the provided seven-level hybrid clamped inverter (output -1 / 6U dc );

[0047] FIG2(j) is an equivalent circuit diagram of the provided seven-level hybrid clamped inverter (output -1 / 3U dc );

[0048] FIG2(k) is an equivalent circuit diagram of the provided seven-level hybrid clamped inverter (output -1 / 3U dc );

[0049] FIG2(l) is an equivalent circuit diagram of the provided seven-level hybrid clamped inverter (output -1 / 2U dc );

[0050] Figure 3 A voltage balancing modulation strategy for a seven-level hybrid clamped inverter;

[0051] Figure 4 is the switch tube T in the A phase circuit of the seven-level hybrid clamped inverter a1 , S a1 , S a2 , S a3 The switch sequence;

[0052] Figure 5 Figure 3 shows the influence of various switching states of the seven-level hybrid clamped inverter on the charging and discharging of the flying capacitor. DETAILED DESCRIPTION

[0053] The technical solution of the present invention is further specifically described below through embodiments and in conjunction with the accompanying drawings.

[0054] Example:

[0055] The present invention provides a Figure 1 The seven-level hybrid clamped inverter topology shown in the figure consists of a DC input source (U dc ), two series DC bus capacitors (C 1 , C 2 ) and three-phase circuit.

[0056] The A phase circuit of the proposed seven-level hybrid clamped inverter topology consists of switch tube T a1 , switch tube T a2 , switch tube T a3 , switch tube T a4 , switch tube S a1 , switch tube S a2 , switch tube S a3 , switch tube S a4 , switch tube S a5 , switch tube S a6 , switch tube S a7 , switch tube S a8 and the flying capacitor C fa1 、Flying capacitor C fa2 composition.

[0057] Among them, the switch tube T a1 , switch tube T a2 , switch tube T a3 , switch tube T a4 Working at the fundamental frequency, IGBT devices can be selected; switch tube S a1 , switch tube S a2 , switch tube S a3 , switch tube S a4 , switch tube S a5 , switch tube S a6 , switch tube S a7 , switch tube S a8When operating at high switching frequencies, wide bandgap devices such as SiC MOSFET or GaN devices can be used.

[0058] The switch tube T a1 The collector of is connected to the DC input source U dc The positive terminal and capacitor C 1 The positive pole of the switch tube T a1 The emitter is connected to the switch tube T a2 The collector and switch tube S a1 The drain of the switch tube T a2 The emitter is connected to the switch tube T a3 The collector and bus capacitance C 1 , C 2 The center point N, the switch tube T a3 The emitter is connected to the switch tube T a4 The collector and switch tube S a6 The source of the switch tube S a6 The drain of fa2 The negative electrode and the switch tube S a5 The source of the switch tube S a5 The drain of the switch tube S a8 The source and switch tube S a4 The source of the switch tube S a4 The drain of the switch tube S a3 The source of the A phase circuit is used as the output terminal, and the switch tube S a3 The drain of the switch tube S a7 The drain and switch S a2 The source of the switch tube S a7 The source of the switch S a8 The drain and flying capacitor C fa1 The negative electrode and flying capacitor C fa2 The positive electrode of the switch tube S a2 The drain of the switch tube S a1 The source and flying capacitor C fa1 The positive electrode of the switch tube S a1 The drain of the switch tube T a1 The emitter and switch tube T a2 The collector.

[0059] The B phase circuit of the proposed seven-level hybrid clamped inverter topology consists of switch tube T b1 , switch tube T b2 , switch tube T b3 , switch tube T b4 , switch tube S b1 , switch tube S b2 , switch tube S b3 , switch tube S b4, switch tube S b5 , switch tube S b6 , switch tube S b7 , switch tube S b8 and the flying capacitor C fb1 、Flying capacitor C fb2 composition.

[0060] Among them, the switch tube T b1 , switch tube T b2 , switch tube T b3 , switch tube T b4 Working at the fundamental frequency, IGBT devices can be selected; switch tube S b1 , switch tube S b2 , switch tube S b3 , switch tube S b4 , switch tube S b5 , switch tube S b6 , switch tube S b7 , switch tube S b8 When operating at high switching frequencies, wide bandgap devices such as SiC MOSFET or GaN devices can be used.

[0061] The switch tube T b1 The collector of is connected to the DC input source U dc The positive terminal and capacitor C 1 The positive pole of the switch tube T b1 The emitter is connected to the switch tube T b2 The collector and switch tube S b1 The drain of the switch tube T b2 The emitter is connected to the switch tube T b3 The collector and bus capacitance C 1 , C 2 The center point N, the switch tube T b3 The emitter is connected to the switch tube T b4 The collector and switch tube S b6 The source of the switch tube S b6 The drain of fb2 The negative electrode and the switch tube S b5 The source of the switch tube S b5 The drain of the switch tube S b8 The source and switch tube S b4 The source of the switch tube S b4 The drain of the switch tube S b3 The source of the B-phase circuit is used as the output terminal, and the switch tube S b3 The drain of the switch tube S b7 The drain and switch S b2 The source of the switch tube S b7 The source of the switch Sb8 The drain and flying capacitor C fb1 The negative electrode and flying capacitor C fb2 The positive electrode of the switch tube S b2 The drain of the switch tube S b1 The source and flying capacitor C fb1 The positive electrode of the switch tube S b1 The drain of the switch tube T b1 The emitter and switch tube T b2 The collector.

[0062] The C phase circuit of the proposed seven-level hybrid clamped inverter topology consists of switch tube T c1 , switch tube T c2 , switch tube T c3 , switch tube T c4 , switch tube S c1 , switch tube S c2 , switch tube S c3 , switch tube S c4 , switch tube S c5 , switch tube S c6 , switch tube S c7 , switch tube S c8 and the flying capacitor C fc1 、Flying capacitor C fc2 composition.

[0063] Among them, the switch tube T c1 , switch tube T c2 , switch tube T c3 , switch tube T c4 Working at the fundamental frequency, IGBT devices can be selected; switch tube S c1 , switch tube S c2 , switch tube S c3 , switch tube S c4 , switch tube S c5 , switch tube S c6 , switch tube S c7 , switch tube S c8 When operating at high switching frequencies, wide bandgap devices such as SiC MOSFET or GaN devices can be used.

[0064] The switch tube T c1 The collector of is connected to the DC input source U dc The positive terminal and capacitor C 1 The positive pole of the switch tube T c1 The emitter is connected to the switch tube T c2 The collector and switch tube S c1 The drain of the switch tube T c2 The emitter is connected to the switch tube T c3 The collector and bus capacitance C1 , C 2 The center point N, the switch tube T c3 The emitter is connected to the switch tube T c4 The collector and switch tube S c6 The source of the switch tube S a6 The drain of fc2 The negative electrode and the switch tube S c5 The source of the switch tube S c5 The drain of the switch tube S c8 The source and switch tube S c4 The source of the switch tube S c4 The drain of the switch tube S c3 The source of the C phase circuit is used as the output terminal of the switch tube S c3 The drain of the switch tube S c7 The drain and switch S c2 The source of the switch tube S c7 The source of the switch S c8 The drain and flying capacitor C fc1 The negative electrode and flying capacitor C fc2 The positive electrode of the switch tube S c2 The drain of the switch tube S c1 The source and flying capacitor C fc1 The positive electrode of the switch tube S c1 The drain of the switch tube T c1 The emitter and switch tube T c2 The collector.

[0065] When working, taking the A phase circuit of the seven-level hybrid clamp inverter topology as an example, the switching sequence of each switch tube is as follows: Figure 4 As shown, the corresponding equivalent circuit of the A-phase circuit is shown in Figure 2.

[0066] (1) As shown in Figure 2(a), the switch tube T a1 , switch tube T a3 , switch tube S a1 , switch tube S a2 , switch tube S a3 conduction, output voltage u a The size is 1 / 2U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a1 , switch tube S a1 , switch tube S a2 And switch tube S a3 When the current i a When the current i a Flowing through the switch tube S a3, switch tube S a2 , switch tube S a1 And switch tube T a1 In this switching state, the flying capacitor C fa1 and the flying capacitor C fa2 The capacitor voltage remains unchanged.

[0067] (2) As shown in Figure 2(b), the switch tube T a1 , switch tube T a3 , switch tube S a2 , switch tube S a3 And switch tube S a6 conduction, output voltage u a The size is 1 / 3U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a3 , switch tube S a6 、Flying capacitor C fa2 、Flying capacitor C fa1 , switch tube S a2 And switch tube S a3 , flying capacitor C fa1 and the flying capacitor C fa2 Discharge; when the current i a When the current i a Flowing through the switch tube S a3 , switch tube S a2 、Flying capacitor C fa1 、Flying capacitor C fa2 , switch tube S a6 And switch tube T a3 The anti-parallel diode, flying capacitor C fa1 and the flying capacitor C fa2 Charge.

[0068] (3) As shown in Figure 2(c), the switch tube T a1 , switch tube T a3 , switch tube S a1 , switch tube S a3 , switch tube S a4 And switch tube S a7 conduction, output voltage u a The size is 1 / 3U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a1 , switch tube S a1 、Flying capacitor C fa1 , switch tube S a7 And switch tube S a3 , flying capacitor Cfa1 Discharge the flying capacitor C fa2 The voltage remains constant; when the current i a When the current i a Flowing through the switch tube S a3 , switch tube S a2 、Flying capacitor C fa1 、Flying capacitor C fa2 , switch tube S a6 And switch tube T a3 The anti-parallel diode, flying capacitor C fa1 and the flying capacitor C fa2 Charge.

[0069] (4) As shown in Figure 2(d), the switch tube T a1 , switch tube T a3 , switch tube S a3 , switch tube S a4 , switch tube S a6 , switch tube S a7 , switch tube S a8 conduction, output voltage u a The size is 1 / 6U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a3 , switch tube S a6 、Flying capacitor C fa2 , switch tube S a7 , switch tube S a3 , switch tube S a4 , switch tube S a8 , flying capacitor C fa2 Discharge the flying capacitor C fa1 The voltage remains constant; when the current i a When the current i a Flowing through the switch tube S a3 , switch tube S a4 , switch tube S a7 , switch tube S a3 、Flying capacitor C fa2 , switch tube S a6 And switch tube T a3 The anti-parallel diode, flying capacitor C fa2 Charge the flying capacitor C fa1 The voltage remains unchanged.

[0070] (5) As shown in Figure 2(e), the switch tube T a1 , switch tube T a3 , switch tube S a1 , switch tube S a4 , switch tube S a5, switch tube S a7 conduction, output voltage u a The size is 1 / 6U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a1 , switch tube S a1 、Flying capacitor C fa1 、Flying capacitor C fa2 , switch tube S a5 And switch tube S a4 , flying capacitor C fa1 and the flying capacitor C fa2 are all charged; when the current i a When the current i a Flowing through the switch tube S a4 , switch tube S a5 、Flying capacitor C fa2 、Flying capacitor C fa1 , switch tube S a1 And switch tube T a1 The anti-parallel diode, flying capacitor C fa1 and the flying capacitor C fa2 All discharge.

[0071] (6) As shown in Figure 2(f), the switch tube T a1 , switch tube T a3 , switch tube S a4 , switch tube S a5 , switch tube S a6 And switch tube S a7 conduction, output voltage u a The magnitude is 0. When the current i a When flowing out, the current i a Flowing through the switch tube T a3 , switch tube S a6 , switch tube S a5 And switch tube S a4 , flying capacitor C fa1 and the flying capacitor C fa2 The voltage remains constant; when the current i a When the current i a Flowing through the switch tube S a4 , switch tube S a5 , switch tube S a6 And switch tube T a3 The anti-parallel diode, flying capacitor C fa1 and the flying capacitor C fa2 The voltage remains unchanged.

[0072] (7) As shown in Figure 2(g), the switch tube T a2 , switch tube Ta4 , switch tube S a1 , switch tube S a2 , switch tube S a3 And switch tube S a8 conduction, output voltage u a The magnitude is 0. When the current i a When flowing out, the current i a Flowing through the switch tube T a2 The anti-parallel diode and switch tube S a1 , switch tube S a2 And switch tube S a3 , flying capacitor C fa1 and the flying capacitor C fa2 The voltage remains constant; when the current i a When the current i a Flowing through the switch tube S a3 , switch tube S a2 , switch tube S a1 And switch tube T a2 , flying capacitor C fa1 and the flying capacitor C fa2 The voltage remains unchanged.

[0073] (8) As shown in Figure 2(h), the switch tube T a2 , switch tube T a4 , switch tube S a2 , switch tube S a3 , switch tube S a6 And switch tube S a8 conduction, output voltage u a The size is -1 / 6U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a4 The anti-parallel diode and switch tube S a6 、Flying capacitor C fa2 、Flying capacitor C fa1 , switch tube S a2 And switch tube S a3 , flying capacitor C fa1 and the flying capacitor C fa2 All discharge; when the current i a When the current i a Flowing through the switch tube S a3 , switch tube S a2 、Flying capacitor C fa1 、Flying capacitor C fa2 , switch tube S a6 And switch tube T a4 , flying capacitor C fa1 and the flying capacitor C fa2All charged.

[0074] (9) As shown in Figure 2(i), the switch tube T a2 , switch tube T a4 , switch tube S a1 , switch tube S a3 , switch tube S a4 , switch tube S a7 And switch tube S a8 conduction, output voltage u a The size is -1 / 6U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a2 The anti-parallel diode and switch tube S a1 、Flying capacitor C fa1 , switch tube S a7 , switch tube S a8 , switch tube S a3 And switch tube S a4 , flying capacitor C fa1 Charge the flying capacitor C fa2 The voltage remains constant; when the current i a When the current i a Flowing through the switch tube S a3 , switch tube S a4 , switch tube S a7 , switch tube S a8 、Flying capacitor C fa1 , switch tube S a1 And switch tube T a2 , flying capacitor C fa1 Discharge the flying capacitor C fa2 The voltage remains unchanged.

[0075] (10) As shown in Figure 2(j), the switch tube T a2 , switch tube T a4 , switch tube S a3 , switch tube S a4 , switch tube S a6 , switch tube S a7 And switch tube S a8 conduction, output voltage u a The size is -1 / 3U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a4 The anti-parallel diode and switch tube S a6 、Flying capacitor C fa2 , switch tube S a7 , switch tube S a8 , switch tube Sa3 And switch tube S a4 , flying capacitor C fa2 Discharge the flying capacitor C fa1 The voltage remains constant; when the current i a When the current i a Flowing through the switch tube S a3 , switch tube S a4 , switch tube S a7 , switch tube S a8 、Flying capacitor C fa2 , switch tube S a6 And switch tube T a2 , flying capacitor C fa1 Charge the flying capacitor C fa1 The voltage remains unchanged.

[0076] (11) As shown in Figure 2(k), the switch tube T a2 , switch tube T a4 , switch tube S a1 , switch tube S a4 , switch tube S a5 And switch tube S a7 conduction, output voltage u a The size is -1 / 3U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a2 The anti-parallel diode and flying capacitor C fa1 、Flying capacitor C fa2 , switch tube S a5 And switch tube S a4 , flying capacitor C fa1 and the flying capacitor C fa2 are all charged; when the current i a When the current i a Flowing through the switch tube S a4 , switch tube S a5 、Flying capacitor C fa2 、Flying capacitor C fa1 , switch tube S a1 And switch tube T a2 , flying capacitor C fa1 and the flying capacitor C fa2 All discharge.

[0077] (12) As shown in Figure 2(l), the switch tube T a2 , switch tube T a4 , switch tube S a4 , switch tube S a5 , switch tube S a6 And switch tube S a7conduction, output voltage u a The size is -1 / 2U dc When the current i a When flowing out, the current i a Flowing through the switch tube T a4 The anti-parallel diode and switch tube S a6 , switch tube S a5 And switch tube S a4 , flying capacitor C fa1 and the flying capacitor C fa2 The voltage remains constant; when the current i a When the current i a Flowing through the switch tube S a4 , switch tube S a5 , switch tube S a6 And switch tube T a4 , flying capacitor C fa1 and the flying capacitor C fa2 The voltage remains unchanged.

[0078] The modulation signal of the seven-level hybrid clamped inverter is defined as:

[0079]

[0080] Among them, u refa is the modulation signal of phase A circuit, u refb is the modulation signal of the B phase circuit, u refc is the modulation signal of the C phase circuit; m is the modulation ratio, f m is the fundamental frequency.

[0081] In the A phase circuit, based on the modulation signal u refa The modulated signal u can be obtained refa1 、u refa2 、u refa3 for:

[0082]

[0083]

[0084] Similarly, for the B phase circuit, based on the modulation signal u refb The modulated signal u can be obtained refb1 、u refb2 、u refb3 for:

[0085]

[0086]

[0087] For the C phase circuit, based on the modulation signal u refcThe modulated signal u can be obtained refc1 、u refc2 、u refc3 for:

[0088]

[0089]

[0090] The deviation between the flying capacitor voltage and the reference voltage is defined as:

[0091]

[0092] Among them, ΔU fa1 , ΔU fa2 They are respectively the flying capacitor C of phase A circuit fa1 , C fa2 Voltage deviation, ΔU fb1 , ΔU fb2 They are respectively the flying capacitor C of phase B circuit fb1 , C fb2 Voltage deviation, ΔU fc1 , ΔU fc2 They are respectively the flying capacitor C of the C phase circuit fc1 , C fc2 voltage deviation.

[0093] Taking the A phase circuit as an example, the voltage balance modulation strategy is as follows: Figure 3 As shown, the waveforms of the modulation logic comparison and key switch tube signals are as follows Figure 4 The effect of the switching state of the A phase circuit on the flying capacitor voltage is shown in Figure 5 As shown, based on this figure, the flying capacitor voltage balance control strategy of the A phase circuit is described as follows:

[0094] 1) In order to output phase voltage u a =1 / 2U dc , select switch state A1.

[0095] 2) In order to output phase voltage u a =1 / 3U dc , when the output phase current i a ≥0 and satisfy: ①ΔU fa1 ≥0 or ②ΔU fa1 <0, ΔU fa2 >0,|ΔU fa1 |<|ΔU fa2 |, select switch state B1, otherwise select switch state B2; when the output phase current i a <0 and satisfies: ①ΔU fa1 <0 or ②ΔU fa1 ≥0, ΔU fa2≤0,|ΔU fa1 |≤|ΔU fa2 |, select switch state B1, otherwise select switch state B2.

[0096] 3) For output voltage u a =1 / 6U dc , when the output phase current i a ≥0 and satisfy: ①ΔU fa2 ≤0 or ②ΔU fa1 <0, ΔU fa2 >0,|ΔU fa1 |>|ΔU fa2 |, select switch state C2, otherwise select switch state C1; when the output phase current i a <0 and satisfies: ①ΔU fa2 >0 or ②ΔU fa1 ≥0, ΔU fa2 ≤0,|ΔU fa1 |≥|ΔU fa2 |, select switch state C2, otherwise select switch state C1.

[0097] 4) In order to output phase voltage u a =0, select switch state D1 or D2.

[0098] 5) In order to output phase voltage u a =-1 / 6U dc , when the output phase current i a ≥0 and satisfy: ①ΔU fa1 ≥0 or ②ΔU fa1 <0, ΔU fa2 >0,|ΔU fa1 |<|ΔU fa2 |, select switch state E1, otherwise select switch state E2; when the output phase current i a <0 and satisfies: ①ΔU fa1 <0 or ②ΔU fa1 ≥0, ΔU fa2 ≤0,|ΔU fa1 |≤|ΔU fa2 |, select switch state E1, otherwise select switch state E2.

[0099] 6) For output voltage u a =-1 / 3U dc , when the output phase current i a ≥0 and satisfy: ①ΔU fa2 ≤0 or ②ΔU fa1 <0, ΔU fa2 >0,|ΔU fa1 |>|ΔUfa2 |, select switch state F2, otherwise select switch state F1; when the output phase current i a <0 and satisfies: ①ΔU fa2 >0 or ②ΔU fa1 ≥0, ΔU fa2 ≤0,|ΔU fa1 |≥|ΔU fa2 |, select switch state F2, otherwise select switch state F1.

[0100] 7) In order to output phase voltage u a =-1 / 2U dc , select switch state G1.

[0101] Through the proposed voltage balance modulation strategy, the output voltage u of each phase can be x The size is 1 / 2U dc , or 1 / 3U dc , or 1 / 6U dc , or 0, or -1 / 6U dc , or -1 / 3U dc , or -1 / 2U dc .

[0102] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific implementation cases described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the attached claims.

Claims

1. A seven-level hybrid clamped inverter topology, It is characterized in that Including DC input source U dc 、Two series DC bus capacitors C 1 and C 2 , and the input and three-phase circuit DC bus capacitor C 1 and C 2 Three-phase circuits in parallel; The three-phase circuits have the same structure and all include switch tubes T connected in series. x1 To switch tube T x4 ; and the switch tubes S connected in series x1 To switch tube S x6 ; Switch tubes S connected in series x1 To switch tube S x6 One end is connected to the switch tube T x1 And switch tube T x2 In parallel, the other end is connected to the switch tube T x3 And switch tube T x4 Parallel; switch tube S x7 , switch tube S x8 and the flying capacitor C fx1 、Flying capacitor C fx2 The H bridge is connected across the switch tube S x1 To switch tube S x6 Upper: Switching tube S x3 And switch tube S x4 The connection node is the output u x ; Where x is the three phases a, b and c; In the A phase circuit, the switch tube T a1 The collector of is connected to the DC input source U dc The positive terminal and capacitor C 1 The positive pole of the switch tube T a1 The emitter is connected to the switch tube T a2 The collector and switch tube S a1 The drain of the switch tube T a2 The emitter is connected to the switch tube T a3 The collector and bus capacitance C 1 , C 2 The center point N, the switch tube T a3 The emitter is connected to the switch tube T a4 The collector and switch tube S a6 The source of the switch tube S a6 The drain of fa2 The negative electrode and the switch tube S a5 The source of the switch tube S a5 The drain of the switch tube S a8 The source and switch tube S a4 The source of the switch tube S a4 The drain of the switch tube S a3 The source of the A phase circuit is used as the output terminal, and the switch tube S a3 The drain of the switch tube S a7 The drain and switch S a2 The source of the switch tube S a7 The source of the switch S a8 The drain and flying capacitor C fa1 The negative electrode and flying capacitor C fa2 The positive electrode of the switch tube S a2 The drain of the switch tube S a1 The source and flying capacitor C fa1 The positive electrode of the switch tube S a1 The drain of the switch tube T a1 The emitter and switch tube T a2 The collector; In the B phase circuit, the switch tube T b1 The collector of is connected to the DC input source U dc The positive terminal and capacitor C 1 The positive pole of the switch tube T b1 The emitter is connected to the switch tube T b2 The collector and switch tube S b1 The drain of the switch tube T b2 The emitter is connected to the switch tube T b3 The collector and bus capacitance C 1 , C 2 The center point N, the switch tube T b3 The emitter is connected to the switch tube T b4 The collector and switch tube S b6 The source of the switch tube S b6 The drain of fb2 The negative electrode and the switch tube S b5 The source of the switch tube S b5 The drain of the switch tube S b8 The source and switch tube S b4 The source of the switch tube S b4 The drain of the switch tube S b3 The source of the B-phase circuit is used as the output terminal, and the switch tube S b3 The drain of the switch tube S b7 The drain and switch S b2 The source of the switch tube S b7 The source of the switch S b8 The drain and flying capacitor C fb1 The negative electrode and flying capacitor C fb2 The positive electrode of the switch tube S b2 The drain of the switch tube S b1 The source and flying capacitor C fb1 The positive electrode of the switch tube S b1 The drain of the switch tube T b1 The emitter and switch tube T b2 The collector; In the B phase circuit, the switch tube T c1 The collector of is connected to the DC input source U dc The positive terminal and capacitor C 1 The positive pole of the switch tube T c1 The emitter is connected to the switch tube T c2 The collector and switch tube S c1 The drain of the switch tube T c2 The emitter is connected to the switch tube T c3 The collector and bus capacitance C 1 , C 2 The center point N, the switch tube T c3 The emitter is connected to the switch tube T c4 The collector and switch tube S c6 The source of the switch tube S a6 The drain of fc2 The negative electrode and the switch tube S c5 The source of the switch tube S c5 The drain of the switch tube S c8 The source and switch tube S c4 The source of the switch tube S c4 The drain of the switch tube S c3 The source of the C phase circuit is used as the output terminal of the switch tube S c3 The drain of the switch tube S c7 The drain and switch S c2 The source of the switch tube S c7 The source of the switch S c8 The drain and flying capacitor C fc1 The negative electrode and flying capacitor C fc2 The positive electrode of the switch tube S c2 The drain of the switch tube S c1 The source and flying capacitor C fc1 The positive electrode of the switch tube S c1 The drain of the switch tube T c1 The emitter and switch tube T c2 The collector.

2. A seven-level hybrid clamped inverter topology according to claim 1, It is characterized in that in, Switching tube T x1 , switch tube T x2 , switch tube T x3 , switch tube T x4 Working at fundamental frequency, IGBT device is selected; switch tube S x1 , switch tube S x2 , switch tube S x3 , switch tube S x4 , switch tube S x5 , switch tube S x6 , switch tube S x7 , switch tube S x8 When operating at high switching frequencies, wide bandgap devices can be used, specifically SiC MOSFET or GaN devices.

3. A voltage balancing modulation method using the seven-level hybrid clamped inverter topology of claim 1, It is characterized in that The modulation signal of the seven-level hybrid clamped inverter is defined as: Among them, u refa is the modulation signal of phase A circuit, u refb is the modulation signal of the B phase circuit, u refc is the modulation signal of the C phase circuit; m is the modulation ratio, f m is the fundamental frequency; In the A phase circuit, based on the modulation signal u refa The modulated signal u can be obtained refa1 、u refa2 、u refa3 for: Similarly, for the B phase circuit, based on the modulation signal u refb The modulated signal u can be obtained refb1 、u refb2 、u refb3 for: For the C phase circuit, based on the modulation signal u refc The modulated signal u can be obtained refc1 、u refc2 、u refc3 for: The deviation between the flying capacitor voltage and the reference voltage is defined as: Among them, ΔU fa1 , ΔU fa2 They are respectively the flying capacitor C of phase A circuit fa1 , C fa2 Voltage deviation, ΔU fb1 , ΔU fb2 They are respectively the flying capacitor C of phase B circuit fb1 , C fb2 Voltage deviation, ΔU fc1 , ΔU fc2 They are respectively the flying capacitor C of the C phase circuit fc1 , C fc2 voltage deviation.

Images