Multi-level inverter topological structure, control method thereof and multi-level inverter

Abstract

The invention discloses a multi-level inverter topological structure, a control method thereof and a multi-level inverter, and relates to the technical field of voltage conversion. The circuit comprises a topology module and an H-bridge circuit coupled with the topology module. The topology module comprises a first DC voltage source, a DC voltage source group and a switch tube assembly. The direct-current voltage source group is coupled with the first direct-current voltage source to form a voltage loop. The direct-current voltage source group comprises at least two cascaded target direct-current voltage sources. And the switching tube assembly is embedded in the voltage loop, controls a current conduction path between the first direct current voltage source and each target direct current voltage source, and is used for adjusting a voltage value input to the H-bridge circuit from the voltage loop. A multi-level inverter topological structure can be formed by adopting a direct-current voltage source, a switch tube and an H-bridge circuit, a higher voltage level and more levels are expanded through cascade connection of topological modules, and the complexity and the production cost of the multi-level inverter topological structure are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage conversion, and in particular to a multi-level inverter topology structure and a control method thereof, and a multi-level inverter. Background Art

[0002] A multilevel inverter is a power electronic conversion device that generates AC power of multiple voltage levels at the output end through multiple DC power supplies or capacitor voltage division, making its output voltage waveform closer to a sine wave.

[0003] Current multilevel inverter topologies typically include diode-clamped, flying capacitor, and cascaded H-bridge. Aiming for higher voltage levels requires the addition of a large number of unidirectional or bidirectional semiconductor devices, which increases the number of electronic components required and significantly raises production costs. Summary of the Invention

[0004] In view of the problem that when the current type of topology structure pursues higher voltage levels, the number of electronic components required is large and the production cost is greatly increased, the present invention is proposed to provide a multi-level inverter topology structure and its control method, as well as a multi-level inverter that overcomes or at least partially solves the above-mentioned problems.

[0005] According to a first aspect of the present invention, a multilevel inverter topology structure is provided. The multilevel inverter topology structure includes at least one topology module and an H-bridge circuit. The H-bridge circuit is coupled to a voltage output terminal of the topology module to adjust the voltage direction across a load coupled to the H-bridge circuit. The topology module includes:

[0006] a first DC voltage source;

[0007] a DC voltage source group, the DC voltage source group being coupled to the first DC voltage source to form a voltage loop, the DC voltage source group comprising at least two cascaded target DC voltage sources;

[0008] a switch tube assembly, the switch tube assembly being embedded in the voltage loop, controlling a current conduction path between the first DC voltage source and each of the target DC voltage sources through the switch tube assembly, and being used to adjust a voltage value input from the voltage loop to the H-bridge circuit; and

[0009] The switch tube assembly cooperates with the control switch tube in the H-bridge circuit to output alternating current to the load.

[0010] In an optional invention, the DC voltage source group includes a second DC voltage source and a third DC voltage source, and the switch tube assembly includes:

[0011] a first switching tube and a second switching tube, wherein the first switching tube and the second switching tube are connected in series and coupled between the positive electrode of the DC voltage source group and the first input terminal of the H-bridge circuit;

[0012] a third switching tube, a fourth switching tube, and a fifth switching tube, wherein the three switching tubes, the fourth switching tube, and the fifth switching tube are connected in series and coupled to both ends of the second switching tube, wherein the positive electrode of the first DC voltage source is coupled between the fourth switching tube and the fifth switching tube;

[0013] a sixth switching transistor, coupled to a side of the first switching transistor away from the second switching transistor and between the negative electrode of the first DC voltage source, wherein a connection between the sixth switching transistor and the first switching transistor serves as a first output end of the voltage loop;

[0014] a seventh switching tube, one end of the seventh switching tube being coupled between the third switching tube and the fourth switching tube, and the other end of the seventh switching tube being coupled to the negative electrode of the first DC voltage source;

[0015] an eighth switching transistor, the eighth switching transistor being coupled between the negative electrode of the first DC voltage source and the negative electrode of the DC voltage source group, wherein the connection between the eighth switching transistor and the DC voltage source group serves as the second output terminal of the voltage loop and is coupled to the second input terminal of the H-bridge circuit;

[0016] a ninth switching tube, wherein one end of the ninth switching tube is coupled between the second DC voltage source and the third DC voltage source, and the other end of the ninth switching tube is coupled between the third switching tube and the seventh switching tube.

[0017] An optional invention content, the DC voltage source group further includes a fourth DC voltage source connected in series with the third DC voltage source;

[0018] The switch tube assembly further includes a tenth switch tube, one end of which is coupled between the third DC voltage source and the fourth DC voltage source, and the other end of which is coupled between the third switch tube and the seventh switch tube.

[0019] In an optional invention, when the DC voltage source group includes at least N target DC voltage sources, at least N target DC voltage sources are connected in series, where N is a positive integer greater than or equal to 4;

[0020] The switch tube assembly also includes N-2 target switch tubes, one of which is coupled between each of two adjacent target DC voltage sources, and the other end of each target switch tube is coupled between the third switch tube and the seventh switch tube.

[0021] An optional invention content is that when at least M topology modules are provided, the Mth topology module is connected in series to the second output end of the M-1th topology module, where M is a positive integer greater than or equal to 2.

[0022] According to a second aspect of the present invention, a multilevel inverter is provided. The multilevel inverter includes the multilevel inverter topology structure as described in any one of the above inventions.

[0023] In an optional invention, when there are three multi-level inverter topology structures, the load of each multi-level inverter topology structure includes a transformer, so as to output three-phase alternating current through the transformer.

[0024] According to a third aspect of the present invention, a control method for a multi-level inverter topology structure is further provided. The multi-level inverter topology structure includes the multi-level inverter topology structure as described in any one of the above inventions. The control method includes:

[0025] Obtain a sinusoidal reference wave and a triangular carrier wave to generate a first pulse width modulation pulse for each switch tube in the switch tube assembly and a second pulse width modulation pulse for the switch tube in the H-bridge circuit;

[0026] controlling the operation of the switch tube in the switch tube assembly according to the first pulse width modulation pulse to adjust the voltage value output to the load;

[0027] According to the second pulse width modulation pulse, the action of the control switch tube in the H-bridge circuit is controlled to adjust the voltage direction on both sides of the load.

[0028] In an optional invention, controlling the action of the control switch in the H-bridge circuit according to the second pulse width modulation pulse includes:

[0029] According to the second pulse width modulation pulse, the first control switch tube and the second control switch tube in the H-bridge circuit are controlled to be turned on; or,

[0030] According to the second pulse width modulation pulse, the third control switch tube and the fourth control switch tube in the H-bridge circuit are controlled to be turned on, so as to convert the direction of the voltage across the load.

[0031] In an optional invention, controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes:

[0032] According to the first pulse width modulation pulse, the sixth switch tube and the seventh switch tube in the switch tube assembly are controlled to be turned on, so that the voltage value across the two ends of the load is zero.

[0033] In an optional invention, controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes:

[0034] According to the first pulse width modulation pulse, the first switch tube, the fifth switch tube and the eighth switch tube in the switch tube assembly are controlled to be turned on, so that the voltage value across the load is the voltage value output by the first DC voltage source.

[0035] In an optional invention, controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes:

[0036] Based on the first pulse width modulation pulse, the first switch tube, the fifth switch tube, the seventh switch tube and the ninth switch tube in the switch tube assembly are controlled to be turned on, so that the voltage value across the load is: the cumulative voltage value of the voltage value output by the first DC voltage source and the voltage value output by the second DC voltage source.

[0037] In an optional invention, controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes:

[0038] Based on the first pulse width modulation pulse, the first switch tube and the second switch tube in the switch tube assembly are controlled to be turned on, so that the voltage value at both ends of the load is: the cumulative voltage value of the voltage value output by the second DC voltage source, the voltage value output by the third DC voltage source, and the voltage value output by the fourth DC voltage source.

[0039] In an optional invention, controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes:

[0040] Based on the first pulse width modulation pulse, the first switch tube, the third switch tube, the fifth switch tube and the seventh switch tube in the switch tube assembly are controlled to be turned on, so that the negative voltage value at both ends of the load is: the cumulative voltage value of the voltage value output by the first DC voltage source, the voltage value output by the second DC voltage source, the voltage value output by the third DC voltage source and the voltage value output by the fourth DC voltage source.

[0041] Compared to the prior art, the present invention includes at least one topology module and an H-bridge circuit. The H-bridge circuit is coupled to the voltage output terminal of the topology module to adjust the voltage direction across a load coupled to the H-bridge circuit. The topology module includes a first DC voltage source, a DC voltage source group, and a switch assembly. The DC voltage source group is coupled to the first DC voltage source to form a voltage loop. The DC voltage source group includes at least two cascaded target DC voltage sources. The switch assembly is embedded in the voltage loop and controls the current conduction path between the first DC voltage source and each of the target DC voltage sources to adjust the voltage input from the voltage loop to the H-bridge circuit. Furthermore, the switch assembly cooperates with the control switch in the H-bridge circuit to output AC power to the load. A multilevel inverter topology can be constructed using multiple DC voltage sources, multiple switches, and an H-bridge circuit. Cascading topology modules can be used to expand to higher voltage levels and a greater number of levels, thereby reducing the number of semiconductor components and lowering the complexity and production cost of the multilevel inverter topology.

[0042] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be construed as limiting the present invention. The same reference numerals are used throughout the accompanying drawings to denote the same components.

[0044] In the attached figure:

[0045] Figure 1 1 is a schematic diagram of a circuit structure of a multi-level inverter topology structure provided by an embodiment of the present invention;

[0046] Figure 2 1 is a circuit diagram of another multi-level inverter topology structure provided by an embodiment of the present invention;

[0047] Figure 3 is a schematic diagram of a first current conduction path of another multi-level inverter topology structure provided by an embodiment of the present invention;

[0048] Figure 4 is a schematic diagram of a second current conduction path of another multi-level inverter topology structure provided by an embodiment of the present invention;

[0049] Figure 5 is a schematic diagram of a third current conduction path of another multi-level inverter topology provided by an embodiment of the present invention;

[0050] Figure 6 is a schematic diagram of a fourth current conduction path of another multi-level inverter topology provided by an embodiment of the present invention;

[0051] Figure 7 is a schematic diagram of a fifth current conduction path of another multi-level inverter topology provided by an embodiment of the present invention;

[0052] Figure 8 is a schematic diagram of a sixth current conduction path of another multi-level inverter topology structure provided by an embodiment of the present invention;

[0053] Figure 9 is a schematic diagram of a seventh current conduction path of another multi-level inverter topology provided by an embodiment of the present invention;

[0054] Figure 10 is a schematic diagram of an eighth current conduction path of another multi-level inverter topology structure provided by an embodiment of the present invention;

[0055] Figure 11 is a schematic diagram of a ninth current conduction path of another multi-level inverter topology structure provided by an embodiment of the present invention;

[0056] Figure 12 is a schematic diagram of a tenth current conduction path of another multi-level inverter topology provided by an embodiment of the present invention;

[0057] Figure 13 is a schematic diagram of an eleventh current conduction path of another multi-level inverter topology provided by an embodiment of the present invention;

[0058] Figure 14 1 is a circuit diagram of another multi-level inverter topology structure provided by an embodiment of the present invention;

[0059] Figure 15 1 is a circuit diagram of another multi-level inverter topology structure provided by an embodiment of the present invention;

[0060] Figure 16 1 is a schematic diagram of a circuit structure of a multi-level inverter provided by an embodiment of the present invention;

[0061] Figure 17 1 is a schematic flow chart of a control method for a multi-level inverter topology structure provided by an embodiment of the present invention;

[0062] Figure numerals: 1. topology module; 11. DC voltage source group; 12. switch tube assembly; 2. H-bridge circuit; 3. load. DETAILED DESCRIPTION

[0063] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0064] A multilevel inverter is a power electronic conversion device that generates AC power of multiple voltage levels at the output end through multiple DC power supplies or capacitor voltage division, making its output voltage waveform closer to a sine wave.

[0065] Current multilevel inverter topologies typically include diode-clamped, flying capacitor, and cascaded H-bridge. Aiming for higher voltage levels requires the addition of a large number of unidirectional or bidirectional semiconductor devices, which increases the number of electronic components required and significantly raises production costs.

[0066] To address the above technical issues, an embodiment of the present invention is proposed. This embodiment may include at least one topology module 1 and an H-bridge circuit 2. The H-bridge circuit 2 is coupled to the voltage output terminal of the topology module 1 to adjust the voltage direction across a load 3 coupled to the H-bridge circuit 2. The topology module 1 includes a first DC voltage source V11, a DC voltage source group 11, and a switch assembly 12. The DC voltage source group 11 is coupled to the first DC voltage source V11 to form a voltage loop. The DC voltage source group 11 includes at least two cascaded target DC voltage sources. The switch assembly 12 is embedded in the voltage loop and controls the current conduction path between the first DC voltage source V11 and each of the target DC voltage sources to adjust the voltage input from the voltage loop to the H-bridge circuit 2. Furthermore, the switch assembly 12 cooperates with the control switch in the H-bridge circuit 2 to output AC power to the load 3. Using multiple DC voltage sources, multiple switches, and an H-bridge circuit 2 can form a multi-level inverter topology. And a higher voltage level can be expanded by cascading the topology modules 1, thereby reducing the number of semiconductor devices and lowering the complexity and production cost of the multi-level inverter topology.

[0067] Reference Figure 1-15As shown, an embodiment of the present invention provides a multilevel inverter topology structure. The multilevel inverter topology structure may include at least one topology module 1 and an H-bridge circuit 2. The H-bridge circuit 2 is coupled to the voltage output terminal of the topology module 1 to adjust the voltage direction across a load 3 coupled to the H-bridge circuit 2. The topology module 1 includes a first DC voltage source V11, a DC voltage source group 11, and a switch tube assembly 12. The DC voltage source group 11 is coupled to the first DC voltage source V11 to form a voltage loop. The DC voltage source group 11 includes at least two cascaded target DC voltage sources. The switch tube assembly 12 is embedded in the voltage loop and controls the current conduction path between the first DC voltage source V11 and each of the target DC voltage sources to adjust the voltage value input from the voltage loop to the H-bridge circuit 2. The switch tube assembly 12 also cooperates with the control switch tube in the H-bridge circuit 2 to output AC power to the load 3.

[0068] In an embodiment of the present invention, the multilevel inverter topology structure may include at least one topology module 1 and an H-bridge circuit 2. The topology module 1 refers to a substructure constituting the multilevel inverter topology structure. When the multilevel inverter topology structure includes at least two topology modules 1, at least two topology modules 1 are cascaded.

[0069] The H-bridge circuit 2 is coupled to the voltage output terminal of the topology module 1. The H-bridge circuit 2 includes four control switches, symmetrically connected in pairs, with a load 3 connected in the middle, forming an H-shaped structure. For example, the H-bridge circuit 2 may include a first control switch Sa, a second control switch Sb, a third control switch Sc, and a fourth control switch Sd. The first, second, third, and fourth control switches Sa, Sb, Sc, and Sd are connected in series. One end of the load 3 is coupled between the first and fourth control switches Sa and Sd, and the other end of the load 3 is coupled between the second and third control switches Sb and Sc. The connection between the first and third control switches Sa and Sc serves as the first input terminal of the H-bridge circuit 2. The connection between the second and fourth control switches Sb and Sd serves as the second input terminal of the H-bridge circuit 2. The H-bridge circuit 2 is primarily used to adjust the voltage direction across the load 3.

[0070] For each of the topological modules 1, the topological module 1 may include a first DC voltage source V11, a DC voltage source group 11, and a switch tube assembly 12. The first DC voltage source V11 is a device capable of outputting a stable DC voltage. The DC voltage source group 11 refers to a voltage source combination including at least two target DC voltage sources, with at least two of the target DC voltage sources being cascaded (also referred to as series). Thus, by cascading multiple target DC voltage sources, higher voltage levels (higher voltage amplitudes) and more voltage levels can be expanded.

[0071] The DC voltage source group 11 is coupled to the first DC voltage source V11 to form a voltage loop. The switch tube assembly 12 may include multiple switches, which are embedded in the voltage loop. "Embedded" can be understood as meaning that some of the switches in the switch tube assembly 12 are connected in series within the voltage loop, while others are connected in parallel within the voltage loop. Thus, the multiple switches in the switch tube assembly 12 can be used to control the current conduction path between the first DC voltage source and each target DC voltage source in the DC voltage source group 11. By changing the current conduction path, the output voltage of the voltage loop is adjusted, thereby changing the voltage input to the H-bridge circuit 2. Consequently, the voltage flowing to the load 3 is changed by the switch tube assembly 12, and the direction of the voltage across the load 3 is changed in conjunction with the control switches in the H-bridge circuit 2. Thus, by utilizing multiple DC voltage sources, multiple switches, and an H-bridge circuit 2 to output multiple different voltage levels with different polarities, AC power can be provided to the load 3 while reducing the harmonic content of the output waveform.

[0072] In addition, by cascading multiple target DC voltage sources in the DC voltage source group 11 and / or cascading multiple topology modules 1, it is possible to expand the output to a higher voltage level. This can reduce the number of semiconductor devices, for example, the number of switching devices can be reduced, thereby reducing power loss and reducing the complexity and production cost of the multi-level inverter topology. Moreover, the cascaded modular design facilitates the expansion of voltage levels and the number of levels, which can adapt to different power requirements, thereby improving the scenario applicability of the multi-level inverter topology. For example, it can be widely used in scenarios such as electric vehicles and renewable energy that have high requirements for power quality and efficiency.

[0073] In an optional embodiment of the invention, referring to Figure 1As shown, the DC voltage source group 11 may include a second DC voltage source V12 and a third DC voltage source V13, and the switch tube assembly 12 may include a first switch tube S11, a second switch tube S12, a third switch tube S13, a fourth switch tube S14, a fifth switch tube S15, a sixth switch tube S16, a seventh switch tube S17, an eighth switch tube S18, and a ninth switch tube S19. Each of the nine switch tubes may be an IGBT (Insulated Gate Bipolar Transistor) device. Each switch tube may be controlled to be turned on or off by a controller. The first switch tube S11 and the second switch tube S12 are connected in series and coupled between the positive electrode of the DC voltage source group 11 and the first input terminal of the H-bridge circuit 2.

[0074] The three switching transistors, the fourth switching transistor S14, and the fifth switch are connected in series and coupled to both ends of the second switching transistor S12. The positive electrode of the first DC voltage source V11 is coupled between the fourth switching transistor S14 and the fifth switching transistor S15. In other words, one end of the third switching transistor S13 is coupled to the second switching transistor S12 and the positive electrode of the DC voltage source group 11, and one end of the fifth switching transistor S15 is coupled between the first switching transistor S11 and the second switching transistor S12.

[0075] The sixth switch S16 is coupled to a side of the first switch S11 away from the second switch S12 and between the negative electrode of the first DC voltage source V11. The connection between the sixth switch S16 and the first switch S11 serves as the first output terminal of the voltage loop. The first output terminal is coupled to the first input terminal of the H-bridge circuit 2. One end of the seventh switch S17 is coupled between the third switch S13 and the fourth switch S14, and the other end is coupled to the negative electrode of the first DC voltage source V11. The eighth switch S18 is coupled between the negative electrode of the first DC voltage source V11 and the negative electrode of the DC voltage source group 11. The connection between the eighth switch S18 and the DC voltage source group 11 serves as the second output terminal of the voltage loop and is coupled to the second input terminal of the H-bridge circuit 2. One end of the ninth switch S19 is coupled between the second DC voltage source V12 and the third DC voltage source V13 , and the other end is coupled between the third switch S13 and the seventh switch S17 .

[0076] In summary, the first switch S11, the second switch S12, the third switch S13, the fourth switch S14, the fifth switch S15, the sixth switch S16, the seventh switch S17, the eighth switch S18, and the ninth switch S19 can be combined to control the current conduction path between the first DC voltage power supply and each of the target DC voltage sources in the DC voltage source group 11, and by changing the current conduction path, the output voltage value of the voltage loop is adjusted, that is, the voltage value input to the H-bridge circuit 2 is changed. For example, when the first control switch Sa and the second control switch Sb are turned on, the first switch S11, the fifth switch S15, and the eighth switch S18 in the switch assembly 12 are turned on, and the other switch tubes in the multi-level inverter topology are all in the off state, the voltage value input to the load 3 can be a first DC voltage value, which is the voltage value output by the first DC voltage source V11. For another example, when the first control switch Sa and the second control switch Sb in the H-bridge circuit 2 are turned on, the first switch S11, the fifth switch S15, the seventh switch S17, and the ninth switch S19 in the switch assembly 12 are turned on, and the other switches in the multi-level inverter topology are all in the off state, the voltage value input to the load 3 is the cumulative voltage value of the voltage output by the first DC voltage source V11 and the voltage output by the second DC voltage source V12.

[0077] Thus, by turning on and off the switches in the switch assembly 12, the voltage between each target DC voltage source in the DC voltage source group 11 and the first DC voltage source V11 is added or subtracted, causing the output voltage of the voltage loop to fluctuate between zero and the cumulative voltage output by all DC voltage sources. Combined with the control switches in the H-bridge circuit 2, the voltage direction across the load 3 is changed, outputting multiple different voltage levels with different polarities, thereby providing AC power to the load 3.

[0078] In an optional embodiment of the invention, referring to Figure 1 As shown, the DC voltage source group 11 may further include a fourth DC voltage source V14 connected in series with the third DC voltage source V13. The switch tube assembly 12 further includes a tenth switch tube S110, one end of which is coupled between the third DC voltage source V13 and the fourth DC voltage source V14, and the other end of which is coupled between the third switch tube S13 and the seventh switch tube S17. Figure 3As shown, when the first control switch tube Sa and the second control switch tube Sb in the H-bridge circuit 2 are turned on, the sixth switch tube S16 and the seventh switch tube S17 in the switch tube assembly 12 are turned on, and the other switch tubes in the multi-level inverter topology are in the off state, the voltage across the load 3 is zero.

[0079] In one or more embodiments, referring to Figure 4 As shown, when the first control switch tube Sa and the second control switch tube Sb in the H-bridge circuit 2 are turned on, the first switch tube S11, the fifth switch tube S15 and the eighth switch tube S18 in the switch tube assembly 12 are turned on, and the other switch tubes in the multi-level inverter topology are in the off state, the voltage value input to the load 3 can be a first DC voltage value, which is the voltage value output by the first DC voltage source V11. Figure 5 As shown, when the third control switch tube Sc and the fourth control switch tube Sd in the H-bridge circuit 2 are turned on, so that the first control switch tube Sa and the second control switch tube Sb are turned off, the voltage value input to the load 3 can be the first DC voltage value, and the voltage direction is opposite.

[0080] In one or more embodiments, referring to Figure 6 As shown, the first control switch tube Sa and the second control switch tube Sb in the H-bridge circuit 2 are turned on, the first switch tube S11, the fifth switch tube S15, the seventh switch tube S17 and the ninth switch tube S19 in the switch tube assembly 12 are turned on, and the other switch tubes in the multi-level inverter topology are in the off state. The voltage value input to the load 3 is the cumulative voltage value of the voltage value output by the first DC voltage source V11 and the voltage value output by the second DC voltage source V12. Figure 7 As shown, when the third control switch tube Sc and the fourth control switch tube Sd in the H-bridge circuit 2 are turned on, so that the first control switch tube Sa and the second control switch tube Sb are turned off, the voltage value input to the load 3 can be the cumulative voltage value of the voltage value output by the first DC voltage source V11 and the voltage value output by the second DC voltage source V12, and the voltage direction is opposite to the voltage direction when the first control switch tube Sa and the second control switch tube Sb are turned on.

[0081] In one or more embodiments, referring to Figure 8As shown, the first control switch tube Sa and the second control switch tube Sb in the H-bridge circuit 2 are turned on, the first switch tube S11 and the second switch tube S12 in the switch tube assembly 12 are turned on, and the other switch tubes in the multi-level inverter topology are in the off state. The voltage value input to the load 3 is the cumulative voltage value of the voltage value output by the second DC voltage source V12, the voltage value output by the third DC voltage source V13, and the voltage value output by the fourth DC voltage source V14. Therefore, in the topology module 1, a voltage several times higher than the minimum voltage step can be generated by the two switching devices of the first switch tube S11 and the second switch tube S12. Figure 9 As shown, when the third control switch tube Sc and the fourth control switch tube Sd in the H-bridge circuit 2 are turned on, so that the first control switch tube Sa and the second control switch tube Sb are turned off, the voltage value input to the load 3 can be the cumulative voltage value of the voltage value output by the second DC voltage source V12, the voltage value output by the third DC voltage source V13, and the voltage value output by the fourth DC voltage source V14, and the voltage direction is opposite to the voltage direction when the first control switch tube Sa and the second control switch tube Sb are turned on.

[0082] In one or more embodiments, referring to Figure 10 As shown, the first control switch tube Sa and the second control switch tube Sb in the H-bridge circuit 2 are turned on, the first switch tube S11, the third switch tube S13, the fifth switch tube S15 and the seventh switch tube S17 in the switch tube assembly 12 are turned on, and the other switch tubes in the multi-level inverter topology are in the off state. The voltage value input to the load 3 is the cumulative voltage value of the voltage value output by the first DC voltage source V11, the voltage value output by the second DC voltage source V12, the voltage value output by the third DC voltage source V13 and the voltage value output by the fourth DC voltage source V14. Figure 11 As shown, when the third control switch Sc and the fourth control switch Sd in the H-bridge circuit 2 are turned on, so that the first control switch Sa and the second control switch Sb are turned off, the voltage input to the load 3 can be the cumulative voltage value output by the first DC voltage source V11, the voltage value output by the second DC voltage source V12, the voltage value output by the third DC voltage source V13, and the voltage value output by the fourth DC voltage source V14, and the voltage direction is opposite to the voltage direction when the first control switch Sa and the second control switch Sb are turned on. Therefore, based on the above-mentioned combined control of each switch in the switch assembly 12 and a target switch in the H-bridge circuit 2, a 9-level inverter topology can be expanded.

[0083] In another embodiment, referring to Figure 12As shown, the first control switch tube Sa and the second control switch tube Sb in the H-bridge circuit 2 are turned on, the fourth switch tube S14, the sixth switch tube S16 and the ninth switch tube S19 in the switch tube assembly 12 are turned on, and the other switch tubes in the multi-level inverter topology are in the off state. The voltage value input to the load 3 is the voltage value obtained by subtracting the voltage value output by the first DC voltage source V11 from the voltage value output by the second DC voltage source V12. Figure 13 As shown, when the third control switch Sc and the fourth control switch Sd in the H-bridge circuit 2 are turned on, so that the first control switch Sa and the second control switch Sb are turned off, the voltage input to the load 3 can be a voltage value obtained by subtracting the voltage value output by the first DC voltage source V11 from the voltage value output by the second DC voltage source V12. The voltage direction is opposite to the voltage direction when the first control switch Sa and the second control switch Sb are turned on.

[0084] Thus, by controlling the combination of the switches in the switch assembly 12 and the target switch in an H-bridge circuit 2, an 11-level inverter topology can be developed. This facilitates expansion of the number of levels, allowing the voltage waveform output by the multi-level inverter topology to be synthesized with a smaller voltage step and a greater number of levels, thereby making the output voltage waveform closer to an ideal sine wave and reducing electromagnetic interference and total harmonic distortion.

[0085] In an optional embodiment of the invention, referring to Figure 14As shown, when the DC voltage source group 11 includes at least N target DC voltage sources, at least N target DC voltage sources are connected in series, where N is a positive integer greater than or equal to 4. The switch tube assembly 12 also includes N-2 target switch tubes, one of which is coupled between each of two target DC voltage sources at adjacent positions, and the other end of each target switch tube is coupled between the third switch tube S13 and the seventh switch tube S17. The target switch tube coupled between two target DC power sources at adjacent positions is used to control whether the target DC power sources on both sides thereof output voltage. For example, the N-2 target switch tubes may include: the tenth switch tube S110, the eleventh switch tube S111, and the N+7th switch tube S1(N+7). When the first control switch tube Sa and the second control switch tube Sb in the H-bridge circuit 2 are turned on, the first switch tube S11, the third switch tube S13, the fifth switch tube S15, and the seventh switch tube S17 in the switch tube assembly 12 are turned on, and the other switch tubes in the multi-level inverter topology are in the off state, the voltage value input to the load 3 is the cumulative voltage value of the voltage value output by the first DC voltage source V11, the voltage value output by the second DC voltage source V12, the voltage value output by the third DC voltage source V13, the voltage value output by the fourth DC voltage source V14, the voltage value output by the fifth DC voltage source V15, and the voltage value output by the Nth target DC voltage source V1(N+1), thereby increasing the voltage amplitude of the output AC power.

[0086] Furthermore, by controlling the on and off states of other switches in the switch assembly 12, the voltage between each target DC voltage source in the DC voltage source group 11 and the first DC voltage source V11 can be added or subtracted, causing the output voltage value of the voltage loop to vary within a certain range. The control switches in the H-bridge circuit 2 change the direction of the voltage across the load 3. Thus, by cascading multiple target DC voltage sources and corresponding newly added target switches, the voltage level and number of levels can be expanded to accommodate the power requirements of different loads 3. Furthermore, the multi-level inverter topology utilizes a limited number of device types and switching devices, thereby simplifying the structural complexity of the multi-level inverter topology, reducing production costs, and minimizing power losses caused by the large number of switching devices.

[0087] In the embodiment of the present application, those skilled in the art can determine the cascade number of target DC voltage sources in the DC voltage source group 11 according to the voltage level to be expanded (the voltage level can be understood as the voltage amplitude), and no further restrictions are made here.

[0088] In an optional embodiment of the invention, referring to Figure 15As shown, when at least M topology modules 1 are provided, the Mth topology module 1 is connected in series to the second output end of the M-1th topology module 1, where M is a positive integer greater than or equal to 2.

[0089] In the embodiment of the present invention, when at least two topology modules 1 are cascaded, the Mth topology module 1 is connected in series to the second output end of the M-1th topology module 1. For example, when there are two topology modules 1, the second topology module 1 is connected in series to the second output end of the first topology module 1.

[0090] Thus, it is convenient to control the turning off and on of each switch in the first switch device, as well as the first switch SM1, the second switch SM2, the third switch SM3, the fourth switch SM4, the fifth switch SM5, the sixth switch SM6, the seventh switch SM7, the eighth switch SM8, the ninth switch SM9, and the tenth switch SM10 in the Mth switch assembly. The voltage value provided to the load 3 fluctuates between zero and the cumulative voltage value output by all DC voltage sources in all topology modules 1 (the cumulative value of the cumulative voltage value from the first topology module to the cumulative voltage value of the Mth topology module). The DC voltage source group in the Mth topology module may include a second DC voltage source VM2, a third DC voltage source VM3, and a fourth DC voltage source VM4. In another embodiment, the DC voltage source group in the Mth topology module may include a second DC voltage source VM2 and a third DC voltage source VM3. That is, when at least M topology modules 1 are cascaded, the number of target DC voltage sources in the cascade in the DC voltage source group in each topology module 1 may differ.

[0091] This allows for convenient expansion to higher voltage levels and a greater number of levels through a modular cascade design. This makes the waveform output by the multi-level inverter topology closer to a sine wave and reduces electromagnetic interference. Therefore, in the embodiments of this application, those skilled in the art can determine the number of cascaded topology modules 1 based on the voltage level and number of levels to be expanded, and no further limitations are imposed herein.

[0092] In summary, embodiments of the present invention provide a multilevel inverter topology structure. The multilevel inverter topology structure may include at least one topology module 1 and an H-bridge circuit 2. The H-bridge circuit 2 is coupled to the voltage output terminal of the topology module 1 to adjust the voltage direction across a load 3 coupled to the H-bridge circuit 2. The topology module 1 includes a first DC voltage source V11, a DC voltage source group 11, and a switch assembly 12. The DC voltage source group 11 is coupled to the first DC voltage source V11 to form a voltage loop. The DC voltage source group 11 includes at least two cascaded target DC voltage sources. The switch assembly 12 is embedded in the voltage loop and controls the current conduction path between the first DC voltage source V11 and each of the target DC voltage sources to adjust the voltage input from the voltage loop to the H-bridge circuit 2. Furthermore, the switch assembly 12 cooperates with the control switch in the H-bridge circuit 2 to output AC power to the load 3. A multi-level inverter topology can be constructed using multiple DC voltage sources, multiple switching transistors, and an H-bridge circuit 2. Furthermore, higher voltage levels can be expanded by cascading topology modules 1, thereby reducing the number of semiconductor components and lowering the complexity and production cost of the multi-level inverter topology.

[0093] An embodiment of the present invention further discloses a multi-level inverter, which includes at least one multi-level inverter topology structure as described in any one of the above-mentioned embodiments of the invention.

[0094] In an embodiment of the present invention, a multilevel inverter having the above-mentioned multilevel inverter topology structure can expand to a higher voltage level by cascading the target DC voltage sources in the DC voltage source group 11 and / or by cascading the topology modules 1, thereby reducing the number of semiconductor devices and reducing the complexity and production cost of the multilevel inverter topology structure, so that the multilevel inverter can adapt to different power requirements and voltage requirements, thereby improving the product applicability of the multilevel inverter.

[0095] In an optional embodiment of the invention, referring to Figure 16 As shown, when the number of multilevel inverter topologies is set to three, the load 3 of each multilevel inverter topology includes a transformer T1 to output three-phase AC power through the transformer. For example, the load 3 in each multilevel inverter topology can be a high-voltage transformer, wherein all target DC voltage sources of the topology modules 1 in each multilevel inverter topology can be shared, thereby reducing the number of DC voltage sources of the multilevel inverter.

[0096] In one example, the three transformers T1 can be connected in a delta connection or in a star connection according to the load 3 requirements of the three-phase load device. The three-phase load device may include a three-phase motor, etc. The modular design of the multi-level inverter topology structure can facilitate the use of a modular combination of multiple multi-level inverter topologies, so that the multi-level inverter outputs three-phase alternating current. Therefore, on the basis of simplifying the structure of the multi-level inverter, the convenience of expanding the voltage level and the number of levels of the multi-level inverter can be improved, thereby adapting to the power requirements of different load 3 devices. In one example, the three-phase alternating current output by the multi-level inverter can also be used as a power supply component of an uninterruptible power supply.

[0097] Reference Figure 17 As shown, an embodiment of the present invention discloses a control method for a multi-level inverter topology structure, and the control method may include:

[0098] S1701. Obtain a sinusoidal reference wave and a triangular carrier wave to generate a first pulse width modulation pulse for each switch tube in the switch tube assembly and a second pulse width modulation pulse for each switch tube in the H-bridge circuit.

[0099] S1702. Control the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse to adjust the voltage value output to the load.

[0100] S1703: Control the action of the control switch tube in the H-bridge circuit according to the second pulse width modulation pulse to adjust the voltage direction on both sides of the load.

[0101] In an embodiment of the present invention, the control method can be applied to a controller of the multilevel inverter. For example, the controller can be an FPGA (Field-Programmable Gate Array). By comparing the voltage values ​​of the sinusoidal reference wave and the triangular carrier, it can be determined whether the corresponding switch is turned on or off. The triangular carrier has a higher signal output frequency than the sinusoidal reference wave.

[0102] When the sinusoidal reference wave is higher than the triangular carrier wave, the corresponding switch is turned on. When the sinusoidal reference wave is lower than the triangular carrier wave, the corresponding switch is turned off. This generates a pulse sequence whose width varies according to the frequency of the sinusoidal wave. Based on this logic, the sinusoidal reference wave and corresponding triangular carrier wave for each switch can be determined in advance based on the expanded voltage amplitude and number of levels. This also determines the first pulse-width modulation pulse corresponding to each switch in the switch assembly 12 and the second pulse-width modulation pulse for each switch in the H-bridge circuit 2.

[0103] Therefore, according to the first pulse width modulation pulse, the action of the switch tube in the switch tube assembly 12 is controlled to adjust the voltage value output to the load 3, so that the output voltage value of the voltage loop fluctuates between zero and the cumulative voltage value output by all DC voltage sources.

[0104] For example, the first switch tube S11, the second switch tube S12, the third switch tube S13, the fourth switch tube S14, the fifth switch tube S15, the sixth switch tube S16, the seventh switch tube S17, the eighth switch tube S18 and the ninth switch tube S19 in the switch tube assembly 12 can be controlled according to the first pulse width modulation pulse, and operate according to the control logic in the above-mentioned embodiment of the invention, so that a sine wave with 9 levels, or a sine wave with 11 levels, or a sine wave with more levels, etc. can be output.

[0105] Based on the second pulse-width modulation pulse, the control switches in the H-bridge circuit 2 are controlled to adjust the direction of the voltage across the load 3, thereby outputting two voltages of equal magnitude and opposite directions to the load 3. By turning the switches in the switch assembly 12 on and off, the voltage between each target DC voltage source in the DC voltage source group 11 and the first DC voltage source V11 is added or subtracted, causing the output voltage of the voltage loop to fluctuate between zero and the cumulative voltage output by all DC voltage sources. Combined with the control switches in the H-bridge circuit 2, the direction of the voltage across the load 3 is changed, outputting multiple different voltage levels with different polarities, thereby providing AC power to the load 3.

[0106] In summary, embodiments of the present invention disclose a control method for a multi-level inverter topology. The control method may include first obtaining a sinusoidal reference wave and a triangular carrier wave to generate a first pulse-width modulated pulse for each switch in the switch assembly 12 and a second pulse-width modulated pulse for each switch in the H-bridge circuit 2. The first pulse-width modulated pulse is then used to control the operation of the switches in the switch assembly 12 to adjust the voltage output to the load 3. The second pulse-width modulated pulse is then used to control the operation of the control switches in the H-bridge circuit 2 to adjust the voltage direction across the load 3. The first pulse-width modulated pulse for controlling the on / off switching of each switch in the switch assembly 12 and the first pulse-width modulated pulse for controlling the on / off switching of each switch in the H-bridge circuit 2 can be determined in advance based on the desired output sinusoidal waveform. This combined control of the current conduction path between the first DC voltage source and each target DC voltage source in the DC voltage source group 11 is then achieved. By varying the current conduction path, the output voltage of the voltage loop is adjusted, i.e., the voltage input to the H-bridge circuit 2 is altered. Thus, the voltage flowing to the load 3 is changed by the switch tube assembly 12, and the direction of the voltage across the load 3 is changed in combination with the control switch tube in the H-bridge circuit 2. The combined output of multiple different voltage levels with different polarities can provide AC power with different voltage steps, different voltage amplitudes, and different levels to the load 3, and can reduce the harmonic content of the output waveform.

[0107] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0108] It is easy for those skilled in the art to think that any combination of the above embodiments is feasible, so any combination of the above embodiments is an implementation scheme of the present invention. However, due to space limitations, this specification will not describe them in detail here.

[0109] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0110] Similarly, it should be understood that in order to streamline the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof.

[0111] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

Claims

1. A multi-level inverter topology, characterized in that: The multi-level inverter topology structure includes at least one topology module and an H-bridge circuit. The H-bridge circuit is coupled to a voltage output terminal of the topology module to adjust the voltage direction across a load coupled to the H-bridge circuit. The topology module includes: a first DC voltage source; a DC voltage source group, the DC voltage source group being coupled to the first DC voltage source to form a voltage loop, the DC voltage source group comprising at least two cascaded target DC voltage sources; a switch tube assembly, the switch tube assembly being embedded in the voltage loop, controlling a current conduction path between the first DC voltage source and each of the target DC voltage sources through the switch tube assembly, and being used to adjust a voltage value input from the voltage loop to the H-bridge circuit; and The switch tube assembly cooperates with the control switch tube in the H-bridge circuit to output alternating current to the load.

2. The multi-level inverter topology according to claim 1, characterized in that: The DC voltage source group includes a second DC voltage source and a third DC voltage source, and the switch tube assembly includes: a first switching tube and a second switching tube, wherein the first switching tube and the second switching tube are connected in series and coupled between the positive electrode of the DC voltage source group and the first input terminal of the H-bridge circuit; a third switching tube, a fourth switching tube, and a fifth switching tube, wherein the three switching tubes, the fourth switching tube, and the fifth switching tube are connected in series and coupled to both ends of the second switching tube, wherein the positive electrode of the first DC voltage source is coupled between the fourth switching tube and the fifth switching tube; a sixth switching transistor, coupled to a side of the first switching transistor away from the second switching transistor and between the negative electrode of the first DC voltage source, wherein a connection between the sixth switching transistor and the first switching transistor serves as a first output end of the voltage loop; a seventh switching tube, one end of the seventh switching tube being coupled between the third switching tube and the fourth switching tube, and the other end of the seventh switching tube being coupled to the negative electrode of the first DC voltage source; an eighth switching transistor, the eighth switching transistor being coupled between the negative electrode of the first DC voltage source and the negative electrode of the DC voltage source group, wherein the connection between the eighth switching transistor and the DC voltage source group serves as the second output terminal of the voltage loop and is coupled to the second input terminal of the H-bridge circuit; a ninth switching tube, wherein one end of the ninth switching tube is coupled between the second DC voltage source and the third DC voltage source, and the other end of the ninth switching tube is coupled between the third switching tube and the seventh switching tube.

3. The multi-level inverter topology according to claim 2, characterized in that: The DC voltage source group further includes a fourth DC voltage source connected in series with the third DC voltage source; The switch tube assembly further includes a tenth switch tube, one end of which is coupled between the third DC voltage source and the fourth DC voltage source, and the other end of which is coupled between the third switch tube and the seventh switch tube.

4. The multi-level inverter topology structure according to claim 2, characterized in that: In the case where the DC voltage source group includes at least N target DC voltage sources, at least N target DC voltage sources are connected in series, where N is a positive integer greater than or equal to 4; The switch tube assembly also includes N-2 target switch tubes, one of which is coupled between each of two adjacent target DC voltage sources, and the other end of each target switch tube is coupled between the third switch tube and the seventh switch tube.

5. The multi-level inverter topology according to claim 2, characterized in that: In the case where at least M topology modules are provided, the Mth topology module is connected in series to the second output end of the M-1th topology module, wherein M is a positive integer greater than or equal to 2.

6. A multi-level inverter, characterized in that: The multilevel inverter includes at least one multilevel inverter topology structure according to any one of claims 1 to 5.

7. The multilevel inverter according to claim 6, characterized in that: In the case where there are three multi-level inverter topology structures, the load of each multi-level inverter topology structure includes a transformer, so as to output three-phase alternating current through the transformer.

8. A control method for a multi-level inverter topology structure, characterized in that: The multilevel inverter topology structure includes the multilevel inverter topology structure according to any one of claims 1 to 5, and the control method includes: Obtain a sinusoidal reference wave and a triangular carrier wave to generate a first pulse width modulation pulse for each switch tube in the switch tube assembly and a second pulse width modulation pulse for the switch tube in the H-bridge circuit; controlling the operation of the switch tube in the switch tube assembly according to the first pulse width modulation pulse to adjust the voltage value output to the load; According to the second pulse width modulation pulse, the action of the control switch tube in the H-bridge circuit is controlled to adjust the voltage direction on both sides of the load.

9. The control method of the multi-level inverter topology structure according to claim 8, characterized in that: The step of controlling the operation of the control switch in the H-bridge circuit according to the second pulse width modulation pulse comprises: According to the second pulse width modulation pulse, the first control switch tube and the second control switch tube in the H-bridge circuit are controlled to be turned on; or, According to the second pulse width modulation pulse, the third control switch tube and the fourth control switch tube in the H-bridge circuit are controlled to be turned on, so as to convert the direction of the voltage across the load.

10. The control method of the multi-level inverter topology structure according to claim 9, characterized in that: The step of controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes: According to the first pulse width modulation pulse, the sixth switch tube and the seventh switch tube in the switch tube assembly are controlled to be turned on, so that the voltage value across the two ends of the load is zero.

11. The control method of the multi-level inverter topology structure according to claim 9, characterized in that: The step of controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes: According to the first pulse width modulation pulse, the first switch tube, the fifth switch tube and the eighth switch tube in the switch tube assembly are controlled to be turned on, so that the voltage value across the load is the voltage value output by the first DC voltage source.

12. The control method of the multi-level inverter topology structure according to claim 9, characterized in that: The step of controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes: Based on the first pulse width modulation pulse, the first switch tube, the fifth switch tube, the seventh switch tube and the ninth switch tube in the switch tube assembly are controlled to be turned on, so that the voltage value across the load is: the cumulative voltage value of the voltage value output by the first DC voltage source and the voltage value output by the second DC voltage source.

13. The control method of the multi-level inverter topology structure according to claim 9, characterized in that: The step of controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes: Based on the first pulse width modulation pulse, the first switch tube and the second switch tube in the switch tube assembly are controlled to be turned on, so that the voltage value at both ends of the load is: the cumulative voltage value of the voltage value output by the second DC voltage source, the voltage value output by the third DC voltage source, and the voltage value output by the fourth DC voltage source.

14. The control method of the multi-level inverter topology structure according to claim 9, characterized in that: The step of controlling the action of the switch tube in the switch tube assembly according to the first pulse width modulation pulse includes: Based on the first pulse width modulation pulse, the first switch tube, the third switch tube, the fifth switch tube and the seventh switch tube in the switch tube assembly are controlled to be turned on, so that the negative voltage value at both ends of the load is: the cumulative voltage value of the voltage value output by the first DC voltage source, the voltage value output by the second DC voltage source, the voltage value output by the third DC voltage source and the voltage value output by the fourth DC voltage source.

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