Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes: a substrate, a plurality of signal lines, a first power line, at least one first detection signal line, and at least one second detection signal line. The first power line is on one side close to the bending area outside the area where the orthographic projection of the first power line on the surface of the substrate is located. The orthographic projections of at least one first detection signal line and at least one second detection signal line on the surface of the substrate do not overlap with the orthographic projection of the plurality of signal lines on the surface of the substrate. The display substrate can improve the electrostatic resistance of the second detection signal line and improve the product yield.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] In the display industry, with the rapid development and application of flexible OLED (Organic Light-emitting Diode) display technology (AMOLED, Active-matrix Organic Light-emitting Diode), reducing the production cost of current flexible products and improving the yield of flexible products have become one of the key issues to be solved for current flexible products. In order to reduce the production cost of current flexible display panels, better improve the product yield and production quality control, a PCD (Crack Detection) detection signal can be introduced on the display panel, which can effectively detect defective problems such as line cracks on the backplane circuit of the display panel. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a substrate, a plurality of signal lines, a first power line, at least one first detection signal line, and at least one second detection signal line. The substrate includes a display area and a peripheral area surrounding the display area. Among them, the display area includes a pixel array, the pixel array includes a plurality of sub-pixels, and the peripheral area includes a bending area on a first side of the display area, a shift register on at least one of a second side and a third side of the display area, and the first side is adjacent to the second side and the third side. One end of the plurality of signal lines is led out from the bending area, and the other end of the plurality of signal lines is connected to the shift register. The first power line is led out from the bending area and runs around the display area. At least one second detection signal line is disposed on at least one of the side where the shift register is located and a fourth side, wherein a first end of the at least one second detection signal line is led out from the bending area, and on a side close to the bending area outside the area where the orthographic projection of the first power line on the surface of the substrate is located, the orthographic projections of the at least one first detection signal line and the at least one second detection signal line on the surface of the substrate do not overlap with the orthographic projection of the plurality of signal lines on the surface of the substrate.

[0004] For example, in the display substrate provided by at least one embodiment of the present disclosure, on the first side of the display area, in the area where the orthographic projection of the first power line on the surface of the substrate is located, the orthographic projection of the at least one second detection signal line on the surface of the substrate overlaps with the orthographic projection of the plurality of signal lines on the surface of the substrate.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, in the region where the orthographic projection of the at least one second detection signal line on the surface of the substrate substrate overlaps with the orthographic projection of the multiple signal lines on the surface of the substrate substrate, the entire region is covered by the region where the orthographic projection of the first power supply line on the surface of the substrate substrate is located.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, on the first side of the display area, the second ends of the at least one first detection signal line and the second ends of the at least one second detection signal line are connected in series.

[0007] For example, in the display substrate provided by at least one embodiment of the present disclosure, on the first side of the display area and in the direction perpendicular to the surface of the substrate substrate, at least a part of the film layer where the first power supply line is located is between the film layer where the at least one second detection signal line is located and the film layer where the multiple signal lines are located.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, on one side close to the bending area outside the region where the orthographic projection of the first power supply line on the surface of the substrate substrate is located, the multiple signal lines are routed in parallel, at least a part of the line segments of the at least one first detection signal line and at least a part of the line segments of the at least one second detection signal line are routed in parallel with the multiple signal lines, and the at least one second detection signal line is located on the side of the at least one first detection signal line away from the multiple signal lines.

[0009] For example, in the display substrate provided by at least one embodiment of the present disclosure, on the first side of the display area, the at least one second detection signal line includes multiple first line segments respectively connected to its first end and second end, the multiple first line segments extend in a first direction, in the region where the orthographic projection of the first power supply line on the surface of the substrate substrate is located, the orthographic projections of the multiple first line segments on the surface of the substrate substrate and the orthographic projections of the multiple signal lines on the surface of the substrate substrate overlap.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, the length range in the first direction of the region where the orthographic projection of the multiple first line segments on the surface of the substrate substrate overlaps with the orthographic projection of the multiple signal lines on the surface of the substrate substrate is 220 microns - 260 microns.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, on one side close to the bending area outside the region where the orthographic projection of the first power supply line on the surface of the substrate substrate is located, the orthographic projection of the multiple first line segments on the surface of the substrate substrate also overlaps with the orthographic projection of the at least one first detection signal line on the surface of the substrate substrate.

[0012] For example, in the display substrate provided by at least one embodiment of the present disclosure, the at least one second detection signal line further includes a plurality of second line segments. One of the plurality of first line segments is connected to the first end of the at least one second detection signal line through one of the plurality of second line segments, and another of the plurality of first line segments is connected to the second end of the at least one second detection signal line through another of the plurality of second line segments. The plurality of second line segments are located between the plurality of first line segments and the bending region. The second line segments are routed in a direction intersecting the first direction. The at least one first detection signal line includes a plurality of third line segments respectively connected to its first end and second end. The orthographic projection of the plurality of third line segments on the surface of the substrate substrate overlaps with the orthographic projection of the plurality of first line segments on the surface of the substrate substrate. The plurality of third line segments and the plurality of second line segments are parallel and arranged side by side. The plurality of third line segments are located on the side of the plurality of second line segments close to the display area and between the plurality of second line segments and the plurality of signal lines.

[0013] For example, in the display substrate provided by at least one embodiment of the present disclosure, in a direction perpendicular to the routing directions of the plurality of second line segments and the plurality of third line segments, the plurality of second line segments and the plurality of third line segments are routed parallel to the line segments of the plurality of signal lines corresponding to the second line segments and the third line segments.

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second line segment connected to the first end of the at least one second detection signal line and the third line segment connected to the first end of the at least one first detection signal line are adjacent, and in a direction perpendicular to the routing directions of the plurality of second line segments and the plurality of third line segments, the interval width between the second line segment and the third line segment ranges from 2 micrometers to 3 micrometers.

[0015] For example, in the display substrate provided by at least one embodiment of the present disclosure, on the side of the bending region close to the display area, the position where the second ends of the at least one first detection signal line and the at least one second detection signal line are connected in series is located between the first end of the at least one second detection signal line and the first end of the at least one first detection signal line. The first end of the at least one first detection signal line is located on the side of the first end of the at least one second detection signal line away from the plurality of signal lines.

[0016] For example, in the display substrate provided by at least one embodiment of the present disclosure, the at least one second detection signal line further includes a plurality of first broken lines arranged in parallel. One of the plurality of first broken lines is connected to one of the plurality of second line segments and the first end of the at least one second detection signal line, and another one of the plurality of first broken lines is connected to another one of the plurality of second line segments and the second end of the at least one second detection signal line. The line width of the plurality of first broken lines is greater than the line width of the plurality of second line segments.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, at least part of the line segments of the plurality of first broken lines are routed along a second direction different from the first direction.

[0018] For example, in the display substrate provided by at least one embodiment of the present disclosure, the at least one first detection signal line further includes a plurality of fourth line segments. The plurality of fourth line segments are routed along the first direction. One of the plurality of third line segments is connected to the first end of the at least one first detection signal line through one of the plurality of fourth line segments, and another one of the plurality of third line segments is connected to the second end of the at least one first detection signal line through another one of the plurality of fourth line segments. The orthographic projections of the plurality of fourth line segments on the surface of the substrate respectively overlap with the orthographic projections of at least one of the plurality of first broken lines on the surface of the substrate.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the sub-pixel includes a pixel structure, and the pixel structure includes a pixel driving circuit, a first planarization layer, and a light-emitting element. Among them, the pixel driving circuit includes a first display area metal layer, a second display area metal layer, a third display area metal layer, a first insulating layer, a second insulating layer, an interlayer insulating layer, a first planarization layer, and a pixel defining layer. The first planarization layer is on the side of the pixel driving circuit away from the substrate to provide a first planarized surface and includes a first via. The light-emitting element includes a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode. The first electrode is on the side of the first planarization layer away from the substrate, and the first electrode is electrically connected to the third display area metal layer of the pixel driving circuit through the first via. The pixel defining layer is on the side of the first electrode away from the substrate and defines the light-emitting area of the light-emitting element. The first insulating layer is on the substrate, the first display area metal layer is on the side of the first insulating layer away from the substrate, the second insulating layer is on the side of the first display area metal layer away from the substrate, the second display area metal layer is on the side of the second insulating layer away from the substrate, the interlayer insulating layer is between the first planarization layer and the second insulating layer, the third display area metal layer is on the side of the interlayer insulating layer away from the substrate. The display substrate further includes a packaging layer and a touch metal layer. The packaging layer is on the side of the light-emitting element away from the substrate, and the touch metal layer is on the side of the packaging layer away from the substrate. Among them, the at least one second detection signal line is at least disposed on the same layer as the touch metal layer, the at least one first detection signal line is at least disposed on the same layer as the second display area metal layer, and the first power supply line is at least disposed on the same layer as the third display area metal layer.

[0020] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a second via hole, a first peripheral insulating layer, and a second peripheral insulating layer. Among them, the at least one first detection signal line is located on a side of the first peripheral insulating layer close to the substrate, the second peripheral insulating layer is located on a side of the first peripheral insulating layer away from the substrate, the at least one second detection signal line is located on a side of the second peripheral insulating layer away from the substrate, the first peripheral insulating layer is provided on the same layer as the interlayer insulating layer, the second peripheral insulating layer is provided on the same layer as the first planarization layer, the second via hole penetrates at least the first peripheral insulating layer and the second peripheral insulating layer, the second ends of the at least first detection signal line and the at least one second detection signal line are connected in series through the second via hole, and in a direction perpendicular to the plane of the substrate, no insulating layer on the same layer as the pixel defining layer is provided between the second ends of the at least one first detection signal line and the at least one second detection signal line.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, on a side of the display substrate where the shift register is located, the at least one first detection signal line and the at least one second detection signal line are located on a side of the shift register away from the display area.

[0022] At least one embodiment of the present disclosure provides a display device, including the display substrate described in any one of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0024] Figure 1 Schematic diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0025] Figure 2 Schematic diagram of the crack detection principle of a display substrate provided by at least another embodiment of the present disclosure;

[0026] Figure 3 Schematic diagram of the planar layout of partial traces in the peripheral area of a display substrate provided by at least one embodiment of the present disclosure;

[0027] Figure 4 For Figure 3 Magnified view of area A1 in

[0028] Figure 5 For Figure 3 Magnified view of area A2 in

[0029] Figure 6 For Figure 3 an enlarged view of area A3 in

[0030] Figure 7 a cross-sectional view of a display area of a display substrate provided by at least one embodiment of the present disclosure;

[0031] Figure 8 along Figure 6 a cross-sectional view taken along the center line B1 - B2; and

[0032] Figure 9 a schematic diagram of a display device provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0033] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0034] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art belonging to the field of the present disclosure. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents. For the convenience of description, in some of the accompanying drawings, "upper", "lower", "front" and "rear" are given. In the embodiments of the present disclosure, the vertical direction is the direction from top to bottom, the vertical direction is the direction of gravity, the horizontal direction is the direction perpendicular to the vertical direction, and the horizontal direction from right to left is the direction from front to back.

[0035] The existing FMLOC (Flexible Metal-layer on cell touch) has already been a trend design product. Compared with the external touch panel, it can greatly reduce costs, and its integration is higher, and the product is thinner and lighter. In order to simultaneously detect the crack phenomenon generated during the processes of the TFT (Thin Film Transistor) layer metal (Display) and the touch metal layer (Touch) of the FMLOC product, usually the PCD signal for detecting cracks in the TFT layer metal and the PCD signal for detecting the touch metal layer are detected. For example, the PCD signal for detecting cracks in the TFT layer metal and the PCD signal for detecting the touch metal layer can be connected in series. However, due to the limitation of the border space of the display panel (Panel), usually in the periphery of the display panel border (especially at the PCD trace of the touch metal layer detection on one side of the display panel's set bonding area where the PCD trace crosses the signal line (such as the connection design with the GOA (Shift Register))), the signal line between the PCD trace and the display area of the display panel is prone to lack of DC signal shielding such as the cathode, resulting in the problem of interference between the signal lines (such as GOA signal lines) in the display area of the display panel and the PCD signal of the touch metal layer, thus causing the poor anti-static (ESD) ability of the PCD trace of the touch metal layer detection and electrostatic shock damage.

[0036] For example, the PCD signal for detecting cracks in the TFT layer metal and the PCD signal for detecting the touch metal layer can also adopt other methods before being connected in series.

[0037] Therefore, how to solve the problem that the anti-static ability of the PCD trace of the touch metal layer detection on one side of the display panel's set bonding area of the FMLOC product (such as the connection design with the GOA (Shift Register)) is poor, resulting in electrostatic shock damage and interference between the display area signal and the PCD signal of the touch metal layer is one of the key problems that the FMLOC technology urgently needs to solve. The above problems can also seriously reduce the product yield and cause problems such as the PCD being unable to detect.

[0038] At least one embodiment of the present disclosure provides a display substrate, which includes: a substrate substrate, a plurality of signal lines, a first power line, at least one first detection signal line, and at least one second detection signal line. The substrate substrate includes a display area and a peripheral area surrounding the display area. The display area includes a pixel array, and the pixel array includes a plurality of sub-pixels. The peripheral area includes a bending area located on a first side of the display area, a shift register located on at least one of a second side and a third side of the display area, and the first side is adjacent to the second side and the third side. One end of the plurality of signal lines is led out from the bending area, and the other end of the plurality of signal lines is connected to the shift register. The first power line is led out from the bending area and runs around the display area. At least one first detection signal line is disposed on at least one of the side where the shift register is located and a fourth side opposite to the first side of the display area, and a first end of the at least one first detection signal line is led out from the bending area. At least one second detection signal line is disposed on at least one of the side where the shift register is located and the fourth side, and a first end of the at least one second detection signal line is led out from the bending area. On a side close to the bending area outside the area where the orthographic projection of the first power line on the plane of the substrate substrate is located, the orthographic projections of the at least one first detection signal line and the at least one second detection signal line on the plane of the substrate substrate do not overlap with the orthographic projection of the plurality of signal lines on the plane of the substrate substrate.

[0039] At least one embodiment of the present disclosure further provides a display device including the above display substrate.

[0040] In the display substrate and the display device provided in the above embodiments, the display substrate can improve the electrostatic resistance of at least one second detection signal line, especially improve the electrostatic resistance of at least one second detection signal line between the bending area and the display area, and improve the product yield.

[0041] The embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0042] Figure 1 It is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure. Figure 2 It is a schematic diagram of the crack detection principle of a display substrate provided by at least another embodiment of the present disclosure. Figure 3 It is a schematic plan layout of partial wiring of the peripheral area of a display substrate provided by at least one embodiment of the present disclosure.

[0043] For example, in some embodiments, such as Figure 1As shown, the display substrate 1 includes a substrate substrate 100. The substrate substrate 100 includes a display area 10 and a peripheral area 20. The peripheral area 20 surrounds the display area 10. The peripheral area 20 includes a test circuit CT, a bending area 30, and a bonding area 40 located on a first side S1 of the display area 10. In a first direction X, the test circuit CT is located between the bending area 30 and the bonding area 40, that is, the test circuit CT is located on a side of the bending area 30 away from the display area 10. The bonding area 40 includes a plurality of contact pads (as Figure 2 shown) for bonding with a signal input component. For example, the signal input component includes a data driving circuit (IC). Combining Figure 2 shown, the test circuit CT includes a plurality of test units CT1. For example, taking the test unit CT1 as an N-type transistor as an example.

[0044] For example, in other embodiments, based on the design requirements of the display substrate 1, on the first side S1 of the display area 10, the bending area 30 can also be designed to be located on a side of the test circuit CT away from the display area 10.

[0045] It should be noted that the test unit CT1 can also be selected as a P-type transistor, and the embodiments of the present disclosure are not limited thereto.

[0046] As Figure 1 shown, the display substrate 1 further includes a shift register GOA located on a second side S2 and a third side S3 of the display area 10. The first side S1 is adjacent to the second side S2 and the third side S3. In the embodiments of the present disclosure, the shift register GOA is arranged on both sides of the display area 20 for bilateral driving. According to the circuit setting requirements of the display substrate 1, unilateral driving can also be adopted, and the embodiments of the present disclosure are not limited thereto. For example, the display area 10 includes a pixel array P110, and the pixel array P110 includes a plurality of sub-pixels P111. The plurality of sub-pixels P111 are arranged in multiple rows and multiple columns in the display area 10 along the first direction X and the second direction Y. The display substrate 1 further includes a plurality of data lines DL along the first direction X and a plurality of gate lines GL along the second direction Y. The plurality of data lines DL are located in the display area 10 and are respectively electrically connected to the plurality of column sub-pixels P111, that is, each of the plurality of data lines DL is connected to each column of the plurality of sub-pixels P111 (for example, the column direction refers to Figure 1are electrically connected in one-to-one correspondence with the first direction X) in the [description]. A plurality of data lines DL are configured to provide data signals to multiple columns of sub-pixels P111. For example, one end of the plurality of data lines DL also extends to the test circuit CT to receive test data signals. A plurality of gate lines GL pass through the display area 10 horizontally (for example, the second direction Y in the figure) and are electrically connected to the shift register GOA and multiple sub-pixels P111 (arranged in a horizontal row) to provide a gate scan signal and a light emission control signal to the sub-pixels P111. For example, the shift register GOA may include a shift register unit that provides a gate scan signal and a light emission control unit that provides a light emission control signal, which will not be elaborated in detail here.

[0047] For example, as Figure 2 and Figure 3 shown, the display substrate includes a plurality of signal lines CL. One end of the plurality of signal lines CL (located on the first side S1 of the display area) is led out from the bending area 30 (not shown in the figure), and one end of the plurality of signal lines CL (located on the side where the shift register GOA is located) is connected to the shift register unit GOA. For example, the plurality of signal lines CL include a first clock signal line GCB, a second clock signal line GCK, a first trigger signal line GSTV, a second power supply line VGH (for example, providing a high level), a third power supply line VGL (for example, providing a high level), an initialization signal line VINT, and a third clock signal line ECB, a fourth clock signal line ECK, a fourth trigger signal line ESTV, a fourth power supply line VGH, and a fifth power supply line VGL (not shown in the figure) connected to the light emission control unit. The first clock signal line GCB, the second clock signal line GCK, and the first trigger signal line GSTV are used to provide a first clock signal, a second clock signal, and a first trigger signal to the shift register unit respectively. The initialization signal line VINT is configured to be electrically connected to multiple sub-pixels P111 and provide an initialization signal to the multiple sub-pixels P111. For example, the initialization signal line VINT also provides a constant low voltage, which can be a negative voltage or the like. For example, in some examples, this low voltage can be a ground voltage. The third clock signal line ECB, the fourth clock signal line ECK, and the fourth trigger signal line ESTV are used to provide a third clock signal, a fourth clock signal, and a second trigger signal to the light emission control unit respectively.

[0048] For example, in some embodiments, as Figure 2 and Figure 3As shown, the display substrate 1 further includes a first detection signal line BPL and a second detection signal line FML. The first detection signal line BPL is disposed on the side where the shift register GOA is located (e.g., the second side S2 and the third side S3 of the display area) and the fourth side S4 opposite to the first side S1 of the display area 10. The first end BPL1 of the first detection signal line BPL is led out from the bending area 30. The second detection signal line FML is disposed on the side where the shift register GOA is located (e.g., the second side S2 and the third side S3 of the display area) and the fourth side S4. The first end FML1 of the second detection signal line FML is led out from the bending area 30, and on the first side S1 of the display area 10, the second end BPL2 of the first detection signal line BPL is connected in series with the second end FML2 of the second detection signal line FML. For example, the position where the second end BPL2 of the first detection signal line BPL is connected in series with the second end FML2 of the second detection signal line FML is at Figure 2 shown as position L1. Figure 2 In Figure 2 , the first detection signal line BPL and the second detection signal line FML are symmetrically routed on both sides of the display substrate. Combining Figure 3 As shown, the second detection signal line FML is closer to the bending area 30 than the first detection signal line BPL. For example, in the first direction, the second detection signal line FML is located on the side of the first detection signal line BPL away from the plurality of signal lines CL. For example, the bending area 30 may include a plurality of connection leads 3001 along the first direction X. The first end FML1 of the second detection signal line FML and the first end BPL1 of the first detection signal line BPL are respectively connected to the connection leads 3001.

[0049] For example, in other embodiments, the second end BPL2 of the first detection signal line BPL and the second end FML2 of the second detection signal line FML may also be connected in other ways other than in series, and the embodiments of the present disclosure are not limited thereto.

[0050] For example, as Figure 2 shown, in some embodiments, on the side of the display substrate 1 where the shift register GOA is located (e.g., the second side S2 and the third side S3 of the display area), the first detection signal line BPL and the second detection signal line FML are located on the side of the shift register GOA away from the display area 10 to reduce signal interference between the respective traces.

[0051] For example, as Figure 2As shown, the first contact pad ET1 of multiple contact pads in the bonding area 40 of the display area 10 is electrically connected to the first detection signal line BPL. The second contact pad ET2 of the multiple contact pads is electrically connected to the first end (the end far from the display area 10) of the test circuit CT through the test connection line CTD. The third contact pad ET3 of the multiple contact pads is electrically connected to the control end of the test circuit CT through the test control connection line CTSW. The second end of the test circuit CT is electrically connected to the data line DL. During the test stage of the display substrate, the signal input component provides test control signals and test data signals to the test circuit through the second contact pad ET2 and the third contact pad ET3 to light up the display area 10. The signal input component provides electrical signals to the first detection signal line BPL and the second detection signal line FML through the first contact pad ET1 for crack detection. For example, in combination with Figure 3 As shown, the connection lead 3001 in the bending area 30 can also be connected to the contact pad in the bonding area 40.

[0052] For example, in some embodiments, as Figure 3 As shown, on the first side S1 of the display area 10, the region where the positive projection of the first power supply line VSS on the board surface S of the substrate 100 (as Figure 7 shown) is located, the positive projection of the second detection signal line FML on the board surface S of the substrate 100 overlaps with the positive projection of multiple signal lines CL on the board surface S of the substrate 100. That is, the place where the second detection signal line FML overlaps with multiple signal lines CL also overlaps with the first power supply line VSS. For example, on one side close to the bending area 30 outside the region where the positive projection of the first power supply line VSS on the board surface S of the substrate 100 is located, the positive projections of the first detection signal line BPL and the second detection signal line FML on the board surface S of the substrate 100 do not overlap with the positive projection of multiple signal lines CL on the board surface S of the substrate 100. That is, in the region without the first power supply line VSS trace, the second detection signal line FML and multiple signal lines CL do not overlap. Thus, it is possible to avoid the poor electrostatic resistance caused by the shielding of the signals (frequency conversion signals) provided by multiple signal lines CL by the electrical signals provided by the first power supply line in the space without the first power supply line trace, so as to improve the electrostatic resistance of the second detection signal line FML and the product yield.

[0053] For example, in some embodiments, as Figure 3As shown, in the region where the orthographic projection of at least one second detection signal line FML on the surface S of the substrate 100 overlaps with the orthographic projection of multiple signal lines CL on the surface S of the substrate 100, the entire region is covered by the region where the orthographic projection of the first power supply line VSS on the surface S of the substrate 100 is located. That is, in the region outside the orthographic projection of VSS on the surface S of the substrate 100 in the figure, the second detection signal line FML does not overlap with the multiple signal lines CL, thereby improving the electrostatic resistance ability and product yield of the second detection signal line FML.

[0054] For example, in some embodiments, as Figure 3 shown, on the first side S1 of the display area 10 and in the direction perpendicular to the surface S of the substrate 100, at least a part of the film layer where the first power supply line VSS is located is between the film layer where the second detection signal line FML is located and the film layer where the multiple signal lines CL are located. That is to say, in the direction perpendicular to the surface S of 100, the second detection signal line FML is on the side of the first power supply line VSS away from the substrate 100, and the multiple signal lines CL are on the side of the first power supply line VSS close to the substrate 100. The second detection signal line FML is designed such that the electrical signals of the first power supply line VSS completely cover the area of the multiple signal lines CL. That is, the region where the second detection signal line FML overlaps with the multiple signal lines CL is completely covered by the first power supply line VSS, thereby effectively shielding the interference problem between the variable-frequency signals of the second detection signal line FML and the multiple signal lines CL by using the DC signal of the first power supply line VSS, thus avoiding the formation of a strong interference electric field in the overlapping region between the second detection signal line FML and the multiple signal lines CL, and effectively reducing the charge aggregation problem caused by the variable-frequency signals of the multiple signal lines CL at the position where the second detection signal line FML crosses the multiple signal lines CL, greatly improving the electrostatic resistance ability and signal interference problem of the second detection signal line FML in this region.

[0055] It should be noted that the film layer where the first power supply line VSS is located, the film layer where the second detection signal line FML is located, and the film layer where the multiple signal lines CL are located will be introduced in detail later in combination with the cross-sectional view of the display area.

[0056] For example, in some embodiments, as Figure 3 shown, on the side of the region outside the orthographic projection of the first power supply line VSS on the surface S of the substrate 100 and close to the bending region 30, the multiple signal lines CL are arranged in substantially the same direction so that they do not overlap. For example, they can be arranged in parallel. At least a part of the line segments (such as some line segments) of the first detection signal line BPL and at least a part of the line segments (such as some line segments) of the second detection signal line FML are arranged in substantially the same direction as the multiple signal lines CL so that they do not overlap. For example, they can be arranged in parallel. In Figure 3In the A2 area, the segments of the first detection signal line BPL and the segments of the second detection signal line FML are parallel to multiple signal lines CL and are routed in a direction that intersects both the first direction X and the second direction Y. The first detection signal line BPL is located between the second detection signal line FML and the multiple signal lines CL, that is, the first detection signal line BPL is on the side of the second detection signal line FML away from the multiple signal lines CL. Thus, the second detection signal line FML is located outside the multiple signal lines CL and is parallel to the multiple signal lines CL, thereby completely avoiding the problems of poor electrostatic resistance and signal interference caused by the frequency conversion signals of the multiple signal lines CL in this section of space interfering with the second detection signal line FML.

[0057] For example, in the present disclosure, the included angle between the first direction X and the second direction Y is between 70° and 90°, and includes 70° and 90°. For example, the included angle between the first direction X and the second direction Y is 70°, 90°, or 80°, etc., which can be set according to actual situations, and the embodiments of the present disclosure do not limit this. For example, the included angle between the first direction X and the second direction Y can also be 75°, 85°, etc.

[0058] It should be noted that in the embodiments of the present disclosure, "substantially" means that the directions of two routed lines are the same or slightly different. For example, the included angle of the deviation in the routing directions between the two routed lines is, for example, less than about 10°, or for example, less than about 5°, etc.

[0059] Figure 4 For Figure 3 an enlarged view of the A1 area in

[0060] For example, in some embodiments, as Figure 3 and Figure 4 shown, on the first side S1 of the display area 10, the second detection signal line FML includes multiple first segments FML3 respectively connected to the first end FML1 and the second end FM2 of the second detection signal line FML. The multiple first segments FML3 extend substantially along the first direction X. For example, they can extend completely along the first direction X. For example, the multiple first segments FML3 include a first segment FML31 and a first segment FML32. The first segment FML31 is connected to the first end FML1 of the second detection signal line FML, and the first segment FML32 is connected to the second end FM2 of the second detection signal line FML. In Figure 3Among them, the first line segment FML31 is located on the right side of the first line segment FML32. In the region where the positive projection of the first power supply line VSS on the plate surface S of the substrate 100 is located, the positive projections of multiple first line segments FML3 on the plate surface S of the substrate 100 and the positive projections of multiple signal lines CL on the plate surface S of the substrate 100 overlap. That is to say, the first line segment FML3 is stacked with the first power supply line VSS and overlaps with multiple signal lines CL. In some embodiments, the region where the second detection signal line FML overlaps with multiple signal lines CL is completely covered by the first power supply line VSS. Thus, the interference problem between the variable-frequency signals of the second detection signal line FML and multiple signal lines CL is effectively shielded by the DC signal of the first power supply line VSS, thereby avoiding the formation of a strong interference electric field in the overlapping region between the second detection signal line FML and multiple signal lines CL, and effectively reducing the charge aggregation problem caused by the variable-frequency signals of multiple signal lines CL at the position where the second detection signal line FML crosses multiple signal lines CL, greatly improving the electrostatic resistance ability and signal interference problem of the second detection signal line FML in this region.

[0061] For example, in some embodiments, as Figure 4 shown, on one side close to the bending region 30 outside the region where the positive projection of the first power supply line VSS on the plate surface S of the substrate 100 is located, the positive projections of multiple first line segments FML3 on the plate surface S of the substrate 100 also overlap with the positive projections of at least one first detection signal line BPL (such as the third line segment BPL3) on the plate surface S of the substrate 100. Thus, the risk of crack generation caused by the cutting process on the mother board where the display substrate 1 is located can be reduced.

[0062] For example, in other embodiments, as Figure 4 shown, when the space in the peripheral region 20 of the display substrate 1 permits, the edge of the first power supply line VSS close to the first detection signal line BPL can continue to extend towards the first detection signal line BPL, so that the positive projection of the first power supply line VSS on the plate surface S of the substrate 100 covers the overlapping region of the positive projections of multiple first line segments FML3 and the first detection signal line BPL (such as the third line segment BPL3) on the plate surface S of the substrate 100. Thus, the electrostatic resistance ability of the second detection signal line FML can be further improved. For example, in some embodiments, as Figure 4 shown, the length D1 range of the region where the positive projections of multiple first line segments FML3 on the plate surface S of the substrate 100 overlap with the positive projections of multiple signal lines CL on the plate surface S of the substrate 100 in the first direction X is about 220 micrometers - 260 micrometers. Thus, the interference problem between the variable-frequency signals of the second detection signal line FML and multiple signal lines CL is effectively shielded by the DC signal of the first power supply line VSS.

[0063] Figure 5 is Figure 3 an enlarged view of area A2 in

[0064] For example, in some embodiments, as Figure 3 and Figure 5 shown, the second detection signal line FML further includes a plurality of second line segments FML4. For example, the plurality of second line segments FML4 are routed in a direction intersecting the first direction X, for example, in a direction not parallel to either the first direction X or the second direction Y. For example, the routing directions of the plurality of second line segments FML4 are parallel (e.g., substantially parallel) to the routing directions of the plurality of signal lines CL. For example, the plurality of second line segments FML4 include a second line segment FML41 and a second line segment FML42, and the second line segment FML41 is located on the side of the second line segment FML42 closer to the plurality of signal lines CL. One of the plurality of first line segments FML3 (e.g., the first line segment FML31) is connected to the first end FML1 of the second detection signal line FML through one of the plurality of second line segments FML4 (e.g., the second line segment FML41). Another one of the plurality of first line segments FML3 (e.g., the first line segment FML31) is connected to the second end FML2 of the second detection signal line FML through another one of the plurality of second line segments FML4 (e.g., the second line segment FML42). The plurality of second line segments FML4 are located between the plurality of first line segments FML3 and the bending region 30. The connection between FML3 and FML4 can be a gentle or smooth transition. For example, it can be at a certain angle, but the angle can be designed with an arc or a chamfer. In some embodiments, the angle can be about 90°. "About" means not strictly limiting the boundary and can include other angles for achieving a gentle or smooth transition.

[0065] For example, the plurality of first line segments FML3 can also not be parallel to the first direction X, for example, intersect the first direction X at a certain angle. For example, the intersection angle is less than or equal to about 20°.

[0066] It should be noted that in the embodiments of the present disclosure, "about" means that it can fluctuate within, for example, ±15% or ±5% of the value it takes.

[0067] For example, in some embodiments, as Figure 3 and Figure 5As shown, the first detection signal line BPL includes a plurality of third line segments BPL3 respectively connected to the first end BPL1 and the second end BPL2 of the first detection signal line BPL. For example, the plurality of third line segments BPL3 are routed in a direction intersecting the first direction X, for example, in a direction not parallel to either the first direction X or the second direction Y. For example, the routing direction of the plurality of third line segments BPL3 is parallel (e.g., substantially parallel) to the routing direction of the plurality of signal lines CL. For example, the plurality of third line segments BPL3 include a third line segment BPL31 and a third line segment BPL32, and the third line segment BPL31 is located on the side of the third line segment BPL32 away from the plurality of signal lines CL. For example, the third line segment BPL31 is adjacent to the second line segment FML41. For example, the orthographic projection of the plurality of third line segments BPL3 on the board surface S of the substrate 100 overlaps with the orthographic projection of the plurality of first line segments FML3 on the board surface S of the substrate 100, and the plurality of third line segments BPL3 and the plurality of second line segments FML4 are routed in parallel (e.g., substantially parallel) and arranged side by side. That is, in Figure 3 In, the second line segment FML4 not only intersects the plurality of signal lines CL, but also intersects the plurality of third line segments BPL3 on the side close to the bending region 30 outside the first power supply line VSS. The plurality of third line segments BPL3 are located on the side of the plurality of second line segments FML4 close to the display region 10 and between the plurality of second line segments FML4 and the plurality of signal lines CL. Thus, while effectively shielding the interference problem between the variable-frequency signals of the second detection signal line FML and the plurality of signal lines CL by the DC signal of the first power supply line VSS, the wiring space can also be reduced.

[0068] For example, in some embodiments, as Figure 5 shown, in the direction perpendicular to the routing directions of the plurality of second line segments FML4 and the plurality of third line segments BPL3, the plurality of second line segments ML4 and the plurality of third line segments BPL3 are routed in parallel (e.g., substantially parallel) to the corresponding segments of the plurality of signal lines CL. Thus, the signal interference of the plurality of signal lines CL on the first detection signal line BPL and the second detection signal line FML can be reduced, and the wiring space can also be reduced.

[0069] For example, in some embodiments, as Figure 5 shown, the second line segment FML41 connected to the first end FML1 of the second detection signal line FML is adjacent to the third line segment BPL31 connected to the first end BPL1 of the first detection signal line BPL. In the direction perpendicular to (e.g., substantially perpendicular to) the routing directions of the plurality of second line segments FML4 and the plurality of third line segments BPL3, the interval width D2 between the second line segment FML41 and the third line segment BPL31 adjacent to each other ranges from about 2 microns to 3 microns, so that the distance between the first detection signal line BPL and the second detection signal line FML can be made smaller, reducing the wiring space.

[0070] For example, in some embodiments, as Figure 3 shown, on the side of the bending region 30 close to the display region 10, the position L1 where the second end BPL2 of the first detection signal line BPL and the second end FML2 of the second detection signal line FML are connected in series is located between the first end FML1 of the second detection signal line FML and the first end BPL1 of the first detection signal line BPL. The first end BPL1 of the first detection signal line BPL is located on the side away from the plurality of signal lines CL of the first end FML1 of the second detection signal line FML. Thereby, the wiring space can be reduced.

[0071] Figure 6 is Figure 3 an enlarged view of area A3 in.

[0072] For example, in some embodiments, as Figure 3 and Figure 6 shown, the second detection signal line FML further includes a plurality of first broken lines FML5 with substantially the same arrangement profile, for example, which can be juxtaposed. For example, the plurality of first broken lines FML5 are bent and routed along the first direction X and the second direction Y. For example, the plurality of first broken lines FML5 include a first broken line FML51 and a first broken line FML52. The first broken line FML51 connects the first end FML1 of the second detection signal line FML and the second line segment FML41. The first broken line FML52 connects the second end FML2 of the second detection signal line FML and the second line segment FML42. One of the plurality of first broken lines FML5, for example, the first broken line FML51, is connected to one of the plurality of second line segments FML4 (for example, the second line segment FML41) and the first end FML1 of the second detection signal line FML. The other of the plurality of first broken lines FML5 (for example, the first broken line FML52) is connected to the other of the plurality of second line segments FML4 (for example, the second line segment FML42) and the second end FML1 of the second detection signal line FML. The line width of the plurality of first broken lines FML5 is greater than the line width of the plurality of second line segments FML4. For example, in the direction perpendicular to the routing direction of the plurality of second line segments FML4 (the second line segment FML41 or the second line segment FML42), the line width of the second line segment FML4 is about 15 - 20 microns. For example, in the direction perpendicular to the routing of the plurality of first broken lines FML5 (the first broken line FML51 or the first broken line FML52), the line width of the first broken line FML5 is about 25 - 30 microns. Thereby, the anti-electrostatic interference ability of the second detection signal line FML can be increased.

[0073] For example, in some embodiments, as Figure 6As shown, at least part of the multiple first folded line segments FML5 runs along the second direction Y. As shown in the figure, the first folded line segment FML52 extends first along the second direction Y (e.g., substantially parallel to the second direction Y) from near the second end of the second detection signal line FML and then extends along the first direction X (e.g., substantially parallel to the first direction X) to connect with the second line segment FML4. The first folded line segment FML51 extends first along the first direction X from near the second end of the second detection signal line FML, then extends along the second direction Y, and then extends along the first direction X to connect with the second line segment FML4.

[0074] For example, some segments of the routing of the multiple first folded line segments FML5 (extending along the first direction X) may not be parallel to the first direction X, e.g., intersect the first direction X at a certain angle. For example, the intersection angle is less than or equal to about 20°. Some segments of the routing of the multiple first folded line segments FML5 (extending along the second direction Y) may not be parallel to the second direction Y, e.g., intersect the second direction Y at a certain angle. For example, the intersection angle is less than or equal to about 20°.

[0075] For example, in some embodiments, as Figure 6 shown, the first detection signal line BPL further includes multiple fourth line segments BPL4. The multiple fourth line segments BPL4 run along the first direction X, e.g., the routing method of the fourth line segments BPL4 is substantially parallel to the first direction X. For example, the multiple fourth line segments BPL4 include a fourth line segment BPL41 and a fourth line segment BPL42. The fourth line segment BPL41 is located on the side of the fourth line segment BPL42 away from the multiple signal lines CL. One of the multiple third line segments BPL3 (e.g., the third line segment BPL31) is connected to the first end BPL1 of the first detection signal line BPL through one of the multiple fourth line segments BPL4 (e.g., the fourth line segment BPL41). Another of the multiple third line segments BPL3 (e.g., the third line segment BPL31) is connected to the second end BPL2 of the first detection signal line BPL through another of the multiple fourth line segments BPL4 (e.g., the fourth line segment BPL42). The orthographic projections of the multiple fourth line segments BPL4 on the board surface S of the substrate 100 respectively overlap with the orthographic projections of at least one of the multiple first folded line segments FML5 on the board surface S of the substrate 100. Specifically, the orthographic projection of the fourth line segment BPL41 on the board surface S of the substrate 100 overlaps with the orthographic projections of both the first folded line segment FML51 and the first folded line segment FML52 on the board surface S of the substrate 100. The orthographic projection of the fourth line segment BPL42 on the board surface S of the substrate 100 overlaps with the orthographic projection of the first folded line segment FML51 on the board surface S of the substrate 100. Thus, the routing space can be reduced without affecting the anti-static interference ability of the second detection signal line FML.

[0076] For example, multiple fourth line segments BPL4 may not be parallel to the first direction X either, for example, intersecting the first direction X at a certain angle. For example, the intersection angle is less than or equal to about 20°.

[0077] For example, as Figure 3 and Figure 6 As shown, the second end BPL2 of the first detection signal line BPL and the second end FML2 of the first detection signal line FML are connected through the second via GK1. The second end BPL2 of the first detection signal line BPL may also be connected to the lead 3001 of the bending area 30 through the third via GK2, and the first end BPL1 of the first detection signal line BPL may also be connected to the lead 3001 of the bending area 30 through the fourth via GK3.

[0078] Figure 7 It is a cross-sectional schematic diagram of a display area of a display substrate provided by at least one embodiment of the present disclosure. Figure 8 It is a cross-sectional schematic diagram along Figure 6 the center line B1 - B2.

[0079] For example, in some examples, as Figure 7 shown, each of the multiple sub-pixels P111 includes a pixel structure, and the pixel structure includes a pixel driving circuit 103. The pixel driving circuit 103 includes a first display area metal layer 301, a second display area metal layer 302, and a third display area metal layer 303. The first display area metal layer 301 is located on the substrate 100, that is, between the first insulating layer 1242 (i.e., the first gate insulating layer) and the second insulating layer 1243 (i.e., the second gate insulating layer). The second display area metal layer 302 is located on the side of the first metal layer 301 away from the substrate 100, that is, between the second insulating layer 1243 and the interlayer insulating layer 1244. The third display area metal layer 303 is located on the side of the second display area metal layer 302 away from the substrate 100, that is, on the side of the interlayer insulating layer 1244 away from the substrate 100.

[0080] For example, the substrate 100 may be a glass plate, a quartz plate, a metal plate, a resin plate, etc. For example, the material of the substrate may include organic materials, for example, the organic materials may be resin materials such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate; for example, the substrate 100 may be a flexible substrate or a non-flexible substrate, and the embodiments of the present disclosure do not limit this.

[0081] For example, as Figure 7As shown, the pixel driving circuit 103 further includes a plurality of transistors and capacitors. The plurality of transistors include a transistor directly electrically connected to the light-emitting device, such as a switching transistor (e.g., a light-emitting control transistor) or a driving transistor. The plurality of capacitors include storage capacitors (for storing the written data signal). In one embodiment, the pixel driving circuit 103 includes a driving transistor 12 and a storage capacitor 13. The driving transistor 12 includes a gate 122, a source 123, a drain 124, and an active layer 121. The display substrate 1 further includes a barrier layer 1240, a buffer layer 1241, a first insulating layer 1242, a second insulating layer 1243, and an interlayer insulating layer 1244. The storage capacitor 13 includes a first electrode plate 131 and a second electrode plate 132. The first electrode plate 131 and the second electrode plate 132 are stacked opposite to each other. The barrier layer 1240 is located on the substrate 100, and the buffer layer 1241 is located on the side of the barrier layer 1240 away from the substrate 100. The buffer layer 1241 serves as a transition layer, which can prevent harmful substances in the substrate from invading the inside of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate 100. The barrier layer 1240 can provide a flat surface for forming the pixel driving circuit 103 and can prevent impurities that may exist in the substrate 100 from diffusing into the sub-pixel driving circuit or the pixel driving circuit 103 and adversely affecting the performance of the display substrate.

[0082] For example, the material of the buffer layer 1241 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The material of one or more of the first insulating layer 1242, the second insulating layer 1243, and the interlayer insulating layer 1244 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The materials of the first insulating layer 1242, the second insulating layer 1243, and the interlayer insulating layer 1244 may be the same or different.

[0083] For example, the material of the barrier layer 1240 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0084] For example, continue as Figure 7As shown, the active layer 121 is disposed on the substrate 100 and is located on the side of the buffer layer 1241 away from the substrate 100. The first insulating layer 1242 is located on the side of the active layer 121 away from the substrate 100. The gate 122 and the first electrode plate 131 are disposed on the same layer on the side of the first insulating layer 1242 away from the substrate 100. The second insulating layer 1243 is located on the side of the gate 122 and the first electrode plate 131 away from the substrate 100. The second electrode plate 132 is disposed on the side of the second insulating layer 1243 in the display area away from the substrate 100. The interlayer insulating layer 1244 is located on the side of the second electrode plate 132 away from the substrate 100. The source electrode 123 and the drain electrode 124 are disposed on the side of the interlayer insulating layer 1244 away from the substrate 100 and are electrically connected to the active layer 121 through vias in the first insulating layer 1242, the second insulating layer 1243, and the interlayer insulating layer 1244. The gate 122 and the first electrode plate 131 are located in the first display area metal layer 301, the second electrode plate 132 is located in the second display area metal layer 302, and the source electrode 123 and the drain electrode 124 are located in the third display area metal layer 303.

[0085] For example, the material of the active layer 121 may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)). The material of the gate 122 may include a metal material or an alloy material, such as a single-layer or multi-layer structure of metals formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). The material of the source electrode 123 and the drain electrode 124 may include a metal material or an alloy material, such as a single-layer or multi-layer structure of metals formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of the respective functional layers. For example, the material of the second electrode plate 132 may include a metal material or an alloy material, such as a single-layer or multi-layer structure of metals formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)).

[0086] For example, as Figure 7 shown, the display substrate 1 further includes a first planarization layer 1245. The first planarization layer 1245 provides a first planarized surface on the side of the source electrode 123 and the drain electrode 124 (i.e., the pixel driving circuit 103) away from the substrate 100 to planarize the surface of the pixel driving circuit 103 on the side away from the substrate 100. The first planarization layer 1245 includes a first via 233, and the pixel driving circuit 103 (e.g., the third display area metal layer 303) is electrically connected to the light-emitting device (e.g., through the first transfer electrode 241) through the first via 233.

[0087] As Figure 7As shown, the display substrate 1 further includes a first transfer electrode 241 and a second planarization layer 251 located in the fourth display area metal layer 304. The first transfer electrode 241 is disposed on a side of the first planarization layer 1245 away from the substrate 100. The first transfer electrode 241 is electrically connected to the drain 124 (or the source 123) through a first via 233. The first transfer electrode 241 can avoid directly forming a straight through via with a relatively large aperture in the first planarization layer 232, thereby improving the quality of the via electrical connection. At the same time, the first transfer electrode 241 can also be formed in the same layer as other signal lines, thus not causing an increase in process steps.

[0088] For example, the materials of the first planarization layer 1245 and the second planarization layer 251 include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may also include organic insulating materials such as polyimide, polyphthalimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure are not limited thereto.

[0089] For example, the material of the first transfer electrode 241 may include a metal material or an alloy material, such as a single-layer or multi-layer structure formed by molybdenum, aluminum, titanium, etc.

[0090] For example, as Figure 7 As shown, the display substrate 1 further includes a passivation layer 1246, and the passivation layer 1246 is located between the pixel driving circuit 106 and the first planarization layer 1245. At this time, the first via 233 also penetrates through the passivation layer 1246. The passivation layer 1246 can protect the source 123 and the drain 124 of the pixel driving circuit 103 from being corroded by water vapor. The pixel driving circuit 103 and the first transfer electrode 241 are electrically connected through the first via 233.

[0091] For example, the material of the passivation layer 1246 may include an organic insulating material or an inorganic insulating material. For example, the silicon nitride material, due to its high dielectric constant and good hydrophobic function, can well protect the pixel driving circuit 103 from being corroded by water vapor.

[0092] For example, as Figure 7 As shown, the second planarization layer 251 is disposed on a side of the first transfer electrode 241 away from the substrate 100 to provide a planarized surface on a side of the first transfer electrode 241 away from the substrate 100. And, a via 252 is formed in the second planarization layer 251 to expose the first transfer electrode 241.

[0093] For example, as Figure 7As shown, the display substrate 1 further includes a pixel defining layer 146 and a light-emitting element 11. The light-emitting element 11 is disposed on a side of the second planarization layer 251 away from the substrate 100. The light-emitting element 11 includes a first electrode 113 (e.g., an anode), a light-emitting layer 112, and a second electrode 111 (e.g., a cathode). The first electrode 113 is located on a side of the first planarization layer 1245 away from the substrate 100 and is connected to the first transfer electrode 241 through a via 252 of the second planarization layer 251 to be electrically connected to the pixel driving circuit 103 (e.g., the drain 124 of the driving transistor 12). The second electrode 111 is located on a side of the pixel defining layer 146 away from the substrate 100. The pixel defining layer 146 is located on a side of the first electrode 113 away from the substrate 14 and includes a first pixel opening 1461. The first pixel opening 1461 is disposed corresponding to the light-emitting element 11. The light-emitting layer 112 is located in the first pixel opening 1461 and between the first electrode 113 and the second electrode 111. The portion of the light-emitting layer 112 directly sandwiched between the first electrode 113 and the second electrode 111 will emit light after being powered on, and thus the region occupied by this portion corresponds to the light-emitting area of the light-emitting element 11.

[0094] For example, the pixel driving circuit 103 generates a light-emitting driving current under the control of a data signal provided by the data driving circuit through the data line DL, a gate scanning signal provided by the shift register through the gate line GL, a light-emitting control signal, etc. The light-emitting driving current enables the light-emitting element 11 to emit red light, green light, blue light, or white light, etc.

[0095] For example, the pixel driving circuit 103 includes a conventional 7T1C (i.e., seven transistors and one capacitor) pixel circuit. The seven transistors include at least one switching transistor and one driving transistor (such as Figure 7 the driving transistor 103 as mentioned). The gate of the switching transistor is electrically connected to the shift register unit to receive a gate following signal, and the source or drain of the switching transistor is connected to the data line DL to receive a data signal. In different embodiments, the pixel driving circuit 103 may further include a compensation circuit, which includes an internal compensation circuit or an external compensation circuit. The compensation circuit may include transistors, capacitors, etc. For example, according to needs, the pixel circuit may further include a reset circuit, a light-emitting control circuit, a detection circuit, etc. The embodiments of the present disclosure do not limit the type of the first light-emitting device and the specific structure of the pixel circuit.

[0096] For example, the material of the pixel defining layer 146 may include organic insulating materials such as polyimide, polyphthalimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin, or may include inorganic insulating materials such as silicon oxide, silicon nitride, etc. The embodiments of the present disclosure do not limit this.

[0097] For example, the material of the first electrode 113 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode 113 may include a metal with a high reflectivity as a reflective layer, such as silver (Ag).

[0098] For example, for an OLED, the light-emitting layer 112 may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent light-emitting material or a phosphorescent light-emitting material, may emit red light, green light, blue light, or may emit white light; and, according to needs, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0099] For a QLED, the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, etc., and the particle size of the quantum dots is 2 - 20 nm.

[0100] For example, the second electrode 111 may include various conductive materials. For example, the second electrode 111 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc.

[0101] For example, as Figure 7 shown, the display substrate 1 further includes a packaging layer 147. The packaging layer 147 is located on the side of the second electrode 111 away from the substrate 100. The packaging layer 147 seals the light-emitting element 11 (light-emitting element 11), thereby reducing or preventing the deterioration of the light-emitting element 11 caused by moisture and / or oxygen included in the environment. The packaging layer 147 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which an inorganic layer and an organic layer are stacked. The packaging layer 147 includes at least one packaging sub-layer. For example, the packaging layer 147 may include a first inorganic packaging layer, a first organic packaging layer, and a second inorganic packaging layer arranged in sequence.

[0102] For example, the material of the packaging layer 147 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic packaging layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and can relieve the stress between the first inorganic packaging layer and the second inorganic packaging layer, and may also include water-absorbing materials such as desiccants to absorb substances such as water and oxygen that invade the interior.

[0103] For example, as Figure 7As shown, the display substrate 1 further includes a touch layer 28 on the side of the encapsulation layer 147 away from the substrate 100. The touch layer 28 includes at least one touch metal layer and a touch insulating layer 283. The at least one touch metal layer includes a first touch pattern layer 282 and a second touch pattern layer 281. The first touch pattern layer 282 includes first touch signal lines Rx and second touch signal lines Tx that are alternately connected. The second touch pattern layer 281 is located on the side of the first touch pattern layer 282 close to the substrate. The touch insulating layer 283 is located between the first touch pattern layer 282 and the second touch pattern layer 281. The second touch pattern layer 281 includes a plurality of first transfer portions RL. The plurality of first transfer portions RL are located at positions where the first touch signal lines Rx and the second touch signal lines Tx cross each other. The plurality of first transfer portions RL are electrically connected to the first touch signal lines Rx through vias passing through the touch insulating layer 283. The second touch signal lines Tx and the first touch signal lines Rx overlap each other in a direction perpendicular to the plane of the substrate 100 to form a touch sensor, and a touch sensor is also formed between adjacent second touch signal lines Tx and first touch signal lines Rx.

[0104] For example, in other embodiments, the first touch pattern layer 282 and the second touch pattern layer 281 may respectively include second touch signal lines Tx and first touch signal lines Rx. The second touch signal lines Tx are electrically connected to the first touch signal lines Rx through vias penetrating the touch insulating layer 283. The first touch signal lines Rx are continuous. At this time, there is no need to set the first transfer portions RL anymore. The second touch signal lines Tx and the first touch signal lines Rx overlap each other in a direction perpendicular to the plane of the substrate 200 to form a touch sensor, and a touch sensor is also formed between adjacent second touch signal lines Tx and first touch signal lines Rx.

[0105] For example, the first touch pattern layer 282 and the second touch pattern layer 281 are made of a transparent conductive material. For example, the transparent conductive material may be a transparent conductive metal oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), indium gallium zinc oxide (IGZO), etc. For example, in other examples, the second touch signal lines Tx and the first touch signal lines Rx may be in a metal mesh structure. For example, the material of the metal mesh may be gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), or an alloy material of the above metals.

[0106] For example, in some embodiments, the second detection signal line FML is provided on the same layer as the first touch pattern layer 282.

[0107] For example, in other embodiments, the second detection signal line FML may also be provided on the same layer as the second touch pattern layer 281.

[0108] For example, as Figure 7 shown, the display substrate 1 further includes a protective layer 284 located on the side of the touch layer 28 away from the substrate. For example, the material of the protective layer 284 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc. Polymer resin, etc. can planarize the surface of the display panel and relieve stress.

[0109] For example, in some embodiments, in combination with Figure 7 and Figure 8 shown, the second detection signal line FML is disposed on the same layer as the touch metal layer (e.g., the first touch pattern layer 282 and / or the second touch pattern layer 281), the first detection signal line BPL is disposed on the same layer as the second display area metal layer 302 (e.g., the second electrode plate 132 of the storage capacitor 13), and the first power supply line VSS is disposed on the same layer as the third display area metal layer 303. The following will be described in detail with reference to the cross-sectional view along line B1 - B2 in Figure 6 .

[0110] For example, in other embodiments, the first detection signal line BPL may also be disposed on the same layer as the third display area metal layer 303. It should be noted that on the side of the bending area 30 close to the display area, when both the first detection signal line BPL and the first power supply line VSS are disposed on the same layer as the third display area metal layer 303, the positive projections of the first power supply line and the first detection signal line BPL on the board surface S of the substrate 100 do not overlap. When the first detection signal line BPL is disposed on the same layer as the second display area metal layer 302 and the first power supply line VSS is disposed on the same layer as the third display area metal layer 303, when the space in the peripheral area 20 of the display substrate 1 permits, the edge of the first power supply line VSS close to the first detection signal line BPL can continue to extend towards the first detection signal line BPL, so that the positive projection of the first power supply line VSS on the board surface S of the substrate 100 covers the overlapping area of the positive projections of multiple first line segments FML3 and the first detection signal line BPL (e.g., the third line segment BPL3) on the board surface S of the substrate 100.

[0111] For example, in combination with Figure 3 and Figure 6 shown, the multiple signal lines CL may include at least one metal layer. For example, each of the multiple signal lines CL includes two spaced metal layers. For example, one of the metal layers is disposed on the same layer as the first display area metal layer 301, and for example, the other metal layer is disposed on the same layer as the second display area metal layer 302. For example, the two metal layers are insulated by a second insulating layer 1243 therebetween.

[0112] For example, multiple signal lines CL also extend to the bending region 30 and are connected to corresponding leads 3001 in the bending region 30. At least one metal layer in the lead 3001 is provided on the same layer as the fourth display region metal layer 304. For example, the metal layer in the multiple signal lines CL that is on the same layer as the second display region metal layer 302 is connected to the lead 3001 through a via hole that penetrates through a multi-layer insulating layer that is on the same layer as the interlayer insulating layer 1244, the first planarization layer 1245, and the passivation layer 1246.

[0113] For example, the first power supply line VSS also extends to the bending region 30 and is connected to corresponding leads 3001 in the bending region 30. At least one metal layer in the lead 3001 is provided on the same layer as the fourth display region metal layer 304. For example, the metal layer in the first power supply line VSS that is on the same layer as the second display region metal layer 302 is connected to the lead 3001 through a via hole that penetrates through a multi-layer insulating layer that is on the same layer as the first planarization layer 1245 and the passivation layer 1246.

[0114] It should be noted that in the embodiments of the present disclosure, "being provided on the same layer" includes that two functional layers or structural layers are on the same layer and formed of the same material in the hierarchical structure of the display substrate. That is, in the manufacturing process, these two functional layers or structural layers can be formed from the same material layer and the required patterns and structures can be formed through the same patterning process. A patterning process includes, for example, processes such as the formation of photoresist, exposure, development, and etching.

[0115] For example, as Figure 8 shown, on the first side S1 of the display region 10, the display substrate 1 includes a first peripheral insulating layer 2244 and a second peripheral insulating layer 2245. The first detection signal line BPL is located on the side of the first peripheral insulating layer 2244 close to the substrate 100, the second peripheral insulating layer 2245 is located on the side of the first peripheral insulating layer 2244 away from the substrate 100, and the second detection signal line FML is located on the side of the second peripheral insulating layer 2245 away from the substrate 100. The first peripheral insulating layer 2244 is on the same layer as the interlayer insulating layer 1244, and the second peripheral insulating layer 2245 is on the same layer as the first planarization layer 1245. The second via hole GK1 penetrates at least the first peripheral insulating layer 2244 and the second peripheral insulating layer 2245. The second end BPL2 of the first detection signal line BPL and the second end FML2 of the second detection signal line FML are connected in series through the second via hole GK1.

[0116] For example, as Figure 8As shown, the second via G1 includes a first sub-via GK11 and a second sub-via GK12. The display substrate 1 further includes a peripheral passivation layer 2246, a third peripheral insulating layer 2251, a fourth peripheral insulating layer 2283, a second transfer electrode ZL1, and a third transfer electrode ZL2. The peripheral passivation layer 2246 is disposed between the first peripheral insulating layer 2244 and the second peripheral insulating layer 2245, and is disposed on the same layer as the passivation layer 1246. The third peripheral insulating layer 2251 is disposed on a side of the second peripheral insulating layer 2245 away from the substrate 100. The second transfer electrode ZL1 and the third transfer electrode ZL2 are located between the third peripheral insulating layer 2251 and the second peripheral insulating layer 2245, and are disposed on the same layer as the first transfer electrode 241. The fourth peripheral insulating layer 2283 is disposed on a side of the second transfer electrode ZL1 and the third transfer electrode ZL2 away from the substrate 100. The second detection signal line FML is disposed on a side of the fourth peripheral insulating layer 2283 away from the substrate. The first sub-via GK11 penetrates through the first peripheral insulating layer 2244, the peripheral passivation layer 2246, and the second peripheral insulating layer 2245, and is configured to expose the second end BPL2 of the first detection signal line BPL. The second sub-via GK12 penetrates through the third peripheral insulating layer 2251 and the fourth peripheral insulating layer 2283, and is configured to expose the second transfer electrode ZL1. The second transfer electrode ZL1 is connected to the second end BPL2 of the first detection signal line BPL through the first sub-via GK11, and a part of the second end FML2 of the second detection signal line FML is connected to the second transfer electrode ZL1 through the second sub-via GK12, so as to realize the series connection of the second end FML2 of the second detection signal line FML and the second end BPL2 of the first detection signal line BPL. The second transfer electrode ZL1 can avoid directly forming a through-via with a relatively large aperture in the insulating layer between the first detection signal line BPL and the second detection signal line FML, thereby improving the quality of the via electrical connection.

[0117] For example, as Figure 8 shown, in the direction perpendicular to the plane S of the substrate 100, no insulating layer on the same layer as the pixel defining layer 1461 is provided between the second end BPL2 of the first detection signal line BPL and the second end FML2 of the second detection signal line FML, so as to reduce the film thickness and improve the connection quality of the first detection signal line BPL and the second detection signal line FML.

[0118] For example, continuing as Figure 8As shown, the sub-via GK21 of the third via GK2 penetrates through the third peripheral insulating layer 2251 and the fourth peripheral insulating layer 2283, and is configured to expose the second transfer electrode ZL1. The second end FML2 of the second detection signal line FML is connected to the second transfer electrode ZL1 through the sub-via GK21 of the third via GK2. For example, the second transfer electrode ZL1 may be arranged on the same layer as one layer of the lead 3001 in the bending area 30, for example, a metal layer on the same layer as the fourth display area metal layer 304, or may be on a different layer from the lead 3001 in the bending area 30 and the second transfer electrode ZL1 is connected to the lead 3001 in the bending area 30 through other sub-vias of the third via GK2. The sub-via GK31 of the fourth via GK3 penetrates through the third peripheral insulating layer 2251 and the fourth peripheral insulating layer 2283, and is configured to expose the third transfer electrode ZL2. The first end FML1 of the second detection signal line FML is connected to the third transfer electrode ZL2 through the sub-via GK31 of the fourth via GK3. For example, the third transfer electrode ZL2 may be arranged on the same layer as one layer of the lead 3001 in the bending area 30, for example, a metal layer on the same layer as the fourth display area metal layer 304, or may be on a different layer from the lead 3001 in the bending area 30 and the third transfer electrode ZL2 is connected to the lead 3001 in the bending area 30 through other sub-vias of the fourth via GK3.

[0119] For example, as Figure 8 shown, take the second transfer electrode ZL1 and the third transfer electrode ZL2 being on the same layer as the fourth display area metal layer 304 as an example.

[0120] It should be noted that in the embodiments of the present disclosure, a metal layer (for example, including the second transfer electrode ZL1 and the third transfer electrode ZL2) on the same layer as the first transfer electrode 241 is provided in the projection area of the first end FML1 and the second end FML2 of the second detection signal line FML on the board surface S of the substrate 100 to improve the connection quality of the second detection signal line FML.

[0121] For example, in some embodiments, as Figure 6 shown, the first end BPL1 of the first detection signal line BPL is connected to the corresponding lead 3001 in the bending area 30. At least one metal layer in the lead 3001 is arranged on the same layer as the fourth display area metal layer 304. For example, when the first detection signal line BPL is arranged on the same layer as the second display area metal layer 302, the first end BPL1 of the first detection signal line BPL is connected to the lead 3001 through a via penetrating through the second peripheral insulating layer 2245, the first peripheral insulating layer 2244, and the peripheral passivation layer 2246.

[0122] For example, in some embodiments, as Figure 6As shown, the display substrate 1 further includes a third detection signal line BPL5. The first end BPL51 and the second end BPL52 of the third detection signal line BPL5 are led out from the bending area 30. For example, the first end BPL51 and the second end BPL52 of the third detection signal line BPL5 are respectively connected to the lead 3001 in the bending area 30. The third detection signal line BPL5 is disposed on the side where the first detection signal line BPL is located in the shift register GOA (such as the second side S2 and the third side S3 of the display area) and the fourth side S4 opposite to the first side S1 of the display area 10, that is, it runs around the display area 10. The third detection signal line BPL5 is not connected to the second detection signal line FML, and it separately detects the PCD signal of the crack in the TFT layer metal of the display substrate. The third detection signal line BPL5 is located on the side of the first end FML1 of the second detection signal line FML away from the second end FML2 of the second detection signal line FML, that is, it is located between the plurality of signal lines CL and the first end FML1 of the second detection signal line FML.

[0123] For example, as Figure 6 shown, the routing layout shape of the third detection signal line BPL5 is substantially the same as that of the first detection signal line BPL. For example, the third detection signal line BPL5 further includes a fifth line segment BPL53 connected to the first end BPL51 and a fifth line segment BPL54 connected to the second end BPL2. The fifth line segment BPL53 and the fifth line segment BPL54 are parallel (such as substantially parallel) to the fourth line segment BPL41 and the fourth line segment BPL42. Thereby, the wiring space is saved.

[0124] For example, as Figure 5 shown, for example, the third detection signal line BPL5 further includes a sixth line segment BPL55 connected to the fifth line segment BPL53 and a sixth line segment BPL56 connected to the fifth line segment BPL54. The sixth line segment BPL55 and the fifth line segment BPL54 are parallel (such as substantially parallel) to the third line segment BPL31 and the third line segment BPL32. The sixth line segment BPL55 and the fifth line segment BPL54 are located between the third line segment BPL32 and the plurality of signal lines CL. Thereby, the wiring space is saved.

[0125] For example, as Figure 6As shown, a bend occurs between the second segment FML42 and the first bent segment FML52 of the second detection signal line FML. The corner C1 at the connection of the second segment FML42 and the first bent segment FML52 is an obtuse angle. For example, the value range of the corner C1 is greater than 90 degrees, for example, the value is approximately 110 degrees. A bend occurs between the second segment FML41 and the first bent segment FML51 of the second detection signal line FML. The corner C2 at the connection of the second segment FML41 and the first bent segment FML51 is an obtuse angle. For example, the value range of the corner C2 is greater than 90 degrees, for example, the value is approximately 110 degrees. A bend occurs between the fourth segment BPL41 and the third segment BPL31 of the first detection signal line BPL. The corner C3 at the connection of the fourth segment BPL41 and the third segment BPL31 is an obtuse angle. For example, the value range of the corner C3 is greater than 90 degrees, for example, the value is approximately 110 degrees. For example, the size of the corner at the connection of the fourth segment BPL42 and the third segment BPL32 of the first detection signal line BPL can be the same as that of the corner C3, which will not be elaborated here in detail. Thus, the wiring space is reduced.

[0126] For example, as Figure 6 shown, the width H1 of the corner C1 formed at the connection of the second segment FML42 and the first bent segment FML52, for example, the value range is 32 - 40 microns, for example, the value is approximately 36 microns. For example, the width H2 of the corner C2 formed at the connection of the second segment FML41 and the first bent segment FML51, for example, the value range is 32 - 40 microns, for example, the value is approximately 36 microns. For example, the value range of the spacing H3 between the corner C1 and the corner C2 is 40 - 60 microns, for example, the value is approximately 50 microns. For example, the value range of the spacing H4 between the second segment FML42 and the second segment FML41 is 15 - 20 microns, for example, the value is approximately 18 microns. Thus, the wiring space is reduced.

[0127] For example, in other embodiments, in the region where the positive projection of the first power supply line VSS on the board surface S of the substrate 100 is located, the second detection signal line FML and the first detection signal line BPL can cross with multiple signal lines CL to reduce the wiring space. The first power supply line VSS can play a role in signal shielding and reduce the interference between each wiring. For example, as Figure 4 shown, for example, the first detection signal line BPL runs parallel to multiple signal lines CL. Outside the region where the positive projection of the first power supply line VSS on the board surface S of the substrate 100 is located, the second detection signal line FML and the first detection signal line BPL can cross multiple signal lines CL.

[0128] For example, as Figure 5As shown, multiple third line segments BPL3 of the first detection signal line BPL are arranged in parallel. The value range of the pitch between multiple third line segments BPL3 in the direction perpendicular to the line arrangement direction is, for example, greater than or equal to 1 micrometer, and for example, the value is about 1 micrometer, so as to reduce interference between signals or avoid the generation of parasitic capacitance.

[0129] For example, as Figure 8 As shown, the display substrate 1 further includes a peripheral barrier layer 2240, a peripheral buffer layer 2241, a first peripheral gate insulating layer 2242, a second peripheral gate insulating layer 2243, and a peripheral protective layer 2284. The peripheral barrier layer 2240 is disposed on the substrate 100 and is in the same layer as the barrier layer 1240. The peripheral buffer layer 2241 is disposed on the side of the peripheral barrier layer 2240 away from the substrate 100 and is in the same layer as the buffer layer 1241. The first peripheral gate insulating layer 2242 is disposed on the side of the peripheral buffer layer 2241 away from the substrate 100 and is in the same layer as the first insulating layer 1242. The second peripheral gate insulating layer 2243 is disposed on the side of the first peripheral gate insulating layer 2242 away from the substrate 100 and is in the same layer as the second insulating layer 1243. The peripheral protective layer 2284 is disposed on the side of the second detection signal line FML away from the substrate 100 and is in the same layer as the protective layer 284. Thus, the manufacturing process is simplified.

[0130] Figure 9 It is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.

[0131] At least one embodiment of the present disclosure further provides a display device. Figure 9 It is a schematic diagram of a display device provided by an embodiment of the present disclosure. As Figure 9 shown, the display device 2 includes the display substrate 1 provided by any embodiment of the present disclosure and a signal input element. For example, the display substrate 1 adopts the display substrate 1 shown in Figure 1 .

[0132] As Figure 9 shown, the portion of the display substrate 1 located in the peripheral area 20 is bent to the back side of the portion DS of the display substrate 1 located in the display area 10. For example, the back side refers to the operation side of the display substrate 1 (or the opposite side where a plurality of sub-pixels P111 are provided). When the substrate 100 adopts a flexible substrate, it is beneficial for the bending operation of the bending area 30 of the display substrate 1. The display device 2 formed by the bending process has a narrow border. For example, the signal input element includes a data driving circuit IC. For example, the data driving circuit IC can be bonded to the bonding area 40 of the display substrate 1. The data driving circuit IC provides a display signal for the display substrate 1 during the display stage, so that the sub-pixels P111 display an image.

[0133] It should be noted that the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc. The display device 2 may further include other components, such as a data driving circuit, a timing controller, etc., and the embodiments of the present disclosure do not limit this.

[0134] It should be noted that, for the sake of clarity and conciseness, the embodiments of the present disclosure do not give all the constituent units of the display device. To implement the substrate function of the display device, those skilled in the art can provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0135] Regarding the technical effects of the display device 2 provided in the above embodiments, reference can be made to the technical effects of the display substrate 1 provided in the embodiments of the present disclosure, which will not be elaborated here.

[0136] The following points need to be noted:

[0137] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0138] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0139] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all of them should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising: A substrate substrate, including a display area and a peripheral area surrounding the display area, wherein the display area includes a pixel array, the pixel array includes a plurality of sub-pixels, the peripheral area includes a bending area located on a first side of the display area, and a shift register located on at least one of a second side and a third side of the display area, and the first side is adjacent to the second side and the third side. A plurality of signal lines, wherein one end of the plurality of signal lines is led out from the bending area, and the other end of the plurality of signal lines is connected to the shift register. A first power supply line, led out from the bending area and routed around the display area. At least one first detection signal line, disposed on at least one of the side where the shift register is located and a fourth side opposite to the first side of the display area, wherein a first end of the at least one first detection signal line is led out from the bending area, and At least one second detection signal line, disposed on at least one of the side where the shift register is located and the fourth side, wherein a first end of the at least one second detection signal line is led out from the bending area. Wherein, on a side close to the bending area outside the area where the positive projection of the first power supply line on the board surface of the substrate substrate is located, the positive projections of the at least one first detection signal line and the plurality of signal lines on the board surface of the substrate substrate do not overlap, and the positive projection of the at least one second detection signal line on the board surface of the substrate substrate does not overlap with the positive projection of the plurality of signal lines on the board surface of the substrate substrate. On the first side of the display area, in the area where the positive projection of the first power supply line on the board surface of the substrate substrate is located, the positive projection of the at least one second detection signal line on the board surface of the substrate substrate overlaps with the positive projection of the plurality of signal lines on the board surface of the substrate substrate.

2. The display substrate according to claim 1, wherein, The area where the positive projection of the at least one second detection signal line on the board surface of the substrate substrate overlaps with the positive projection of the plurality of signal lines on the board surface of the substrate substrate is entirely covered by the area where the positive projection of the first power supply line on the board surface of the substrate substrate is located.

3. The display substrate according to claim 1 or 2, wherein On the first side of the display area, a second end of the at least one first detection signal line is connected in series with a second end of the at least one second detection signal line.

4. The display substrate according to claim 1 or 2, wherein On the first side of the display area and in a direction perpendicular to the board surface of the substrate substrate, at least a part of the film layer where the first power supply line is located is located between the film layer where the at least one second detection signal line is located and the film layer where the plurality of signal lines are located.

5. The display substrate according to claim 1 or 2, wherein On a side close to the bending area outside the area where the positive projection of the first power supply line on the board surface of the substrate substrate is located, the plurality of signal lines are routed in parallel. At least a part of the at least one first detection signal line and at least a part of the at least one second detection signal line are routed in parallel with the plurality of signal lines, and the at least one second detection signal line is located on a side of the at least one first detection signal line away from the plurality of signal lines.

6. The display substrate according to claim 1 or 2, wherein On a first side of the display area, the at least one second detection signal line includes a plurality of first line segments respectively connected to its first end and second end, and the plurality of first line segments extend in a first direction. In a region where a positive projection of the first power supply line on the surface of the substrate is located, a positive projection of the plurality of first line segments on the surface of the substrate and a positive projection of the plurality of signal lines on the surface of the substrate overlap.

7. The display substrate according to claim 6, wherein In a region where a positive projection of the plurality of first line segments on the surface of the substrate overlaps with a positive projection of the plurality of signal lines on the surface of the substrate, a length range in the first direction is 220 micrometers - 260 micrometers.

8. The display substrate according to claim 6, wherein On a side of the first power supply line on the surface of the substrate outside the region where the positive projection is located and close to the bending region, a positive projection of the plurality of first line segments on the surface of the substrate also overlaps with a positive projection of the at least one first detection signal line on the surface of the substrate.

9. The display substrate according to claim 6, wherein The at least one second detection signal line further includes a plurality of second line segments. One of the plurality of first line segments is connected to the first end of the at least one second detection signal line through one of the plurality of second line segments, and another of the plurality of first line segments is connected to the second end of the at least one second detection signal line through another of the plurality of second line segments. The plurality of second line segments are located between the plurality of first line segments and the bending region, and the second line segments are routed in a direction intersecting with the first direction. The at least one first detection signal line includes a plurality of third line segments respectively connected to its first end and second end. A positive projection of the plurality of third line segments on the surface of the substrate overlaps with a positive projection of the plurality of first line segments on the surface of the substrate. The plurality of third line segments and the plurality of second line segments are routed in parallel and arranged side by side. The plurality of third line segments are located on a side of the plurality of second line segments close to the display area and between the plurality of second line segments and the plurality of signal lines.

10. The display substrate according to claim 9, wherein In a direction perpendicular to the routing directions of the plurality of second line segments and the plurality of third line segments, the plurality of second line segments and the plurality of third line segments are routed in parallel with corresponding line segments of the plurality of signal lines.

11. The display substrate according to claim 10, wherein The second line segment connected to the first end of the at least one second detection signal line and the third line segment connected to the first end of the at least one first detection signal line are adjacent, and In a direction perpendicular to the routing directions of the plurality of second line segments and the plurality of third line segments, the value range of the interval width between the adjacent second line segment and the third line segment is 2 micrometers - 3 micrometers.

12. The display substrate according to claim 9, wherein, On a side of the bending region close to the display region, the position where the second ends of the at least one first detection signal line and the second ends of the at least one second detection signal line are connected in series is located between the first end of the at least one second detection signal line and the first end of the at least one first detection signal line, The first end of the at least one first detection signal line is located on a side of the first end of the at least one second detection signal line away from the plurality of signal lines.

13. The display substrate according to claim 9, wherein, The at least one second detection signal line further includes a plurality of first broken line segments arranged in parallel. One of the plurality of first broken line segments is connected to one of the plurality of second line segments and the first end of the at least one second detection signal line, and another one of the plurality of first broken line segments is connected to another one of the plurality of second line segments and the second end of the at least one second detection signal line, The line width of the plurality of first broken line segments is greater than the line width of the plurality of second line segments.

14. The display substrate according to claim 13, wherein, At least some of the plurality of first broken line segments are routed in a second direction different from the first direction.

15. The display substrate according to claim 13, wherein, The at least one first detection signal line further includes a plurality of fourth line segments routed along the first direction, One of the plurality of third line segments is connected to the first end of the at least one first detection signal line through one of the plurality of fourth line segments, and another one of the plurality of third line segments is connected to the second end of the at least one first detection signal line through another one of the plurality of fourth line segments, The orthographic projections of the plurality of fourth line segments on the surface of the substrate substrate respectively overlap with the orthographic projections of at least one of the plurality of first broken line segments on the surface of the substrate substrate.

16. The display substrate according to claim 1 or 2, wherein, The sub-pixel includes a pixel structure, and the pixel structure includes a pixel driving circuit, a first planarization layer, and a light-emitting element, Wherein, the pixel driving circuit includes a first display region metal layer, a second display region metal layer, a third display region metal layer, a first insulating layer, a second insulating layer, an interlayer insulating layer, a first planarization layer, and a pixel defining layer. The first planarization layer provides a first planarized surface on a side of the pixel driving circuit away from the substrate substrate and includes a first via hole. The light-emitting element includes a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode. The first electrode is located on a side of the first planarization layer away from the substrate. The first electrode is electrically connected to the third display region metal layer of the pixel driving circuit through the first via hole. The pixel defining layer is located on a side of the first electrode away from the substrate and defines a light-emitting region of the light-emitting element. The first insulating layer is located on the substrate. The first display region metal layer is located on a side of the first insulating layer away from the substrate. The second insulating layer is located on a side of the first display region metal layer away from the substrate. The second display region metal layer is located on a side of the second insulating layer away from the substrate. The interlayer insulating layer is located between the first planarization layer and the second insulating layer. The third display region metal layer is located on a side of the interlayer insulating layer away from the substrate. The display substrate further includes a packaging layer and a touch control metal layer. The packaging layer is located on a side of the light-emitting element away from the substrate. The touch control metal layer is located on a side of the packaging layer away from the substrate. Wherein, the at least one second detection signal line is disposed at least in the same layer as the touch control metal layer, the at least one first detection signal line is disposed at least in the same layer as the second display region metal layer, and the first power supply line is disposed at least in the same layer as the third display region metal layer.

17. The display substrate according to claim 16, further comprising a second via hole, a first peripheral insulating layer, and a second peripheral insulating layer, wherein, The at least one first detection signal line is located on a side of the first peripheral insulating layer close to the substrate. The second peripheral insulating layer is located on a side of the first peripheral insulating layer away from the substrate. The at least one second detection signal line is located on a side of the second peripheral insulating layer away from the substrate. The first peripheral insulating layer is disposed in the same layer as the interlayer insulating layer. The second peripheral insulating layer is disposed in the same layer as the first planarization layer. The second via hole penetrates at least the first peripheral insulating layer and the second peripheral insulating layer. The second ends of the at least one first detection signal line and the second ends of the at least one second detection signal line are connected in series through the second via hole, and In a direction perpendicular to the plane of the substrate, no insulating layer in the same layer as the pixel defining layer is provided between the second ends of the at least one first detection signal line and the second ends of the at least one second detection signal line.

18. The display substrate according to claim 1 or 2, wherein, On a side of the display substrate where the shift register is located, the at least one first detection signal line and the at least one second detection signal line are located on a side of the shift register away from the display region.

19. A display device includes the display substrate according to any one of claims 1-18.

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