Power modulator and power modulated amplifier
By introducing a combination of switching elements and drive circuits into the power modulator, and using pulse width modulation signals to control the switching state, the problem of excessive power supply quantity in the external power supply circuit is solved, achieving circuit simplification and resource saving.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2020-04-09
- Publication Date
- 2026-05-12
AI Technical Summary
Existing power modulators require an external power supply circuit to provide up to five voltages, resulting in circuit complexity and wasted resources.
By employing a combination of a first switching element, a second switching element, a first driving circuit, and a second driving circuit, the switching elements are controlled to open and close using a pulse width modulation signal, thereby reducing the number of power supplies required by the external power supply circuit.
This allows the external power supply circuit to operate normally with fewer than five power sources, simplifying the circuit structure and reducing resource requirements.
Smart Images
Figure CN115380474B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to power modulators and power modulation amplifiers incorporating power modulators. Background Technology
[0002] Power-modulated amplifiers sometimes include a power modulator that switches the bias voltage of the power amplifier based on the signal level of the high-frequency signal.
[0003] The power modulator disclosed in Non-Patent Document 1 below includes a first transistor, a second transistor, a third transistor, and a fourth transistor.
[0004] A first voltage, which is a positive voltage, is applied to the drain terminal of the first transistor. The source terminal of the first transistor is connected to the output terminal. The drain terminal of the second transistor is connected to both the source terminal and the output terminal of the first transistor. The source terminal of the second transistor is grounded.
[0005] A second voltage, which is positive, is applied to the drain terminal of the third transistor via a resistor. Furthermore, the drain terminal of the third transistor is connected to the gate terminal of the first transistor. A fifth voltage, which is negative, is applied to the source terminal of the third transistor. A fourth voltage, which is positive, is applied to the drain terminal of the fourth transistor via a resistor. Furthermore, the drain terminal of the fourth transistor is connected to the gate terminal of the second transistor. A fifth voltage, which is negative, is applied to the source terminal of the fourth transistor.
[0006] Existing technical documents
[0007] Non-patent literature
[0008] Non-patent literature 1: S.Shinjo, et.al. "High Speed High Analog Bandwidth BuckConverter Using GaN HEMTs for Envelope Tracking Power AmplifierApplications," 2013 IEEE Topical Conference on Wireless Sensors and SensorNetworks Summary of the Invention
[0009] The problem the invention aims to solve
[0010] When driving the power modulator disclosed in Non-Patent Document 1, the following problem exists: the external power supply circuit has 5 power supplies, and the first voltage, second voltage, third voltage, fourth voltage and fifth voltage must be provided to the power modulator respectively.
[0011] This disclosure was made to solve the above-mentioned problems, and its purpose is to provide a power modulator that enables the external power supply circuit to have fewer than 5 power supplies.
[0012] means for solving problems
[0013] The power modulator disclosed herein includes: a first switching element having a first terminal and a second terminal, the first terminal being applied with a first voltage and the second terminal being connected to an output terminal; a second switching element having a third terminal and a fourth terminal, the third terminal being connected to both the output terminal and the second terminal, and the fourth terminal being applied with a second voltage lower than the first voltage; a first drive circuit having a fifth terminal and a sixth terminal, the fifth terminal being applied with the first voltage and the sixth terminal being grounded, the resistance value between the fifth terminal and the sixth terminal varying according to the signal level of a pulse width modulation signal, thereby controlling the opening and closing of the first switching element; and a second drive circuit having a seventh terminal and an eighth terminal, the seventh terminal being grounded and the eighth terminal being applied with a second voltage, the resistance value between the seventh terminal and the eighth terminal varying according to the signal level of an inverted signal of the pulse width modulation signal, thereby controlling the opening and closing of the second switching element.
[0014] The first switching element is the first transistor; terminal 1 is the drain terminal of the first transistor; terminal 2 is the source terminal of the first transistor; the second switching element is the second transistor; terminal 3 is the drain terminal of the second transistor; terminal 4 is the source terminal of the second transistor; the first driving circuit is the third transistor; the gate terminal of the third transistor is supplied with a pulse width modulation signal; terminal 5 is the drain terminal of the third transistor, which is connected to the gate terminal of the first transistor; terminal 6 is the source terminal of the third transistor; the second driving circuit is the fourth transistor; the gate terminal of the fourth transistor is supplied with an inverted pulse width modulation signal; and terminal 7 is the fourth transistor... The source terminal of the transistor is 8, and the drain terminal of the fourth transistor is connected to the gate terminal of the second transistor. The power modulator includes: a first resistor, one end of which is connected to the gate terminal of the first transistor and the drain terminal of the third transistor respectively; a diode, the cathode terminal of which is connected to the other end of the first resistor, and the anode terminal of which is subjected to a third voltage; a capacitor, one end of which is connected to the other end of the first resistor and the cathode terminal of the diode respectively, and the other end of which is connected to the source terminal of the first transistor; and a second resistor, one end of which is connected to the gate terminal of the second transistor and the drain terminal of the fourth transistor respectively, and the other end of which is connected to the source terminal of the second transistor.
[0015] The effects of the invention
[0016] According to this disclosure, the number of power supplies that an external power supply circuit can have is less than 5. Attached Figure Description
[0017] Figure 1 This is a structural diagram showing a power modulation type amplifier equipped with the power modulation 1 of Embodiment 1.
[0018] Figure 2 This is a structural diagram showing the power modulator 1 of Embodiment 1.
[0019] Figure 3 This is a structural diagram showing another power modulator 1 in Embodiment 1.
[0020] Figure 4 This is a structural diagram showing the power modulator 1 of Embodiment 2.
[0021] Figure 5 This is a structural diagram showing the power modulator 1 of embodiment 3.
[0022] Figure 6A This is an explanatory diagram showing a portion of the power modulator 1 when the third transistor 16 is in the off state. Figure 6B This is an explanatory diagram showing a portion of the power modulator 1 during the state transition of the third transistor 16 from the off state to the on state. Figure 6C This is an explanatory diagram showing a portion of the power modulator 1 when the third transistor 16 is in the on state.
[0023] Figure 7 This is an explanatory diagram showing the current-voltage characteristics of a current control circuit including a first resistor 19 and a fifth transistor 23.
[0024] Figure 8 This is a structural diagram showing another power modulator 1 in embodiment 3.
[0025] Figure 9 This is a structural diagram showing the power modulator 1 of embodiment 4.
[0026] Figure 10 This is a structural diagram showing the power modulator 1 of embodiment 5. Detailed Implementation
[0027] The following description, in order to illustrate the present disclosure in more detail, describes the manner in which the present disclosure is carried out with reference to the accompanying drawings.
[0028] Implementation method 1.
[0029] Figure 1 This is a structural diagram showing a power modulation type amplifier equipped with the power modulation 1 of Embodiment 1.
[0030] Figure 1The power modulation amplifier shown includes a power modulator 1, a low-pass filter (hereinafter referred to as "LPF") 2, and a power amplifier 3.
[0031] A first pulse width modulation signal (hereinafter referred to as "PWM signal") related to the high-frequency signal to be amplified is provided to the input terminal 1a from the outside.
[0032] A second PWM signal, which is related to the high-frequency signal being amplified, is provided from the outside to input terminal 1b.
[0033] The first pulse width modulation signal is a high-frequency signal whose duty cycle increases with the amplitude of the signal.
[0034] The second PWM signal is the inverted version of the first pulse width modulation signal.
[0035] The power modulator 1 is a device for switching the bias voltage of the power amplifier 3 according to the signal level of the first PWM signal and the signal level of the second PWM signal, respectively.
[0036] Output terminal 1c is used to output the output voltage of power modulator 1 to LPF2.
[0037] LPF2 generates a bias voltage by removing high-order harmonics and other contaminants from the voltage output from the output terminal 1c of the power modulator 1, and provides the bias voltage to the power amplifier 3.
[0038] Power amplifier 3 uses the bias voltage output from LPF2 to amplify the high-frequency signal that is being amplified.
[0039] Figure 2 This is a structural diagram showing the power modulator 1 of Embodiment 1.
[0040] The power modulator 1 includes a first switching element 11, a second switching element 13, a first driving circuit 15, a second driving circuit 17, a first resistor 19, and a second resistor 20.
[0041] The first switching element 11 has a first terminal and a second terminal.
[0042] A first voltage V1 is applied to the first terminal of the first switching element 11. The second terminal of the first switching element 11 is connected to the output terminal 1c and the third terminal of the second switching element 13, respectively. The first voltage V1 is provided by an external power supply circuit not shown.
[0043] exist Figure 2 In the power modulator 1 shown, the first switching element 11 is implemented by the first transistor 12.
[0044] The first terminal of the first switching element 11 is the drain terminal of the first transistor 12. The second terminal of the first switching element 11 is the source terminal of the first transistor 12.
[0045] A first voltage V1 is applied to the drain terminal of the first transistor 12. The source terminal of the first transistor 12 is connected to the drain terminal of the second transistor 14 (described later) and the output terminal 1c, respectively.
[0046] The gate terminal of the first transistor 12 is connected to the drain terminal of the third transistor 16 (described later) and one end of the first resistor 19, respectively.
[0047] exist Figure 2 In the power modulator 1 shown, the first switching element 11 is implemented by the first transistor 12. However, this is just one example; the first switching element 11 can also be implemented by an on / off switch, for example.
[0048] The second switching element 13 has a third terminal and a fourth terminal.
[0049] The third terminal of the second switching element 13 is connected to the output terminal 1c and the second terminal of the first switching element 11, respectively. A second voltage V2, which is lower than the first voltage V1, is applied to the fourth terminal of the second switching element 13. The second voltage V2 is provided by an external power supply circuit not shown.
[0050] exist Figure 2 In the power modulator 1 shown, the second switching element 13 is implemented by the second transistor 14.
[0051] The third terminal of the second switching element 13 is the drain terminal of the second transistor 14. The fourth terminal of the second switching element 13 is the source terminal of the second transistor 14.
[0052] The drain terminal of the second transistor 14 is connected to the source terminal and the output terminal 1c of the first transistor 12, respectively.
[0053] A second voltage V2 is applied to the source terminal of the second transistor 14.
[0054] The gate terminal of the second transistor 14 is connected to the drain terminal of the fourth transistor 18 (not shown) and one end of the second resistor 20, respectively.
[0055] exist Figure 2 In the power modulator 1 shown, the second switching element 13 is implemented by the second transistor 14. However, this is just one example; the second switching element 13 can also be implemented, for example, by an on / off switch.
[0056] The first drive circuit 15 has a 5th terminal and a 6th terminal.
[0057] A first voltage V1 is applied to the fifth terminal of the first drive circuit 15 via the first resistor 19. The sixth terminal of the first drive circuit 15 is grounded.
[0058] In the first drive circuit 15, the resistance value between the fifth terminal and the sixth terminal changes according to the signal level of the first PWM signal provided to the input terminal 1a, thereby controlling the opening and closing of the first switching element 11.
[0059] Specifically, in the first drive circuit 15, if the signal level of the first PWM signal is H level, the resistance between the fifth terminal and the sixth terminal becomes approximately 0Ω, thereby making the first switching element 11 turn on.
[0060] In the first drive circuit 15, if the signal level of the first PWM signal is L level, the resistance value between the 5th terminal and the 6th terminal becomes such that the current hardly flows between the 5th terminal and the 6th terminal, thereby causing the first switching element 11 to be in the closed state.
[0061] exist Figure 2 In the power modulator 1 shown, the first drive circuit 15 is implemented by the third transistor 16.
[0062] The fifth terminal of the first driving circuit 15 is the drain terminal of the third transistor 16. The sixth terminal of the first driving circuit 15 is the source terminal of the third transistor 16.
[0063] The drain terminal of the third transistor 16 is connected to the gate terminal of the first transistor 12 and one end of the first resistor 19, respectively.
[0064] The source terminal of transistor 16 is grounded.
[0065] The gate terminal of the third transistor 16 is connected to the input terminal 1a.
[0066] exist Figure 2 In the power modulator 1 shown, the first drive circuit 15 is implemented by the third transistor 16. However, this is just one example; the first drive circuit 15 can also be implemented, for example, by an on / off switch.
[0067] In addition, Figure 2 In the power modulator 1 shown, the first drive circuit 15 is implemented by the third transistor 16. However, this is just one example, and the first drive circuit 15 may also include the third transistor 16 and the first resistor 19.
[0068] The second drive circuit 17 has a 7th terminal and an 8th terminal.
[0069] Terminal 7 of the second drive circuit 17 is grounded. A second voltage V2 is applied to terminal 8 of the second drive circuit 17 via the second resistor 20.
[0070] In the second drive circuit 17, the resistance value between the 7th terminal and the 8th terminal changes according to the signal level of the second PWM signal provided to the input terminal 1b, thereby controlling the opening and closing of the second switching element 13.
[0071] Specifically, in the second drive circuit 17, if the signal level of the second PWM signal is H level, the resistance between the 7th terminal and the 8th terminal becomes approximately 0Ω, thereby making the second switching element 13 open.
[0072] In the second drive circuit 17, if the signal level of the second PWM signal is L level, the resistance value between the 7th terminal and the 8th terminal becomes such that the current hardly flows between the 7th terminal and the 8th terminal, thereby causing the second switching element 13 to be in the closed state.
[0073] exist Figure 2 In the power modulator 1 shown, the second drive circuit 17 is implemented by the fourth transistor 18.
[0074] Terminal 7 of the second drive circuit 17 is the source terminal of the fourth transistor 18. Terminal 8 of the second drive circuit 17 is the drain terminal of the fourth transistor 18.
[0075] The source terminal of transistor 418 is grounded.
[0076] The drain terminal of the fourth transistor 18 is connected to the gate terminal of the second transistor 14 and one end of the second resistor 20, respectively.
[0077] The gate terminal of the fourth transistor 18 is connected to the input terminal 1b.
[0078] exist Figure 2 In the power modulator 1 shown, the second drive circuit 17 is implemented by the fourth transistor 18. However, this is just one example; the second drive circuit 17 can also be implemented, for example, by an on / off switch.
[0079] In addition, Figure 2 In the power modulator 1 shown, the second drive circuit 17 is implemented by the fourth transistor 18. However, this is just one example, and the second drive circuit 17 may also include the fourth transistor 18 and the second resistor 20.
[0080] Next, regarding Figure 1 The operation of the power supply modulation amplifier shown will be explained.
[0081] When the power modulator 1 is supplied with the first PWM signal and the second PWM signal, it switches the voltage output from the output terminal 1c to the LPF2 according to the signal level of the first PWM signal and the signal level of the second PWM signal.
[0082] For example, if the signal level of the first PWM signal is H level and the signal level of the second PWM signal is L level, then the power modulator 1 outputs the second voltage V2 from the output terminal 1c to the LPF2.
[0083] For example, if the signal level of the first PWM signal is L level and the signal level of the second PWM signal is H level, then the power modulator 1 outputs the first voltage V1 from the output terminal 1c to the LPF2.
[0084] The operation of power modulator 1 will be explained in detail below.
[0085] The first PWM signal is provided to the gate terminal of the third transistor 16, and the second PWM signal is provided to the gate terminal of the fourth transistor 18.
[0086] If the signal level of the first PWM signal is H level, then the signal level of the second PWM signal is L level; if the signal level of the first PWM signal is L level, then the signal level of the second PWM signal is H level.
[0087] If the signal level of the first PWM signal is H level, then the voltage applied to the gate terminal of the third transistor 16 is higher than the threshold voltage of the third transistor 16. Therefore, the third transistor 16 becomes on. The on state of the third transistor 16 is when the resistance between the drain terminal and the source terminal of the third transistor 16 is approximately 0Ω.
[0088] When the third transistor 16 is in the ON state, the voltage applied to the gate terminal of the first transistor 12 is approximately ground potential. Therefore, the gate voltage of the first transistor 12 is lower than the threshold voltage of the first transistor 12, and thus, the first transistor 12 is in the OFF state (ON state).
[0089] If the signal level of the second PWM signal is low, the voltage applied to the gate terminal of the fourth transistor 18 is lower than the threshold voltage of the fourth transistor 18. Therefore, the fourth transistor 18 becomes off. The off state in the fourth transistor 18 is a state in which the resistance between the drain terminal and the source terminal of the fourth transistor 18 becomes such that current hardly flows from the drain terminal to the source terminal.
[0090] When the fourth transistor 18 is in the off state, a second voltage V2 is applied to the gate terminal of the second transistor 14 through the second resistor 20. Therefore, the gate voltage of the second transistor 14 is higher than the threshold voltage of the second transistor 14, and thus the second transistor 14 is in the on state (off state).
[0091] If the first transistor 12 is in the off state and the second transistor 14 is in the on state, then the second voltage V2 is output from the output terminal 1c to LPF2.
[0092] Next, if the signal level of the first PWM signal is L level, the voltage applied to the gate terminal of the third transistor 16 is lower than the threshold voltage of the third transistor 16. Therefore, the third transistor 16 becomes off. The off state in the third transistor 16 is a state in which the resistance between the drain terminal and the source terminal of the third transistor 16 is such that current hardly flows from the drain terminal to the source terminal.
[0093] When the third transistor 16 is in the off state, a first voltage V1 is applied to the gate terminal of the first transistor 12 through the first resistor 19. Therefore, the gate voltage of the first transistor 12 is higher than the threshold voltage of the first transistor 12, and thus the first transistor 12 is in the on state (off state).
[0094] If the signal level of the second PWM signal is H level, then the voltage applied to the gate terminal of the fourth transistor 18 is higher than the threshold voltage of the fourth transistor 18. Therefore, the fourth transistor 18 becomes on. The on state of the fourth transistor 18 is when the resistance between the drain and source terminals of the fourth transistor 18 is approximately 0Ω.
[0095] When the fourth transistor 18 is in the ON state, the voltage applied to the gate terminal of the second transistor 14 is approximately ground potential. Therefore, the gate voltage of the second transistor 14 is lower than the threshold voltage of the second transistor 14, and thus, the second transistor 14 is in the OFF state (ON state).
[0096] If the first transistor 12 is in the on state and the second transistor 14 is in the off state, then the first voltage V1 is output from the output terminal 1c to LPF2.
[0097] By varying the signal levels of the first PWM signal and the second PWM signal, the first voltage V1 or the second voltage V2 is output from the output terminal 1c to LPF2.
[0098] LPF2 generates a bias voltage by removing high-order harmonics from the voltage output from the output terminal 1c of the power modulator 1, i.e., the first voltage V1 or the second voltage V2, and provides the bias voltage to the power amplifier 3.
[0099] Power amplifier 3 uses the bias voltage output from LPF2 to amplify the high-frequency signal of the amplified object and output the amplified high-frequency signal to the outside.
[0100] In Embodiment 1 described above, the power modulator 1 includes: a first switching element 11 having a first terminal and a second terminal, the first terminal being supplied with a first voltage and the second terminal being connected to an output terminal; and a second switching element 13 having a third terminal and a fourth terminal, the third terminal being connected to both the output terminal and the second terminal, and the fourth terminal being supplied with a second voltage lower than the first voltage. Furthermore, the power modulator 1 includes: a first drive circuit 15 having a fifth terminal and a sixth terminal, the fifth terminal being supplied with a first voltage and the sixth terminal being grounded, the resistance between the fifth and sixth terminals varying according to the signal level of the pulse width modulation signal, thereby controlling the opening and closing of the first switching element 11; and a second drive circuit 17 having a seventh terminal and an eighth terminal, the seventh terminal being grounded and the eighth terminal being supplied with a second voltage, the resistance between the seventh and eighth terminals varying according to the signal level of the inverted signal of the pulse width modulation signal, thereby controlling the opening and closing of the second switching element 13.
[0101] Therefore, the power modulator 1 enables the external power circuit to have fewer than 5 power sources.
[0102] exist Figure 2 In the power modulator 1 shown, the drain terminal of the third transistor 16 is connected to the drain terminal of the first transistor 12 via the first resistor 19. However, this is just one example, as... Figure 3 As shown, the drain terminal of the third transistor 16 can also be connected to the source terminal of the first transistor 12 via the first resistor 19.
[0103] exist Figure 3 The power modulator 1 shown also has Figure 2 Similarly, in the power modulator 1 shown, when the third transistor 16 is in the on state, the first transistor 12 and the fourth transistor 18 are in the off state, and the second transistor 14 is in the on state.
[0104] Furthermore, when the third transistor 16 is in the off state, the first transistor 12 and the fourth transistor 18 are in the on state, and the second transistor 14 is in the off state.
[0105] Figure 3 This is a structural diagram showing another power modulator 1 in Embodiment 1.
[0106] but, Figure 3 The timing of the first transistor 12 of the power modulator 1 changing from the off state to the on state. Figure 2The timing of the first transistor 12 of the power modulator 1 changing from the off state to the on state is different.
[0107] That is, when the third transistor 16 is in the off state, Figure 2 The first transistor 12 of the power modulator 1 shown is turned on.
[0108] Figure 3 The first transistor 12 of the power modulator 1 shown is in the on state during the timing changes shown below.
[0109] First, when transistor 12 is in the off state, transistor 14 is in the on state, and transistor 16 is in the on state, a second voltage V2 is applied to resistor 19. When transistor 14 changes to the off state and transistor 16 changes to the off state, the voltage applied to resistor 19 decreases towards 0V. During the decrease of the voltage applied to resistor 19, when the drain voltage and source voltage of transistor 12 become equal, transistor 12 becomes on.
[0110] Implementation method 2.
[0111] In Embodiment 2, a power modulator 1 having a diode 21 and a capacitor 22 will be described.
[0112] Figure 4 This is a structural diagram showing the power modulator 1 according to Embodiment 2. Figure 4 In, with Figure 2 and Figure 3 The same labels indicate the same or equivalent parts, so the description is omitted.
[0113] A third voltage V3 is applied to the anode terminal of diode 21. The third voltage V3 is provided by an external power supply circuit not shown in the figure.
[0114] The cathode terminal of diode 21 is connected to the other end of the first resistor 19 and one end of capacitor 22, respectively.
[0115] One end of capacitor 22 is connected to the other end of first resistor 19 and the cathode terminal of diode 21, respectively.
[0116] The other end of capacitor 22 is connected to the source terminal of the first transistor 12, the drain terminal of the second transistor 14, and the output terminal 1c, respectively.
[0117] Next, regarding Figure 4 The operation of the power modulator 1 shown will be explained.
[0118] Besides diode 21 and capacitor 22, with Figure 3The power modulator 1 shown is the same, therefore, only the operation of diode 21 and capacitor 22 will be described here.
[0119] Since a third voltage V3 is applied to the anode terminal of diode 21, when transistor 12 is in the off state and transistor 14 is in the on state, current flows through diode 21 and capacitor 22 to transistor 14. At this time, capacitor 22 is charged.
[0120] Subsequently, when the second transistor 14 changes to the off state, the charge in the capacitor 22 is discharged, charging the gate capacitance of the first transistor 12. By charging the gate capacitance of the first transistor 12, the voltage required for the first transistor 12 to change from the off state to the on state can be suppressed to a lower level.
[0121] Right now, Figure 4 The first transistor 12 shown is... Figure 3 Compared to the first transistor 12 shown, it changes from the off state to the on state even when the gate voltage is low. Therefore, Figure 4 The power modulator 1 shown is Figure 3 Compared to the power modulator 1 shown, it consumes less power.
[0122] Implementation method 3.
[0123] In Embodiment 3, a power modulator 1 having a fifth transistor 23 and a sixth transistor 24 will be described.
[0124] Figure 5 This is a structural diagram showing the power modulator 1 of Embodiment 3. Figure 5 In, with Figure 2 The same labels indicate the same or equivalent parts, so the description is omitted.
[0125] The source terminal of the fifth transistor 23 is connected to the other end of the first resistor 19.
[0126] The drain terminal of transistor 5 23 is connected to the drain terminal of transistor 1 12.
[0127] The gate terminal of the fifth transistor 23 is connected to one end of the first resistor 19, the drain terminal of the third transistor 16, and the gate terminal of the first transistor 12, respectively.
[0128] The source terminal of the sixth transistor 24 is connected to the other end of the second resistor 20.
[0129] The drain terminal of transistor 6 24 is connected to the source terminal of transistor 2 14.
[0130] The gate terminal of the sixth transistor 24 is connected to one end of the second resistor 20, the drain terminal of the fourth transistor 18, and the gate terminal of the second transistor 14, respectively.
[0131] Next, regarding Figure 5 The operation of the power modulator 1 shown will be explained.
[0132] Apart from transistors 5 (23) and 6 (24), with Figure 2 The power modulator 1 shown is the same, therefore, only the operation of the 5th transistor 23 and the 6th transistor 24 will be described here.
[0133] Transistor 23 (5th transistor) and transistor 24 (6th transistor) are normally on transistors.
[0134] In transistors 5 (23) and 6 (24), the resistance between the drain and source terminals varies depending on the voltage applied between them. Therefore, in Figure 5 In the power modulator 1 shown, with Figure 2 Compared to the power modulator 1 shown, the time required for the switching states of the first transistor 12 and the second transistor 14 to change is shorter.
[0135] Figure 6A This is an explanatory diagram showing a portion of the power modulator 1 when the third transistor 16 is in the off state.
[0136] Figure 6B This is an explanatory diagram showing a portion of the power modulator 1 during the state transition of the third transistor 16 from the off state to the on state.
[0137] Figure 6C This is an explanatory diagram showing a portion of the power modulator 1 when the third transistor 16 is in the on state.
[0138] exist Figure 6A In the diagram, the third transistor 16, which is in the off state, is represented as a switch in the on state. Figure 6B In the diagram, the third transistor 16 during the state transition is represented as a resistor. Figure 6C In the diagram, the third transistor 16, which is in the on state, is represented as a switch in the off state.
[0139] Figure 7 This is an explanatory diagram showing the current-voltage characteristics of a current control circuit including a first resistor 19 and a fifth transistor 23.
[0140] exist Figure 7 In the diagram, (a) shows that the third transistor 16 is in the off state. Figure 6A (a) shows the current and voltage when transistor 3 16 is in a state transition. Figure 6B(c) shows the current and voltage when transistor 3 16 is in the on state. Figure 6C The current and voltage at that time.
[0141] When the third transistor 16 is in the off state, the current and voltage of the current control circuit become Figure 7 As shown in (a), almost no current flows to the first resistor 19 and the fifth transistor 23.
[0142] When the third transistor 16 undergoes a state transition, the current voltage of the current control circuit becomes... Figure 7 As shown in (b), the current flowing to the first resistor 19 and the fifth transistor 23 increases with the increase of voltage.
[0143] When the third transistor 16 is in the on state, the current voltage of the current control circuit becomes Figure 7 As shown in (c), the current flowing to the first resistor 19 and the fifth transistor 23 becomes saturated.
[0144] Therefore, when the third transistor 16 changes from the off state to the on state, the resistance value of the current control circuit, which includes the first resistor 19 and the fifth transistor 23, changes from a smaller value to a larger value.
[0145] On the other hand, when the third transistor 16 changes from the on state to the off state, the resistance value of the current control circuit, which includes the first resistor 19 and the fifth transistor 23, changes from a larger value to a smaller value.
[0146] When the resistance value of the current control circuit changes from a large value to a small value, the current flowing to the gate terminal of the first transistor 12 increases, and therefore, the change from the off state to the on state in the first transistor 12 becomes faster.
[0147] When the resistance value of the current control circuit changes from a small value to a large value, the current flowing to the gate terminal of the first transistor 12 decreases, and therefore, the change from the on state to the off state in the first transistor 12 becomes faster.
[0148] Figure 7 The current-voltage characteristics of the current control circuit including the first resistor 19 and the fifth transistor 23 are shown. The current-voltage characteristics of the current control circuit including the second resistor 20 and the sixth transistor 24 are the same as those of the current control circuit including the first resistor 19 and the fifth transistor 23.
[0149] Therefore, when the fourth transistor 18 changes from the off state to the on state, the resistance value of the current control circuit, which includes the second resistor 20 and the sixth transistor 24, changes from a smaller value to a larger value.
[0150] On the other hand, when the fourth transistor 18 changes from the on state to the off state, the resistance value of the current control circuit, which includes the second resistor 20 and the sixth transistor 24, changes from a larger value to a smaller value.
[0151] When the resistance value of the current control circuit, which includes the second resistor 20 and the sixth transistor 24, changes from a large value to a small value, the current flowing to the gate terminal of the second transistor 14 increases, and therefore, the change from the off state to the on state in the second transistor 14 becomes faster.
[0152] When the resistance value of the current control circuit changes from a small value to a large value, the current flowing to the gate terminal of the second transistor 14 decreases, and therefore, the change from the on state to the off state in the second transistor 14 becomes faster.
[0153] Based on the above, Figure 5 In the power modulator 1 shown, with Figure 2 Compared to the power modulator 1 shown, the time required for the switching states of the first transistor 12 and the second transistor 14 to change is shorter.
[0154] exist Figure 5 In the power modulator 1 shown, the drain terminal of the fifth transistor 23 is connected to the drain terminal of the first transistor 12. However, this is just one example, as... Figure 8 As shown, the drain terminal of the fifth transistor 23 can also be connected to the source terminal of the first transistor 12.
[0155] exist Figure 8 In the power modulator 1 shown, it is also related to Figure 5 Similarly, in the power modulator 1 shown, when the third transistor 16 is in the on state, the first transistor 12 and the fourth transistor 18 are in the off state, and the second transistor 14 is in the on state.
[0156] Furthermore, when the third transistor 16 is in the off state, the first transistor 12 and the fourth transistor 18 are in the on state, and the second transistor 14 is in the off state.
[0157] Figure 8 This is a structural diagram showing another power modulator 1 in embodiment 3.
[0158] Implementation method 4.
[0159] exist Figure 8 In the power modulator 1 shown, the drain terminal of the third transistor 16 and one end of the first resistor 19 are respectively connected to the gate terminal of the first transistor 12.
[0160] In Embodiment 4, a power modulator 1 will be described with the source terminal of the fifth transistor 23 and the other end of the first resistor 19 connected to the gate terminal of the first transistor 12, respectively.
[0161] Figure 9 This is a structural diagram showing the power modulator 1 of embodiment 4.
[0162] exist Figure 8 In the power modulator 1 shown, the resistance from the source terminal of the first transistor 12 to the gate terminal of the first transistor 12 is the on-resistance of the fifth transistor 23 and the first resistor 19.
[0163] exist Figure 9 In the power modulator 1 shown, the resistance from the source terminal of the first transistor 12 to the gate terminal of the first transistor 12 is only the on-resistance of the fifth transistor 23.
[0164] Therefore, in Figure 9 In the power modulator 1 shown, with Figure 8 Compared to the power modulator 1 shown, the change in resistance from the source terminal of the first transistor 12 to the gate terminal of the first transistor 12 is larger, therefore, the time required for the first transistor 12 to change its on / off state is shorter.
[0165] Implementation method 5.
[0166] In embodiment 5, a power modulator 1 having a diode 25 and a capacitor 26 will be described.
[0167] Figure 10 This is a structural diagram showing the power modulator 1 of Embodiment 5. Figure 10 In, with Figure 2 and Figure 9 The same labels indicate the same or equivalent parts, so the description is omitted.
[0168] A third voltage V3 is applied to the anode terminal of diode 25.
[0169] The cathode terminal of diode 25 is connected to the drain terminal of transistor 5 and one end of capacitor 26, respectively.
[0170] One end of capacitor 26 is connected to the drain terminal of transistor 5 and the cathode terminal of diode 25, respectively.
[0171] The other end of capacitor 26 is connected to the source terminal of the first transistor 12, the drain terminal of the second transistor 14, and the output terminal 1c, respectively.
[0172] Next, regarding Figure 5 The operation of the power modulator 1 shown will be explained.
[0173] Besides diode 25 and capacitor 26, with Figure 9 The power modulator 1 shown is the same, therefore, only the operation of diode 25 and capacitor 26 will be described here.
[0174] Because a third voltage V3 is applied to the anode terminal of diode 25, when transistor 12 is off and transistor 14 is on, current flows through diode 25 and capacitor 26 to transistor 14. At this time, capacitor 26 is charged.
[0175] Subsequently, when the second transistor 14 changes to the off state, the charge in the capacitor 26 is discharged, charging the gate capacitance of the first transistor 12. By charging the gate capacitance of the first transistor 12, the voltage required for the first transistor 12 to change from the off state to the on state can be suppressed to a lower level.
[0176] Right now, Figure 10 The first transistor 12 shown is... Figure 9 Compared to the first transistor 12 shown, it changes from the off state to the on state even when the gate voltage is low. Therefore, Figure 10 The power modulator 1 shown is Figure 9 Compared to the power modulator 1 shown, it consumes less power.
[0177] Furthermore, this disclosure allows for free combination of various embodiments or modification of any structural elements of various embodiments, or allows for the omission of any structural elements in various embodiments.
[0178] Industrial utilization
[0179] This disclosure is applicable to power modulators.
[0180] This disclosure is applicable to power-modulated amplifiers with a power modulator.
[0181] Explanation of reference numerals in the attached figures
[0182] 1. Power modulator, 1a, 1b input terminals, 1c output terminal, 2. LPF, 3. Power amplifier, 11. First switching element, 12. First transistor, 13. Second switching element, 14. Second transistor, 15. First drive circuit, 16. Third transistor, 17. Second drive circuit, 18. Fourth transistor, 19. First resistor, 20. Second resistor, 21. Diode, 22. Capacitor, 23. Fifth transistor, 24. Sixth transistor, 25. Diode, 26. Capacitor.
Claims
1. A power modulator, wherein, The power modulator includes: A first switching element has a first terminal and a second terminal, wherein a first voltage is applied to the first terminal and the second terminal is connected to an output terminal; The second switching element has a third terminal and a fourth terminal, the third terminal being connected to the output terminal and the second terminal respectively, and the fourth terminal being subjected to a second voltage that is lower than the first voltage; The first driving circuit has a fifth terminal and a sixth terminal, wherein the fifth terminal is subjected to the first voltage, the sixth terminal is grounded, and the resistance value between the fifth terminal and the sixth terminal varies according to the signal level of the pulse width modulation signal, thereby controlling the opening and closing of the first switching element. as well as The second driving circuit has a 7th terminal and an 8th terminal, the 7th terminal being grounded, the 8th terminal being supplied with the second voltage, and the resistance between the 7th and 8th terminals varying according to the signal level of the inverted signal of the pulse width modulation signal, thereby controlling the opening and closing of the second switching element. The first switching element is the first transistor. The first terminal is the drain terminal of the first transistor, and the second terminal is the source terminal of the first transistor. The second switching element is a second transistor. The third terminal is the drain terminal of the second transistor, and the fourth terminal is the source terminal of the second transistor. The first driving circuit is the third transistor. The pulse width modulation signal is provided at the gate terminal of the third transistor. The fifth terminal is the drain terminal of the third transistor, and the drain terminal of the third transistor is connected to the gate terminal of the first transistor. The sixth terminal is the source terminal of the third transistor. The second driving circuit is the fourth transistor. The gate terminal of the fourth transistor is provided with the inverted signal of the pulse width modulation signal. The 7th terminal is the source terminal of the 4th transistor. The eighth terminal is the drain terminal of the fourth transistor, and the drain terminal of the fourth transistor is connected to the gate terminal of the second transistor. The power modulator includes: The first resistor has one end connected to the gate terminal of the first transistor and the drain terminal of the third transistor, respectively. A diode, wherein the cathode terminal is connected to the other end of the first resistor, and a third voltage is applied to the anode terminal; A capacitor, one end of which is connected to the other end of the first resistor and the cathode terminal of the diode, and the other end of which is connected to the source terminal of the first transistor; and The second resistor has one end connected to the gate terminal of the second transistor and the drain terminal of the fourth transistor, and the other end connected to the source terminal of the second transistor.
2. A power modulator, wherein, The power modulator includes: A first switching element has a first terminal and a second terminal, wherein a first voltage is applied to the first terminal and the second terminal is connected to an output terminal; The second switching element has a third terminal and a fourth terminal, the third terminal being connected to the output terminal and the second terminal respectively, and the fourth terminal being subjected to a second voltage that is lower than the first voltage; The first driving circuit has a fifth terminal and a sixth terminal, wherein the fifth terminal is subjected to the first voltage, the sixth terminal is grounded, and the resistance value between the fifth terminal and the sixth terminal varies according to the signal level of the pulse width modulation signal, thereby controlling the opening and closing of the first switching element. as well as The second driving circuit has a 7th terminal and an 8th terminal, the 7th terminal being grounded, the 8th terminal being supplied with the second voltage, and the resistance between the 7th and 8th terminals varying according to the signal level of the inverted signal of the pulse width modulation signal, thereby controlling the opening and closing of the second switching element. The first switching element is the first transistor. The first terminal is the drain terminal of the first transistor, and the second terminal is the source terminal of the first transistor. The second switching element is a second transistor. The third terminal is the drain terminal of the second transistor, and the fourth terminal is the source terminal of the second transistor. The first driving circuit is the third transistor. The pulse width modulation signal is provided at the gate terminal of the third transistor. The fifth terminal is the drain terminal of the third transistor. The sixth terminal is the source terminal of the third transistor. The second driving circuit is the fourth transistor. The gate terminal of the fourth transistor is provided with the inverted signal of the pulse width modulation signal. The 7th terminal is the source terminal of the 4th transistor. The eighth terminal is the drain terminal of the fourth transistor, and the drain terminal of the fourth transistor is connected to the gate terminal of the second transistor. The power modulator includes: The first resistor has one end connected to the drain terminal of the third transistor and the other end connected to the gate terminal of the first transistor. The fifth transistor has its source terminal connected to the other end of the first resistor and the gate terminal of the first transistor, its drain terminal connected to the source terminal of the first transistor, and its gate terminal connected to one end of the first resistor. The second resistor has one end connected to the gate terminal of the second transistor and the drain terminal of the fourth transistor, respectively; and The sixth transistor has its source terminal connected to the other end of the second resistor, its drain terminal connected to the source terminal of the second transistor, and its gate terminal connected to one end of the second resistor.
3. A power modulator, wherein, The power modulator includes: A first switching element has a first terminal and a second terminal, wherein a first voltage is applied to the first terminal and the second terminal is connected to an output terminal; The second switching element has a third terminal and a fourth terminal, the third terminal being connected to the output terminal and the second terminal respectively, and the fourth terminal being subjected to a second voltage that is lower than the first voltage; The first driving circuit has a fifth terminal and a sixth terminal, wherein the fifth terminal is subjected to the first voltage, the sixth terminal is grounded, and the resistance value between the fifth terminal and the sixth terminal varies according to the signal level of the pulse width modulation signal, thereby controlling the opening and closing of the first switching element. as well as The second driving circuit has a 7th terminal and an 8th terminal, the 7th terminal being grounded, the 8th terminal being supplied with the second voltage, and the resistance between the 7th and 8th terminals varying according to the signal level of the inverted signal of the pulse width modulation signal, thereby controlling the opening and closing of the second switching element. The first switching element is the first transistor. The first terminal is the drain terminal of the first transistor, and the second terminal is the source terminal of the first transistor. The second switching element is a second transistor. The third terminal is the drain terminal of the second transistor, and the fourth terminal is the source terminal of the second transistor. The first driving circuit is the third transistor. The pulse width modulation signal is provided at the gate terminal of the third transistor. The fifth terminal is the drain terminal of the third transistor, and the drain terminal of the third transistor is connected to the gate terminal of the first transistor. The sixth terminal is the source terminal of the third transistor. The second driving circuit is the fourth transistor. The gate terminal of the fourth transistor is provided with the inverted signal of the pulse width modulation signal. The 7th terminal is the source terminal of the 4th transistor. The eighth terminal is the drain terminal of the fourth transistor, and the drain terminal of the fourth transistor is connected to the gate terminal of the second transistor. The power modulator includes: The first resistor has one end connected to the drain terminal of the third transistor and the gate terminal of the first transistor, respectively. The fifth transistor has its source terminal connected to the other end of the first resistor and its gate terminal connected to one end of the first resistor; A diode, the cathode terminal of which is connected to the drain terminal of the fifth transistor, and the anode terminal is subjected to a third voltage; A capacitor, one end of which is connected to the drain terminal of the fifth transistor and the cathode terminal of the diode, and the other end of which is connected to the source terminal of the first transistor; The second resistor has one end connected to the gate terminal of the second transistor and the drain terminal of the fourth transistor, respectively; and The sixth transistor has its source terminal connected to the other end of the second resistor, its drain terminal connected to the source terminal of the second transistor, and its gate terminal connected to one end of the second resistor.
4. A power supply modulation amplifier, wherein, The power-modulated amplifier includes: The power modulator according to any one of claims 1 to 3; A power amplifier that amplifies the high-frequency signal associated with the pulse-width modulation signal; and A low-pass filter generates a bias voltage supplied to the power amplifier based on the voltage output from the output terminal of the power modulator.