Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. The array substrate comprises a base substrate, a scan routing layer, and a common electrode layer. The scan routing layer is disposed on the base substrate and includes vertical scan lines. The common electrode layer is disposed on a side of the scan routing layer away from the base substrate and includes a common electrode and horizontal scan lines. The horizontal scan lines are spaced apart from the common electrodes and are electrically connected to the vertical scan lines. The orthographic projection of the common electrode on the base substrate at least partially overlaps the orthographic projection of the vertical scan lines on the base substrate. The array substrate provided by this application can reduce parasitic capacitance between the vertical scan lines and the pixel electrodes, thereby improving display quality.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] As panel products increasingly move toward narrow bezels and higher resolutions, the application of ultra-narrow bezels (less than 5.5mm) and ultra-narrow bezels (less than 1mm)—such as ultra-high-definition LCDs—is injecting new vitality into the panel industry. By utilizing a chip-on-film packaging design for the gate driver, the drive signals for the scan and data lines are aligned on the same side, reducing the width of the left and right sides of the LCD and achieving an ultra-narrow bezel.

[0003] In the design of a gate driver using a chip-on-film packaging method, since there are traces perpendicular to the scan lines within the pixels, and parasitic capacitance exists between the traces perpendicular to the scan lines and the pixels, the parasitic capacitance between the traces perpendicular to the scan lines and the pixels has a coupling effect on the pixels, causing crosstalk in the display panel and affecting the product quality of the display panel.

[0004] Therefore, how to reduce the parasitic capacitance between the scanning lines in the vertical direction and the pixels is an urgent problem to be solved in this field. Summary of the Invention

[0005] The present application provides an array substrate and a display panel, which can reduce the parasitic capacitance between vertical scanning lines and pixel electrodes and improve the display effect.

[0006] On the one hand, an embodiment of the present application provides an array substrate, comprising: a base substrate, a scanning wiring layer and a common electrode layer; the scanning wiring layer is arranged on the base substrate, and the scanning wiring layer includes vertical scanning lines; the common electrode layer is arranged on a side of the scanning wiring layer away from the base substrate, and the common electrode layer includes a common electrode and a horizontal scanning line, the horizontal scanning line is arranged at intervals from the common electrode, and the horizontal scanning line is electrically connected to the vertical scanning line; wherein the orthographic projection of the common electrode on the base substrate at least partially covers the orthographic projection of the vertical scanning line on the base substrate.

[0007] Optionally, in some embodiments of the present application, the array substrate further includes a data wiring layer, the data wiring layer is provided on a side of the common electrode layer away from the base substrate, and the data wiring layer includes data signal lines.

[0008] Optionally, in some embodiments of the present application, the array substrate further includes a pixel electrode layer, which is arranged on a side of the data wiring layer away from the base substrate, and the pixel electrode layer includes a pixel electrode, the orthographic projection of the pixel electrode on the base substrate covers the orthographic projection of the data signal line on the base substrate, and the orthographic projection of the pixel electrode on the base substrate at least partially covers the orthographic projection of the common electrode on the base substrate.

[0009] Optionally, in some embodiments of the present application, the vertical scan line is provided between two adjacent pixel electrodes.

[0010] Optionally, in some embodiments of the present application, the orthographic projection of the data signal line on the base substrate is located on a center line of the orthographic projection of the pixel electrode on the base substrate.

[0011] Optionally, in some embodiments of the present application, the orthographic projection of the common electrode on the base substrate covers the orthographic projection of the vertical scan line on the base substrate.

[0012] Optionally, in some embodiments of the present application, the common electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode and the second sub-electrode are arranged at intervals, the first sub-electrode at least partially overlaps with the pixel electrode, and the first sub-electrode partially overlaps with the vertical scan line; the second sub-electrode is arranged between two adjacent pixel electrodes, and the second sub-electrode partially overlaps with the vertical scan line.

[0013] Optionally, in some embodiments of the present application, the number of the vertical scan lines is equal to the number of the data signal lines.

[0014] Optionally, in some embodiments of the present application, the array substrate further includes a first insulating layer, a second insulating layer and a third insulating layer, the first insulating layer is arranged between the scanning wiring layer and the common electrode layer, the second insulating layer is arranged between the common electrode layer and the data wiring layer, and the third insulating layer is arranged between the data wiring layer and the pixel electrode layer.

[0015] On the other hand, the present application provides a display panel including the above-mentioned array substrate.

[0016] The present application provides an array substrate and a display panel, the array substrate comprising: a base substrate, a scan routing layer, and a common electrode layer; the scan routing layer being disposed on the base substrate and comprising vertical scan lines; the common electrode layer being disposed on a side of the scan routing layer away from the base substrate and comprising a common electrode and horizontal scan lines, the horizontal scan lines being spaced apart from the common electrodes and electrically connected to the vertical scan lines; wherein the orthographic projection of the common electrode on the base substrate at least partially covers the orthographic projection of the vertical scan lines on the base substrate. The array substrate provided by the present application can reduce the parasitic capacitance between the vertical scan lines and the pixel electrodes, improve the coupling effect of the parasitic capacitance on each pixel, reduce the risk of crosstalk, and enhance the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. The drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 Schematic diagram of the pixel array structure of the array substrate provided in an embodiment of the present application;

[0019] Figure 2 yes Figure 1 Equivalent circuit diagram of pixel unit 11;

[0020] Figure 3 yes Figure 1 One of the cross-sectional views of the array substrate along the AA' direction;

[0021] Figure 4 yes Figure 1 A schematic diagram of the top view of the pixel unit 11;

[0022] Figure 5 yes Figure 1 A cross-sectional view of the array substrate along the BB' direction;

[0023] Figure 6 yes Figure 1 The second cross-sectional view of the array substrate along the AA' direction;

[0024] Figure 7 yes Figure 1 The third cross-sectional view of the array substrate along the AA' direction;

[0025] Figure 8 It is a schematic diagram of the connection relationship between the vertical scan lines and the horizontal scan lines in the array substrate. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0027] The embodiments of the present application provide an array substrate and a display panel, which can reduce the parasitic capacitance between the vertical scanning line and the pixel electrode, thereby improving the display effect. The following are detailed descriptions. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments. In addition, in the description of this application, the term "including" means "including but not limited to". The terms "first", "second", "third", etc. are used only as labels to distinguish different objects, rather than to describe a specific order.

[0028] See also Figures 1 to 5 , Figure 1 Schematic diagram of the pixel array structure of the array substrate provided in an embodiment of the present application; Figure 2 yes Figure 1 Equivalent circuit diagram of pixel unit 11; Figure 3 yes Figure 1 One of the cross-sectional views of the array substrate along the AA' direction; Figure 4 yes Figure 1 A schematic diagram of the top view of the pixel unit 11; Figure 5 yes Figure 1 The cross-sectional view of the array substrate along the BB' direction. Figures 1 to 5 As shown, an embodiment of the present application provides an array substrate 100, comprising: a base substrate 10, a scanning wiring layer 20 and a common electrode layer 30; the scanning wiring layer 20 is arranged on the base substrate 10, and the scanning wiring layer 20 includes a vertical scanning line 21; the common electrode layer 30 is arranged on a side of the scanning wiring layer 20 away from the base substrate 10, and the common electrode layer 30 includes a common electrode 31 and a horizontal scanning line 32, the horizontal scanning line 32 is spaced apart from the common electrode 31, and the horizontal scanning line 32 is electrically connected to the vertical scanning line 21; wherein, the orthographic projection of the common electrode 31 on the base substrate 10 at least partially covers the orthographic projection of the vertical scanning line 21 on the base substrate 10.

[0029] The array substrate 100 provided in the present application is provided with a scanning wiring layer 20 and a common electrode layer 30 so that the orthographic projection of the common electrode 31 in the common electrode layer 30 on the base substrate 10 can at least partially cover the orthographic projection of the vertical scanning line 21 in the scanning wiring layer 20 on the base substrate 10, thereby reducing parasitic capacitance, avoiding crosstalk caused by parasitic capacitance, and improving display effect.

[0030] In the embodiments of this application, Figure 1 and Figure 2 As shown, the array substrate includes a plurality of pixel units 11, vertical scan lines 21, horizontal scan lines 32 and data signal lines 41 arranged in an array, wherein the pixel unit 11 includes a pixel electrode 51 and a switching transistor T1. Specifically, the vertical scan line 21 is located between adjacent columns of pixel units 11 arranged along the width direction Y of the array substrate, and extends along the width direction Y of the array substrate; the horizontal scan line 32 is located between adjacent rows of pixel units 11 arranged along the length direction X of the array substrate, and extends along the length direction X of the array substrate; the data signal line 41 is located on the column of pixel units 11 arranged along the width direction Y of the array substrate, and extends along the width direction Y of the array substrate. The vertical scan line 21 is electrically connected to at least one horizontal scan line 32. Specifically, the vertical scan line 21 can be electrically connected to 1, 2, 3, ... n horizontal scan lines 32. Figure 1 The figure only illustrates the electrical connection between the vertical scan line 21 and one horizontal scan line 32. Persons skilled in the art may adjust this as needed, and this application does not limit this. The source s of the switching transistor T1 is electrically connected to the data signal line 41, the gate g of the switching transistor T1 is electrically connected to the horizontal scan line 32, and the drain d of the switching transistor T1 is electrically connected to the pixel electrode 51. The switching transistor T1 can be located on one side of the same data signal line 41, or on both sides of the data signal line 41.

[0031] like Figure 2 As shown, during the driving process of the array substrate 100, the scanning signal is transmitted to the corresponding horizontal scanning line 32 through the vertical scanning line 21, and then loaded onto the gate g of the switching transistor T1 to turn on the switching transistor T1, and the data signal is loaded onto the source s of the switching transistor T1 through the data signal line 41. lc It is composed of a pixel electrode 51 provided on the array substrate 100 and a common electrode 31 provided on the color filter substrate (not shown in the figure), the common electrode 31 is also known as A-COM; a storage capacitor C st It is composed of the pixel electrode 51 and the common electrode 31 provided on the array substrate 100; the parasitic capacitance C vgp It is composed of the vertical scanning line 21 and the pixel electrode 51; the parasitic capacitance C hgp It is composed of horizontal scanning lines 32 and pixel electrodes 51. When the scanning signal turns on the switch transistor T1, the data signal is loaded to the liquid crystal capacitor C through the drain electrode d of the switch transistor T1. lc The pixel electrode 51. When the liquid crystal capacitor C lcWhen the voltage between the vertical scanning lines 21 changes, the deflection direction of the liquid crystal molecules in the liquid crystal layer (not shown in the figure) also changes, thereby controlling the light transmittance through the pixel unit 11, and further controlling the display brightness of each pixel unit 11. When the parasitic capacitance between the pixel electrode 51 and the vertical scanning line 21 is large, the signal change on the vertical scanning line 21 will cause significant interference to the pixel voltage of the pixel electrode 51. The present application covers the vertical scanning line 21 by providing a common electrode layer 30 to shield the interference of the vertical scanning line 21 on the pixel electrode 51, reduce the parasitic capacitance between the vertical scanning line 21 and the pixel electrode 51, avoid crosstalk caused by the parasitic capacitance between the vertical scanning line 21 and the pixel electrode 51, and improve the display effect.

[0032] In the embodiments of this application, Figure 3 As shown, the array substrate further includes a data wiring layer 40 , which is disposed on a side of the common electrode layer 30 away from the base substrate 10 . The data wiring layer 40 includes data signal lines 41 . The data signal lines 41 provide data signals to the pixel units 11 .

[0033] In the embodiment of the present application, the cross-sectional width of the data signal line 41 is preferably greater than the cross-sectional width of the vertical scan line 21. This design helps reduce the impedance on the data signal line 41, thereby reducing the loss of the data signal on the data signal line 41 during transmission and improving display quality. It should be noted that the cross-sectional width refers to the length along the length direction X of the array substrate.

[0034] like Figure 3 As shown, the common electrode 31 partially covers the vertical scan line 21. This design enables the common electrode 31 to shield the electric field between the vertical scan line 21 and the pixel unit 11, greatly reducing the parasitic capacitance between the vertical scan line 21 and the pixel unit 11. As a result, when the signal on the vertical scan line 21 changes, the impact on the pixel voltage of the pixel unit 11 is significantly reduced or no longer affected. In addition, the difference between the pixel voltage of the pixel unit 11 at the connection between the vertical scan line 21 and the horizontal scan line 32 and the pixel voltage of the pixel unit 11 at other locations is greatly reduced, which is conducive to improving or eliminating display anomalies of the display screen.

[0035] In the embodiments of this application, Figure 3As shown, the array substrate further includes a pixel electrode 51 layer 50, which is disposed on a side of the data wiring layer 40 away from the base substrate 10. The pixel electrode 51 layer 50 includes pixel electrodes 51, and the orthographic projection of the pixel electrode 51 on the base substrate 10 covers the orthographic projection of the data signal line 41 on the base substrate 10, and the orthographic projection of the pixel electrode 51 on the base substrate 10 at least partially covers the orthographic projection of the common electrode 31 on the base substrate 10. It should be noted that the data wiring layer 40 can also be disposed on the side of the pixel electrode 51 layer 50 away from the base substrate 10. Those skilled in the art can adjust as needed, and this application does not specifically limit this.

[0036] In the embodiment of the present application, the vertical scan line 21 is disposed between two adjacent pixel electrodes 51. This design is beneficial for increasing the distance between the vertical scan line 21 and the data signal line 41, thereby reducing the parasitic capacitance between the data signal line 41 and the vertical scan line 21. Furthermore, it is beneficial for reducing the area of ​​the vertical scan line 21 facing the pixel electrode 51, thereby reducing the parasitic capacitance between the vertical scan line 21 and the pixel electrode 51. Furthermore, the vertical scan line 21 is shielded by the common electrode 31, thereby further reducing the parasitic capacitance between the vertical scan line 21 and the pixel electrode 51, thereby improving the display effect.

[0037] In the embodiment of the present application, the common electrode 31 and the pixel electrode 51 are stacked correspondingly, and the cross-sectional width of the common electrode 31 along the length direction X of the array substrate is greater than the cross-sectional width of the pixel electrode 51 along the length direction X of the array substrate. This design is conducive to shielding the vertical scan line 21.

[0038] In the embodiment of the present application, the data signal line 41 extends along the width direction Y of the array substrate, and the orthographic projection of the data signal line 41 on the base substrate 10 overlaps with the orthographic projection of the pixel electrode 51 on the base substrate 10. Figure 4As shown, the orthographic projection of the data signal line 41 on the base substrate 10 is located on the center line of the orthographic projection of the pixel electrode 51 on the base substrate 10. Specifically, the data signal line 41 is located on the trunk area of ​​the pixel electrode 51. Such a design maximizes the spacing between the data signal line 41 and the vertical scan line 21, and maximizes the spacing between two adjacent data signal lines 41, thereby minimizing the interference on the pixel voltage of the pixel electrode 51 when the signal on the vertical scan line 21 changes, thereby improving the stability of the pixel voltage. At the same time, it avoids the prior art in which the data signal line 41 and the vertical scan line 21 are both arranged between two adjacent pixel electrodes 51, and the parasitic capacitance between the data signal line 41 and its left and right pixel electrodes 51 is the same, that is, the influence of the data signal line 41 on the pixel voltages of its left and right pixel electrodes 51 is symmetrical, and there will be no problem of different effects of the data signal line 41 on the pixel voltages of the two adjacent pixel electrodes 51 due to the different distances between the data signal line 41 and the two adjacent pixel electrodes 51, resulting in poor crosstalk differences between the data signal line 41 and the left and right pixel electrodes 51, thereby improving display quality. In addition, arranging the data signal line 41 in the trunk area of ​​the pixel electrode 51 is conducive to reducing the number of signal lines arranged between adjacent pixel electrodes 51, thereby improving the aperture ratio.

[0039] In the embodiments of this application, Figure 5 As shown, the common electrode layer 30 includes a common electrode 31 and a horizontal scan line 32. The horizontal scan line 32 is spaced apart from the common electrode 31 and electrically connected to the vertical scan line 21. Specifically, the horizontal scan line 32 is electrically connected to the vertical scan line 21 through a via. The horizontal scan line 32 is spaced apart from the common electrode 31 to avoid signal interference caused by crossing signal lines, thereby improving the display effect.

[0040] In the embodiment of the present application, the array substrate 100 further includes a first insulating layer 60, a second insulating layer 70, and a third insulating layer 80. The first insulating layer 60 is disposed between the scan wiring layer 20 and the common electrode layer 30, the second insulating layer 70 is disposed between the common electrode layer 30 and the data wiring layer 40, and the third insulating layer 80 is disposed between the data wiring layer 40 and the pixel electrode 51 layer 50. Specifically, the materials of the first insulating layer 60, the second insulating layer 70, and the third insulating layer 80 can be organic resin materials or inorganic insulating materials, such as at least one of silicon oxide, silicon nitride, and a combination thereof, or other low-dielectric-constant materials. Using low-dielectric-constant materials and relatively increasing the thickness of the first insulating layer 60, the second insulating layer 70, and the third insulating layer 80 is beneficial, so that the parasitic capacitance C between the horizontal scan line 32 and the pixel electrode 51 is reduced. hgp , the parasitic capacitance between the data signal line 41 and the pixel electrode 51 and the parasitic capacitance C between the vertical scanning line 21 and the pixel electrode 51 vgpAt the same time, since the dielectric constant of organic resin materials is small, the above-mentioned parasitic capacitance can be further reduced, which is beneficial to improving the display effect.

[0041] As a specific embodiment of this application, please refer to Figure 6 , Figure 6 yes Figure 1 The second cross-sectional view of the array substrate along the AA' direction. Figure 5 and Figure 6 As shown, the present application provides an array substrate 200 . The difference between the array substrate 200 and the array substrate 100 is that the orthographic projection of the common electrode 31 on the base substrate 10 covers the orthographic projection of the vertical scanning line 21 on the base substrate 10 .

[0042] In the embodiment of the present application, the array substrate 200 includes: a base substrate 10, a scanning wiring layer 20, a first insulating layer 60, a common electrode layer 30, a second insulating layer 70, a data wiring layer 40, a third insulating layer 80 and a pixel electrode layer 51 50.

[0043] The scanning wiring layer 20 is disposed on the base substrate 10 , and includes vertical scanning lines 21 . The first insulating layer 60 is disposed between the scanning wiring layer 20 and the common electrode layer 30 .

[0044] The common electrode layer 30 is disposed on a side of the scan wiring layer 20 away from the base substrate 10. The common electrode layer 30 includes a common electrode 31 and a horizontal scan line 32. The horizontal scan line 32 is spaced apart from the common electrode 31 and electrically connected to the vertical scan line 21. The orthographic projection of the common electrode 31 on the base substrate 10 overlaps the orthographic projection of the vertical scan line 21 on the base substrate 10. A second insulating layer 70 is disposed between the common electrode layer 30 and the data wiring layer 40.

[0045] The data wiring layer 40 is disposed on a side of the common electrode layer 30 away from the base substrate 10 , and includes data signal lines 41 . The third insulating layer 80 is disposed between the data wiring layer 40 and the pixel electrode layer 50 .

[0046] The pixel electrode 51 layer 50 is disposed on a side of the data wiring layer 40 away from the base substrate 10. The pixel electrode 51 layer 50 includes a pixel electrode 51. The orthographic projection of the pixel electrode 51 on the base substrate 10 covers the orthographic projection of the data signal line 41 on the base substrate 10, and the orthographic projection of the pixel electrode 51 on the base substrate 10 at least partially covers the orthographic projection of the common electrode 31 on the base substrate 10. The vertical scan line 21 is disposed between two adjacent pixel electrodes 51. It should be noted that the data wiring layer 40 can also be disposed on a side of the pixel electrode 51 layer 50 away from the base substrate 10. Those skilled in the art can adjust as needed, and this application does not specifically limit this.

[0047] On the one hand, the array substrate 200 provided in the present application covers the orthographic projection of the vertical scanning line 21 on the base substrate 10 through the orthographic projection of the common electrode 31 on the base substrate 10, thereby shielding the influence of the vertical scanning line 21 on the pixel voltage of the pixel electrode 51 to the maximum extent, minimizing the parasitic capacitance between the vertical scanning line 21 and the pixel electrode 51, avoiding crosstalk caused by the parasitic capacitance between the vertical scanning line 21 and the pixel electrode 51, and improving the display effect.

[0048] On the other hand, the orthographic projection of the data signal line 41 on the base substrate 10 in the array substrate 200 is located on the center line of the orthographic projection of the pixel electrode 51 on the base substrate 10. Specifically, the data signal line 41 is located on the trunk area of ​​the pixel electrode 51. This design maximizes the spacing between the data signal line 41 and the vertical scan line 21, and also maximizes the spacing between two adjacent data signal lines 41. This minimizes the interference on the pixel voltage of the pixel electrode 51 when the signal on the vertical scan line 21 changes, improves the stability of the pixel voltage, and helps reduce the number of signal lines between adjacent pixel electrodes 51, thereby improving the aperture ratio.

[0049] As a specific embodiment of this application, please refer to Figure 7 , Figure 7 yes Figure 1 The third cross-sectional view of the array substrate along the AA' direction. Figure 5 and Figure 7 As shown, the present application provides an array substrate 300. The difference between the array substrate 300 and the array substrate 100 is that: the common electrode 31 includes a first sub-electrode 311 and a second sub-electrode 312, the first sub-electrode 311 and the second sub-electrode 312 are arranged at intervals, the first sub-electrode 311 and the pixel electrode 51 at least partially overlap, and the first sub-electrode 311 partially overlaps with the vertical scan line 21; the second sub-electrode 312 partially overlaps with the vertical scan line 21.

[0050] In the embodiment of the present application, the array substrate 300 includes: a base substrate 10 , a scan wiring layer 20 , a first insulating layer 60 , a common electrode layer 30 , a second insulating layer 70 , a data wiring layer 40 , a third insulating layer 80 and a pixel electrode layer 51 50 .

[0051] The scanning wiring layer 20 is disposed on the base substrate 10 , and includes vertical scanning lines 21 . The first insulating layer 60 is disposed between the scanning wiring layer 20 and the common electrode layer 30 .

[0052] The common electrode layer 30 is disposed on a side of the scan wiring layer 20 away from the base substrate 10. The common electrode layer 30 includes a common electrode 31 and a horizontal scan line 32. The horizontal scan line 32 is spaced apart from the common electrode 31 and electrically connected to the vertical scan line 21. The common electrode 31 includes a first sub-electrode 311 and a second sub-electrode 312. The first sub-electrode 311 and the second sub-electrode 312 are spaced apart from each other. The first sub-electrode 311 at least partially overlaps with the pixel electrode 51 and partially overlaps with the vertical scan line 21. The second sub-electrode 312 is disposed between two adjacent pixel electrodes 51 and partially overlaps with the vertical scan line 21. A second insulating layer 70 is disposed between the common electrode layer 30 and the data wiring layer 40.

[0053] The data wiring layer 40 is disposed on a side of the common electrode layer 30 away from the base substrate 10 , and includes data signal lines 41 . The third insulating layer 80 is disposed between the data wiring layer 40 and the pixel electrode layer 50 .

[0054] The pixel electrode 51 layer 50 is disposed on a side of the data wiring layer 40 away from the base substrate 10. The pixel electrode 51 layer 50 includes a pixel electrode 51. The orthographic projection of the pixel electrode 51 on the base substrate 10 covers the orthographic projection of the data signal line 41 on the base substrate 10, and the orthographic projection of the pixel electrode 51 on the base substrate 10 at least partially covers the orthographic projection of the common electrode 31 on the base substrate 10. The vertical scan line 21 is disposed between two adjacent pixel electrodes 51. It should be noted that the data wiring layer 40 can also be disposed on a side of the pixel electrode 51 layer 50 away from the base substrate 10. Those skilled in the art can adjust as needed, and this application does not specifically limit this.

[0055] On the one hand, the array substrate 300 provided in the present application covers the portion of the vertical scanning line 21 close to the pixel electrode 51 through the first sub-electrode 311, and covers the portion of the vertical scanning line 21 close to the adjacent pixel electrode 51 through the second sub-electrode 312, thereby maximally shielding the influence of the vertical scanning line 21 on the pixel voltage of the two adjacent pixel electrodes 51, minimizing the parasitic capacitance between the vertical scanning line 21 and the two adjacent pixel electrodes 51, avoiding crosstalk caused by the parasitic capacitance between the vertical scanning line 21 and the two adjacent pixel electrodes 51, and improving the display effect.

[0056] On the other hand, the orthographic projection of the data signal line 41 on the base substrate 10 in the array substrate 300 is located on the center line of the orthographic projection of the pixel electrode 51 on the base substrate 10. Specifically, the data signal line 41 is located on the trunk area of ​​the pixel electrode 51. This design maximizes the spacing between the data signal line 41 and the vertical scan line 21, and also maximizes the spacing between two adjacent data signal lines 41. This minimizes the interference on the pixel voltage of the pixel electrode 51 when the signal on the vertical scan line 21 changes, improves the stability of the pixel voltage, and helps reduce the number of signal lines between adjacent pixel electrodes 51, thereby improving the aperture ratio.

[0057] As a specific embodiment of this application, please refer to Figure 8 , Figure 8 Schematic diagram of the connection relationship between the vertical scanning lines and the horizontal scanning lines in the array substrate. Figure 8 As shown, the present application provides an array substrate 400 . The difference between the array substrate 400 and the array substrate 100 is that the number of vertical scan lines 21 is equal to the number of data signal lines 41 .

[0058] In an embodiment of the present application, the array substrate 400 includes a plurality of pixel units 11 arranged in an array, N columns of pixel units 11 correspond to N data signal lines 41, and M rows of pixel units 11 correspond to M horizontal scan lines 32, wherein each column of pixel units 11 is also provided with a corresponding vertical scan line 21, and the vertical scan lines 21 are electrically connected to the horizontal scan lines 32 in a one-to-one correspondence, and N and M are both positive integers. Figure 8 In the figure, six data signal lines 41, six horizontal scan lines 32 and six vertical scan lines 21 are taken as an example.

[0059] It should be noted that this is a preferred setting for balancing the number of signal lines between each column of pixel units 11 and the size of the parasitic capacitance. Those skilled in the art may also make adjustments according to actual needs, and this application does not make any specific limitations here.

[0060] By setting the same number of vertical scan lines 21 and data signal lines 41 in the array substrate 400, it is beneficial to balance the number of signal lines between each column of pixel units 11 and the size of the parasitic capacitance, so that the parasitic capacitance on the left and right sides of the pixel electrode 51 is consistent. While minimizing the parasitic capacitance as much as possible, the parasitic capacitance on the left and right sides of the data signal line 41 is consistent and offsets each other, which is beneficial to further improve the coupling effect of the parasitic capacitance on each pixel unit 11, further reduce the risk of crosstalk caused by the parasitic capacitance between the vertical scan line 21 and the pixel electrode 51, and ensure the display effect.

[0061] On the other hand, the present application provides a display panel including the above-mentioned array substrate.

[0062] The present application provides an array substrate and a display panel, comprising: a base substrate 10, a scan trace layer 20, and a common electrode layer 30. The scan trace layer 20 is disposed on the base substrate 10 and includes vertical scan lines 21. The common electrode layer 30 is disposed on a side of the scan trace layer 20 away from the base substrate 10 and includes a common electrode 31. The orthographic projection of the common electrode 31 on the base substrate 10 at least partially overlaps the orthographic projection of the vertical scan lines 21 on the base substrate 10. The array substrate provided by the present application can reduce the parasitic capacitance between the vertical scan lines 21 and the pixel electrodes 51, improve the coupling effect of the parasitic capacitance on each pixel, reduce the risk of crosstalk, and enhance the display effect.

[0063] The above is a detailed introduction to an array substrate and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A scanning wiring layer, the scanning wiring layer is provided on the base substrate, and the scanning wiring layer includes vertical scanning lines; a common electrode layer, the common electrode layer being disposed on a side of the scan wiring layer away from the base substrate, the common electrode layer comprising a common electrode and a horizontal scan line, the horizontal scan line being spaced apart from the common electrode and electrically connected to the vertical scan line; a data wiring layer, the data wiring layer being provided on a side of the common electrode layer away from the base substrate, the data wiring layer including data signal lines; a pixel electrode layer, the pixel electrode layer being disposed on a side of the data wiring layer away from the base substrate, the pixel electrode layer comprising a pixel electrode, the pixel electrode being configured to form a liquid crystal capacitor with a common electrode of the color filter substrate; The orthographic projection of the pixel electrode on the base substrate covers the orthographic projection of the data signal line on the base substrate; the orthographic projection of the common electrode on the base substrate at least partially covers the orthographic projection of the vertical scanning line on the base substrate.

2. The array substrate according to claim 1, wherein: The orthographic projection of the pixel electrode on the base substrate at least partially covers the orthographic projection of the common electrode on the base substrate.

3. The array substrate according to claim 2, wherein: The vertical scanning line is arranged between two adjacent pixel electrodes.

4. The array substrate according to claim 2, wherein: The orthographic projection of the data signal line on the base substrate is located on a center line of the orthographic projection of the pixel electrode on the base substrate.

5. The array substrate according to claim 2, wherein: The orthographic projection of the common electrode on the base substrate covers the orthographic projection of the vertical scanning line on the base substrate.

6. The array substrate according to claim 2, wherein: The common electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode and the second sub-electrode are arranged at intervals, the first sub-electrode at least partially overlaps with the pixel electrode, and the first sub-electrode partially overlaps with the vertical scanning line; the second sub-electrode is arranged between two adjacent pixel electrodes, and the second sub-electrode partially overlaps with the vertical scanning line.

7. The array substrate according to claim 2, wherein: The number of the vertical scan lines is equal to the number of the data signal lines.

8. The array substrate according to claim 2, wherein: The array substrate further includes a first insulating layer, a second insulating layer and a third insulating layer. The first insulating layer is arranged between the scanning wiring layer and the common electrode layer, the second insulating layer is arranged between the common electrode layer and the data wiring layer, and the third insulating layer is arranged between the data wiring layer and the pixel electrode layer.

9. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 8.

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