Control loop identification method, device, storage medium and electronic equipment

Abstract

The present application discloses a method, device, storage medium and electronic device for identifying a control loop. The method comprises: obtaining a morphological description rule of a typical loop, wherein the morphological description rule comprises: a target connection relationship between a target function block and other function blocks in a typical loop and a target type of the target function block, wherein the typical loop is a standard control loop of configuration data that matches a target application scenario; identifying a control program to be identified according to the morphological description rule to obtain an identification result, wherein the control program is used to define the control logic of a process flow; and determining a target typical loop in the control program according to the identification result. The present application solves the technical problems of long time consumption, low efficiency and inaccurate identification results caused by the manual identification of typical loops in related technologies.

Description

Technical Field

[0001] The present application relates to the field of industrial control, and more specifically, to a control loop identification method, device, storage medium, and electronic equipment. Background Art

[0002] As the scale of the factory expands, engineering implementation personnel often ignore the industry specifications for editing configuration data during the implementation process or because of incomplete consideration, there are hidden data transmission problems in the control loops in the configuration data. For example: a control loop requires receiving data within the range of 0 to 100 units, but the data range of the output end received by its input end is -20 to 120 units. Once the data at the output end exceeds the data range of the input end, it may cause hidden dangers or failures in the operation of the controller. For another example: a control loop requires that when output A is connected to input B, input C must be set to empty. If C is connected to other outputs at this time, it will inevitably cause data disorder. In related technologies, typical loops can generally be manually identified by manual inspection and relying on manual experience. This method is time-consuming, inefficient, and the identification results are inaccurate and prone to errors.

[0003] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0004] The embodiments of the present application provide a control loop identification method, device, storage medium and electronic device to at least solve the technical problems of time-consuming, low efficiency and inaccurate identification results caused by the related technology of manually identifying typical loops.

[0005] According to one aspect of an embodiment of the present application, a method for identifying a control loop is provided, comprising: obtaining a morphological description rule of a typical loop, wherein the morphological description rule includes: a target connection relationship between a target function block and other function blocks in the typical loop and a target type of the target function block, the typical loop being a standard control loop of configuration data matching a target application scenario; identifying a control program to be identified according to the morphological description rule to obtain an identification result, wherein the control program is used to define the control logic of a process flow; and determining a target typical loop in the control program according to the identification result.

[0006] Optionally, the control program to be identified is identified according to the morphological description rules to obtain an identification result, including: searching for various types of first function blocks included in the control program; filtering out second function blocks of the same type as the target from the first function blocks; obtaining the connection relationship between the second function block and the third function block, wherein the third function block is the function block in the first function block other than the second function block; determining whether the connection relationship satisfies the target connection relationship to obtain an identification result.

[0007] Optionally, the morphological description rules also include: the connection relationship of each pin in the target functional block, identifying the control program to be identified according to the morphological description rules to obtain an identification result, including: obtaining the current connection relationship of each pin in the second functional block; determining whether the current connection relationship is the same as the connection relationship of each pin in the target functional block to obtain an identification result.

[0008] Optionally, after obtaining the connection relationship between the second functional block and the third functional block, the method further includes: parsing the connection relationship, classifying the third functional block based on the parsing result, and dividing the third functional block into a preceding node of the second functional block and a following node of the second functional block; determining that the control loop composed of the preceding node of the second functional block is the main loop, and determining that the control loop composed of the following node of the second functional block is the secondary loop.

[0009] Optionally, the morphological description rules also include: the connection relationship between the target main circuit and the various pins in the target sub-circuit in the typical circuit, identifying the control program to be identified according to the morphological description rules, and obtaining an identification result, including: determining whether the connection relationship between the various pins in the main circuit and the sub-circuit satisfies the morphological description rules, and obtaining an identification result, wherein the target main circuit is a control circuit composed of the preceding nodes of the target function block, and the target sub-circuit is a control circuit composed of the following nodes of the target function block.

[0010] Optionally, the morphological description rules also include: a first type of the target main circuit and a second type of the target sub-circuit, and the control program to be identified is identified according to the morphological description rules to obtain an identification result, including: when it is determined that the connection relationship between each pin in the main circuit and the sub-circuit meets the morphological description rules, determining whether the types corresponding to the main circuit and the sub-circuit meet the first type and the second type respectively to obtain an identification result.

[0011] Optionally, determining a target typical loop in the control program according to the recognition result includes: obtaining a target control loop that meets a morphological description rule in the recognition result, and determining the target control loop as a target typical loop.

[0012] According to one aspect of an embodiment of the present application, a control loop identification device is also provided, including: an acquisition module for acquiring morphological description rules of a typical loop, wherein the morphological description rules include: the target connection relationship between the target function block and other function blocks in the typical loop and the target type of the target function block, and the typical loop is a standard control loop of configuration data that matches the target application scenario; an identification module for identifying a control program to be identified according to the morphological description rules to obtain an identification result, wherein the control program is used to define the control logic of the process flow; and a determination module for determining the target typical loop in the control program according to the identification result.

[0013] According to another aspect of an embodiment of the present application, a non-volatile storage medium is further provided, the storage medium including a stored program, wherein when the program is running, the device where the storage medium is located is controlled to execute any one of the control loop identification methods.

[0014] According to one aspect of an embodiment of the present application, an electronic device is further provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement any control loop identification method.

[0015] In an embodiment of the present application, a method of identifying a control program based on morphological description rules is adopted, by obtaining morphological description rules of typical loops, wherein the morphological description rules include: the target connection relationship between the target function block and other function blocks in the typical loop and the target type of the target function block, and the typical loop is a standard control loop of configuration data that matches the target application scenario; the control program to be identified is identified according to the morphological description rules to obtain an identification result, wherein the control program is used to define the control logic of the process flow; the target typical loop in the control program is determined according to the identification result, thereby achieving the technical effect of automatically and accurately identifying typical loops, saving identification time, and improving identification efficiency, thereby solving the technical problems of long time consumption, low efficiency and inaccurate identification results caused by the manual identification of typical loops in related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 is a flow chart of an optional control loop identification method according to an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of the morphological description process in an embodiment of the present application;

[0019] Figure 3 This is a search and identification flow chart in an embodiment of the present application;

[0020] Figure 4 Schematic diagram of control procedure - typical loop - override control in an embodiment of the present application;

[0021] Figure 5 This is a diagram of control program-typical loop-override control-identification results in the embodiment of the present application;

[0022] Figure 6is a schematic structural diagram of an optional control loop identification device according to an embodiment of the present application;

[0023] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present application is shown. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] In order to facilitate those skilled in the art to better understand the relevant embodiments of the present application, the technical terms or nouns that may be involved in the present application are explained as follows:

[0027] Control system / industrial control system: A control system based on computer technology, communication technology and control technology, which can realize the collection of production equipment signal data, control logic calculation, and then control the production equipment through signals.

[0028] Controller: A digital logic controller used for automated control that can load control instructions into memory for storage and execution at any time.

[0029] Configuration data: In order to realize data collection and control of production equipment, the control system needs to preset simulation data of production equipment, write control logic programs, and other pre-set data. These data are called configuration data.

[0030] Control program: A method for defining control logic within a control system. Control logic can be defined graphically, and the control system can calculate and further process these corresponding logics.

[0031] Control loop: A controller determines an output based on an input quantity according to certain rules and algorithms. In this way, the input and output form a control loop.

[0032] Typical loops: Engineering implementation personnel developed control loop specifications for application in certain scenarios based on the control loops in the configuration data during the implementation process.

[0033] Bit number: The data source or output source in the control system. The data of the instrument hardware in the control system is connected to the controller through hardware wiring. The bit number represents the input data of the instrument or the data to be output to the instrument.

[0034] Function Block: A computational block in a control program within a control system that implements a specific function. It comes in various types. For example, an ADD function block performs an addition operation on a data source.

[0035] Node: When the control program is abstracted into a graph, the bit number and function block are displayed as several nodes. The node refers to the bit number or function block.

[0036] Current Node: The node currently being identified and checked.

[0037] Predecessor node: The node that is input to the current node.

[0038] Post-node: The node to which the current node outputs.

[0039] Main loop: The main data control loop, which usually determines the input of the secondary loop and must be upstream of the secondary loop.

[0040] Auxiliary loop: A secondary control loop, usually used to directly control the output value of the bit number, must be downstream of the main loop.

[0041] Pin: A specific functional value in a node.

[0042] According to an embodiment of the present application, an embodiment of a control loop identification method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0043] Figure 1 is a control loop identification method according to an embodiment of the present application, such as Figure 1 As shown, the method includes the following steps:

[0044] Step S102: Acquire a morphological description rule of a typical circuit, wherein the morphological description rule includes: a target connection relationship between a target function block and other function blocks in the typical circuit, and a target type of the target function block. The typical circuit is a standard control circuit of configuration data matching a target application scenario.

[0045] Step S104, identifying the control program to be identified according to the morphological description rules to obtain an identification result, wherein the control program is used to define the control logic of the process flow;

[0046] Step S106: determining a target typical loop in the control program according to the recognition result.

[0047] In the control loop identification method, a morphological description rule of a typical loop is obtained, wherein the morphological description rule includes: a target connection relationship between a target function block and other function blocks in the typical loop and a target type of the target function block, and the typical loop is a standard control loop of configuration data that matches a target application scenario; a control program to be identified is identified according to the morphological description rule to obtain an identification result, wherein the control program is used to define the control logic of a process flow; and a target typical loop in the control program is determined according to the identification result, thereby achieving the technical effect of automatically and accurately identifying the typical loop, saving identification time, and improving identification efficiency, thereby solving the technical problems of long time consumption, low efficiency, and inaccurate identification results caused by the manual identification of typical loops in related technologies.

[0048] As an optional implementation method, the control program to be identified is identified according to the morphological description rules to obtain the identification result. This can be achieved in the following way. Specifically, various types of first function blocks included in the control program are searched; second function blocks of the same target type are filtered out from the first function blocks; the connection relationship between the second function block and the third function block is obtained, wherein the third function block is the function block in the first function block other than the second function block; and whether the connection relationship satisfies the target connection relationship to obtain the identification result.

[0049] In some embodiments of the present application, the morphological description rules also include: the connection relationship of each pin in the target functional block. Therefore, the control program to be identified is identified according to the morphological description rules to obtain an identification result. It is also possible to obtain the current connection relationship of each pin in the second functional block; determine whether the current connection relationship is the same as the connection relationship of each pin in the target functional block to obtain an identification result.

[0050] In some optional embodiments of the present application, after obtaining the connection relationship between the second functional block and the third functional block, the connection relationship can be analyzed, and the third functional block can be classified based on the analysis result, and the third functional block can be divided into the leading node of the second functional block and the trailing node of the second functional block; the control loop composed of the leading node of the second functional block is determined to be the main loop, and the control loop composed of the trailing node of the second functional block is determined to be the secondary loop.

[0051] In some embodiments of the present application, the morphological description rules also include: the connection relationship between the target main circuit and the target sub-circuit in the typical circuit. Therefore, the control program to be identified is identified according to the morphological description rules to obtain the identification result, which can be achieved in the following way: determine whether the connection relationship between the main circuit and the pins in the sub-circuit meets the morphological description rules to obtain the identification result, wherein the target main circuit is a control circuit composed of the preceding nodes of the target function block, and the target sub-circuit is a control circuit composed of the following nodes of the target function block.

[0052] In an exemplary embodiment of the present application, the morphological description rules also include: a first type of the target main circuit and a second type of the target sub-circuit. Therefore, the control program to be identified is identified according to the morphological description rules to obtain an identification result, including: when it is determined that the connection relationship between each pin in the main circuit and the sub-circuit meets the morphological description rules, determining whether the types corresponding to the main circuit and the sub-circuit meet the first type and the second type respectively, to obtain an identification result.

[0053] It is easy to notice that, by determining the target typical loop in the control program according to the recognition result, the target control loop that satisfies the morphological description rule in the recognition result can be obtained, and the target control loop can be determined as the target typical loop.

[0054] In one embodiment of the present application, the above scheme can be implemented in two steps. First, a morphological description of the typical circuit to be identified can be made. Second, the data in the control program can be searched and identified based on the morphological description.

[0055] Figure 2 This is a schematic diagram of the morphological description process in this application, such as Figure 2 As shown in the figure, the process described in this form mainly includes:

[0056] 1. Select a representative control node in a typical circuit as the key node. This step usually requires a certain understanding of the typical circuit's engineering applications. The following identification will focus on this key node.

[0057] 2. Describe the connection relationship of the node from the following perspectives (Note: The description should be as brief as possible and avoid repeated recognition from the overall perspective. The accuracy of the description will determine the accuracy of recognition):

[0058] The existence of the node's predecessor node: Some input pins of the node must be connected to the node. The consistency of the node's predecessor node: Whether the predecessor node is the same node. The inconsistency of the node's predecessor node: Whether the predecessor node cannot be the same node. The matching of the predecessor node's pins with the current node's pins: An output of the predecessor node must be connected to a specific input of the node. Node type: The node must be a certain type of function block.

[0059] 3. Find all the predecessor nodes of the node and describe them according to the same principle.

[0060] 4. Find all the subsequent nodes of this node and describe them according to the same principle.

[0061] 5. If there is a function block node as the predecessor node of this node, jump to step 3 based on this predecessor node.

[0062] 6. If there is a function block node after this node, jump to step 4 based on this previous node.

[0063] 7. Repeat the cycle until all the functional block nodes in the typical circuit are described.

[0064] Figure 3 This is a search and identification flow chart in an embodiment of the present application, such as Figure 3 As shown, the process mainly includes:

[0065] 1. Search for function blocks in all control programs and save an index list of all types of function blocks.

[0066] 2. Select a typical circuit type from the typical circuit description library. If no typical circuit type that has not been identified can be found, jump to step 9.

[0067] 3. Obtain the function block type of the key node defined in the current typical loop, and obtain all function block indexes of this type from the result of step 1 - the function block index list.

[0068] 4. Remove functional blocks that have been identified as components of other typical circuits.

[0069] 5. Select an unidentified function block from the results of step 4. If it cannot be found, jump to step 2.

[0070] 6. Determine whether the current node meets the requirements defined in the typical circuit description. If not, jump to step 5.

[0071] 7. Get the connection relationship information of the current function block. If there is a predecessor node, jump to step 6. If there is a successor node, jump to step 6. If there is no node, jump to step 8.

[0072] 8. If the function blocks included in the current typical circuit type have been checked and all meet the requirements, then record the function blocks taken out in step 4 as key nodes of the typical circuit and save them into the database.

[0073] 9. Identification is completed.

[0074] The above technical solution of the present application is now described with reference to a specific example.

[0075] Figure 4 This is a schematic diagram of control program-typical loop-override control, such as Figure 4 As shown in the figure, the larger rectangular blocks (A, B, C, D) are function block nodes; the smaller rectangular bars (not A, B, C, D) are bit number nodes; the top bar of the function block node indicates the function block type. For example, PIDEX is written above the A node, ASH is written above the C node, and MANUAL is written above the D node. This means that node A is a PIDEX type function block, node C is an ASH type function block, and node D is a MANUAL type function block.

[0076] The PIDEX function block performs a regulation function based on a measured value and a setpoint. (For example, if the measured value of a pool is 0 and the setpoint is 100, the output of the pipe will be larger; if the measured value is 80 and the setpoint is 100, the output of the pipe will be smaller).

[0077] The ASH function block is a high selection function block that selects two inputs and selects the higher input for output.

[0078] The MANUAL function block is a handheld function block that allows you to select manual or automatic mode. In manual mode, the output value is manually adjusted, while in automatic mode, the output is adjusted according to the input value. The channels connected to the outside world, shown in the center of the function block, are the pins of this function block. The ones on the left are input pins, and the ones on the right are output pins.

[0079] Now according to Figure 4 To identify a typical circuit:

[0080] 1. Select a representative node in a typical circuit as the key node.

[0081] The typical control program loop in the example, Override Control, is a selective control loop designed to prevent output from exceeding limits. It's easy to notice that bit 2601FI80006 is output to function block A, while bit 2601PI80009 is output to function block B. Both A and B are output to function block C, which is then output to function block D, which is then output to bit 2601FV800006. To prevent the input to function block D from being too low, the inputs of both blocks A and B are selected, with the higher input selected by block B and outputted to function block D.

[0082] Therefore, based on our understanding of this typical loop, we can designate the key node of this typical loop—override control—as function block C, or the ASH high-select function block. (Actually, this could also be the ASL low-select function block, meaning it selects the lower input for output, but this is not discussed here.) The node preceding this key node is typically defined as the primary loop, while the node following it is typically defined as the secondary loop.

[0083] 2. Determine the existence of the node preceding the node pin.

[0084] Because the output of the key node C function block needs to be determined based on the input values ​​of IN1 and IN2, the input pins IN1 and IN2 of the key node C function block must be connected to a node.

[0085] 3. Determine the uniformity of the node pin's preceding node.

[0086] The input pins BKIN and BKINERR of the key node C function block must be connected to a node if there is an input. This is an implicit engineering rule and is just an analogy, so I will not elaborate on it here.

[0087] 4. Determine the inconsistency of the node pin's preceding node

[0088] If the key node C function block processes two inputs with the same value, it will be meaningless. Therefore, the predecessor nodes connected to IN1 and IN2 must be different nodes.

[0089] 5. Determine whether the pins of the previous node match the pins of the current node.

[0090] The predecessor nodes A and B of the key node C functional block must have their output pins MV connected to the input pins IN1 and IN2 of ASH respectively.

[0091] 6. Determine the node type. The key node C function block must be an ASH or ASL type function block.

[0092] 7. Based on the above, the following descriptions describe the key node configuration: The key node's input pins IN1 and IN2 must be connected to the same node; the key node's input pins BKIN and BKINERR must be connected to the same node; the key node's input pins IN1 and IN2 must be connected to different nodes; the node preceding the key node's input pins IN1 and IN2 must be the MV output to IN1 and IN2. Key nodes must be ASH or ASL types.

[0093] 8. According to the above rules, determine the morphological description of the predecessor node (main loop) of key node C:

[0094] The MV pin of the main circuit must be connected to a node; the PV and PVERR pins of the main circuit must be connected to a node; the BKIN, BKINERR, and MV pins of the main circuit must be connected to the same node; the PV and PVERR pins of the main circuit must be connected to the same node; the BKIN and BKINERR of the main circuit must be connected to the BKOUT and BKOUTERR of the key node; the main circuit must be PID or PIDEX type.

[0095] 9. Determine the morphological description of the subsequent node (sub-loop) of the key node C according to the above rules: the MV pin of the sub-loop must be connected to a node; the IN pin of the sub-loop must be connected to a node; the BKIN, BKINERR, and MV pins of the sub-loop must be connected to the same node; the IN pin of the sub-loop must be connected to the OUT pin of the key node; the sub-loop must be of MANAUL type.

[0096] Figure 5 This diagram shows the control program, typical loop, override control, and identification results in this embodiment. As can be understood, this application provides a judgment rule that can describe typical loop morphologies and identifies and documents them through a computer program. By identifying the control program, it is possible to detect anomalies in the design of typical loops, thereby enhancing the robustness of the control system.

[0097] Figure 6 is a control loop identification device according to an embodiment of the present application, such as Figure 6 As shown, the identification device includes:

[0098] an acquisition module 60 for acquiring a morphological description rule of a typical circuit, wherein the morphological description rule includes: a target connection relationship between a target function block and other function blocks in the typical circuit, and a target type of the target function block; a typical circuit is a canonical control circuit of configuration data matching a target application scenario;

[0099] The recognition module 62 is used to recognize the control program to be recognized according to the morphological description rules and obtain a recognition result, wherein the control program is used to define the control logic of the process flow;

[0100] The determination module 64 is configured to determine a target typical loop in the control program according to the identification result.

[0101] In the control loop identification device, the acquisition module 60 is used to obtain the morphological description rules of the typical loop, wherein the morphological description rules include: the target connection relationship between the target function block and other function blocks in the typical loop and the target type of the target function block, and the typical loop is a standard control loop of the configuration data that matches the target application scenario; the identification module 62 is used to identify the control program to be identified according to the morphological description rules to obtain an identification result, wherein the control program is used to define the control logic of the process flow; the determination module 64 is used to determine the target typical loop in the control program according to the identification result, thereby achieving the technical effect of automatically and accurately identifying the typical loop, saving identification time, and improving identification efficiency, thereby solving the technical problems of long time consumption, low efficiency and inaccurate identification results caused by the manual identification of typical loops in related technologies.

[0102] According to another aspect of an embodiment of the present application, a non-volatile storage medium is further provided, the storage medium including a stored program, wherein when the program is running, the device where the storage medium is located is controlled to execute any one of the control loop identification methods.

[0103] Specifically, the above storage medium is used to store program instructions for the following functions to implement the following functions:

[0104] Acquire morphological description rules for typical loops, wherein the morphological description rules include: a target connection relationship between a target function block and other function blocks in the typical loop, and a target type of the target function block, wherein the typical loop is a standard control loop of configuration data that matches a target application scenario; identify a control program to be identified according to the morphological description rules to obtain an identification result, wherein the control program is used to define the control logic of a process flow; and determine a target typical loop in the control program according to the identification result.

[0105] Alternatively, in this embodiment, the storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or apparatuses, or any suitable combination thereof. More specific examples of the storage medium may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0106] In an exemplary embodiment of the present application, a computer program product is further provided, including a computer program. When the computer program is executed by a processor, the computer program implements any of the above control loop identification methods.

[0107] Optionally, the computer program may implement the following steps when executed by a processor:

[0108] Acquire morphological description rules for typical loops, wherein the morphological description rules include: a target connection relationship between a target function block and other function blocks in the typical loop, and a target type of the target function block, wherein the typical loop is a standard control loop of configuration data that matches a target application scenario; identify a control program to be identified according to the morphological description rules to obtain an identification result, wherein the control program is used to define the control logic of a process flow; and determine a target typical loop in the control program according to the identification result.

[0109] According to an embodiment of the present application, an electronic device is provided, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute any of the above-mentioned control loop identification methods.

[0110] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0111] Figure 7A schematic block diagram of an example electronic device 700 that can be used to implement an embodiment of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0112] like Figure 7 As shown, the device 700 includes a computing unit 701, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 702 or a computer program loaded from a storage unit 704 into a random access memory (RAM) 703. Various programs and data required for the operation of the device 700 can also be stored in the RAM 703. The computing unit 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0113] Various components in device 700 are connected to I / O interface 705, including: input unit 706, such as a keyboard, mouse, etc.; output unit 707, such as various types of displays, speakers, etc.; storage unit 704, such as a magnetic disk, optical disk, etc.; and communication unit 709, such as a network card, modem, wireless communication transceiver, etc. Communication unit 709 allows device 700 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0114] The computing unit 701 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 701 performs the various methods and processes described above, such as the control loop identification method. For example, in some embodiments, the control loop identification method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 704. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the control loop identification method described above can be performed. Alternatively, in other embodiments, the computing unit 701 can be configured to perform the control loop identification method by any other appropriate means (e.g., by means of firmware).

[0115] In the relevant embodiments of the present application, a method of identifying a control program based on morphological description rules is adopted, by obtaining the morphological description rules of a typical loop, wherein the morphological description rules include: the target connection relationship between the target function block and other function blocks in the typical loop and the target type of the target function block, and the typical loop is a standard control loop of configuration data that matches the target application scenario; the control program to be identified is identified according to the morphological description rules to obtain an identification result, wherein the control program is used to define the control logic of the process flow; the target typical loop in the control program is determined according to the identification result, thereby achieving the technical effect of automatically and accurately identifying the typical loop, saving identification time, and improving identification efficiency, thereby solving the technical problems of long time consumption, low efficiency and inaccurate identification results caused by the manual identification of typical loops in related technologies.

[0116] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0117] The program code for implementing the methods of the present application can be written in any combination of one or more programming languages. Such program code can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the program code is executed by the processor or controller, the functions / operations specified in the flow charts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0118] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0119] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0120] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0121] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0122] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0123] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0124] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0125] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0126] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0127] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0128] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A control loop identification method, characterized in that: include: Obtaining a morphological description rule for a typical circuit, wherein the morphological description rule includes: a target connection relationship between a target function block and other function blocks in the typical circuit and a target type of the target function block, wherein the typical circuit is a standard control circuit of configuration data matching a target application scenario; Identify the control program to be identified according to the morphological description rule to obtain an identification result, wherein the control program is used to define the control logic of the process flow; determining a target typical loop in the control program according to the identification result; The morphological description rules also include: the connection relationship between each pin in the target function block, the connection relationship between each pin in the target main loop and the target sub-loop in the typical loop, wherein the target main loop is a control loop composed of the preceding nodes of the target function block, and the target sub-loop is a control loop composed of the following nodes of the target function block.

2. The method according to claim 1, characterized in that The control program to be identified is identified according to the morphological description rule to obtain an identification result, including: searching for various types of first function blocks included in the control program; Filtering out a second functional block having the same type as the target from the first functional block; Acquire a connection relationship between the second functional block and a third functional block, wherein the third functional block is a functional block in the first functional block excluding the second functional block; Determine whether the connection relationship satisfies the target connection relationship, and obtain the recognition result.

3. The method according to claim 2, characterized in that The control program to be identified is identified according to the morphological description rule to obtain an identification result, including: Obtaining the current connection relationship of each pin in the second functional block; Determine whether the current connection relationship is the same as the connection relationship of each pin in the target functional block to obtain the recognition result.

4. The method according to claim 2, characterized in that After obtaining the connection relationship between the second functional block and the third functional block, the method further includes: parsing the connection relationship, and classifying the third functional block based on the parsing result, dividing the third functional block into a preceding node of the second functional block and a succeeding node of the second functional block; A control loop composed of the preceding nodes of the second functional block is determined as a main loop, and a control loop composed of the following nodes of the second functional block is determined as a sub-loop.

5. The method according to claim 4, characterized in that The control program to be identified is identified according to the morphological description rule to obtain an identification result, including: Determine whether the connection relationship between the main circuit and each pin in the secondary circuit meets the morphological description rule to obtain the recognition result.

6. The method according to claim 5, characterized in that The morphological description rule further includes: a first type of the target main loop and a second type of the target sub-loop; and identifying the control program to be identified according to the morphological description rule to obtain an identification result, including: When it is determined that the connection relationship between the pins in the main circuit and the secondary circuit meets the morphological description rule, it is determined whether the types corresponding to the main circuit and the secondary circuit meet the first type and the second type respectively, to obtain the recognition result.

7. The method according to any one of claims 1 to 6, characterized in that Determining a target typical loop in the control program according to the identification result includes: A target control loop that satisfies the morphological description rule in the recognition result is obtained, and the target control loop is determined to be the target typical loop.

8. A control loop identification device, characterized in that: include: An acquisition module is configured to acquire a morphological description rule of a typical circuit, wherein the morphological description rule includes: a target connection relationship between a target function block and other function blocks in the typical circuit and a target type of the target function block, wherein the typical circuit is a standard control circuit of configuration data matching a target application scenario; the morphological description rule also includes: a connection relationship between each pin in the target function block, a connection relationship between each pin in a target main circuit and a target sub-circuit in the typical circuit, wherein the target main circuit is a control circuit composed of a preceding node of the target function block, and the target sub-circuit is a control circuit composed of a following node of the target function block; an identification module, configured to identify a control program to be identified according to the morphological description rule to obtain an identification result, wherein the control program is used to define the control logic of the process flow; A determination module is used to determine a target typical loop in the control program according to the recognition result.

9. A non-volatile storage medium, characterized in that: The storage medium includes a stored program, wherein when the program is executed, the device where the storage medium is located is controlled to execute the control loop identification method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the control loop identification method according to any one of claims 1 to 7.

Images