A system and method for read-write access of a mask-based GPU pixel stream cache

Abstract

The application relates to a mask-based GPU pixel stream Cache read-write access system and method. The system of the application comprises a TAG comparison logic module, a replacement algorithm module, a write-back logic module and an update logic module, the TAG comparison logic module is connected with the replacement algorithm module, the write-back logic module and the update logic module respectively, the replacement algorithm module is connected with the write-back logic module and the update logic module respectively, and the write-back logic module is connected with the update logic module. The application uses a design of storing data and storing a mask at the same time to replace the replacement process of a general Cache when a write operation is missed, reduces the delay of the Cache, makes the pixel stream of the GPU have a higher caching effect, and is more suitable for the caching of the pixel stream of a graphic processor.

Description

Technical Field

[0001] This invention belongs to the field of inherited circuit design technology, and in particular to a mask-based GPU pixel stream cache read / write access system and method. Background Technology

[0002] GPU pixel stream caches prioritize data caching over data locality. Each write operation might only contain a color value. However, general-purpose caches only cache data, not the mask. To maintain data consistency, when a read / write hit occurs, the data in main memory must be replaced back into the cache. Under good data locality, this replacement can result in multiple hits. However, GPU data stream caching demands more than data locality, leading to a lower hit rate and more frequent misses. Misses require replacement operations, increasing cache latency and impacting GPU rendering speed. Therefore, this invention proposes a mask-based GPU pixel stream cache read / write access mechanism. This mechanism stores both data and the mask simultaneously, replacing the replacement process required by general-purpose caches during write misses. This reduces cache latency and is more suitable for GPU pixel stream caching. Summary of the Invention

[0003] To address the technical problems existing in the background art, this invention provides a read / write access system and method for GPU pixel stream cache based on a mask. It replaces the replacement process in general cache when a write operation is missed by using a storage mask design while storing data. When a cache write hit occurs, data and the mask are directly written; when a write miss occurs, no replacement operation is performed. A mask check for the corresponding data is added to the read operation missing judgment, ensuring data consistency, reducing cache read replacement latency, and improving the pixel rendering speed of the graphics processor.

[0004] The technical solution of this invention is as follows: This invention is a mask-based GPU pixel stream cache read / write access system, which is characterized in that: the system includes a TAG comparison logic module, a replacement algorithm module, a write-back logic module, and an update logic module. The TAG comparison logic module is connected to the replacement algorithm module, the write-back logic module, and the update logic module, respectively. The replacement algorithm module is connected to the write-back logic module and the update logic module, respectively. The write-back logic module is connected to the update logic module.

[0005] Furthermore, the TAG comparison logic module includes a TAG marker register, a mask RAM, and a byte-enabled data RAM. The TAG marker register stores the TAG, the valid bit of the data block, and the dirty bit of the data block.

[0006] Furthermore, the TAG comparison logic module completes the read / write control of the TAG marker register, mask RAM, and data RAM, as well as the determination of whether the cache read / write operation is a hit or a miss.

[0007] Furthermore, the processing procedure for read / write operations of the TAG comparison logic module is as follows:

[0008] Read request: First, read the data from the TAG register, mask RAM, and data RAM according to the index; then, determine whether the TAG is hit based on the read TAG data. In addition, it is necessary to check the mask hit based on the TAG hit. If the TAG is hit, the data block is valid, and the mask is hit, it means that the current read request is hit. If the TAG is missing, it means that the current read request is missing. If the TAG is hit, the data block is valid, and the mask is missing, it means that the current read request mask is missing.

[0009] Write request: First, read the data from the TAG register, mask RAM and data RAM according to the index; then, based on the read TAG data, determine whether the TAG is hit. If the TAG is hit and the data block is valid, it means that the current write request is hit; otherwise, it means that the current write request is missing.

[0010] If a read request is hit, the output data and mask are selected from the multiple read data based on the hit road number; if a write request is hit, the data and mask are directly written to the data RAM and mask RAM based on the hit road group number.

[0011] If a read request is missing, first check the dirty bit flag of the data block read from the TAG flag register. If there is a dirty bit, start the write-back logic module, wait for the write-back to finish, and then start the replacement algorithm module. If there is no dirty bit, start the replacement algorithm module directly. After the replacement is completed, return the read data and mask.

[0012] If the read request mask is missing, the update logic module is started. It generates the complete data for the address based on the mask information by reading the corresponding data from main memory and the data in data RAM, and returns the read data and the corresponding mask.

[0013] If a write request is successful, the data and mask are written to the corresponding data RAM and mask RAM.

[0014] If a write request is missing, the system first checks the dirty bit flag of the data block read from the TAG flag register. If a dirty bit is present, the write-back logic module is initiated. After the write-back is completed, the data and mask are written to the corresponding data RAM and mask RAM. If no dirty bit is present, the data and mask are directly written to the corresponding data RAM and mask RAM.

[0015] Furthermore, the replacement algorithm module uses a pseudo least recently used algorithm to generate the block number that needs to be replaced when a read / write miss occurs.

[0016] Furthermore, when a read / write request is missing and there are dirty bits, the write-back logic module reads the data RAM, mask RAM, and TAG register according to the replacement algorithm. The read TAG generates the address to write to main memory, and at the same time, the read data and mask are written back to main memory, and the mask of the replacement block is cleared as invalid.

[0017] Furthermore, when the read mask is missing, the update logic module reads the data from the main memory and stores the data from the main memory into the data RAM according to the replacement algorithm, so that the mask is stored as fully valid.

[0018] Furthermore, when the read mask is missing, the update logic module reads data from the main memory and generates a write data enable signal for the write data RAM based on the offset bit of the read address. This ensures that the replaced data does not overwrite the originally written data, and the data read from the main memory is written into the path group data RAM of the TAG hit according to the generated write data enable signal.

[0019] A method for implementing the above-mentioned mask-based GPU pixel stream cache read / write access system is characterized by the following steps:

[0020] 1) The cache receives a read request:

[0021] 1.1) First, start the TAG comparison logic module and read the data from the TAG flag register, four mask RAMs, and four data RAMs according to the index. Then, based on the read TAG data, determine whether the TAG is hit. In addition, it is necessary to perform a mask hit judgment based on the TAG hit. If the TAG is hit, the data block is valid, and the mask is hit, it means that the current read request is hit. If the TAG is missing, it means that the current read request is missing. If the TAG is hit, the data block is valid, and the mask is missing, it means that the current read request mask is missing.

[0022] 1.2) If a read request is hit, select the output data and mask from the four read data based on the hit road number;

[0023] 1.3) If a read request is missing, first check the dirty bit flag of the data block read from TAG RAM. If a dirty bit is found, start the write-back logic module. According to the replacement algorithm, read the data RAM, mask RAM, and TAG flag register. The read TAG generates the address to write to main memory. At the same time, write the read data and mask back to main memory and clear the mask of the replacement block to invalid. Wait for the write-back to finish and start the replacement algorithm module. If there is no dirty bit, start the replacement algorithm module directly, read the data from main memory, and store the data from main memory into the data RAM according to the replacement algorithm. Store the mask as fully valid. After the replacement is completed, return the read data and mask.

[0024] 1.4) If the read request mask is missing, the update logic module is started, reads the data from the main memory, generates a write data enable signal for the write data RAM based on the offset of the read address, so that the replaced data does not overwrite the originally written data. The data read from the main memory is written to the path group data RAM of the TAG hit according to the generated write data enable signal; at the same time, the corresponding data read from the main memory and the data in the data RAM are used to generate the complete data at that address based on the mask information, and the read data and the corresponding mask are returned.

[0025] 2) The cache receives a write request:

[0026] 2.1) First, start the TAG comparison logic module and read the data from the TAG flag register, four mask RAMs and four data RAMs according to the index; then, based on the read TAG data, determine whether the TAG is hit. If the TAG is hit and the data block is valid, it means that the current write request is hit; otherwise, it means that the current write request is missing.

[0027] 2.2) If a write request is hit, write the data and mask into the corresponding data RAM and mask RAM;

[0028] 2.3) If a write request is missing, first check the dirty bit flag of the data block read from the TAG flag register. If there is a dirty bit, start the write-back logic module. Read the data RAM, mask RAM and TAG RAM according to the replacement algorithm. The read TAG generates the address to write to main memory. At the same time, write the read data and mask back to main memory and clear the mask of the replacement block as invalid. After the write-back is completed, write the data and mask into the corresponding data RAM and mask RAM. If there is no dirty bit, write the data and mask directly into the corresponding data RAM and mask RAM.

[0029] This invention proposes a mask-based GPU pixel stream cache read / write access system and method. During cache write operations, it checks whether the current write address is hit. If a write hit occurs, the data and mask are stored directly. If a write miss occurs, it first checks whether a write-back is needed. If a write-back is needed, the data is written back to main memory, and then the current data and mask are stored. Otherwise, the current data and mask are stored directly. Cache read operations are processed in a manner similar to those of a general cache, except that address hit checks require further checks on mask hits, ensuring cache data consistency. Therefore, this invention uses a mask-storage design that replaces the general cache's replacement process in case of a write miss, reducing cache latency and resulting in faster caching of GPU pixel streams, making it more suitable for GPU pixel stream caching. Attached Figure Description

[0030] Figure 1This is a block diagram of the method of the present invention. Detailed Implementation

[0031] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] See Figure 1 The specific implementation of the mask-based GPU pixel stream cache read / write access system of the present invention consists of the following modules: a TAG comparison logic module, a replacement algorithm module, a write-back logic module, and an update logic module. The TAG comparison logic module is connected to the replacement algorithm module, the write-back logic module, and the update logic module, respectively. The replacement algorithm module is connected to both the write-back logic module and the update logic module, respectively. The write-back logic module is connected to the update logic module. Wherein:

[0033] The TAG comparison logic module includes a TAG register, a mask RAM, and a byte-enabled data RAM. The TAG RAM stores the TAG, data block valid bits, and data block dirty bits. This module controls read / write operations in the TAG RAM, mask RAM, and data RAM, and determines cache hits or misses. The processing flow for read / write operations in the TAG comparison logic module is as follows:

[0034] Read request: First, read the data from the TAG register, mask RAM, and data RAM according to the index; then, determine whether the TAG is hit based on the read TAG data. In addition, it is necessary to check the mask hit based on the TAG hit. If the TAG is hit, the data block is valid, and the mask is hit, it means that the current read request is hit. If the TAG is missing, it means that the current read request is missing. If the TAG is hit, the data block is valid, and the mask is missing, it means that the current read request mask is missing.

[0035] Write request: First, read the data from the TAG register, mask RAM and data RAM according to the index; then, based on the read TAG data, determine whether the TAG is hit. If the TAG is hit and the data block is valid, it means that the current write request is hit; otherwise, it means that the current write request is missing.

[0036] If a read request is hit, the output data and mask are selected from the multiple read data based on the hit road number; if a write request is hit, the data and mask are directly written to the data RAM and mask RAM based on the hit road group number.

[0037] If a read request is missing, first check the dirty bit flag of the data block read from the TAG flag register. If there is a dirty bit, start the write-back logic module, wait for the write-back to finish, and then start the replacement algorithm module. If there is no dirty bit, start the replacement algorithm module directly. After the replacement is completed, return the read data and mask.

[0038] If the read request mask is missing, the update logic module is started. It generates the complete data for the address based on the mask information by reading the corresponding data from main memory and the data in data RAM, and returns the read data and the corresponding mask.

[0039] If a write request is successful, the data and mask are written to the corresponding data RAM and mask RAM.

[0040] If a write request is missing, the system first checks the dirty bit flag of the data block read from the TAG flag register. If a dirty bit is present, the write-back logic module is initiated. After the write-back is completed, the data and mask are written to the corresponding data RAM and mask RAM. If no dirty bit is present, the data and mask are directly written to the corresponding data RAM and mask RAM.

[0041] When a read / write miss occurs, the replacement algorithm module uses a pseudo least recently used algorithm to generate the block number that needs to be replaced.

[0042] When a read / write request is missing and there are dirty bits, the write-back logic module reads the data RAM, mask RAM, and TAG register according to the replacement algorithm. The read TAG generates the address to write to main memory, and at the same time, the read data and mask are written back to main memory, and the mask of the replacement block is cleared to be invalid.

[0043] When the read mask is missing, the update logic module reads data from main memory and stores it in the data RAM according to the replacement algorithm, ensuring the mask is fully valid. When the read mask is missing, the update logic module reads data from main memory and generates a write enable signal for the data RAM based on the offset of the read address. This ensures that the replaced data does not overwrite the originally written data. The data read from main memory is then written to the path group data RAM where the TAG has been hit, based on the generated write enable signal.

[0044] In a specific embodiment of the mask-based GPU pixel stream cache read / write access method of the present invention: the pixel cache in the GPU is 8KB in size, adopts a 4-way set-associative design, with 32 blocks per channel, each block having a size of 2*256 bits of data, and the main memory is a DDR2 SDRAM chip, with a data size of 2*256 bits per request.

[0045] 1) The cache receives a read request:

[0046] 1.1) First, start the TAG comparison logic module and read the data from the TAG flag register, four mask RAMs, and four data RAMs according to the index. Then, based on the read TAG data, determine whether the TAG is hit. In addition, it is necessary to perform a mask hit judgment based on the TAG hit. If the TAG is hit, the data block is valid, and the mask is hit, it means that the current read request is hit. If the TAG is missing, it means that the current read request is missing. If the TAG is hit, the data block is valid, and the mask is missing, it means that the current read request mask is missing.

[0047] 1.2) If a read request is hit, select the output data and mask from the four read data based on the hit road number;

[0048] 1.3) If a read request is missing, first check the dirty flag of the data block read from the TAG flag register. If a dirty flag is present, start the write-back logic module. According to the replacement algorithm, read the data RAM, mask RAM, and TAG RAM. The read TAG generates an address for writing to main memory. Simultaneously, write the read data and mask back to main memory, and clear the mask of the replacement block to invalid. Wait for the write-back to complete, then start the replacement algorithm module. If no dirty flag is present, directly start the replacement algorithm module, read the data from main memory, and store the main memory data into the data RAM according to the replacement algorithm. The mask is stored as fully valid. After the replacement is complete, return the read data and mask.

[0049] 1.4) If the read request mask is missing, the update logic module is activated. It reads data from main memory and generates a write data enable signal for the write data RAM based on the offset of the read address. This ensures that the replaced data does not overwrite the originally written data. The data read from main memory is then written to the path group data RAM corresponding to the TAG hit, based on the generated write data enable signal. Simultaneously, the corresponding data read from main memory and the data in the data RAM are used to generate the complete data for that address based on the mask information. The read data and the corresponding mask are then returned.

[0050] 2) The cache receives a write request:

[0051] 2.1) First, start the TAG comparison logic module and read the data from four TAG marker registers, four mask RAMs, and four data RAMs according to the index; then, based on the read TAG data, determine whether the TAG is hit. If the TAG is hit and the data block is valid, it means that the current write request is hit; otherwise, it means that the current write request is missing.

[0052] 2.2) If a write request is hit, write the data and mask into the corresponding data RAM and mask RAM;

[0053] 2.3) If a write request is missing, first check the dirty bit flag of the data block read from the TAG flag register. If a dirty bit is found, initiate the write-back logic module. Based on the replacement algorithm, read the data RAM, mask RAM, and TAG flag register. The read TAG generates the address for writing to main memory. Simultaneously, write the read data and mask back to main memory, and clear the mask of the replacement block to invalid. After the write-back is complete, write the data and mask into the corresponding data RAM and mask RAM. If there is no dirty bit, directly write the data and mask into the corresponding data RAM and mask RAM.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A mask-based GPU pixel flow Cache read-write access system, characterized in that: The system includes a TAG comparison logic module, a replacement algorithm module, a write-back logic module, and an update logic module. The TAG comparison logic module is connected to the replacement algorithm module, the write-back logic module, and the update logic module, respectively. The replacement algorithm module is connected to the write-back logic module and the update logic module, respectively. The write-back logic module is connected to the update logic module. The TAG comparison logic module includes a TAG RAM, a mask RAM, and a byte-enabled data RAM. The TAG RAM stores the TAG, data block valid bits, and data block dirty bits. The TAG comparison logic module performs read / write control of the TAG RAM, mask RAM, and data RAM, and determines cache read / write operations hit or miss operations. The processing procedure for read / write operations in the TAG comparison logic module is as follows: Read request: First, read data from TAG RAM, mask RAM, and data RAM based on the index; then, determine whether the TAG is hit based on the read TAG data. In addition, it is necessary to check the mask hit based on the TAG hit. If the TAG is hit, the data block is valid, and the mask is hit, the current read request is hit. If the TAG is missing, the current read request is missing. If the TAG is hit, the data block is valid, and the mask is missing, the current read request mask is missing. Write request: First, read data from TAG RAM, mask RAM, and data RAM based on the index; Then, based on the read TAG data, it is determined whether the TAG is hit. If the TAG is hit and the data block is valid, it means that the current write request is hit; otherwise, it means that the current write request is missing. If a read request is hit, select the output data and mask from the multiple read data based on the hit road number; If a write request is hit, the data and mask are directly written to the data RAM and mask RAM based on the hit road group number. If a read request is missing, first check the dirty bit flag of the data block read from TAG RAM. If there is a dirty bit, start the write-back logic module, wait for the write-back to finish, and then start the replacement algorithm module. If there is no dirty bit, start the replacement algorithm module directly. After the replacement is completed, return the read data and mask. If the read request mask is missing, the update logic module is started. It generates complete address data based on the mask information by combining the corresponding data read from main memory and the data in data RAM, and returns the read data and the corresponding mask. If a write request is successful, the data and mask are written to the corresponding data RAM and mask RAM. If a write request is missing, the dirty bit flag of the data block read from the TAG RAM is checked first. If a dirty bit is found, the write-back logic module is started. After the write-back is completed, the data and mask are written into the corresponding data RAM and mask RAM. If there is no dirty bit, the data and mask are directly written into the corresponding data RAM and mask RAM.

2. The mask-based GPU pixel flow Cache read-write access system of claim 1, wherein: The replacement algorithm module uses a pseudo least recently used algorithm to generate the block number that needs to be replaced when a read / write miss occurs.

3. The mask-based GPU pixel flow Cache read-write access system of claim 2, wherein: When a read / write request is missing and there are dirty bits, the write-back logic module reads the data RAM, mask RAM, and TAG RAM according to the replacement algorithm. The read TAG generates an address for writing to main memory, and at the same time, the read data and mask are written back to main memory, and the mask of the replacement block is cleared as invalid.

4. The mask-based GPU pixel flow Cache read-write access system of claim 3, wherein: When the read mask is missing, the update logic module reads the data from the main memory and stores the data from the main memory into the data RAM according to the replacement algorithm, so that the mask is stored as fully valid.

5. The mask-based GPU pixel flow Cache read-write access system of claim 3, wherein: When the read mask is missing, the update logic module reads data from the main memory and generates a write data enable signal for the write data RAM based on the offset bit of the read address. This ensures that the replaced data does not overwrite the originally written data. The data read from the main memory is then written into the road group data RAM of the TAG hit according to the generated write data enable signal.

6. A method for implementing the mask-based GPU pixel stream cache read / write access system as described in claim 1, characterized in that: The method includes the following steps: 1) The cache receives a read request: 1.1) First, start the TAG comparison logic module to read data from four TAG RAMs, four mask RAMs, and four data RAMs according to the index; then, determine whether the TAG is hit based on the read TAG data. In addition, it is necessary to check the mask hit based on the TAG hit. If the TAG is hit, the data block is valid, and the mask is hit, it means that the current read request is hit. If the TAG is missing, it means that the current read request is missing. If the TAG is hit, the data block is valid, and the mask is missing, it means that the current read request mask is missing. 1.2) If a read request is hit, select the output data and mask from the four read data based on the hit road number; 1.3) If a read request is missing, first check the dirty bit flag of the data block read from TAG RAM. If a dirty bit is present, start the write-back logic module. According to the replacement algorithm, read the data RAM, mask RAM, and TAG RAM. The read TAG generates an address for writing to main memory. At the same time, write the read data and mask back to main memory and clear the mask of the replacement block to invalid. Wait for the write-back to finish and start the replacement algorithm module. If there is no dirty bit, start the replacement algorithm module directly, read the data from main memory, and store the data from main memory into the data RAM according to the replacement algorithm. Store the mask as fully valid. After the replacement is completed, return the read data and mask. 1.4) If the read request mask is missing, the update logic module is started, reads the data from the main memory, generates a write data enable signal for the write data RAM based on the offset of the read address, so that the replaced data does not overwrite the originally written data. The data read from the main memory is written to the path group data RAM of the TAG hit according to the generated write data enable signal; at the same time, the corresponding data read from the main memory and the data in the data RAM are used to generate the complete data at that address based on the mask information, and the read data and the corresponding mask are returned. 2) The cache receives a write request: 2.1) First, start the TAG comparison logic module and read the data from four TAG RAMs, four mask RAMs, and four data RAMs according to the index; then, based on the read TAG data, determine whether the TAG is hit. If the TAG is hit and the data block is valid, it means that the current write request is hit; otherwise, it means that the current write request is missing. 2.2) If a write request is hit, the data and mask are written to the corresponding data RAM and mask RAM; 2.3) If a write request is missing, first check the dirty bit flag of the data block read from the TAG RAM. If there is a dirty bit, start the write-back logic module. According to the replacement algorithm, read the data RAM, mask RAM and TAG RAM. The read TAG generates the address to write to main memory. At the same time, write the read data and mask back to main memory and clear the mask of the replacement block as invalid. After the write-back is completed, write the data and mask into the corresponding data RAM and mask RAM. If there is no dirty bit, write the data and mask directly into the corresponding data RAM and mask RAM.

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