Memory fault processing method, baseboard management controller and computing system

Abstract

Embodiments of the present application disclose a memory fault processing method, a baseboard management controller and a computing system. The method comprises: receiving correctable error (CE) information of a memory; obtaining CE analysis information according to the CE information; in response to a first trigger signal, saving the CE analysis information to a buffer of the baseboard management controller, wherein the first trigger signal is used to indicate to stop outputting the CE analysis information; and in response to a second trigger signal, outputting the CE analysis information in the buffer, wherein the second trigger signal is used to indicate to output the CE analysis information. The method of the embodiments of the present application reduces the risk that the computing system is interrupted or down due to the fact that the CE information is not processed after the self-healing function is closed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a memory fault processing method, a baseboard management controller and a computing system. BACKGROUND

[0002] With the development of computer technology, the required memory capacity is getting larger and larger, and the basic failure rate is getting higher and higher. Server manufacturers have introduced memory fault prediction and self-healing functions. The prediction and self-healing process includes: after the memory controller detects the correctable error (CE) of the memory, the memory error is reported to the baseboard management controller (BMC) through the basic input / output system (BIOS); the BMC determines the error type and submits a fault isolation request to the BIOS for error repair.

[0003] But if the frequent repair will affect the performance of the computing system. In actual use, users can turn off the self-healing function based on the use demand or periodically, which will lead to the CE error not being processed or not being processed in time, and increase the possibility of computing system downtime. SUMMARY

[0004] The present application provides a memory fault processing method, a baseboard management controller and a computing system, which can reduce the risk of business interruption or downtime of the computing system caused by memory failure.

[0005] The first aspect of the present application provides a memory fault processing method, which comprises:

[0006] receiving correctable error (CE) information of the memory;

[0007] obtaining CE analysis information according to the CE information;

[0008] in response to a first trigger signal, saving the CE analysis information to a buffer area of the baseboard management controller; the first trigger signal is used to indicate to stop outputting the CE analysis information;

[0009] in response to a second trigger signal, outputting the CE analysis information in the buffer area; the second trigger signal is used to indicate to output the CE analysis information.

[0010] The application can avoid the problem that the CE information and the corresponding CE analysis information are not processed when the first trigger signal is triggered, resulting in insufficient samples during CE analysis, thereby improving the accuracy and coverage of memory repair, and reducing the risk of business interruption or downtime of the computing system caused by memory failure.

[0011] In a possible implementation, the buffer is used to save a first quantity of the CE analysis information; and the outputting the CE analysis information in the buffer in response to the second trigger signal comprises: outputting the first quantity of the CE analysis information in the buffer in response to the second trigger signal.

[0012] In a possible implementation, the storage space occupied by the buffer is of a fixed size; and the saving the CE analysis information to the buffer of the baseboard management controller comprises: deleting the CE analysis information stored in the buffer for the longest time when the available space of the buffer is insufficient to store the CE analysis information to be saved.

[0013] In a possible implementation, before the deleting the CE analysis information stored in the buffer for the longest time, the method further comprises: saving the CE analysis information stored for the longest time to a history record file.

[0014] In a possible implementation, the CE analysis information comprises a CE level used to indicate a risk level of the CE; and before the outputting the CE analysis information in the buffer, the method further comprises: sorting the CE analysis information in the buffer according to the CE level; and the outputting the CE analysis information in the buffer comprises: outputting the CE analysis information in the buffer in a descending order of the risk level.

[0015] In a possible implementation, the outputting the CE analysis information in the buffer in response to the second trigger signal comprises: outputting the CE analysis information in the buffer to a central processing unit (CPU) in response to the second trigger signal.

[0016] In a possible implementation, the outputting the CE analysis information in the buffer to the CPU comprises: sending a hardware isolation request carrying the CE analysis information in the buffer to the CPU, so that the BIOS calls the CPU to perform hardware isolation repair on the memory.

[0017] In a possible implementation, the sending of the CE analysis information in the buffer to a central processing unit (CPU) comprises: sending a software isolation request carrying the CE analysis information in the buffer to the CPU, so that an operating system (OS) calls the CPU to perform software isolation repair on the memory.

[0018] The second aspect of the present application provides a computing system, comprising a management device, the management device comprising a memory fault prediction and self-recovery system, the memory fault prediction and self-recovery system comprising an artificial intelligence (AI) module and a self-recovery module;

[0019] The AI module is configured to receive correctable error (CE) information of the memory.

[0020] The AI module is further configured to obtain CE analysis information according to the CE information.

[0021] The self-recovery module is configured to save the CE analysis information to a buffer of a baseboard management controller in response to a first trigger signal; the first trigger signal is used to indicate that the output of the CE analysis information is stopped.

[0022] The self-recovery module is further configured to output the CE analysis information in the buffer in response to a second trigger signal; the second trigger signal is used to indicate that the CE analysis information is output.

[0023] In a possible implementation, the buffer is used to save a first quantity of the CE analysis information; and the self-recovery module is specifically configured to: output the first quantity of the CE analysis information in the buffer in response to the second trigger signal.

[0024] In a possible implementation, the buffer occupies a storage space of a fixed size; and the self-recovery module is specifically configured to: when available space of the buffer is insufficient to store the CE analysis information to be saved, delete the CE analysis information with the earliest storage time in the buffer.

[0025] In a possible implementation, the self-recovery module is specifically further configured to save the CE analysis information with the earliest storage time to a history record file.

[0026] In a possible implementation, the CE analysis information comprises a CE level, the CE level being used to indicate a risk level of the CE; the self-recovery module is further configured to sort the CE analysis information in the buffer according to the CE level; and the self-recovery module is specifically configured to output the CE analysis information in the buffer in a descending order of the risk level.

[0027] In a possible implementation, the self-recovery module is specifically configured to: in response to the second trigger signal, output the CE analysis information in the buffer to the CPU.

[0028] In a possible implementation, the self-recovery module is specifically configured to: send, to the CPU, a hardware isolation request carrying the CE analysis information in the buffer, so that the BIOS invokes the CPU to perform hardware isolation repair on the memory.

[0029] In a possible implementation, the self-recovery module is specifically configured to: send, to the CPU, a software isolation request carrying the CE analysis information in the buffer, so that the OS invokes the CPU to perform software isolation repair on the memory.

[0030] The third aspect of the present application provides a baseboard management controller, which comprises:

[0031] a processor and a memory; the processor and the memory are coupled;

[0032] the memory is configured to store program instructions;

[0033] the processor is configured to execute the program instructions, so that the baseboard management controller performs the method in the first aspect.

[0034] The fourth aspect of the present application provides a computing system, which comprises a CPU, a memory, a BIOS chip and the baseboard management controller in the third aspect; the CPU is coupled with the memory, the BIOS chip and the baseboard management controller; and the OS runs on the CPU.

[0035] It should be understood that the implementation and beneficial effects of the above aspects can be referred to each other. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 a system framework diagram of a computing system 100 provided by an embodiment of the present application;

[0037] Figure 2 a flowchart of a memory fault processing method provided by an embodiment of the present application;

[0038] Figure 3 a structural diagram of a baseboard management controller 300 provided by an embodiment of the present application;

[0039] Figure 4 a structural diagram of a computing system 400 provided by an embodiment of the present application. DETAILED DESCRIPTION

[0040] With reference to the drawings, embodiments of the present application will be described. Obviously, the described embodiments are only a part but not all of the embodiments of the present application. Based on the description of the embodiments, those skilled in the art can know the technical solutions provided by the embodiments of the present application can be applied to similar technical problems.

[0041] The terms "first", "second", and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] Current memory prediction and healing process: the memory controller sends the detected CE information to the BIOS, the BIOS sends the CE information to the "memory fault prediction and self-healing" system of the BMC, the AI module of the system performs prediction and inference analysis, obtains CE analysis information and delivers it to the self-healing module, and the self-healing module submits specific fault isolation requests to the BIOS or operating system (OS) according to the CE analysis information.

[0043] The applicant found that when the user turns off the memory fault self-healing function (hereinafter referred to as the self-healing function), the following problems may exist:

[0044] (1) During the period when the self-healing function is turned off, if a large number of CEs occur, it may trigger the storm suppression mechanism of the BIOS, and during the storm suppression period, the BIOS will stop reporting CEs to the BMC; and the memory fault prediction and self-healing system cannot receive the CEs, which will cause the self-healing function to have no healing effect after being turned on again; (2) If the self-healing function has not been turned on, the CEs cannot be repaired in time after their occurrence, which will cause the self-healing effect to be poor. The above problems will cause the memory fault prediction result to be inaccurate, the self-healing effect to be poor, and the risk of business interruption or downtime of the computing system to increase.

[0045] Wherein, in a certain time period, a certain number of failures are called a storm of failures, which is the name of a failure aggregation in a computing system. When the computing system frequently isolates memory failures, it will affect the performance of the computing system; therefore, when the computing system confirms that a storm of failures has occurred, storm suppression will be triggered, that is, the BIOS will be shielded from reporting failures to avoid frequent processing of failures that cause business stalls or business interruptions.

[0046] To solve the above problems, the embodiments of the present application provide a memory failure processing method, which can reduce the risk of business interruption or downtime of a computing system caused by memory failure.

[0047] The memory failure processing method provided by the embodiments of the present application can be applied to Figure 1 The computing system 100 shown in the figure can be a server, a storage controller, a switch, a router, a base station controller, a computing offload card, a computing acceleration card, etc. The embodiments of the present application do not limit the specific form of the computing system. Figure 1 As shown in the figure, the computing system 100 includes a management device 110, a processor 120, a BIOS chip 130, a memory 150, and an OS 140 running on the processor 120. Figure 1

[0048] The management device 110 can be a management unit of a non-business module, and the management device 110 can also be called an out-of-band management device 110. For example, the management device 110 can perform remote maintenance and management on the computing system 100 through a dedicated data channel; the management device 110 is completely independent of the operating system of the computing system 100, and can communicate with the BIOS chip 130 and the OS 140 running in the processor 120 through the out-of-band management interface of the computing system 100.

[0049] After the computing system 100 is powered on, the processor 120 can be used to obtain the program code in the BIOS chip 130 and run it, and the processor 120 can implement part or all of the functions of the BIOS according to the program code.

[0050] ​Specifically, the management device 110 can be one or more of a combination of a management unit for a running state of the computing system 100, a management unit built in the processor 120, a management system in a management chip outside the processor, a baseboard management controller (BMC), a system management module (SMM), a management unit built in a business unit, or a device management system in an operating system, and the like. The embodiments of the present application do not limit the specific form of the management device, which is only exemplarily described herein.

[0051] The management device 110 includes a memory fault prediction and self-recovery system 1110, which is software running in the management device 110.

[0052] The memory fault prediction and self-recovery system 1110 includes an AI module 1111 and a self-recovery module 1112. The AI module 1111 is configured to receive CE information of the memory 150, and obtain corresponding CE analysis information according to the CE information through a machine learning algorithm, the CE analysis information including a fault feature mode and / or a memory repair technology; the AI module 1111 is further configured to send the CE analysis information to the self-recovery module 1112, and the self-recovery module 1112 is configured to output the CE analysis information to the processor 120.

[0053] Specifically, the self-recovery module 1112 can be configured to send a hardware isolation request or a software isolation request to the processor 120 according to the isolation repair technology indicated by the CE analysis information.

[0054] The processor 120 is a central processing unit (CPU) in the computing system 100, and can also be configured to trigger the BIOS chip 130 or the OS 140 to repair the memory 150 according to the CE analysis information or the two isolation requests.

[0055] Specifically, the BIOS chip 130 or the BIOS function running in the processor 120 can call the CPU to perform hardware isolation repair on the memory 150, and the OS 140 can call the CPU to perform software isolation repair on the memory 150.

[0056] It can be understood that when the BIOS function or the OS runs in other processing units, the self-recovery module 1112 can also output the CE analysis information to the corresponding processing units.

[0057] Specifically, the AI module 1111 can be configured to receive fault information sent by the processor 120.

[0058] Optionally, the AI module 1111 is specifically configured to determine, in combination with the CE information and historical CE information of the memory, whether the current CE information satisfies the condition of a certain fault feature mode, and generate a fault feature mode code for the current memory, the fault feature mode code being used to indicate which fault feature mode conditions the current memory satisfies; and based on one or more fault feature mode codes, predict the fault feature mode of the memory and the probability of each fault feature mode leading to a system-level fault by using a machine learning algorithm, and determine the fault feature mode of the memory based on the probability of each fault feature mode leading to a system-level fault.

[0059] When the self-healing function is turned off, the self-healing module 1112 does not submit the CE analysis information to the processor 120, and saves the CE analysis information to the buffer.

[0060] Optionally, the computing system 100 can control the turning on and off of the self-healing function through a physical switch or a virtual switch; specifically, the computing system 100 can trigger a first trigger signal and a second trigger signal according to the state of the physical switch or the virtual switch, the first trigger signal being used to indicate that the self-healing function is turned off, and the self-healing module 1112 stops outputting the CE analysis information; the second trigger signal being used to indicate that the self-healing function is turned on, and the self-healing module 1112 outputs the CE analysis information.

[0061] Optionally, the buffer can be a temporary file generated by the memory fault prediction and self-healing system 1110.

[0062] Optionally, the buffer can be arranged in the management device 110.

[0063] Optionally, the storage space occupied by the buffer has a fixed size; the self-healing module 1112 is specifically configured to delete the CE analysis information stored in the buffer for the longest time when the available space of the buffer is insufficient to store the to-be-saved CE analysis information; and save the to-be-saved CE analysis information to the buffer when the available space of the buffer is sufficient to store the to-be-saved CE analysis information.

[0064] Optionally, the self-healing module 1112 is further configured to save the CE analysis information stored for the longest time to a historical fault record file in the memory 150, and then delete the CE analysis information stored for the longest time from the buffer.

[0065] Optionally, the buffer is used to save a first number of CE analysis information; the self-healing module 1112 is specifically configured to output the first number of CE analysis information in the buffer to the processor 120 in response to the second trigger signal.

[0066] Optionally, when the total number of CE analysis information saved to the buffer reaches a second number, the self-healing module 1112 outputs an alarm information.

[0067] Optionally, after the self-recovery function is started, the self-recovery module 1112 processes the CE analysis information in the buffer first, and then processes the CE analysis information sent by the AI module 1111 after the self-recovery function is started.

[0068] Optionally, the CE analysis information further includes a CE level, the CE level being used to indicate a risk level of the CE; and the self-recovery module 1112 can be further used to sort the CE analysis information in the buffer according to the CE level, and then output the CE analysis information in the buffer in a descending order of the risk level.

[0069] The processor 120 includes a memory controller 1210. The memory controller 1210 is used to detect whether a memory fault occurs in the memory 150; when detecting that a CE occurs in the memory 150, the memory controller 1310 can send the corresponding CE information to the BIOS chip 130.

[0070] The BIOS chip 130 is used to report the CE information sent by the memory controller 1210 to the AI module 1111.

[0071] The memory 150 can be a running memory of the computing system 100. The memory 150 in the computing system 100 can be one or more, and the memory 150 can be a dynamic random access memory (DRAM).

[0072] Specifically, the memory 150 can be one or more dual inline memory modules (DIMM).

[0073] The OS 140 is an operating system of the computing system 100, and is used to repair the memory by using a corresponding software isolation repair technology according to the received isolation request.

[0074] It should be noted that, in a specific implementation, the computing system 100 can be any device including Figure 1 a similar structure. The embodiments of the present application do not limit the specific component structure of the computing system 100. In addition, Figure 1 the component structure shown in the embodiments of the present application does not constitute a limitation on the computing system 100. In addition to Figure 1 the components shown in the embodiments of the present application, the computing system 100 can include more or less components, or combine certain components, or different arrangement of components.

[0075] Based on the computing system shown in Figure 1 , please refer to Figure 2 , Figure 2 a flowchart of a memory fault processing method provided by the embodiments of the present application, the method including steps 201 to 204.

[0076] Step 201, the management device receives CE information of the memory.

[0077] Before step 201, the memory controller in the computing system detects the occurrence of CE in the memory, obtains the corresponding CE information, and reports the CE information to the management device through the processor.

[0078] Specifically, in a possible implementation, the management device receiving the CE information of the memory can include the management device receiving fault information sent by the CPU or the BIOS of the computing system. It can be understood that in some other embodiments, the management device can also receive CE information sent by other processors having a connection relationship with the memory.

[0079] The CE information is related information when the memory runs CE, and can specifically include the state of the CE, the occurrence time of the CE, the error number of the CE, the physical address information of the CE, the error number of the memory inspection, the error row address of the memory inspection, the error column address of the memory inspection, and the most error row address of the memory inspection. The embodiments of the present application are not limited to the specific content of the CE information, which is only exemplarily described herein.

[0080] The physical address information in the above fault information is used to indicate the physical location of the memory corresponding to the memory fault. That is, based on the physical address information, the specific physical location of the memory fault in the memory can be determined. For example, the physical address information can include one or more of CPU node number, channel number, DIMM slot number, logical rank number, bank group number, bank number, row number, column number, chip particle number, or bit position. The embodiments of the present application are not limited to the specific content of the physical address information, which is only exemplarily described herein.

[0081] Step 202, the management device obtains CE analysis information according to the CE information.

[0082] The management device can input the CE information into a machine learning algorithm to obtain CE analysis information output by the machine learning algorithm.

[0083] The CE analysis information includes fault feature patterns and / or memory repair techniques.

[0084] Exemplarily, the failure characteristic pattern of the memory can include one or more of a page failure pattern, a single bit failure pattern, a Cell failure pattern, a row failure pattern, a column failure pattern, a Bank failure pattern, a Device failure pattern, a Rank failure pattern, a channel failure pattern, a dual in-line memory module (DIMM) failure pattern, a few persistent error failure pattern, a short time burst of a large number of errors failure pattern, and the like. Embodiments of the present application are not limited to the specific granularity of the failure characteristic pattern of the memory, which is exemplarily described herein. With the advancement of technology, there can be finer or coarser granularity of the failure characteristic pattern in the future.

[0085] It can be understood that, for a certain failure characteristic pattern, the management device can determine a corresponding memory repair technology to achieve the best repair effect.

[0086] Exemplarily, the memory repair technology determined by using the machine learning algorithm can be a hardware isolation repair technology or a software isolation repair technology, and embodiments of the present application are not limited thereto.

[0087] For example, the hardware isolation repair technique can include one or more of bit isolation replacement, Cell isolation replacement, Row isolation replacement, column isolation replacement, Bank isolation replacement, Device isolation replacement, Rank isolation replacement, channel isolation replacement, single device data correction (SDDC), single device error correction (SDEC), adaptive double device data correction-multiple region (ADDDC-MR), adaptive data correction-single region (ADC-SR), adaptive double device error correction (ADDEC), partial cache line sparing (PCLS), adaptive cache line sparing (ACLS), hardware post-package repair (HPPR), software post-package repair (SPPR), post-package repair (PPR), or a hardware isolation repair technique that replaces a specific address range of memory. Embodiments of the present application are not limited to the specific feature modes of the hardware isolation repair technique, which are merely exemplary.

[0088] For example, the software isolation repair technique can include one or more of page isolation, address isolation, process isolation, or a software isolation repair technique that replaces a specific address range of memory. Embodiments of the present application are not limited to the specific feature modes of the software isolation repair technique, which are merely exemplary.

[0089] Exemplarily, the machine learning algorithm described above can include a threshold decision-based algorithm, a decision tree algorithm, a supervised machine learning algorithm, an unsupervised machine learning algorithm, a memory pin chain link detection algorithm, etc. For example, the management module can determine the failure feature mode of the memory or the isolation repair technology adopted by the memory for repair based on a decision tree algorithm, a random forest algorithm, or a neural network algorithm. The embodiments of the present application are not limited to the specific feature mode of the machine learning algorithm used to determine the failure feature mode of the memory or the isolation repair technology adopted by the memory for repair, which is only exemplarily described herein.

[0090] In a possible implementation, after the management device receives the CE information of the memory through step S201, the management device obtains the failure feature mode corresponding to the CE according to the CE information, which can include: the management device combines the CE information and the historical failure information of the memory, sequentially judges whether the CE information of the current memory satisfies the condition of a certain failure feature mode, and generates a failure feature mode code for the current memory, the failure mode code being used to indicate which failure feature mode conditions the current memory satisfies; the management device predicts the feature mode of the memory failure and the probability of each failure feature mode leading to system-level failure based on the machine learning algorithm and multiple failure feature mode codes, and determines the failure feature mode of the memory based on the probability of each failure feature mode leading to system-level failure.

[0091] The historical failure information is the failure information received by the management device before receiving the failure information.

[0092] It can be understood that the specific implementation of the management device in step S202 based on the CE information and using the machine learning algorithm to determine the corresponding memory repair technology is similar to the implementation of the management device based on the CE information and using the machine learning algorithm to determine the corresponding failure feature mode, which will not be described herein.

[0093] Specifically, step 202 is performed by an AI module in the memory failure prediction and self-recovery system.

[0094] Step 203, in response to the first trigger signal, the management device saves the CE analysis information to the buffer area of the BMC.

[0095] In the computing system of the embodiment, a self-recovery switch is provided, which is used to control the opening or closing of the self-recovery function. When the self-recovery switch is closed, the self-recovery module in the memory failure prediction and self-recovery system suspends the output of the CE analysis information.

[0096] The self-recovery switch can be a physical hardware switch or a virtual software switch. The self-recovery switch can be arranged in the management device, in the BIOS, or in other hardware modules or software modules in the computing system. Embodiments of the present application do not limit the location and attribute of the self-recovery switch.

[0097] The computing system can send a first trigger signal or a second trigger signal to the management device according to the switch state of the self-recovery switch, to control whether the self-recovery module in the management device outputs the CE analysis information to the processor. Specifically, the first trigger signal is used to instruct the self-recovery module to stop outputting the CE analysis information, and the second trigger signal is used to instruct the self-recovery module to output the CE analysis information.

[0098] The buffer area can be a preset buffer area in the BMC or a temporary buffer area divided by the BMC, and can be a temporary file generated by the BMC. In a possible implementation, the management device can save the CE analysis information, such as the fault feature mode and / or the memory repair technology, to the temporary file.

[0099] In a possible implementation, the storage space occupied by the buffer area has a fixed size. When the available space of the buffer area is insufficient to store the to-be-saved CE analysis information, the management device deletes the CE analysis information stored in the buffer area for the longest time. When the available space of the buffer area is sufficient to store the to-be-saved CE analysis information, the management device saves the to-be-saved CE analysis information to the buffer area.

[0100] Specifically, when the self-recovery module receives new CE analysis information, the management device first determines whether the available space of the buffer area is greater than the size of the CE analysis information. If not, the management device deletes the CE analysis information stored in the buffer area for the longest time, and again determines whether the available space of the buffer area is greater than the size of the CE analysis information, until the available space of the buffer area is greater than the size of the CE analysis information. If yes, the to-be-saved CE analysis information is saved to the buffer area.

[0101] By limiting the size of the buffer area and updating the CE analysis information in the buffer area according to the storage time, the system resources of the management device can be prevented from being excessively occupied. It can be understood that an unprocessed memory fault can derive or evolve into a new memory fault. Therefore, by updating the CE analysis information in the buffer area, the computing system can be repaired according to the latest CE analysis information of the memory after the self-recovery switch is turned on, the risk of downtime of the computing system can be reduced as quickly as possible, and invalid repeated repair can be avoided.

[0102] In a possible implementation, before the management apparatus deletes the CE analysis information with the earliest storage time, the method further includes: saving the CE analysis information with the earliest storage time to a historical fault record file.

[0103] The historical fault record file is used to record the fault analysis result of the machine learning algorithm of the management apparatus, and the historical fault record file can be stored in the memory of the computing system or in the memory of the management apparatus.

[0104] By saving the unprocessed CE analysis information in the historical fault record file, the sample of the machine learning algorithm can be increased, and the accuracy of the machine learning algorithm can be improved.

[0105] In a possible implementation, the buffer is used to save a first quantity of CE analysis information; and outputting the CE analysis information in the buffer in response to the second trigger signal includes: in response to the second trigger signal, the management apparatus outputs the first quantity of CE analysis information in the buffer.

[0106] The first quantity can be a quantity threshold set according to the performance of the computing system. It can be understood that when the computing system performs frequent error correction, a large amount of system resources will be occupied, affecting the performance of the system

[0107] The CE analysis information can be information of a fixed size.

[0108] The first quantity of CE analysis information is saved in the buffer, and when the self-recovery switch is turned on again, the self-recovery module in the management apparatus can process the first quantity of CE analysis information in the buffer and submit a corresponding fault isolation request to the BIOS. By limiting the buffer to save the first quantity of CE analysis information, it can be avoided that too much unprocessed CE analysis information is accumulated when the self-recovery switch is turned off, so that the computing system performs frequent error correction when the self-recovery switch is turned on, occupies too many resources, and affects the performance of the system.

[0109] It can be understood that the storm suppression mechanism exists to prevent the computing system from performing too frequent error correction and affecting the performance of the system, so when the BIOS receives more than a certain quantity threshold of CEs within a certain time, the BIOS will stop reporting CEs to the management apparatus to control the frequency of error correction of the computing system. By controlling the quantity of CE analysis information cached in the buffer, the embodiment of the present application can also achieve the effect of controlling the error correction frequency, while also being able to normally receive the CEs reported by the BIOS, and in combination with the historical fault record file, the machine learning algorithm of the AI module has sufficient algorithm quantity, the prediction accuracy is higher, and the latest CE analysis information is processed after the self-recovery switch is turned on, so that the healing effect is better.

[0110] In a possible implementation, when the total amount of the CE analysis information saved to the buffer reaches a second amount, the management apparatus outputs alarm information.

[0111] The second amount is greater than the first amount.

[0112] By outputting the alarm information when the CE analysis information reaches the second amount after detecting that the self-recovery switch is closed, the user can timely open the self-recovery switch to process the accumulated memory faults, thereby reducing the risk of service interruption or downtime of the computing system.

[0113] Step 204: In response to the second trigger signal, the management apparatus outputs the CE analysis information in the buffer.

[0114] The management apparatus can output the CE analysis information to a processor running BIOS or OS, so that the BIOS or OS on the processor invokes the processor to perform memory repair for the CE. For example, when the BIOS runs independently on a BIOS chip, the management apparatus can output the CE analysis information to the BIOS chip. It can be understood that when the BIOS or the OS runs on a CPU, the management apparatus outputs the CE analysis information to the CPU.

[0115] In a possible implementation, the management apparatus can determine a memory repair technology according to the CE analysis information, and send an isolation request to the CPU to repair the memory according to the memory repair technology; wherein the memory repair technology can include a hardware isolation repair technology and a software isolation repair technology; wherein the isolation request can include a hardware isolation request and a software isolation request, and the isolation request carries the CE analysis information.

[0116] Hardware isolation refers to locally isolating the fault region by using the underlying memory resource of the CPU. For example, the redundant space of the CPU can be used to replace the fault region, thereby locally isolating the fault region.

[0117] Software isolation refers to isolating the region where the memory error occurs at the OS layer. For example, for memory page isolation (page offline), the OS layer can terminate the process using the memory page, or the OS layer can close the application using the memory page.

[0118] Specifically, the management apparatus can send a hardware isolation request corresponding to the hardware isolation repair technology to the CPU. It can be understood that when the CPU receives the hardware isolation request, the BIOS will invoke the CPU to perform the corresponding hardware isolation operation.

[0119] Specifically, the management device can submit a software isolation request corresponding to the software isolation repair technology to the CPU. It can be understood that when the CPU receives the software isolation request, the OS will call the CPU to perform the corresponding software isolation operation.

[0120] Wherein, the BIOS or the OS runs on the CPU, when the CPU receives the isolation request, the CPU can instruct the BIOS or the OS to perform the corresponding isolation operation according to the isolation request, and then the BIOS or the OS calls the CPU to repair the memory.

[0121] In another possible implementation, the management device outputs the CE analysis information in the buffer to the CPU. The CPU triggers the BIOS to call the CPU to perform hardware isolation repair on the memory according to the isolation repair technology determined by the CE analysis information; or, triggers the OS to call the CPU to perform software isolation repair on the memory.

[0122] In a possible implementation, after the management device processes the CE analysis information in the buffer, the method further includes: in response to a second trigger signal, outputting the CE analysis information obtained after the self-healing switch is turned on to the processor.

[0123] In a possible implementation, the CE analysis information further includes a CE level; the management device sorts the CE analysis information in the buffer according to the CE level; and then outputs the CE analysis information in the buffer to the processor in the order from high to low according to the risk level.

[0124] Wherein, the CE level is used to indicate the risk level of the CE. Specifically, the greater the harm of the CE to the computing system, the higher the CE level.

[0125] In the process of processing the CE analysis information by the self-healing module, if new CE analysis information sent by the AI module is received, the CE analysis information is added to the queue of the sorting result according to the fault level of the new CE analysis information. It can be understood that the processed CE analysis information will be deleted from the queue.

[0126] It can be understood that the processed CE analysis information will be saved to the historical fault record file.

[0127] By processing the CE analysis information to be processed in turn according to the size of the harm degree, the risk of business interruption or downtime of the computing system can be reduced.

[0128] The embodiments of the present application can save the CE analysis information to the buffer when the first trigger signal indicating to stop outputting the CE analysis information is triggered, and process the CE analysis information in the buffer to request to repair the memory when the second trigger signal indicating to output the CE analysis information is triggered, so as to avoid the problem that the CE information and the corresponding CE analysis information are not processed when the first trigger signal is triggered, and the sample is insufficient when the CE analysis is performed, thereby improving the accuracy and coverage of the memory repair, and reducing the risk of business interruption or downtime of the computing system.

[0129] Please refer to Figure 3 The embodiments of the present application also provide a baseboard management controller 300, which can be used as the management device in the above embodiments, and is used to implement the method and function of the management device in the above embodiments.

[0130] As Figure 3 shown, the baseboard management controller 300 includes a processor 301 and a memory 302, and the processor 301 and the memory 302 are coupled.

[0131] The memory 302 is configured to store program instructions.

[0132] The processor 301 is configured to execute the program instructions in the memory 302, so that the baseboard management controller 300 performs the processing method of the memory fault as Figure 2 provided.

[0133] Specifically, the processor 301 can be used to support the communication with the BIOS and the OS in the above embodiments.

[0134] As Figure 4 shown, a structural schematic diagram of a computing system 400 provided by the embodiments of the present application is shown. The computing system 400 includes a central processor 401, a memory 402, a bus 403, a BIOS chip 404 and a baseboard management controller 405; the central processor 401 and the memory 402, the BIOS chip 404 and the baseboard management controller 405 are coupled; and the central processor 401 runs an operating system OS. The central processor 401, the memory 402, the BIOS 404 chip and the baseboard management controller 405 are connected to each other through the bus 403. The baseboard management controller 405 can be the baseboard management controller structure and function as Figure 3 shown.

[0135] The central processing unit 401 can be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array, or other programmable logic device, transistor logic, hardware components, or any combination thereof. It can implement or execute the various exemplary logical blocks, modules, and circuits described in connection with the disclosure. The processor can also be a combination of computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like. The bus 403 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, Figure 4 Only one thick line is used in the figure to represent the bus, but it does not mean that there is only one bus or only one type of bus.

[0136] In another embodiment of the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores computer execution instructions. When at least one processor of the device executes the computer execution instructions, the device executes the memory failure processing method described in the above Figure 2 embodiments.

[0137] In another embodiment of the present application, a computer program product is also provided, and the computer program product includes computer execution instructions stored in a computer readable storage medium. At least one processor of the device can read the computer execution instructions from the computer readable storage medium, and the at least one processor executes the computer execution instructions to make the device execute the memory failure processing method described in the above Figure 2 embodiments.

[0138] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0139] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0140] In several embodiments provided by the embodiments of the present application, it should be understood that the disclosed system, device and method can be implemented by other manners. For example, the device embodiments described above are merely illustrative, for example, the division of the units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0141] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place or distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0142] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit.

[0143] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application essentially or the parts of the technical solutions that make contributions to the prior art or the parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

Claims

1. A method for handling memory faults, characterized in that, The method includes: Receive correctable error (CE) information from memory; Based on the CE information, CE analysis information is obtained; In response to a first trigger signal, the CE analysis information is saved to the buffer of the substrate management controller; the first trigger signal is used to indicate that the output of the CE analysis information is stopped; the first trigger signal is used to indicate that the self-healing function is turned off. In response to the second trigger signal, the CE analysis information in the buffer is output; the second trigger signal is used to indicate the output of the CE analysis information; the second trigger signal is used to indicate that the self-healing function is enabled, and when the self-healing function is disabled, the self-healing module does not submit CE analysis information to the processor. The CE analysis information includes a CE level, which indicates the risk level of the CE; before outputting the CE analysis information in the buffer, the method further includes: Sort the CE analysis information in the buffer according to the CE level; The output of the CE analysis information in the buffer includes: The CE analysis information in the buffer is output in descending order of risk level.

2. The method according to claim 1, characterized in that, The buffer is used to store a first quantity of the CE analysis information; The response to the second trigger signal, outputting the CE analysis information in the buffer, includes: In response to the second trigger signal, the first number of CE analysis information in the buffer is output.

3. The method according to claim 1 or 2, characterized in that, The buffer occupies a fixed amount of storage space; the step of saving the CE analysis information to the buffer of the substrate management controller includes: When the available space in the buffer is insufficient to store the CE analysis information to be saved, the earliest stored CE analysis information in the buffer is deleted.

4. The method according to claim 3, characterized in that, Before deleting the earliest CE analysis information stored in the buffer, the method further includes: The earliest stored CE analysis information is saved to the history file.

5. The method according to any one of claims 1, 2, or 4, characterized in that, The response to the second trigger signal, outputting the CE analysis information in the buffer, includes: In response to the second trigger signal, the CE analysis information in the buffer is output to the central processing unit (CPU).

6. The method according to claim 5, characterized in that, The step of outputting the CE analysis information in the buffer to the central processing unit (CPU) includes: A hardware isolation request carrying the CE analysis information in the buffer is sent to the CPU, so that the BIOS of the Basic Input / Output System calls the CPU to perform hardware isolation repair on the memory.

7. The method according to claim 5, characterized in that, Sending the CE analysis information in the buffer to the central processing unit (CPU) includes: A software isolation request carrying the CE analysis information in the buffer is sent to the CPU, so that the operating system OS calls the CPU to perform software isolation repair on the memory.

8. A baseboard management controller, characterized in that, The substrate management controller includes: Processor and memory; the processor and the memory are coupled; The memory is used to store program instructions; The processor is used to run the program instructions, causing the substrate management controller to perform the method of any one of claims 1 to 7.

9. A computing system, characterized in that, The computing system includes a central processing unit (CPU), memory, a BIOS chip, and a baseboard management controller as described in claim 8; the CPU is coupled to the memory, the BIOS chip, and the baseboard management controller; and an operating system (OS) runs on the CPU.

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