A fool-proof device and method for flip chip on board

Abstract

The application provides a fool-proof device and method for on-board chip inversion, which comprises a detection circuit and a switching circuit. The detection circuit is connected with one pin A of a chip. The detection circuit is also connected with another pin A' of the chip through the switching circuit. The another pin A' is a corresponding pin of the one pin A after the chip is inverted. The detection circuit detects the impedance of the input pin to determine whether the chip is inverted. If the chip is inverted, the switching circuit switches the connection with the one pin A to the another pin A'. The application detects the chip inversion by using the different impedance between the pins. After detecting the chip inversion, the application switches to the connection with the correct pin to achieve the effect of correctly installing the pin even if the chip is inverted. The loss caused by the chip inversion is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board, in particular to a foolproof device and method for chip inversion on board. BACKGROUND

[0002] In modern electronic devices, chips with various functions are the basic components of the entire device. For some complex systems, it even needs up to thousands of chips to work in coordination.

[0003] When placing the circuit board device, especially for geometrically symmetrical chips, chip inversion placement is prone to occur. The inverted chip on the board perfectly blends into its original position, and it is difficult to find at first. When the circuit is powered on and debugging is unsuccessful, it is often too late to find the chip inversion.

[0004] For key chips in the system such as SPI ROM (read-only memory for storing UEFI BIOS firmware Bin file) storing BIOS (Basic Input / Output System), in the most serious case, it may cause damage to the device, chip or both. SUMMARY

[0005] The present application provides a foolproof device and method for chip inversion on board, which solves the problem of loss caused by the inability to discover chip inversion on the existing circuit board in time.

[0006] To achieve the above purpose, the present application adopts the following technical solutions:

[0007] The first aspect of the present application provides a foolproof device for chip inversion on board, which comprises a detection circuit and a switching circuit. The detection circuit is connected to one pin A of the chip. The detection circuit is also connected to another pin A' of the chip through the switching circuit. The other pin A' is the corresponding pin of the one pin A after the chip is inverted.

[0008] The detection circuit detects the impedance of the input pin to determine whether the current chip is inverted.

[0009] If so, the connection with the one pin A is switched to the other pin A' through the switching circuit.

[0010] Further, the foolproof device further comprises a latch circuit, which is connected to the detection circuit and the switching circuit respectively. After the detection circuit detects the chip inversion, the signal is latched to maintain the switching state.

[0011] Further, the detection circuit comprises a detection impedance and a comparator. The two ends of the detection impedance are respectively connected to the two input ends of the comparator. The output end of the comparator is connected to the switching circuit.

[0012] Further, the switching circuit comprises a logic OR circuit and a transistor Q1, one input end of the logic OR circuit is connected to the base of the transistor Q1, the collector of the transistor is connected to one end of the detection impedance, and the collector is connected to another pin A' of the chip.

[0013] Further, the switching circuit further comprises a logic NOT circuit and a transistor Q2, the input end of the logic NOT circuit is connected to the latch circuit, the output end is connected to the base of the transistor Q2, the collector of the transistor Q2 is connected to one end of the detection impedance, and the emitter is connected to one pin A of the chip.

[0014] Further, the latch circuit comprises a transistor Q3, the collector of the transistor Q3 is connected to the power supply, the base is connected to the input end of the logic NOT gate, and the emitter is connected to the other input end of the logic OR gate.

[0015] Further, the chip is a center-symmetrical chip, or the chip is a square shape, and the number of pins of each side of the square is the same and arranged the same.

[0016] The second aspect of the present application provides a fool-proof method for on-board chip inversion, the method comprising the following steps:

[0017] The impedance of the input pin of the chip is detected by the detection circuit to determine whether the current chip is inverted;

[0018] If yes, the connection with one pin A is switched to another pin A' by the switching circuit.

[0019] Further, the detection of the impedance of the input pin of the chip by the detection circuit to determine whether the current chip is inverted is specifically:

[0020] The two ends of the impedance are respectively connected to the two input ends of the comparator, and whether the chip is inverted is determined based on the high and low of the level of the output end of the comparator.

[0021] Further, the switching of the connection with one pin A to another pin A' by the switching circuit is specifically:

[0022] When the output end of the comparator outputs a preset level value, the connection of the input end of the chip with the another pin A' is triggered.

[0023] The effects provided in the summary are only the effects of the embodiments, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:

[0024] The application utilizes the property that the impedances between pins are different to detect the chip inversion, and after detecting the chip inversion, switches to the connection with the correct pin, so that the effect that the chip inversion can be correctly installed pins is achieved, and the loss caused by the chip inversion is avoided. Moreover, the application also includes a latch circuit, which latches the detected chip inversion signal, avoids the problem that after the inversion switching, the detection circuit cannot detect the inversion signal, and switches back to the initial state, and ensures the correct connection of the chip pins. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0026] Figure 1 is a structural schematic diagram of the device embodiment of the application;

[0027] Figure 2 is a structural schematic diagram of an implementation circuit of the device of the application;

[0028] Figure 3 is a flow schematic diagram of the method embodiment of the application;

[0029] Figure 4 is a flow schematic diagram of an implementation mode of the method embodiment of the application. DETAILED DESCRIPTION

[0030] In order to clearly illustrate the technical features of the present application, the following will describe the application in detail through specific embodiments, and in combination with the drawings. The following disclosure provides many different embodiments or examples to implement the different structures of the application. In order to simplify the disclosure of the application, the components and settings of specific examples are described in the following. In addition, the application can repeatedly refer to the numbers and / or letters in different examples. Such repetition is for the purpose of simplification and clarity, and it does not indicate the relationship between the various embodiments and / or settings discussed. It should be noted that the components illustrated in the drawings are not necessarily drawn to scale. The application omits the description of well-known components and processing techniques and processes to avoid unnecessary limitation of the application.

[0031] As shown in Figure 1 , the embodiment of the application provides a foolproof device for on-board chip inversion, which comprises a detection circuit 1, a switching circuit 3 and a latch circuit 2, the detection circuit 1 is connected to one pin A of a chip 4, the detection circuit 1 is also connected to another pin A' of the chip 4 through the switching circuit 3, and the other pin A' is the corresponding pin of the one pin A after the chip inversion;

[0032] The detection circuit detects the impedance of the input pin to determine whether the current chip is inverted;

[0033] If yes, the connection between the pin A and another pin A' is switched through the switching circuit.

[0034] The latch circuit 2 is connected with the detection circuit 1 and the switching circuit 3 respectively, and the signal is latched to keep the switching state after the detection circuit 1 detects the chip inversion.

[0035] As shown in the figure, Figure 2 The detection circuit 1 includes a detection impedance and a comparator CMP, two input ends of the detection impedance are connected with two input ends of the comparator respectively, and the output end of the comparator is connected with the switching circuit 3.

[0036] The switching circuit 3 includes a logic or circuit and a transistor Q1, one input end of the logic or circuit is connected with the base of the transistor Q1, the collector of the transistor is connected with one end of the detection impedance, and the collector is connected with another pin A' of the chip.

[0037] The switching circuit further includes a logic not circuit and a transistor Q2, the input end of the logic not circuit is connected with the latch circuit, the output end is connected with the base of the transistor Q2, the collector of the transistor Q2 is connected with one end of the detection impedance, and the emitter is connected with one pin A of the chip.

[0038] The latch circuit includes a transistor Q3, the collector of the transistor Q3 is connected with a power supply, the base is connected with the input end of the logic not circuit, and the emitter is connected with another input end of the logic or circuit.

[0039] The chip suitable for the embodiment of the application is a central symmetric chip, or the chip is a square shape, and the pin number and arrangement of each side of the square are the same.

[0040] If the chip is placed correctly, the comparator CMP outputs low level, the latch circuit outputs low level, the transistor Q2 is turned on, the connection between a and A is turned on, the laser Q1 is cut off, and a and A' are disconnected. If the chip is not placed correctly, the CMP outputs high level, the latch circuit outputs high level and is latched, the transistor Q2 is cut off, the connection between a and A is disconnected, the transistor Q1 is turned on, and a and A' are connected. After switching, the comparator CMP outputs low level, but the latch circuit keeps outputting high level, so the transistor Q1 is continuously turned on, Q2 is continuously cut off, and the connection of the chip is fixed.

[0041] It should be noted that, Figure 2 Only the switching of one pair of pins is shown in the figure, and the same circuit is arranged for the other pins for inversion switching.

[0042] As Figure 3 shown, the embodiment of the present application provides a fool-proof method for flip chip on board, which comprises the following steps:

[0043] S1, detecting the impedance of the chip input pin through a detection circuit to determine whether the current chip is flipped;

[0044] S2, if yes, switching the connection of one pin A to another pin A' through a switching circuit.

[0045] In step S1, the detection of the impedance of the chip input pin through the detection circuit to determine whether the current chip is flipped is specifically: connecting the two ends of the impedance to the two input ends of the comparator respectively, and determining whether the chip is flipped based on the high and low of the output end level of the comparator.

[0046] In step S2, the switching of the connection of one pin A to another pin A' through the switching circuit is specifically: when the output end of the comparator outputs a preset level value, triggering the connection of the chip input end to the other pin A'.

[0047] As Figure 4 shown, the chip is installed on the board and powered on, the comparator outputs low level in the initial stage, the latch circuit outputs low level and no latch signal, the input end a is connected to pin A, and a is disconnected from A'. Whether the chip is correctly installed is determined by detecting the impedance, if yes, the chip works normally according to the connection mode of the previous step, if not correctly installed, the detection impedance is different from the normal condition, the comparator outputs high level, the latch circuit outputs high level and the latch signal, the input end a is disconnected from pin A, and a is connected to A'; the detection impedance is normal, the comparator outputs low level, the latch circuit keeps high level output, the input end a keeps disconnected from pin A, and a keeps connected to A', and the chip works normally.

[0048] Although the specific embodiments of the present application are described above in combination with the drawings, it is not a limitation on the protection scope of the present application, and those skilled in the art should understand that various modifications or changes made by those skilled in the art on the basis of the technical solutions of the present application without creative labor are still within the protection scope of the present application.

Claims

1. A fool-proofing device for flip-chip-on-board, characterized by, The foolproof device comprises a detection circuit and a switching circuit, the detection circuit is connected with one pin A of the chip, and the detection circuit is further connected with another pin A' of the chip through the switching circuit, the another pin A' is a corresponding pin of the one pin A when the chip is inverted; The detection circuit detects the impedance of the input pin to determine whether the chip is inverted; If yes, the switching circuit switches the connection of the one pin A to the another pin A'. The foolproof device further comprises a latch circuit, the latch circuit is connected with the detection circuit and the switching circuit respectively, and the latch circuit latches the signal and maintains the switching state after the detection circuit detects that the chip is inverted.

2. The flip chip on board fool-proofing device of claim 1, wherein, The detection circuit comprises a detection impedance and a comparator, two input ends of the comparator are connected with two ends of the detection impedance respectively, and an output end of the comparator is connected with the switching circuit.

3. The flip chip on board fool-proofing device of claim 2, wherein, The switching circuit comprises a logic OR circuit and a transistor Q1, one input end of the logic OR circuit is connected with a base of the transistor Q1, a collector of the transistor is connected with one end of the detection impedance, and the collector is connected with the another pin A' of the chip.

4. The flip chip on board fool-proofing device of claim 3, wherein the plurality of bumps are arranged in a pattern. The switching circuit further comprises a logic NOT circuit and a transistor Q2, an input end of the logic NOT circuit is connected with the latch circuit, an output end of the logic NOT circuit is connected with a base of the transistor Q2, a collector of the transistor Q2 is connected with one end of the detection impedance, and an emitter of the transistor Q2 is connected with the one pin A of the chip.

5. The flip chip on board fool-proofing device of claim 4, wherein the plurality of bumps are arranged in a pattern. The latch circuit comprises a transistor Q3, a collector of the transistor Q3 is connected with a power supply, a base of the transistor Q3 is connected with an input end of the logic NOT circuit, and an emitter of the transistor Q3 is connected with another input end of the logic OR circuit.

6. A fool-proofing device for flip-chip-on-board according to any of claims 1-5, c h a r a c t e r i s e d i n that The chip is a central-symmetrical chip, or the chip is a square shape, and the number of pins of each side of the square is the same and the pins are arranged the same.

7. A fool-proofing method for flip-chip-on-board, characterized by, The method is implemented by using the device of claim 1, and the method comprises the following steps: The detection circuit detects the impedance of the input pin of the chip to determine whether the chip is inverted; If yes, the switching circuit switches the connection of the one pin A to the another pin A'.

8. The method of claim 7, wherein the method further comprises: The detection circuit detects the impedance of the input pin of the chip to determine whether the chip is inverted, and the detection specifically comprises: Two input ends of a comparator are connected with two ends of the detection impedance respectively, and whether the chip is inverted is determined based on the high and low of the level of the output end of the comparator.

9. The method of claim 8, wherein the method further comprises: The switching circuit switches the connection of the one pin A to the another pin A', and the switching specifically comprises: When a preset level value is output at the output end of the comparator, the connection of the input end of the chip and the another pin A' is triggered.

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