Bus request arbitration method and chip

Abstract

Embodiments of the present application provide a bus request arbitration method and a chip. The present scheme is applicable to various chips including ARM, RISC-V instruction set architecture, such as Internet of Things chips, audio / video chips, etc. The bus request arbitration method comprises: obtaining a plurality of APB requests sent by a plurality of APB request initiators to an APB request receiver through an APB bus; according to the plurality of APB requests, setting the effective bits of the vector bits corresponding to the plurality of APB request initiators in the preset vector signal to generate a request vector signal; polling and arbitrating the plurality of effective bits in the request vector signal according to the rule of low vector bit high priority to select the lowest effective bit; determining the APB request initiator corresponding to the lowest effective bit, and processing the APB request of the determined APB request initiator. The present scheme can make the priority of the APB request initiator dynamically variable, and the APB request can be relatively evenly processed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of intelligent chip, and in particular to a bus request arbitration method and a corresponding chip. BACKGROUND

[0002] An APB bus (Advanced Peripheral Bus) is a bus for low-power peripherals, and is suitable for low-bandwidth peripherals that do not require high-performance pipelines.

[0003] Generally, an APB bus is connected with a master and a slave, and the master and the slave exchange signals and data through the APB bus. With the development of APB bus technology, some chips can now support a multi-master and multi-slave architecture, that is, a plurality of masters and a plurality of slaves are connected through an APB bus. Thus, the requests from the plurality of masters to the slave need to be processed by arbitration, and the master is also referred to as an APB request initiator, and the slave is also referred to as an APB request receiver. However, in the existing arbitration scheme in which the master has a fixed priority, the request of a master with a higher priority is always processed first, and the requests of other masters need to be waited for a long time, thereby causing an imbalance in the waiting time of the requests of the masters. SUMMARY

[0004] Therefore, embodiments of the present application provide a bus request arbitration scheme to at least partially solve the above problems.

[0005] According to a first aspect of embodiments of the present application, a bus request arbitration method is provided, including: obtaining a plurality of APB requests sent by a plurality of APB request initiators to an APB request receiver through an APB bus; setting valid bits of vector bits corresponding to the plurality of APB request initiators in a preset vector signal according to the plurality of APB requests, generating a request vector signal for indicating that the plurality of APB request initiators have initiated APB requests, and performing shift processing on the vector signal according to a certain rule; polling and arbitrating a plurality of valid bits in the request vector signal according to a rule of low vector bit high priority, and selecting a lowest valid bit; determining an APB request initiator corresponding to the selected lowest valid bit, and processing an APB request of the determined APB request initiator.

[0006] According to a second aspect of the embodiments of this application, a chip is provided, wherein an APB bus is provided in the chip, and an arbitration unit is provided in the APB bus, wherein the arbitration unit performs APB request arbitration according to the bus request arbitration method as described in the first aspect.

[0007] According to the bus request arbitration scheme provided in this application embodiment, different APB requests are processed using a priority-based round-robin approach. When multiple APB requests initiated by multiple APB request initiators are received on the APB bus, the specific APB request initiator is indicated by setting the valid bits of the vector signal. The vector signal includes multiple bits, each corresponding to an APB request initiator. This not only provides a valid indication of the APB request and its initiator but also lays the foundation for the priority-based round-robin arbitration method in this application scheme. After setting the valid bits in the vector signal and generating the corresponding request vector signal, the scheme in this application embodiment polls and arbitrates the multiple valid bits according to the rule of low vector bits having high priority, selects the least significant bit, and processes the APB request from the APB request initiator corresponding to the least significant bit. This allows the priority of the APB request initiator to be dynamically variable, ensuring that APB requests initiated by each APB request initiator are processed relatively evenly, and also ensuring that the waiting delay of each initiator is relatively balanced when multiple APB request initiators initiate APB requests. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0009] Figure 1 This is a flowchart illustrating the steps of a bus request arbitration method according to an embodiment of this application;

[0010] Figure 2 for Figure 1 A schematic diagram of the structure of a chip using the APB bus in the illustrated embodiment;

[0011] Figure 3 for Figure 1 A schematic diagram of an arbitration example in the illustrated embodiment;

[0012] Figure 4 for Figure 1 A schematic diagram of another arbitration example in the illustrated embodiment. Detailed Implementation

[0013] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art should fall within the scope of protection of the present application.

[0014] The specific implementation of the embodiments of the present application will be further described below with reference to the drawings of the embodiments of the present application.

[0015] Referring to Figure 1 , a step flowchart of a bus request arbitration method according to an embodiment of the present application is shown.

[0016] For ease of illustration, the chip structure of the APB bus required by the scheme of the present application is first described in the embodiments of the present application. Exemplarily, a PIC (Platform Interrupt Controller, platform interrupt controller) chip is taken as a specific example for description, as shown in Figure 2 . Figure 2 The PIC based on the APB bus supports a plurality of master devices and a plurality of slave devices, and the plurality of APB request initiators are schematically N, which are cluster_0, …, cluster_N-1. The PIC is provided with an APB sync module, an APB matrix module and an APB request receiver (schematically plic and clint in the figure). The APB sync module is responsible for the synchronization of the plurality of clusters, i.e. the APB request initiators, and the synchronization of other signals with the APB of the PIC. The apb_arbiter module in the APB matrix module is responsible for the arbitration of the plurality of synchronized APBs. The apb_fsm module in the APB matrix module is responsible for sending the two APBs obtained after arbitration, which are sent to plic and clint, respectively. The plic is a platform-level interrupt controller, which is used to process external interrupts. The clint is a processor core local interrupt controller, which is used to process timer interrupts and software interrupts.

[0017] It should be noted that, Figure 2 in the example shown, the APB request receiver is only taken as an example of plic and clint, but in actual applications, a person skilled in the art can set more numbers and more types (including the type of non-interrupt signals processing interrupt signals) of APB request receivers according to actual needs, which are all applicable to the scheme of the present application.

[0018] On this basis, the bus request arbitration method provided by the embodiments of the present application comprises the following steps:

[0019] Step S102: Obtain a plurality of APB requests initiated by a plurality of APB request initiators to an APB request receiver through an APB bus.

[0020] In this embodiment, the plurality of APB requests are initiated by a plurality of APB request initiators to one APB request receiver. When the APB request receiver includes a plurality of APB request receivers, each APB request receiver has a set of arbitration mechanisms described in this embodiment, and the bus request arbitration method of this embodiment is used for APB request arbitration.

[0021] The APB request initiated by the APB request initiator to the APB request receiver through the APB bus can be any request conforming to the APB protocol, including but not limited to an interrupt request, a data transmission or read / write request, etc.

[0022] It should be noted that in this embodiment, unless otherwise specified, the number related to "multiple" such as "multiple" and "multiple" means two or more than two.

[0023] Step S104: According to the plurality of APB requests, set valid bits in the preset vector signal corresponding to the plurality of APB request initiators to generate a request vector signal for indicating that the plurality of APB request initiators have initiated APB requests.

[0024] In this embodiment, a vector signal is set for the plurality of APB request initiators, which is composed of a plurality of bit positions. The number of bit positions can be the same as the number of APB request initiators, or more than the number of APB request initiators to reserve for subsequent addition of APB request initiators. However, in order to facilitate processing, the number of bit positions in this embodiment is consistent with the number of APB request initiators, and one bit position corresponds to one APB request initiator.

[0025] Initially, the values of all bit positions in the vector signal can be set to 0. When there is an APB request, the bit position corresponding to the APB request initiator that initiates the APB request is set to 1, that is, the vector bit position corresponding to the APB request initiator is set to valid bit. The vector signal after valid bit setting is the request vector signal.

[0026] For example, assuming that there are 5 APB request initiators, the vector signal includes 5 bit positions from 0-4, and initially the vector signal can be:

[0027] 0 0 0 0 0

[0028] Suppose, after 1s, two of the five APB request initiators initiate APB requests, for example, the first and the last, then the valid bit of the vector signal is set, and the generated request vector signal is:

[0029] 1 0 0 0 1

[0030] It should be noted that although bit position 1 is more in line with the actual application of the valid bit setting form, those skilled in the art should understand that all bit positions 1 are initially set, and when there is an APB request, the bit position 0 corresponding to the APB request initiator of the APB request is also applicable to the scheme of the embodiment of the application. In the embodiment of the application, the bit position 1 is selected to implement the valid bit setting.

[0031] Step S106: According to the rule of low vector bit high priority, the multiple valid bits in the request vector signal are polled and arbitrated to select the lowest valid bit.

[0032] Among them, low vector bit high priority means that the lower the vector bit (i.e. bit) in the vector signal, the higher the priority.

[0033] The request vector signal contains valid bits indicating that the APB request is initiated, such as the bit position 1 in the above request vector signal. In the embodiment of the application, because multiple APB requests initiated by multiple APB request initiators are arbitrated and processed, the valid bits are also multiple.

[0034] Based on this, in a feasible way, according to the rule of low vector bit high priority, polling and arbitrating the multiple valid bits in the request vector signal can be implemented as follows: obtaining the counting information in the preset counter, and performing a shift operation on the request vector signal according to the counting information; according to the rule of low vector bit high priority, polling and arbitrating the multiple valid bits in the request vector signal after the shift operation. Among them, the counter is used to count the number of arbitrations, and the initial value is 0, which is increased by 1 each time. By shifting the request vector signal based on the counting information, the dynamic change and polling of the priority of the multiple APB request initiators are realized, which effectively ensures that the APB requests of each APB request initiator can be processed within a relatively reasonable time.

[0035] Under the rule of low vector bit high priority, the lowest bit position 1 is selected from the multiple bit positions 1. Further, after the lowest bit position 1 is selected, all other bit positions 1 can be set to 0 to facilitate subsequent processing.

[0036] In addition, as mentioned above, the counter is used to count the number of arbitrations, and is incremented by 1 each time arbitration is performed, so at a certain arbitration, it should be the value of the counter updated after the previous arbitration. That is, obtaining the count information in the preset counter, and performing the shift operation on the request vector signal according to the count information can be implemented as follows: obtaining the count information updated in the preset counter; and performing the shift operation on the request vector signal according to the updated count information, so as to ensure the correctness of the shift operation, and further ensure the fairness of the APB requests being processed.

[0037] In another possible implementation, polling arbitration on the plurality of valid bits in the request vector signal according to the rule of low vector bit and high priority can be implemented as follows: obtaining a random code generated by a pseudo-random code generator; and polling arbitration on the plurality of valid bits in the request vector signal according to the rule of low vector bit and high priority according to the random code. The number of random codes can be determined according to the number of APB request initiators, or can be considered as the number of bit positions of the vector signal. Assuming that there are five APB request initiators, five random codes can be set, for example, 0-4. If the random code is 0, it can be determined that the first APB request initiator is selected, if the random code is 2, it can be determined that the third APB request initiator is selected, and so on. By using the random code, one valid bit can be randomly selected from the plurality of valid bits, and the APB request initiated by the APB request initiator corresponding to the valid bit can be determined as the APB request to be processed. This random method can also achieve priority polling, and ensure that the plurality of APB requests can be processed in a reasonable time.

[0038] However, in some cases, the bit position pointed to by the random code can not be a valid bit, for example, the bit position is set to 0 instead of 1. Therefore, in order to improve the efficiency of arbitration and ensure that a valid bit in the request vector signal is selected, in one possible implementation, polling arbitration on the plurality of valid bits in the request vector signal according to the rule of low vector bit and high priority according to the random code can be implemented as follows: determining whether the vector bit corresponding to the random code is a valid bit; if yes, determining that the vector bit corresponding to the random code wins the arbitration; and if no, performing a shift operation on the request vector signal, and determining that the lowest valid bit in the request vector signal after the shift operation wins the arbitration.

[0039] Step S108: determining the APB request initiator corresponding to the selected lowest valid bit, and processing the APB request of the determined APB request initiator.

[0040] Because the request vector signal is typically shifted when determining the least significant bit, it's impossible to directly determine which APB request initiator corresponds to the selected least significant bit. Therefore, after selecting the least significant bit, one feasible approach is to reset the shifted request vector signal; determine the corresponding APB request initiator based on the position of the selected least significant bit in the reset request vector signal; and process the APB request from the determined initiator. The specific implementation of the reset process for the request vector signal can be tailored to the specific needs of those skilled in the art, using appropriate reset methods, such as circular left or circular right shifts. Through the reset process, the positions of each bit in the request vector signal are restored to their original positions corresponding to each APB request initiator, thus enabling efficient and rapid determination of the APB request initiator corresponding to the selected least significant bit. However, this is not the only approach; other methods, such as determining the corresponding APB request initiator based on the number of shift bits, are also applicable.

[0041] Once the APB request initiator is identified, the APB request initiated by that initiator can be processed. For example, the information of the identified APB request initiator can be sent to the target APB request receiver through a strobe register, and the response signal returned by the target APB request receiver can be received.

[0042] Furthermore, as mentioned earlier, in the counter-based approach, the counter value is updated after each arbitration. Therefore, optionally, upon receiving the response from the APB request receiver, the counter information can be incremented. For example, the response signal returned by the target APB request receiver can be returned to the corresponding APB request initiator via a strobe register; subsequently, the value of the strobe register can be cleared, and the counter value incremented by 1 for use in the next arbitration.

[0043] The following example illustrates the bus request arbitration process in the case of multiple APB request initiators and a single APB request receiver.

[0044] First, the arbitrator (such as...) Figure 2 The apb_arbiter module shown detects the psel signal (selecting the valid APB request receiver signal) and the penable signal (enabling signal, which works during the transmission cycle) initiated by each APB request initiator, and determines whether an APB request has been initiated. If so, it generates a request vector signal based on the request signal of each individual bit from each APB request initiator.

[0045] Based on the request vector signal, the arbitration process is described below as an example of two consecutive arbitration procedures, as shown in Figure 3 and Figure 4 . Figure 3 and Figure 4 Among them, the APB request initiator is denoted as master, and the APB request receiver is denoted as slave. There are six masters, namely master0, 1, 2, 3, 4, and 5.

[0046] Among them, Figure 3 the first arbitration process is shown, including:

[0047] 1. This arbitration is the first arbitration. It is assumed that master0, master3, and master4 initiate APB requests, and their corresponding bits in the request vector signal are set to 1.

[0048] 2. According to the count value in the counter, the request vector signal is subjected to a cyclic left shift shift processing. At this time, since the count value is 0, no shift is needed.

[0049] 3. The low vector bit high priority rule is used to arbitrate the multiple valid bits in the request vector signal. In this arbitration, the lowest valid bit bit0 is selected, and all other bit positions are set to 0.

[0050] 4. The request vector signal obtained after setting to 0 is subjected to reset processing, such as cyclic left shift (N-counter value) bits, where N represents the number of masters. At this time, the effective bit is still at bit0 after 6-bit cyclic left shift.

[0051] 5. The request vector signal obtained after reset processing is stored in the gating register. The gating register selects a bit position, i.e., the APB request corresponding to the effective bit, to send to the slave. The gating register is equivalent to recording the winner of this arbitration, i.e., master0.

[0052] 6. The slave replies with the pready signal, which is returned to the corresponding master, i.e., master0 of this arbitration, through the gating register.

[0053] 7. Clear the gating register and make the count value of the counter +1, and the next arbitration can begin.

[0054] Figure 4 the second arbitration process is shown, Figure 4 in which it is assumed that new APB requests have arrived after the first psel0 APB request is processed.

[0055] 1. The second arbitration is after the first arbitration, and master0, master3, master4 still have APB requests, wherein master0 is a new APB request.

[0056] 2. The count value in the counter is 1 after the last arbitration, and based on this, the request vector signal is cyclically left shifted by 1 bit.

[0057] 3. The request vector signal is arbitrated using the rule of low vector bit high priority, and the lowest significant bit bit2 is selected in this arbitration, and the other bit positions are all set to 0.

[0058] 4. The request vector signal obtained after being set to 0 is reset, such as being cyclically left shifted by (N-count value) bits, i.e. 5 bits, and the significant bit is shifted to bit3.

[0059] 5. The request vector signal obtained after reset is stored in the gating register, the gating register selects a bit position, i.e. the significant bit, and sends the corresponding APB request to the slave, and records the winner of this arbitration, i.e. master3.

[0060] 6. The slave returns the pready signal, which is returned to the corresponding master through the gating register, i.e. the gating register returns to the corresponding master3.

[0061] 7. The gating register is cleared, and the count value of the counter is incremented by 1, and the next arbitration can begin.

[0062] As can be seen from the above two arbitration processes, the count value of the counter is incremented by 1 after each arbitration; the increment of the count value cooperates with the shift operation, so that the master priority changes once for each arbitration, so that the probability of each master winning in multiple arbitrations is relatively average, and the time each master waits when multiple APB requests appear at the same time is relatively balanced.

[0063] As described above, the above processes are all exemplified by a plurality of APB request initiators and a single APB request receiver, but in actual application, there is also arbitration in the case of a plurality of APB request initiators and a plurality of APB request receivers. In this case, each APB request receiver has a base address and an address mask. Then, the acquisition of a plurality of APB requests sent by a plurality of APB request initiators to a plurality of APB request receivers through the APB bus in the foregoing step S102 can be implemented as follows: acquiring a plurality of APB requests sent by a plurality of APB request initiators to the APB bus, and determining a plurality of target APB request receivers corresponding to the plurality of APB requests based on the base address and the address mask. Specifically, for each APB request, the target address information carried by the APB request can be acquired; according to the target address information, the matching base address and address mask are determined; and according to the matching base address and address mask, the corresponding target APB request receiver is determined for the APB request.

[0064] Each APB request receiver is configured with the foregoing arbitration logic to ensure that different APB request senders do not block each other when accessing different APB request receivers.

[0065] In a specific actual case, the base address and the address mask of each APB request receiver, denoted as slave, can be configured by binding the input port of the chip. The arbitrator determines the APB request to be sent to which slave through the slave base address, the slave address mask, and the paddress in the APB request sent by the master.

[0066] For example:

[0067] The base address of slave0 is 6’b100000.

[0068] The address mask of slave0 is 6’b111000.

[0069] The base address of slave1 is 6’b110000.

[0070] The address mask of slave1 is 6’b111000.

[0071] Wherein, 6’ means 6 bit positions.

[0072] Suppose the paddress in the APB request sent by the master is 6’b100110.

[0073] Then:

[0074] The judgment of slave0 is: 6’b100000 & 6’b111000 == 6’b100110 & 6’b111000

[0075] slave1 judgment: 6'b110000 & 6'b111000 == 6'b100110 & 6'b111000

[0076] According to the judgment result, the APB request should be sent to slave0.

[0077] It can be seen that by the above method, the accuracy of the target slave judgment in the multi-master multi-slave case can be effectively guaranteed.

[0078] Further, in order to make the arbitration scheme of the present application have better portability, so as to be transplanted into similar arbitration scenarios, in a feasible way, APB bus request arbitration configuration information under different APB request initiator quantity and APB request receiver quantity configurations can also be collected, the configuration information including at least one of the following: the number of APB request initiators, the number of APB request receivers, the APB bus bit width, the APB data bit width, the number of APB interfaces for input and output; the configuration information is generated as a configuration file, which is used to provide configuration parameters for chip integration configured with APB bus.

[0079] Thus, the chip parameterizable configuration in the multi-master multi-slave case based on the APB bus is realized, such as the APB master quantity, the APB slave quantity, the APB address bit width, the APB data bit width, etc. can be parameterizable configured. When the chip is made based on the determined configuration, the number of APB interfaces for input and output can be configured according to the master / slave quantity, and after the number of configurations, the chip is integrated, the slave base address and the slave address mask are configured. Thus, the scheme of the embodiments of the present application has good adaptability, wide applicability, and can be conveniently transplanted into different scenarios.

[0080] By the embodiment of the present application, different APB requests are processed in a priority polling manner. When multiple APB requests initiated by multiple APB request initiators are received on the APB bus, it is indicated which APB request initiator initiates the APB request by setting the valid bits of the vector signal. The vector signal includes multiple bit positions, and each bit position corresponds to an APB request initiator. Thus, the APB request and its initiator can be effectively indicated, and the priority polling manner arbitration of the present application is provided. After the valid bits in the vector signal are set and the corresponding request vector signal is generated, the embodiment of the present application arbitrates the multiple valid bits according to the rule of low vector bit high priority, selects the lowest valid bit, and processes the APB request of the APB request initiator corresponding to the lowest valid bit. Thus, the priority of the APB request initiator is dynamically variable, the APB requests initiated by the APB request initiators can be processed relatively evenly, and the waiting delay of each initiator is relatively even when multiple APB request initiators initiate APB requests.

[0081] The embodiment of the present application also provides a chip, which is provided with an APB bus, and the APB bus is provided with an arbitration unit, for example, the apb_arbiter module shown in Figure 2 . The arbitration unit can perform APB request arbitration according to the bus request arbitration method described in the above embodiment.

[0082] For example, the chip can be a PIC chip as shown in Figure 2 . The apb_arbiter module in the PIC chip is responsible for selecting one APB request from N APB requests according to the access plic and the access clint, respectively, and the two APB requests do not affect each other.

[0083] The arbitration logic of each APB request adopts the polling arbitration priority described in the foregoing method embodiment, and the polling priority changes once for each arbitration. For example, the APB request of cluster0 has the highest priority in the first arbitration, and the APB request of cluster1 has the highest priority in the second arbitration after the transmission is completed.

[0084] In combination with Figure 3 and Figure 4 , for example, the psel_0-5 can be used as the vector signal, and the lowest valid bit is selected as the strobe signal by polling arbitration. The psel used by each arbitration logic is generated by synchronously obtained psel and paddr, and the strobe register is also used for the return of pready. The strobe register cannot be changed until the APB transmission between the cluster and the PIC is completed.

[0085] After the pready signal of the plic / clint is generated, the pready_m of the corresponding cluster is returned through the gating register, the pready_m_pulse of the PIC clock domain is synchronized to obtain the pready_s_pulse of the cluster clock domain. The pready_s_pulse needs to be synchronized back to the PIC clock domain, and the trans_cpmlt is obtained after the gating register is updated.

[0086] RISC-V is an open-source instruction set architecture based on the principle of reduced instruction set (RISC), which can be applied to various aspects such as single-chip microcomputers and FPGA chips. Specifically, it can be applied in the fields of Internet of Things security, industrial control, mobile phones, personal computers, etc. Due to the consideration of small, fast, and low-power reality in its design, it is particularly suitable for modern computing devices such as warehouse-scale computers, high-end mobile phones, and small embedded systems. With the rise of artificial intelligence Internet of Things (AIoT), RISC-V instruction set architecture has received more and more attention and support, and is expected to become the next generation of widely used CPU architecture.

[0087] The computer operation instructions in the embodiments of the present application can be computer operation instructions based on the RISC-V instruction set architecture. Correspondingly, the arbitration unit can be designed based on the RISC-V instruction set. Specifically, the chip provided in the embodiments of the present application can be a chip designed with the RISC-V instruction set. The chip can execute executable code based on the configured instructions, thereby implementing the bus request arbitration method in the above embodiments.

[0088] It should be noted that, according to the needs of implementation, each component / step described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or part of the operations of the components / steps can be combined into new components / steps, to achieve the purpose of the embodiments of the present application.

[0089] The methods according to the embodiments of the present application described above can be implemented in hardware, firmware, or software, or a combination of them, and can be stored in a recording medium such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk, or be downloaded from a network originally stored in a remote recording medium or a non-transitory machine-readable medium and stored in a local recording medium, so that the methods described herein can be processed by such software on a recording medium using a general-purpose computer, a special-purpose processor, or programmable or special-purpose hardware such as an ASIC or an FPGA. It can be understood that the computer, processor, microprocessor controller, or programmable hardware includes a storage component (for example, RAM, ROM, flash memory, etc.) that can store or receive software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code for implementing the methods shown herein, the execution of the code will convert the general-purpose computer into a special-purpose computer for executing the methods shown herein.

[0090] Those skilled in the art can realize that the units and method steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0091] The above embodiments are only used to illustrate but not limit the embodiments of the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, therefore all equivalent technical solutions belong to the scope of the embodiments of the present application, and the patent protection scope of the embodiments of the present application should be defined by the claims.

Claims

1. A bus request arbitration method, comprising: Acquire multiple APB requests sent by the APB request initiator to the APB request receiver via the APB bus; Based on the multiple APB requests, the valid bits of the vector bits corresponding to the multiple APB request initiators in the preset vector signal are set to generate a request vector signal for indicating that the multiple APB request initiators have initiated an APB request. According to the rule of low vector bit high priority, the multiple valid bits in the request vector signal are polled and arbitrated to select the least valid bit. Determine the APB request initiator corresponding to the selected least significant bit, and process the APB request of the determined APB request initiator; The step of polling and arbitrating multiple valid bits in the request vector signal according to the rule of low vector bits having high priority includes: Obtain the counting information from the preset counter, and perform a shift operation on the request vector signal based on the counting information; According to the rule of low vector bits having high priority, multiple valid bits in the request vector signal after the shift operation are polled and arbitrated. Alternatively, the step of polling and arbitrating multiple valid bits in the request vector signal according to the rule of low vector bits having high priority includes: Obtain the random code generated by the pseudo-random code generator; Based on the random code, multiple valid bits in the request vector signal are polled and arbitrated according to the rule of low vector bits having high priority.

2. The method according to claim 1, characterized in that, The method further includes: after receiving the reception response from the APB request receiving end that processes the APB request, updating the counting information by incrementing the count value; The step of obtaining the counting information in the preset counter and performing a shift operation on the request vector signal based on the counting information includes: obtaining the updated counting information in the preset counter; and performing a shift operation on the request vector signal based on the updated counting information.

3. The method according to claim 1, characterized in that, Based on the random code, and following the rule of low vector bits having high priority, multiple valid bits in the request vector signal are polled and arbitrated, including: Determine whether the vector bits corresponding to the random code are valid bits; If so, then the vector bit corresponding to the random code is determined to win the arbitration; If not, then a shift operation is performed on the request vector signal, and the least significant bit in the shifted request vector signal is determined to win the arbitration.

4. The method according to claim 1, 2 or 3, characterized in that, The process of determining the APB request initiator corresponding to the selected least significant bit, and processing the APB request from the determined APB request initiator, includes: The request vector signal after the shift operation is reset. The corresponding APB request initiator is determined based on the position of the selected least significant bit in the request vector signal after the reset process. The APB request from the identified APB request initiator is processed.

5. The method according to claim 4, characterized in that, The process of processing the APB request from the determined APB request initiator includes: The information of the determined APB request initiator is sent to the target APB request receiver via the strobe register. Receive the response signal returned by the target APB request receiver.

6. The method according to claim 1, characterized in that, The APB request receiver includes multiple receivers, each of which has a base address and an address mask. The acquisition of multiple APB requests sent by the initiating end to the receiving end via the APB bus includes: Multiple APB requests sent to the APB bus by multiple APB request initiators are obtained, and multiple target APB request receivers corresponding to the multiple APB requests are determined based on the base address and the address mask.

7. The method according to claim 6, characterized in that, The step of determining multiple target APB request receivers corresponding to the multiple APB requests based on the base address and the address mask includes: For each APB request, obtain the target address information carried by that APB request; Based on the target address information, determine the matching base address and address mask; Based on the matching base address and address mask, determine the corresponding target APB request receiver for this APB request.

8. The method according to claim 1, characterized in that, The method further includes: Collect APB bus request arbitration configuration information under different configurations of the number of APB request initiators and the number of APB request receivers. The configuration information includes at least one of the following: the number of APB request initiators, the number of APB request receivers, the APB bus width, the APB data width, and the number of APB interfaces used for input and output. The configuration information is generated into a configuration file, which is used to provide configuration parameters for chip integration configured with the APB bus.

9. A chip, wherein an APB bus is provided in the chip, and an arbitration unit is provided in the APB bus, wherein the arbitration unit performs APB request arbitration according to the bus request arbitration method as described in any one of claims 1-8.

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