An FPGA-based digital sampling system

Abstract

A logic system for a digital sampling module based on FPGA, belonging to the field of digital acquisition technology, solves the problem of low versatility in FPGA-based digital acquisition. The system of this invention includes: an FPGA, a digital sampling analog front-end, and a DDR (Digital Transfer Circuit). The FPGA includes a digital signal processing unit, a data counting unit, a triggering unit, a waveform calculation unit, a main state machine, a DDR control unit, and a register read / write control unit. This invention is applicable to the system architecture design of FPGA-based digital sampling modules, can meet the functional requirements of digital acquisition modules in most oscilloscope recorders, and has high scalability and development potential. Under this designed architecture, it can meet the requirements of digital downsampling processing, trigger generation, different storage modes, and different sampling timing control under different signal input rates such as high speed and low speed, and realize functions such as real-time data storage, waveform calculation, deep storage, memory partitioning, and data uploading.

Description

Technical Field

[0001] This application relates to the field of digital acquisition technology, and in particular to a logic system for a digital sampling module based on FPGA. Background Technology

[0002] With the rapid development of modern electronic technology and information processing, the acquisition and display functions of modern testing instruments are becoming increasingly diversified. In particular, powerful oscilloscope recorders have seen rapid growth in sampling rate and bandwidth. The flexible splicing of multiple modules can measure and acquire electrical and physical signals from multiple fields, and a user-friendly human-machine interface allows users to observe waveform changes from multiple angles.

[0003] A summary of current digital acquisition module designs reveals that most only focus on optimizations and innovations in specific areas, lacking a unified and standardized design approach. While each has its own characteristics, they lack universality. The universality of FPGA-based digital acquisition modules is specifically reflected in the following functions:

[0004] (1) It supports waveform input at multiple sampling rates and can perform simple processing of input signals such as downsampling and filtering;

[0005] (2) Supports the controllability of analog front-end devices, including the control of analog devices such as front-end filters and gain attenuation;

[0006] (3) Supports multi-channel digital signal acquisition channel input;

[0007] (4) It contains trigger channels that support multiple trigger modes, and the various trigger channels can perform some related logical combinations and calculations. It also includes the triggering function between different digital acquisition modules via PXIe trigger lines;

[0008] (5) Supports real-time calculation units for waveform characteristics;

[0009] (6) Supports onboard DDR storage and high-speed PXIe data transmission. Summary of the Invention

[0010] The purpose of this invention is to solve the problem of low versatility of existing FPGA-based digital acquisition systems and to provide an FPGA-based digital sampling system.

[0011] The present invention is achieved through the following technical solution, providing an FPGA-based digital sampling system, the system including an FPGA, a digital sampling analog front-end and a DDR, the FPGA including a digital signal processing unit, a data counting unit, a triggering unit, a waveform calculation unit, a main state machine, a DDR control unit and a register read / write control unit;

[0012] The digital signal processing unit is used to perform preliminary processing and analysis on the real-time waveforms acquired by the multi-channel ADC. The preliminary processing specifically includes performing primary noise reduction on the real-time waveforms acquired by the multi-channel ADC to obtain the primary noise reduction signal. The analysis processing specifically includes analyzing the real-time waveforms acquired by the multi-channel ADC to obtain the instantaneous waveform and the envelope waveform.

[0013] The digital signal processing unit sends the primary noise reduction signal to the triggering unit, and sends the instantaneous waveform and envelope waveform to the data counting unit;

[0014] The triggering unit is used to analyze the input data, mark the trigger point at the required position to trigger the signal, and send the generated trigger signal to the data counting unit and the main state machine.

[0015] The data counting unit is used to perform time-delay alignment of the signal received from the digital signal processing unit and the trigger signal, and to control the counting of data points in various modes to obtain counting results;

[0016] The data counting unit sends the delayed-aligned data and the counting result to the DDR control unit, and sends the delayed-aligned data to the waveform calculation unit;

[0017] The waveform calculation unit is used to perform real-time waveform calculation on the input data and send the calculation results to the register read / write control unit.

[0018] The master state machine is used to determine the time for writing data to the DDR control unit based on the counting result and the trigger signal, and sends the time signal to the DDR control unit.

[0019] The DDR control unit is used to control DDR read and write based on the data input from the main state machine and the data counting unit, and sends the generated address packet to the register read and write control unit.

[0020] The register read / write control unit is used to distribute the register read / write control instructions parsed by the AXI-Lite protocol to other units, and is also used to upload input data.

[0021] Furthermore, the digital signal processing unit includes an anti-aliasing filtering unit, a downsampling unit, and an envelope extraction unit;

[0022] The anti-aliasing filtering unit includes a low-pass filter bank, which is used to perform low-pass filtering on the signal to prevent spectral aliasing after sampling, and sends the filtered signal to the downsampling sampling unit.

[0023] The downsampling sampling unit is used to extract points from the filtered signal at equal intervals, and output the waveform extracted at equal intervals as an instantaneous waveform. The interval is configurable.

[0024] The envelope extraction unit is used to receive the instantaneous waveform, extract the instantaneous waveform according to a preset envelope sampling rate, extract the maximum and minimum values ​​within a preset sampling time period, and output the envelope waveform.

[0025] Furthermore, the digital signal processing unit also includes a primary noise reduction unit, which is used to perform primary noise reduction on the real-time waveforms acquired by the multi-channel ADC and send the data after primary noise reduction to the triggering unit.

[0026] Furthermore, the input data in the register read / write control unit includes the calculation results output by the waveform calculation unit and the address packets generated by the DDR control unit.

[0027] Furthermore, the DDR control unit includes a DDR address and data control unit, an address FIFO and data FIFO cache unit, and a DDR write control unit;

[0028] The DDR address and data control unit includes a DDR address control unit and a data control unit;

[0029] The DDR address control unit is used to analyze and parse the counting results transmitted from the data counting unit, determine the size of the address to be written to the DDR each time, and send the size of the address to be written to the DDR to the address FIFO and data FIFO buffer unit.

[0030] The data control unit is used to concatenate the incoming waveform signal and write it into the DDR, and send the concatenated waveform signal to the address FIFO and data FIFO buffer unit;

[0031] The address FIFO and data FIFO buffer unit is used to perform clock domain conversion and bit width conversion on the input data, and is also used to save the waveform that has not been written to DDR, and send the converted data and the saved data to the DDR write control unit;

[0032] The DDR write control unit is used to convert input data into a data format that conforms to the AXI protocol and control the reading and writing of DDR.

[0033] Furthermore, before converting the input data into a data format conforming to the AXI protocol, the DDR write control unit further includes:

[0034] The empty signal of the data FIFO and address FIFO is detected. If the empty signal is not 1, the write operation of the AXI protocol is started.

[0035] Furthermore, the waveform calculation unit includes 40 waveform calculation functions, and can generate waveform data corresponding to 16 waveform calculation functions simultaneously through configuration.

[0036] Furthermore, the master state machine is used to determine the time for writing data to the DDR control unit based on the counting result and the trigger signal, specifically including:

[0037] The master state machine is used to determine the time for writing data to the DDR control unit based on the register read / write control instructions received from the register read / write control unit, the counting result, and the trigger signal.

[0038] Furthermore, the DDR control unit uploads the addresses of key points in a predetermined format.

[0039] Furthermore, the register read / write control instructions include one or more of the following: parameter configuration for each functional module, sampling mode configuration, start signal transmission, or stop signal transmission.

[0040] The beneficial effects of this invention are:

[0041] 1. The digital signal processing unit and DDR control unit of the present invention can perform data processing, storage and uploading of input data with multiple channels and different sampling rates, and the maximum sampling rate supports 200MSa / s;

[0042] 2. The main state machine and triggering unit of this invention satisfy the control requirements of multiple sampling times and different triggering conditions;

[0043] 3. The main state machine and DDR control unit of this invention support onboard deep storage, real-time waveform storage, waveform uploading and other functions;

[0044] 4. The master state machine of the present invention can achieve functions such as pre-triggering, post-triggering, trigger priority, repeated triggering, and data storage in normal mode, envelope mode, and dual capture mode.

[0045] 5. The waveform calculation unit of the present invention can realize complex waveform feature calculation functions, including real-time calculation of multiple types of feature quantities.

[0046] This invention is applicable to the system architecture design of FPGA-based digital sampling modules, meeting the functional requirements of digital acquisition modules in most oscilloscope recorders, and possessing high scalability and development potential. Under this architecture, it can meet the requirements of digital downsampling processing, trigger generation, different storage modes, and different sampling timing control for signal inputs of varying speeds (high-speed, low-speed, etc.), and realize functions such as real-time data storage, waveform calculation, deep storage, memory partitioning, and data uploading. Attached Figure Description

[0047] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a schematic diagram of the FPGA system implementation logic of the present invention;

[0049] Figure 2 This is a schematic diagram of the digital signal processing unit of the present invention;

[0050] Figure 3 This is a schematic diagram of the DDR control unit logic of the present invention;

[0051] Figure 4 This is a schematic diagram of the address upload packet format of the present invention. Detailed Implementation

[0052] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0053] Implementation Method 1: A digital sampling system based on FPGA, the system including FPGA, digital sampling analog front-end and DDR, the FPGA including digital signal processing unit, data counting unit, triggering unit, waveform calculation unit, main state machine, DDR control unit and register read / write control unit;

[0054] The digital signal processing unit is used to perform preliminary processing and analysis on the real-time waveforms acquired by the multi-channel ADC. The preliminary processing specifically includes performing primary noise reduction on the real-time waveforms acquired by the multi-channel ADC to obtain the primary noise reduction signal. The analysis processing specifically includes analyzing the real-time waveforms acquired by the multi-channel ADC to obtain the instantaneous waveform and the envelope waveform.

[0055] The digital signal processing unit sends the primary noise reduction signal to the triggering unit, and sends the instantaneous waveform and envelope waveform to the data counting unit;

[0056] The triggering unit is used to analyze the input data, mark the trigger point at the required position to trigger the signal, and send the generated trigger signal to the data counting unit and the main state machine.

[0057] The data counting unit is used to perform time-delay alignment of the signal received from the digital signal processing unit and the trigger signal, and to control the counting of data points in various modes to obtain counting results;

[0058] The data counting unit sends the delayed-aligned data and the counting result to the DDR control unit, and sends the delayed-aligned data to the waveform calculation unit;

[0059] The waveform calculation unit is used to perform real-time waveform calculation on the input data and send the calculation results to the register read / write control unit.

[0060] The master state machine is used to determine the time for writing data to the DDR control unit based on the counting result and the trigger signal, and sends the time signal to the DDR control unit.

[0061] The DDR control unit is used to control DDR read and write based on the data input from the main state machine and the data counting unit, and sends the generated address packet to the register read and write control unit.

[0062] The register read / write control unit is used to distribute the register read / write control instructions parsed by the AXI-Lite protocol to other units, and is also used to upload input data.

[0063] In this embodiment, 1. the digital signal processing unit and DDR control unit of this embodiment can perform data processing, storage and uploading of input data with multiple channels and different sampling rates, and the maximum sampling rate supports 200MSa / s;

[0064] 2. The main state machine and triggering unit in this embodiment satisfy the control requirements of multiple sampling times and different triggering conditions;

[0065] 3. The main state machine and DDR control unit in this embodiment support onboard deep storage, real-time waveform storage, waveform uploading and other functions;

[0066] 4. The main state machine of this embodiment can achieve functions such as pre-triggering, post-triggering, trigger priority, repeated triggering, and data storage in normal mode, envelope mode, and dual capture mode.

[0067] 5. The waveform calculation unit of this embodiment can realize complex waveform feature calculation functions, including real-time calculation of multiple types of feature quantities.

[0068] This implementation method divides the functions to be performed by the digital acquisition module into detailed units, so that each unit is specifically and exclusively responsible for one or more functions. The advantage of this design is that it can clearly depict the modules where each function is located, and as long as the connection conditions between modules and the characteristics of input and output signals are coordinated, it can be implemented quickly and efficiently.

[0069] Furthermore, this implementation method can optimize the functionality between various modules. For example, dedicated counting units, state machine control, DDR memory control, etc., can break down complex tasks into different modules, and at the same time, code simplification, resource optimization, and other operations can be performed for each module to improve system implementation efficiency.

[0070] Implementation Method Two: This implementation method further defines the FPGA-based digital sampling system described in Implementation Method One. In this implementation method, the digital signal processing unit is further defined, specifically including:

[0071] The digital signal processing unit includes an anti-aliasing filtering unit, a downsampling unit, and an envelope extraction unit.

[0072] The anti-aliasing filtering unit includes a low-pass filter bank, which is used to perform low-pass filtering on the signal to prevent spectral aliasing after sampling, and sends the filtered signal to the downsampling sampling unit.

[0073] The downsampling sampling unit is used to extract points from the filtered signal at equal intervals, and output the waveform extracted at equal intervals as an instantaneous waveform. The interval is configurable.

[0074] The envelope extraction unit is used to receive the instantaneous waveform, extract the instantaneous waveform according to a preset envelope sampling rate, extract the maximum and minimum values ​​within a preset sampling time period, and output the envelope waveform.

[0075] In this embodiment, the anti-aliasing filter unit can be flexibly designed and modified according to the maximum sampling rate supported by the digital acquisition module and the complexity of the function: at low speeds, a serial DSP design method can be selected to reduce resource utilization; at high-speed sampling, a parallel design method of multiple DSPs is required to improve the calculation speed; when the difference between the sampling frequency and the cutoff frequency is large, a method of cascading multiple filters can be adopted to meet the filtering requirements of a large span.

[0076] The downsampling level of the envelope waveform and the instantaneous waveform, as well as the cutoff frequency of the filter, can be configured by the user.

[0077] Implementation Method 3 is a further definition of the FPGA-based digital sampling system described in Implementation Method 2. In this implementation method, the digital signal processing unit is further defined, specifically including:

[0078] The digital signal processing unit further includes a primary noise reduction unit, which is used to perform primary noise reduction on the real-time waveforms acquired by the multi-channel ADC and send the data after primary noise reduction to the triggering unit.

[0079] The digital signal processing unit in this embodiment can provide the trigger unit with data that is closer to the original data than the data output after downsampling by this unit. It is more appropriate to use this data as the analysis data for triggering, so as to realize the control of the trigger unit on different triggering conditions.

[0080] This implementation method divides the functions to be implemented into detailed units, so that each unit is specifically and exclusively responsible for a certain function or some functions. This allows for a clear description of the modules in which each function is located. As long as the connection conditions between modules and the characteristics of input and output signals are coordinated, the implementation can be completed quickly and efficiently.

[0081] Implementation Method Four: This implementation method further defines the FPGA-based digital sampling system described in Implementation Method One. In this implementation method, the input data in the register read / write control unit is further defined, specifically including:

[0082] The input data in the register read / write control unit includes the calculation results output by the waveform calculation unit and the address packets generated by the DDR control unit.

[0083] The register read / write control unit in this embodiment enables the uploading of outputs generated by the functional modules.

[0084] Implementation method five is a further definition of the FPGA-based digital sampling system described in implementation method one. In this implementation method, the DDR control unit is further defined, specifically including:

[0085] The DDR control unit includes a DDR address and data control unit, an address FIFO and data FIFO cache unit, and a DDR write control unit;

[0086] The DDR address and data control unit includes a DDR address control unit and a data control unit;

[0087] The DDR address control unit is used to analyze and parse the counting results transmitted from the data counting unit, determine the size of the address to be written to the DDR each time, and send the size of the address to be written to the DDR to the address FIFO and data FIFO buffer unit.

[0088] The data control unit is used to concatenate the incoming waveform signal and write it into the DDR, and send the concatenated waveform signal to the address FIFO and data FIFO buffer unit;

[0089] The address FIFO and data FIFO buffer unit is used to perform clock domain conversion and bit width conversion on the input data, and is also used to save the waveform that has not been written to DDR, and send the converted data and the saved data to the DDR write control unit;

[0090] The DDR write control unit is used to convert input data into a data format that conforms to the AXI protocol and control the reading and writing of DDR.

[0091] In this embodiment, the DDR control unit can realize the storage and uploading of input data from multiple channels with different sampling rates, and supports onboard deep storage, real-time waveform storage, waveform uploading and other functions.

[0092] In this embodiment, some waveforms that have not yet been written to DDR are saved as a buffer. This allows the FIFO to temporarily store some data when DDR data is sent up during real-time storage, thus avoiding the dead zone problem caused by the inability to read and write DDR data simultaneously.

[0093] Implementation method six is ​​a further definition of the FPGA-based digital sampling system described in implementation method one. In this implementation method, the DDR write control unit is further defined, specifically including:

[0094] The DDR write control unit further includes, before converting the input data into a data format conforming to the AXI protocol:

[0095] The empty signal of the data FIFO and address FIFO is detected. If the empty signal is not 1, the write operation of the AXI protocol is started.

[0096] Implementation method seven is a further definition of the FPGA-based digital sampling system described in implementation method one. In this implementation method, the waveform calculation unit is further defined, specifically including:

[0097] The waveform calculation unit includes 40 waveform calculation functions, and can generate waveform data corresponding to 16 waveform calculation functions simultaneously through configuration.

[0098] This embodiment includes 40 waveform measurement functions, such as maximum value, minimum value, average value, RMS value, period, frequency, etc. It can perform complex waveform feature calculations, including real-time calculations of multiple types of feature quantities.

[0099] Implementation method eight is a further limitation on the FPGA-based digital sampling system described in implementation method one. In this implementation method, the timing for the main state machine to determine the data writing time to the DDR control unit based on the counting result and the trigger signal is further limited, specifically including:

[0100] The master state machine is used to determine the time for writing data to the DDR control unit based on the register read / write control instructions received from the register read / write control unit, the counting result, and the trigger signal.

[0101] The master state machine processes signals related to data storage, including data control signals, mode configuration signals, and real-time trigger and counter signals.

[0102] In this embodiment, the main design idea is to process the mode configuration signal, trigger signal, and data point count result in the register read / write control instruction within the state machine.

[0103] The master state machine needs to select either start, stop, or start&stop storage mode depending on the storage timing configuration. Start mode begins storage when a trigger signal arrives and stops when the set number of points is reached; stop mode is manually controlled to begin storage and stops when a trigger is encountered or the set number of points is reached. Start&stop mode begins storage when a trigger is encountered and stops when another trigger is encountered or the set number of points is reached. In start mode, a pre-trigger length can be set, allowing storage of a waveform segment before the trigger start point. In stop mode, a post-trigger setting can be configured, storing a waveform segment after the trigger stop point. Start&stop mode allows both pre-trigger and post-trigger settings. Pre-trigger settings also support trigger priority settings, specifying whether to accept trigger signals before the set pre-trigger length is reached: when trigger priority is enabled, a new trigger signal is considered valid even before the set pre-trigger length is reached; when trigger priority is disabled, a trigger signal is considered valid only after the set pre-trigger length is reached. Finally, after the master state machine integrates all configuration conditions, trigger signals, and data point count results, it inputs a signal representing the start and end times to the DDR control unit.

[0104] Implementation Method Nine: This implementation method further defines the FPGA-based digital sampling system described in Implementation Method One. In this implementation method, the DDR control unit is further defined, specifically including:

[0105] The DDR control unit uploads the addresses of key points in a predetermined format.

[0106] In this embodiment, while controlling the address, the addresses of key points need to be uploaded to the host computer in a predetermined format so that the software can obtain the start and end addresses of DDR storage, pre-trigger and post-trigger points, memory partitioning points, etc.

[0107] Implementation method ten is a further definition of the FPGA-based digital sampling system described in implementation method one. In this implementation method, the register read / write control instructions are further defined, specifically including:

[0108] The register read / write control instructions include one or more of the following: parameter configuration for each functional module, sampling mode configuration, start signal transmission, or stop signal transmission.

[0109] This implementation method allows for the configuration of all functional modules, enabling the digital acquisition module to perform its intended functions.

[0110] Implementation method eleven, this implementation method is based on a specific embodiment of an FPGA-based digital sampling system as described above, and specifically includes:

[0111] The digital acquisition module designed in this embodiment mainly includes an FPGA and other hardware devices such as a digital sampling analog front-end, DDR, and PXIe. The digital sampling analog front-end converts the initial system input data from analog signals to digital signals and then inputs the converted data into the FPGA. The DDR implements onboard storage of data in the FPGA. The PXIe is responsible for retrieving data from the DDR and sending it to the host computer. This embodiment mainly focuses on the design of the FPGA architecture, with the core design being the internal logic design of the FPGA, which is implemented using Verilog.

[0112] The main system logic of FPGA is as follows Figure 1 As shown in the diagram. It should be noted that all thick arrows in the diagram represent waveform signals (in this embodiment, data signal, signal, and data all refer to waveform signals). Thin arrows represent the transmission of control signals, counting signals, trigger signals, and other related signals. The host computer's register configuration is distributed to each module through the "Register Read / Write and Control Unit" below; each module has its own registers.

[0113] The main idea behind this system design is to divide the functions to be implemented by the digital acquisition module into specific units, allowing each unit to be dedicated to a particular function or a set of functions. The advantage of this design is that it clearly outlines the modules responsible for each function, and by coordinating the connection conditions between modules and the characteristics of the input and output signals, implementation can be quick and efficient.

[0114] Furthermore, this system design approach optimizes the functionality between various modules. For example, dedicated counting units, state machine control, and DDR memory control allow complex tasks to be broken down into different modules. Simultaneously, code simplification and resource optimization can be performed on each module, improving system efficiency. The following is a detailed description of the system's functions:

[0115] 1. Digital Signal Processing Unit

[0116] The digital signal processing unit (ADC) is responsible for analyzing and processing the real-time waveforms acquired by multiple ADCs to generate two waveform data streams. ADC stands for Analog-to-Digital Converter.

[0117] The downsampling rate and filter cutoff frequency of both data streams are configurable by the user: one stream of instantaneous waveform with selectable downsampling rate and one stream of envelope waveform with selectable downsampling rate, the envelope waveform not exceeding the sampling rate of the instantaneous waveform.

[0118] Envelope waveforms can monitor the general trend of data in real time and can generate triggers in a timely manner when specific situations occur;

[0119] Instantaneous waveforms refer to waveforms acquired in real time, which are faster than trend waveforms. When a specific situation occurs, the instantaneous waveform near a specific point is saved for later viewing and analysis.

[0120] The configuration parameters of this unit, such as the filter cutoff frequency, can all be configured and sent by the user via a host computer. The main design logic is as follows: Figure 2 As shown.

[0121] This unit mainly consists of three parts: an anti-aliasing filtering unit, a downsampling unit, and an envelope extraction unit.

[0122] 1.1 Anti-aliasing filter unit:

[0123] The anti-aliasing filter unit mainly consists of a low-pass filter bank. Its primary function is to perform low-pass filtering on the signal to prevent spectral aliasing after sampling. This module can be flexibly designed and modified according to the maximum sampling rate supported by the digital acquisition module and the complexity of its functions: at low speeds, a serial DSP design method can be selected to reduce resource utilization; at high-speed sampling, a parallel design method using multiple DSPs is required to improve calculation speed; when there is a large difference between the sampling frequency and the cutoff frequency, multiple filters can be cascaded to meet the filtering requirements across a large range.

[0124] 1.2 Downsampling sampling unit:

[0125] The main function of the downsampling unit is to extract points from the filtered signal at equal intervals. The interval between the extracted points is configurable and can be set to the downsampling value required by the user. The waveform obtained after equal-interval extraction is the downsampled waveform, which can be directly output as the instantaneous waveform.

[0126] Meanwhile, if the user specifies the envelope waveform requirements, this unit will output one data channel to the envelope extraction unit for envelope waveform generation.

[0127] 1.3 Envelope Extraction Unit:

[0128] The main function of the envelope extraction unit is to extract the instantaneous waveform output from the previous step according to the envelope sampling rate set by the user, extract the maximum and minimum values ​​within a certain sampling time period, and output the envelope waveform.

[0129] 2. Data counting unit

[0130] The data counting unit mainly includes delay alignment of input data and trigger signals, and counting control of data points in various modes.

[0131] Since both the downsampling and triggering generation units have their own group delays, it is necessary to align the data signal and the trigger signal in time. Therefore, one function of this module is to adjust the delay according to different user configuration conditions to align the data signal and the trigger signal.

[0132] Another function of the data counting unit is to count the number of data points under different functional types. This unit must support counting for different functional types, including the number of memory blocks, pre-trigger and post-trigger points, and the control of various point counts such as instantaneous waveform and envelope waveform points. The start and stop of each counter are controlled by the timing of the main state machine.

[0133] 3. Triggering Unit

[0134] The main function of the trigger unit is to analyze the input data and mark the trigger point at the required location to trigger the signal. The input to this module is the data after primary noise reduction by the digital signal processing unit. Compared with the data output after downsampling by this unit, this data is closer to the original data, so it is more appropriate to use this data as the analysis data for triggering.

[0135] The triggering unit can generate different types of trigger signals based on different configuration information, such as level triggering, periodic triggering, window triggering, voltage drop triggering, etc.

[0136] The trigger input data counting unit and main state machine generated by this module are used to determine the start and end of storage and control the point counter.

[0137] 4. Waveform Calculation Unit

[0138] The waveform calculation unit is a unit that implements specific waveform calculation functions. This unit can perform real-time waveform calculations for multiple types of computational quantities simultaneously. This module has 40 selectable waveform measurement functions, such as: maximum value, minimum value, average value, RMS value, period, frequency, etc. Users can configure to select and simultaneously measure up to 16 types.

[0139] This module acquires the input waveform in real time and outputs the calculation result after a short delay. The calculation mode is configured through the host computer's control register, and the calculation result is stored in the register and retrieved by the host computer.

[0140] 5. Master State Machine

[0141] The main function of the master state machine is to combine the count of data points and the trigger signal to determine the time to write data to DDR.

[0142] The main design idea is to process all data signals, mode configuration signals issued by registers, trigger signals, and data point count results in the state machine.

[0143] The master state machine needs to select either start, stop, or start&stop storage mode depending on the storage timing configuration. Start mode begins storage when a trigger signal arrives and stops when the set number of points is reached (i.e., the count stops when the set number of points is reached). Stop mode is manually controlled to begin storage and stops when a trigger is encountered or the count reaches the set number of points. Start&stop mode begins storage when a trigger is encountered and stops when another trigger is encountered or the count reaches the set number of points. Furthermore, start mode allows setting a pre-trigger length, meaning a segment of waveform before the trigger start point can be stored in advance; stop mode allows setting a post-trigger, meaning a segment of waveform after the trigger stop point can be stored; and start&stop mode allows setting both pre-trigger and post-trigger. Simultaneously, the pre-trigger setting supports trigger priority configuration, specifying whether to accept trigger signals before the count reaches the set pre-trigger length points: When trigger priority is enabled, even if the count hasn't reached the set pre-trigger length points, a new trigger signal can be considered a valid pre-trigger condition. When trigger priority is disabled, trigger signals must wait until the count reaches the set pre-trigger length points before being considered valid. Finally, the master state machine integrates all configuration conditions, trigger signals, and data point count results, then inputs a signal representing the start and end times to the DDR control unit.

[0144] 6. DDR control unit

[0145] This module requires control of DDR read / write operations based on data received from the main state machine and the data counting unit. This unit includes DDR address and data control, address FIFO, data FIFO buffer, and DDR write control unit. The main modules are as follows: Figure 3 As shown.

[0146] The DDR control unit needs to select whether to store instantaneous waveform, envelope waveform, or both data into the DDR, depending on the sampling mode.

[0147] DDR address control requires analysis and parsing of the counting results from the data counting unit to determine the size of the address to be written to DDR each time; data control requires splicing the incoming waveform signals before writing them into DDR.

[0148] The data FIFO and address FIFO buffers can not only meet the requirements of clock domain conversion and bit width conversion, but also save a part of the waveform. Thus, when the real-time storage function is enabled, the FIFO can temporarily store a part of the data when DDR data is sent up, avoiding the dead zone problem caused by the inability to read and write DDR data at the same time.

[0149] The DDR write control unit needs to directly convert the stream data format output by the FIFO into a data format conforming to the AXI protocol and control the DDR read and write operations. This unit can detect the empty signals of the data FIFO and address FIFO. If the empty signal is not 1, it indicates that there is data and address signals that need to be read or written, and then the AXI protocol write operation is initiated.

[0150] The DDR control unit, while controlling the address, needs to upload the addresses of key points in a predetermined format to the host computer. This allows the software to obtain the start and end addresses of the DDR memory, pre-trigger and post-trigger points, memory partitioning points, etc. The address packet format is as follows: Figure 4 As shown.

[0151] Depend on Figure 4 As can be seen, when an address packet is uploaded, it contains a variety of information, including the address value, address type, trigger ID, and memory segment ID. The address value represents the actual value written to the address represented by the current packet; the address type indicates which address type the currently written address value is, such as start address, end address, pre-trigger address, or post-trigger address; the trigger ID represents the trigger number; and the memory segment indicates which segment of memory this address represents.

[0152] 7. Register read / write control unit

[0153] The primary function of this unit is to distribute the register read / write control instructions parsed by the AXI-Lite protocol to various modules. This includes issuing all modes and commands from the host computer, such as parameter configuration, sampling mode configuration, and start / stop signal transmission for each functional module. It also needs to upload the outputs generated by certain functional modules, such as calculated values ​​from the waveform calculation unit and address packets generated by the DDR address control unit.

Claims

1. A digital sampling system based on an FPGA, the system comprising an FPGA, a digital sampling analog front-end, and a DDR, characterized in that, The FPGA includes a digital signal processing unit, a data counting unit, a triggering unit, a waveform calculation unit, a main state machine, a DDR control unit, and a register read / write control unit; The digital signal processing unit is used to perform preliminary processing and analysis on the real-time waveforms acquired by the multi-channel ADC. The preliminary processing specifically includes performing primary noise reduction on the real-time waveforms acquired by the multi-channel ADC to obtain the primary noise reduction signal. The analysis processing specifically includes analyzing the real-time waveforms acquired by the multi-channel ADC to obtain the instantaneous waveform and the envelope waveform. The digital signal processing unit sends the primary noise reduction signal to the triggering unit, and sends the instantaneous waveform and envelope waveform to the data counting unit; The triggering unit is used to analyze the input data, mark the trigger point at the required position to trigger the signal, and send the generated trigger signal to the data counting unit and the main state machine. The data counting unit is used to perform time-delay alignment of the signal received from the digital signal processing unit and the trigger signal, and to control the counting of data points in various modes to obtain counting results; The data counting unit sends the delayed-aligned data and the counting result to the DDR control unit, and sends the delayed-aligned data to the waveform calculation unit; The waveform calculation unit is used to perform real-time waveform calculation on the input data and send the calculation results to the register read / write control unit. The master state machine is used to determine the time for writing data to the DDR control unit based on the counting result and the trigger signal, and sends the time signal to the DDR control unit. The DDR control unit is used to control DDR read and write based on the data input from the main state machine and the data counting unit, and sends the generated address packet to the register read and write control unit. The register read / write control unit is used to distribute the register read / write control instructions parsed by the AXI-Lite protocol to other units, and is also used to upload input data.

2. The FPGA-based digital sampling system according to claim 1, characterized in that, The digital signal processing unit includes an anti-aliasing filtering unit, a downsampling unit, and an envelope extraction unit. The anti-aliasing filtering unit includes a low-pass filter bank, which is used to perform low-pass filtering on the signal to prevent spectral aliasing after sampling, and sends the filtered signal to the downsampling sampling unit. The downsampling sampling unit is used to extract points from the filtered signal at equal intervals, and output the waveform extracted at equal intervals as an instantaneous waveform. The interval can be configured. The envelope extraction unit is used to receive the instantaneous waveform, extract the instantaneous waveform according to a preset envelope sampling rate, extract the maximum and minimum values ​​within a preset sampling time period, and output the envelope waveform.

3. The FPGA-based digital sampling system according to claim 2, characterized in that, The digital signal processing unit further includes a primary noise reduction unit, which is used to perform primary noise reduction on the real-time waveforms acquired by the multi-channel ADC and send the data after primary noise reduction to the triggering unit.

4. The FPGA-based digital sampling system according to claim 1, characterized in that, The input data in the register read / write control unit includes the calculation results output by the waveform calculation unit and the address packets generated by the DDR control unit.

5. The FPGA-based digital sampling system according to claim 1, characterized in that, The DDR control unit includes a DDR address and data control unit, an address FIFO and data FIFO cache unit, and a DDR write control unit; The DDR address and data control unit includes a DDR address control unit and a data control unit; The DDR address control unit is used to analyze and parse the counting results transmitted from the data counting unit, determine the size of the address to be written to the DDR each time, and send the size of the address to be written to the DDR to the address FIFO and data FIFO buffer unit. The data control unit is used to concatenate the incoming waveform signal and write it into the DDR, and send the concatenated waveform signal to the address FIFO and data FIFO buffer unit; The address FIFO and data FIFO buffer unit is used to perform clock domain conversion and bit width conversion on the input data, and is also used to save the waveform that has not been written to DDR, and send the converted data and the saved data to the DDR write control unit; The DDR write control unit is used to convert input data into a data format that conforms to the AXI protocol and control the reading and writing of DDR.

6. The FPGA-based digital sampling system according to claim 5, characterized in that, The DDR write control unit further includes, before converting the input data into a data format conforming to the AXI protocol: The empty signal of the data FIFO and address FIFO is detected. If the empty signal is not 1, the write operation of the AXI protocol is started.

7. The FPGA-based digital sampling system according to claim 1, characterized in that, The waveform calculation unit includes 40 waveform calculation functions, and can generate waveform data corresponding to 16 waveform calculation functions simultaneously through configuration.

8. The FPGA-based digital sampling system according to claim 1, characterized in that, The master state machine is used to determine the time for writing data to the DDR control unit based on the counting result and the trigger signal, specifically including: The master state machine is used to determine the time for writing data to the DDR control unit based on the register read / write control instructions received from the register read / write control unit, the counting result, and the trigger signal.

9. The FPGA-based digital sampling system according to claim 1, characterized in that, The DDR control unit uploads the addresses of key points in a predetermined format.

10. A digital sampling system based on FPGA according to claim 1, characterized in that, The register read / write control instructions include one or more of the following: parameter configuration for each functional module, sampling mode configuration, start signal transmission, or stop signal transmission.

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