Semiconductor devices and methods for forming trenches with improved removal depth in EMI shielding.

Abstract

This disclosure relates to a semiconductor device and method for forming trenches with improved removal depth in EMI shielding. The semiconductor device is formed by providing a semiconductor package including a shielding layer and forming trenches in the shielding layer using a laser. The laser is turned on and exposed to the shielding layer, wherein the center of the laser is positioned at a first point on the shielding layer. While the laser is held on and exposed to the shielding layer, the laser is moved in a loop. When the center of the laser is positioned at a second point on the shielding layer, the exposure of the laser to the shielding layer is stopped. The distance between the first and second points is approximately equal to the radius of the laser.

Description

Technical Field

[0001] This invention generally relates to semiconductor devices, and more particularly to a method and semiconductor device for forming slots with improved removal depth in an electromagnetic interference shielding layer on an electrical component in a system-in-package (SiP) module. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and generating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices, particularly in high-frequency applications such as radio frequency (RF) communications, typically include one or more integrated passive devices (IPDs) to perform necessary electrical functions. For higher density and expanded electrical functionality in a small space, multiple semiconductor dies and IPDs can be integrated into a System-on-Package (SiP) module. Within the SiP module, semiconductor dies and IPDs are mounted to a substrate for structural support and electrical interconnection. Encapsulant is deposited on the semiconductor dies, IPDs, and substrate. An electromagnetic shielding layer is typically formed on the encapsulant.

[0004] SiP modules comprise highly integrated high-speed digital and RF electrical components designed for small size, low height, and high clock frequencies. Electromagnetic shielding reduces or suppresses EMI, RFI, and other inter-device interference radiated by high-speed digital devices to prevent them from affecting adjacent devices within or near the SiP module. However, conformally applied electromagnetic shielding may not effectively resist EMI loop currents within the shielding material. EMI current loops can originate from high-energy / output devices, such as power amplifiers embodied in one or more electrical components. These EMI loop currents flow through the electromagnetic shielding and cause EMI, RFI, and other inter-device interference within or in sensitive adjacent devices within or near the SiP module. Attached Figure Description

[0005] Figures 1a-1c This illustrates a semiconductor wafer having multiple semiconductor dies separated by cleavage.

[0006] Figure 2a-2k This illustrates the process of mounting electronic components on a substrate in a SiP module with a slotted electromagnetic shielding layer.

[0007] Figure 3a and 3b This demonstrates how to improve the removal depth of molded parts at groove corners by utilizing corner radius;

[0008] Figures 4a-4c This illustrates the formation of a groove without overlapping start and stop points;

[0009] Figures 5a-5c This demonstrates the use of a two-step process to form a groove without overlapping start and stop points;

[0010] Figure 6a and 6b Showing slots with vertical overlap; and

[0011] Figure 7a and 7b This demonstrates the integration of slotted SiP modules into electronic devices. Detailed Implementation

[0012] In the following description, the invention is described in one or more embodiments with reference to the accompanying drawings, in which the same numerals denote the same or similar elements. While the invention is described according to the best mode for carrying out its objectives, those skilled in the art will understand that the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents supported by the following disclosure and the accompanying drawings. The term “semiconductor die” as used herein refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and multiple semiconductor devices.

[0013] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current required to perform the circuit's function.

[0014] Back-end manufacturing refers to the process of dicing or monolithizing a completed wafer into individual semiconductor dies and packaging those dies for structural support, electrical interconnection, and environmental isolation. To monolithize a semiconductor die, the wafer is scribed and broken along non-functional regions called scribe lines or kerfs. The wafer is monolithized using laser cutting tools or saw blades. After monolithization, the individual semiconductor dies are mounted onto a package substrate, which includes pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor die are then connected to contacts within the package. Electrical connections can be made using conductive layers, bumps, column bumps, conductive paste, or wire bonding. Encapsulant or other molding materials can be deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the semiconductor device functional for other system components.

[0015] Figure 1a A semiconductor wafer 100 is shown having a substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials used for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100, separated by passive, inter-die wafer regions, or cleavages 106. Cleavages 106 provide dicing areas to monolithize the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0016] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or passive surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as a digital signal processor (DSP), power amplifier, application-specific integrated circuit (ASIC), memory, or other signal processing circuitry. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0017] A conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as contact pads for electrical connections to circuitry on the active surface 110.

[0018] Conductive bump material is deposited on conductive layer 112 using evaporation, electroplating, electroless plating, droplet plating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, combinations thereof, or other suitable conductive materials with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using suitable adhesion or bonding processes. In one embodiment, the bump material is reflowed to form balls or bumps 114 by heating it above its melting point. In one embodiment, bumps 114 are formed on an under-bump metallization (UBM) layer having a wetting layer, a barrier layer, and an adhesive layer. Bumps 114 can also be compression bonded or thermo-pressed bonded to conductive layer 112. Bumps 114 represent a type of interconnect structure that can be formed on conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, column bumps, microbumps, or other electrical interconnects.

[0019] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to monolithize the semiconductor wafer 100 into individual semiconductor dies 104 through cuts 106. Individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies (KGD) after monolithization.

[0020] Figure 2a-2k This illustrates a process for setting electrical components on an interconnect substrate to form a SiP module with a slotted electromagnetic shielding layer. Figure 2a A cross-sectional view of an interconnect substrate 120 including a conductive layer 122 and an insulating layer 124 is shown. The conductive layer 122 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 122 provides horizontal electrical interconnects across the substrate 120 and vertical electrical interconnects between the top surface 126 and the bottom surface 128 of the substrate 120. Portions of the conductive layer 122 may be electrically shared or electrically isolated, depending on the design and function of the SiP module being formed. The insulating layer 124 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer 124 provides isolation between the conductive layers 122. In other embodiments, any suitable type of substrate or leadframe may be used for the substrate 120.

[0021] exist Figure 2bIn this configuration, electrical components 130a and 130b are mounted to surface 128 of interconnect substrate 120 and electrically and mechanically connected to conductive layer 122 via bumps 114. Each of electrical components 130a and 130b is positioned on substrate 120 using pick-and-place operations. For example, electrical components 130a and 130b may be from… Figure 1c The semiconductor die 104 has an active surface 110 and bumps 114 oriented toward a surface 128 of the substrate 120 on component attachment regions 129a and 129b. Alternatively, electrical components 130a and 130b may include other semiconductor dies, semiconductor packages, surface mount devices, power amplifiers, discrete electrical components, or IPDs, such as resistors, capacitors, and inductors. Any number and type of components can be mounted as desired.

[0022] exist Figure 2d In this process, an encapsulant or molding compound 136 is deposited on and around electrical components 130a, 130b, and substrate 120 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant 136 can be a polymer composite material, such as a polymer with or without fillers, epoxy resin, or epoxy acrylate. The encapsulant 136 is non-conductive, provides structural support, and protects the semiconductor device from external elements and contaminants in the environment. Electrical components 130a and 130b, mounted to interconnect substrate 120 and covered by encapsulant 136, constitute SiP module 138.

[0023] exist Figure 2e In this process, multiple vias 134 are formed into the surface 137 of the encapsulant 136 using etching, drilling, or direct laser ablation (LDA) with laser 139. The vias 134 are aligned with and extend into portions of the conductive layer 122 on the interconnect substrate 120. Figure 2f In this process, vias 134 are filled with Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), polysilicon, combinations thereof, or other suitable conductive materials using paste printing and reflow, electrolytic plating, chemical plating, or other suitable metal deposition processes to form z-direction vertical conductive pillars 140. The conductive pillars 140 are electrically connected to the conductive layer 122. The conductive pillars 140 may be formed on the conductive layer 122 of the substrate 120 prior to encapsulant 136. In this case, encapsulant 136 will be deposited on the conductive pillars 140.

[0024] Electrical components 130a and 130b may include IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included in electrical components 130a and 130b provide the electrical characteristics required for high-frequency applications such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetrical Hi-Q (high quality factor) resonant transformers, and tuning capacitors. In another embodiment, electrical components 130a and 130b include digital circuitry that switches at high frequencies, which may interfere with the operation of the IPDs in the SiP module.

[0025] exist Figure 2g In this process, an electromagnetic shielding layer 142 is formed or disposed on the surface 144 of the encapsulant 136 by conformally applying a shielding material. The shielding layer 142 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the shielding layer 142 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, silicon-iron steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. Furthermore, the shielding layer 142 covers the side surface 146 of the encapsulant 136 and the side surface of the substrate 120.

[0026] SiP module 138 includes high-speed digital and RF electrical components 130a and 130b, which are highly integrated for small size, low profile, and high clock frequency operation. Electromagnetic shielding layer 142 reduces or suppresses EMI, RFI, and other inter-device interference radiated by high-speed digital devices, so as not to affect adjacent devices within or adjacent to SiP module 138. However, the conformally applied electromagnetic shielding layer 142 itself may not effectively resist EMI loop currents within the shielding material. EMI current loops can originate from high-energy / output devices, such as power amplifiers embodied in one or more of electrical components 130a and 130b. EMI loop currents flow through electromagnetic shielding layer 142 and cause EMI, RFI, and other inter-device interference within or in sensitive adjacent components within SiP module 138. As an example, loop current injected by component 130a through shielding layer 142 may potentially flow on component 130b and cause interference in component 130b.

[0027] To neutralize or block EMI loop currents, laser direct ablation (LDA) or laser cutting using laser 151 is used to form grooves, channels, or trenches 150 in the electromagnetic shielding layer 142, such as... Figure 2hAs shown, the groove 150 completely cuts through the electromagnetic shielding layer 142. That is, the groove 150 extends at least into the encapsulant 136 or partially into the encapsulant to completely cut through the electromagnetic shielding layer 142. Figure 2i This is a top view of the SiP module 138, in which a slot 150 is formed to electrically isolate the main body portion 142a of the electromagnetic shielding layer 142 from the corner portion 142b. The slot 150 creates an electrical open or disconnect between the shielding portions 142a and 142b of the electromagnetic shielding layer 142. EMI loop currents cannot flow across the slot 150 between the shielding portions 142a and 142b, and vice versa. There is no conductive path between the shielding portions 142a and 142b. The slot 150 provides an additional layer of protection by electrically isolating the shielding portions 142a and 142b to reduce or suppress EMI, RFI, and other inter-device interference within or in sensitive adjacent components of the SiP module 138.

[0028] In another embodiment, such as Figure 2j As shown, using LDA or laser cutting with laser 151, the groove 150 is formed into a continuous loop in the electromagnetic shielding layer 142. The groove 150 completely cuts through the electromagnetic shielding layer 142. That is, the groove 150 extends at least into the encapsulant 136 or partially into the encapsulant to completely cut through the electromagnetic shielding layer 142. Figure 2k This is a top view of the SiP module 138, in which a slot 150 is formed to electrically isolate the main body portion 142a of the electromagnetic shielding layer 142 from the inner island portion 142b. The slot 150 creates an electrical disconnect or separation between the shielding portions 142a and 142b of the electromagnetic shielding layer 142. EMI loop currents cannot flow across the slot 150 between the shielding portions 142a and 142b, and vice versa. There is no conductive path between the shielding portions 142a and 142b. The slot 150 provides an additional layer of protection by electrically isolating the shielding portions 142a and 142b to reduce or suppress EMI, RFI, and other inter-device interference within or adjacent to sensitive neighboring components of the SiP module 138.

[0029] One issue that could negatively impact the final quality of the SiP module is when the slot 150 is not formed to a uniform depth. If certain areas of the slot 150 are unintentionally formed too deep into the encapsulant 136, there is a risk that the underlying components may be damaged. One area where slot depth can be difficult to control is where the laser 151 must travel around sharp 90-degree corners as it pulls the slot 150 along its path.

[0030] Figure 2iPath 154 shows the position where laser 151 must make a sharp turn to create groove 150. The logic of how the position of laser 151 is controlled means that the movement of the laser may pause briefly at corner 156. Typically, there are two separate mechanisms for movement in the Y and X directions, as shown on axis 158. When reaching a corner, the movement of one of the mechanisms must come to a complete stop, while the movement of the other mechanism begins to lead laser 151 in the opposite direction. The start and stop of movement means that laser 151 is difficult to turn without stopping at corner 156 for at least a brief moment. The brief delay that laser 151 spends at the turning corner 156 allows the laser to dig deeper into the encapsulant 136 in the corner than in the area where the laser travels in a constant linear motion.

[0031] Figure 3a and 3b This illustrates a method for increasing the uniformity of groove depth by applying a radius to the corners of the groove instead of having sharp corners. Figure 3a A groove 160 with rounded corners 162 is shown being formed. Path 164 shows the path taken by laser 151 as it rounds corner 162 to form groove 160. Applying a radius to corner 162 means there are no longer abrupt stops and starts at the corner of the groove. Laser 151 can smoothly transition from motion in the Y direction to motion in the X direction and vice versa over a distance determined by the specific radius used. In contrast, Figure 2k The square corner has a laser 151 that changes direction at essentially a single point.

[0032] In the case of using two separate mechanisms to move laser 151 in the X and Y directions, each mechanism is allowed to smoothly transition between movement and stop, rather than... Figure 2k The abrupt transition in the middle. When laser 151 along... Figure 3a When the path 164 moves, the movement in the Y direction transitions from forward movement when the laser is moving vertically on the page to a stop when the laser is moving horizontally. Simultaneously, the movement in the X direction transitions from a stop when the laser is moving vertically to forward movement when the laser is moving horizontally. Both the X-direction and Y-direction movements transition along the entire curve of corner 162.

[0033] Figure 3b A detailed view of corner 162 is shown as laser 151 transitions from moving in the positive X direction to moving in the negative Y direction. The radius R being applied to corner 162 is shown. C Corner 162 forms an arc around point 170. Point 170 is a radius R. CThe distance from each point on the bend of corner 162. Arrows 172a, 172b, and 172c indicate the same distance between three different points along path 164 around corner 162. In other embodiments, corner 162 is rounded, but not exactly circular. Applying the corner radius to the formation of groove 160 results in a removal depth of corner 162 that is the same as or similar to the removal depth within the straight section between corners. Uniform groove depth reduces the likelihood that components below groove 160 will be damaged by laser 151.

[0034] Another area where material removal by laser 151 may be uneven is where the end of the laser path meets the beginning of the laser path during groove formation. The end of the laser path typically overlaps with the beginning to ensure the groove forms a closed loop. However, exposing the overlapping portion of the groove to laser 151 twice results in an increased groove depth at that point. Double exposure also potentially causes horizontally spreading damage, which can damage not only the surrounding shielding layer but also potentially damage components underneath over a wider area.

[0035] To solve this problem, laser 151 can be controlled to have an end point that does not overlap with the start point. This non-overlapping path is achieved by making the distance from the end point to the start point of the laser equal to or approximately equal to the radius of the beam emitted by laser 151. Laser 151 operates in transverse electromagnetic mode 00 (TEM). 00 The emitted light. Therefore, the energy of the laser 151 from the impact shielding layer 142 has an approximately Gaussian distribution, such as... Figure 4a As shown.

[0036] Figure 4a The energy distribution of the beam from laser 151 is shown in plot 180, where the Y-axis represents the energy level and the X-axis represents the distance. The energy from laser 151 is strongest at the center 182 of the laser beam and decreases with increasing distance from the center. The radius R of the beam from laser 151 is... L It is considered to be the distance from the center 182 to the point on the X-axis where the energy level reaches near zero.

[0037] Figure 4b The diagram shows the coverage area 190a of the laser beam originating from laser 151 at the start of groove formation, superimposed on the coverage area 190b of the laser beam at the end of groove formation. When groove 150 is formed, laser 151 begins at the center 182 of the laser beam at point 192a, follows a complete loop around the groove, and ends at the center of the laser beam at point 192b. Arrow 194a shows the movement of laser 151 when groove formation 150 begins, while arrow 194b shows the movement of the laser when the groove is completed.

[0038] The distance between the starting point 192a and the stopping point 192b of laser 151 is approximately equal to the radius R of the laser beam. L For example, if the laser diameter is 20 micrometers (μm), the distance between points 192a and 192b will be 10 μm. Therefore, the coverage area 190a exposed to laser 151 at the beginning of trench formation partially overlaps with the coverage area 190b exposed to laser 191 at the end of trench formation. However, the initial energy peak at point 192a only overlaps with the relatively low-energy region of coverage area 190b. Similarly, the ending point 192b only overlaps with the relatively low-energy region of coverage area 190a.

[0039] Figure 4c Showing when using from Figure 4b The spacing is the amount of energy received by each region of the slot 150 from the laser 151. Figure 198 shows the total amount of energy received, while the representations of the start coverage region 190a and the end coverage region 190b show the amount of energy received at the time when the laser 151 is at the start and end positions, respectively. The total energy level 198 is substantially flat to the right of coverage region 190a in region 200a and substantially flat to the left of coverage region 190b in region 200b, where the laser 151 simply sweeps across with a constant power output. The total power 198 has: two small peaks 202a and 202b, where coverage regions 190a and 190b overlap near their respective peaks; and a valley 204, where both laser coverage regions are below half power. Even though the power output of the laser 151 is not absolutely constant for the entire formation of the slot 150, it is relatively constant compared to a manufacturing process that forms the slot by completely overlapping the end point 192a and the start point 192b. The power output is kept high enough to completely remove the shielding layer 142 throughout the entire slot loop, but not high enough to cause significant damage to the components below during overlap.

[0040] Figures 4a-4c The process requires highly precise laser control to start and stop the laser within half the diameter of the laser beam.151 Such a high level of control is likely impossible for all laser control systems at the sufficiently high speeds that would be useful in manufacturing. Figures 5a-5c Another option is shown. Initially, in Figure 5a and 5b In this process, laser 151 is used to form a groove 150a from a start point 210 to an end point 212. The coverage area 214 of laser 151 exists around the start point 210, while the coverage area 216 of laser 212 exists at the end point 212.

[0041] A gap 218 exists between points 220 and 222 on the circumferences of coverage areas 210 and 212, respectively, ensuring that the start and end coverage areas of laser 151 do not overlap. The distance between points 220 and 222 can be any suitable amount. One mechanism for leaving the gap 218 between the start and stop points is through laser on / off control. Typically, laser 151 will be on for a certain period before being exposed to shielding layer 142; this is the laser on-delay. After slot 150 is completed, the laser will also typically remain on for a certain period; this is the laser off-delay. During the on-delay and off-delay periods, laser 151 is on and generates a beam, but this beam is not allowed to illuminate shielding layer 142. Although any timing can be used, a typical timing could be an on-delay of 10 microseconds (μs) and an off-delay of 100 μs. With a short on-delay and a long off-delay, the start and stop points may meet. If the timing is changed to include a long turn-on delay and a short turn-off delay, a gap 218 may be left between the start and stop points.

[0042] Laser 151 forms groove 150a at a relatively high rate and power level, thus forming the groove relatively quickly. However, the relatively high speed makes... Figures 4a-4c It becomes difficult to overlap the two parts by exactly one radius. After forming the groove 150a with the gap 218, a laser 151 is used at a lower speed and lower power output to close the gap, so as to have more precise control over the start and stop points.

[0043] exist Figure 5c The second laser phase of the closed gap 218 is shown. In the second phase, the laser 151 changes from being centered at point 222 to being centered at point 220. The overlap between the laser at point 222 and the coverage area 216 is approximately equal to or exactly equal to the radius of the laser beam, similar to... Figure 4b The diagram shown in the figure illustrates this. The overlap between the laser at point 220 and the coverage area 214 is also approximately equal to or exactly equal to the radius of the laser beam. Therefore, the total power profile at the beginning and end of gap 218 is similar to... Figure 4c The outline shown in the image. Figure 5c The second stage of laser etching, as shown, is performed at a lower speed, making precise start and end points easier to achieve. Furthermore, the short distance of gap 218 relative to the entire groove means that the lower speed has a less significant impact on the overall production time.

[0044] Although the loop-shaped groove 150 is shown above, where the start and end meet overlapping, the same basic manufacturing principles apply to any groove design with overlap. Besides the end-to-end overlap just discussed, another common type of overlap is when the groove lines meet at right angles. Figure 6aThe E-shaped groove design is shown. The E-shape includes two external forks 230 and a back 232 that form the bracket shape. The forks 230 and the back 232 can be formed by the laser 151 in a continuous motion using a rounded turn at the corner 233.

[0045] The E-groove also includes an intermediate tooth 234 formed to extend from the back 232 at a 90-degree angle. The tooth 234 is formed with a movement separate from the tooth 230 and the back 232. The laser 151 is turned off or shielded such that when the laser moves from the end point of the tooth 230 to the beginning point of the tooth 234, the laser does not irradiate the shielding layer 142, and vice versa. The tooth 230, tooth 234, and back 232 can be considered as a single E-groove simply formed from two discrete and connected parts. The tooth 234 is formed by the laser 15 and overlaps with the path used to form the back 232. Point 236 is the center of the beam from the laser 151 that forms the back 232. Point 238 is on the circumference of the laser coverage area and is the position where the center of the laser 151 is placed when the formation of the intermediate tooth 234 begins or ends. When the intermediate serration 234 is formed, overlapping the back 232 with a radius that is exactly or approximately the same as that of the laser 151 results in the serration 234 being formed appropriately without significantly increasing the total laser power exposed to the back 232. In other embodiments, the serration 234 is formed before the back 232, but the same radius overlap distance applies.

[0046] Figure 6b An H-shaped groove with two sides 240 connected by a crossbar 242 is shown. The center of laser 151 passes through point 246 when forming the sides 240. When forming the crossbar 242, laser 151 begins at point 248 on the circumference of the laser coverage area when forming the sides 240. Laser 151 also ends once the laser beam coverage area overlaps the radius of the laser with the opposite end 240. The concept of overlapping half the laser diameter can be applied to any groove design with overlap. The groove can also be T-shaped, F-shaped, P-shaped, or any other shape with groove overlap.

[0047] Figure 7a and 7b The above-described package (e.g., SiP module 138) is shown to be incorporated into electronic device 300. Figure 7aA partial cross-section of a SiP module 138, mounted as part of an electronic device 300 onto a printed circuit board (PCB) or other substrate 302, is shown. Bumps 306 are formed on a conductive layer 122 on the bottom of a substrate 120. The conductive bumps 306 can be formed at any stage of the manufacturing process, such as before molding the encapsulant 136, before monolithization, or after forming and patterning the shielding layer 142. The bumps 306 are reflowed onto the conductive layer 304 of the PCB 302 to physically attach and electrically connect the SiP module 138 to the PCB. In other embodiments, thermoforming or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the SiP module 138 and the PCB 302. Components 130a and 130b are electrically coupled to the conductive layer 304 via the substrate 120 and the bumps 306.

[0048] Figure 7b An electronic device 300 is shown having multiple semiconductor packages (including SiP module 138) mounted on a surface of PCB 302. The electronic device may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application. Electronic device 300 may be a standalone system using semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 300 may be a sub-component of a larger system. For example, electronic device 300 may be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device 300 may also be a graphics card, network interface card, or another signal processing card inserted into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, and other semiconductor dies or electrical components.

[0049] exist Figure 7b In this PCB 302, a general substrate is provided for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on the surface of PCB 302 or within layers of PCB 302 using evaporation, electroplating, chemical plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between the semiconductor package, mounted components, and other external systems or components. Trace 304 also provides power and ground connections to the semiconductor package as needed.

[0050] In some embodiments, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB 302. In other embodiments, the semiconductor device may have only a first-level package, wherein the die is directly mechanically and electrically mounted to the PCB 302.

[0051] For illustrative purposes, several types of first-level packages, including wire bond packages 306 and flip chips 308, are shown on PCB 302. Additionally, several types of second-level packages, including ball grid array (BGA) 310, bump chip carrier (BCC) 312, contact grid array (LGA) 316, multi-chip module (MCM) 318, quad flat no-lead (QFN) package 320, quad flat package 322, and eWLB 324, are shown mounted on PCB 302 together with SiP module 138. Conductive traces 304 electrically couple the various packages and components disposed on PCB 302 to SiP module 138, thereby enabling the use of components within SiP module 138 to other components on the PCB.

[0052] Depending on system requirements, any combination of semiconductor packages configured with any combination of first and second level package styles, along with other electronic components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs for consumers.

[0053] While one or more embodiments of the invention have been shown in detail, those skilled in the art will understand that modifications and adaptations to those embodiments may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide semiconductor packaging including a shielding layer; as well as The following steps are used to form grooves in the shielding layer using a laser. The laser is activated and exposed to the shielding layer, wherein the center of the laser beam strikes a first point on the shielding layer of the semiconductor package. While the laser is held on and exposed to the shielding layer, the laser is moved in the loop by moving the laser in a first direction from the first point. Exposure of the laser beam to the shielding layer of the semiconductor package ceases when the center of the laser beam strikes a second point. The distance between the first and second points, in a second direction opposite to the first direction originating from the first point, is approximately equal to the radius of the laser beam. When the center of the laser beam is positioned at a third point on the shielding layer, the laser exposure to the shielding layer is stopped for the first time, wherein the distance between the first point and the third point is greater than the radius of the laser beam. The shielding layer was exposed to the laser a second time, and When the shielding layer is exposed to the laser for the second time, the laser is moved from the fourth point to the second point, wherein the distance from the third point to the fourth point is approximately equal to the radius of the laser beam. Wherein, the first moving rate of the laser when moving the laser in the loop is greater than the second moving rate of the laser when moving the laser from the fourth point to the second point.

2. The method according to claim 1, wherein, The laser's on-time delay is greater than the laser's off-time delay.

3. The method according to claim 1, wherein, The semiconductor package includes electrical components disposed below the loop.

4. The method according to claim 1, wherein, The loop includes rounded corners.

5. A method for manufacturing a semiconductor device, comprising: Provide semiconductor packaging including a shielding layer; and The following steps are used to form grooves in the shielding layer using a laser: The laser is activated and exposed to the shielding layer, wherein the center of the laser beam strikes a first point on the shielding layer of the semiconductor package. While the laser is held on and exposed to the shielding layer, the laser is moved in the loop, and When the center of the laser beam is set at the third point of the shielding layer, the exposure of the laser to the shielding layer is stopped for the first time, wherein the distance between the first point and the third point is greater than the radius of the laser beam; The shielding layer is exposed to the laser for the second time. When the shielding layer is exposed to the laser for the second time, the laser is moved from the fourth point to the second point, wherein the distance from the third point to the fourth point is approximately equal to the radius of the laser beam, wherein the distance between the first point and the second point is approximately equal to the radius of the laser beam, and wherein the laser moves at a lower speed when moving from the fourth point to the second point compared to when moving the laser in the loop.

6. The method of claim 5, wherein the first point is at the beginning of the formation of the groove.

7. The method of claim 5, wherein the second point is at the end of the formation of the groove.

8. The method of claim 5, further comprising forming the groove having rounded corners.

9. A method for manufacturing a semiconductor device, comprising: An encapsulant is provided, the encapsulant comprising a shielding layer formed on the encapsulant; as well as The groove is formed in the shielding layer by the following steps: The laser is activated and exposed to the shielding layer, wherein the center of the laser beam strikes a first point on the shielding layer. While the laser is held on and exposed to the shielding layer, the laser is moved in the loop, and When the center of the laser beam is set at the third point of the shielding layer, the exposure of the laser to the shielding layer is stopped for the first time, wherein the distance between the first point and the third point is greater than the radius of the laser beam; The shielding layer is exposed to the laser for the second time. When the shielding layer is exposed to the laser for the second time, the laser is moved from the fourth point to the second point, wherein the distance from the third point to the fourth point is approximately equal to the radius of the laser beam, wherein the distance between the first point and the second point is approximately equal to the radius of the laser beam, and wherein the moving speed of the laser when it is moved from the fourth point to the second point is different from that when the laser is moved in the loop.

10. The method of claim 9, further comprising: Provide the first electrical components; as well as The encapsulant is deposited on the first electrical component.

11. The method of claim 10, further comprising: Provide a second electrical component; A conductive post is provided between the first electrical component and the second electrical component; as well as The encapsulant is deposited on the second electrical component and the conductive pillar.

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