Method for grabbing object pin, test chip and design method and system thereof

Abstract

The application provides a method for grabbing a pin of an object based on a template, comprising determining an object to be grabbed, which is recorded as a target object; obtaining an object template of the target object, which comprises a matching layer and a winding layer; and grabbing a pin of the target object in a layout based on the object template of the target object. The pin can be connected and defined flexibly according to specific test requirements, and the type of the target object and the number of pins are not limited; not only multiple MOSFETs without direct connection relationship or other connection relationship can be recognized and grabbed, but also various types of test objects which are relatively complex devices or do not belong to the devices can be automatically recognized and grabbed. The application also provides a test chip design method, a test chip design system and a test chip, which have corresponding advantages.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design and manufacturing technology, and particularly relates to a method for picking up object pins based on a template, and a corresponding test chip design method, design system, and test chip. Background Technology

[0002] Currently, in semiconductor design and manufacturing, users typically infer the status of corresponding devices within a product chip by testing the test structures within the test chip. A crucial step in test chip design is pinning key components to create subsequent wire-wound connections for forming test paths. Current automated pin-picking methods are relatively simple, generally only applicable to MOSFETs or their series / parallel connections. They cannot identify multiple MOSFETs without direct or other connections, and are even less capable of automatically identifying more complex devices such as DIODs, BJTs, and varactors, or devices that are not even considered components.

[0003] To understand whether specific components in a product chip have failed and whether their electrical characteristics meet requirements, it is necessary to design test chips capable of testing the electrical parameters of key components in a real physical environment. These test chips are typically created by modifying the interconnect and back-end process layers while keeping the front-end and mid-end process layers of the product chip unchanged, thus providing a realistic physical testing environment for the devices. During the design process of these test chips, current methods for automatically identifying device pins are no longer sufficient to accommodate more types of devices or more complex test structures.

[0004] Therefore, there is a great need to research a method for grasping the pins of target devices that has no restrictions on the type and number of pins of the object under test, as well as a corresponding test chip design method, design system, and test chip that can be applied to grasping the pins of key devices, and then design test chips that can be tested in a real physical test environment with better test results, thereby further promoting the in-depth development and widespread application of semiconductor design and manufacturing technology. Summary of the Invention

[0005] This invention addresses all or part of the problems of the prior art. One aspect of this invention provides a method for picking up target pins based on a template, applicable to picking up target device pins where there are no restrictions on the type or number of pins of the object under test. Another aspect of this invention provides a test chip design method, combining the target pin picking method of this invention for test chip design. This invention also provides a test chip design system and a test chip.

[0006] This invention provides a method for capturing target pins based on a template, comprising: acquiring a layout file; identifying an object in the layout whose pins are to be captured, designating it as a target object; and acquiring an object template for the target object. The object template includes a matching layer and a winding layer. The matching layer is a layer used for graphic matching, and the winding layer is a layer of connecting lines used to bring out the terminals of the object. Capturing the pins of the target object in the layout based on the object template includes: using the matching layer of the object template to perform a matching search in the layout; after finding a graphic that matches the graphic of the matching layer, copying the winding layer of the object template and adding it to the corresponding position in the layout to bring out the terminals of the target object, thereby capturing the pins of the target object. By obtaining the object template of the target object, the pins of the target object can be identified and captured using the object template. The steps are simple, and the pins can be connected and defined according to the test requirements. This breaks through the limitations of existing methods for automatically identifying device pins on the type and number of the target object. It enables the identification and capture of multiple MOSFETs that have no direct connection or other connection relationship in chip design, as well as the effective automatic identification and capture of more complex devices such as DIODE, BJT, and varactor, or objects that are not conventional devices.

[0007] After identifying the target object, the location point of the target object in the layout is also obtained. When performing a matching search in the layout using the matching layer of the object template, the matching search is performed within a preset matching range centered on the location point in the layout.

[0008] The method for obtaining the location point of the target object in the layout includes: pre-setting a layer for matching and identifying the target object as a marker layer or a graphic as a feature graphic; wherein, the marker layer refers to: a feature layer for matching and identifying the target object, or an identifier layer that collects the location point coordinate information of the target object; using the marker layer or feature graphic of the target object to match and identify the target object in the layout, and obtaining the location point coordinate information of the target object.

[0009] The object template also includes a layer: a pin label layer, used to mark the electrodes of the pins. By including the pin label layer to mark the electrodes of the pins, it is possible to clearly identify whether the electrodes of the pins are source, drain, gate, or body in the subsequent pin capture results, which is more conducive to the effective implementation of subsequent related processes.

[0010] The method for obtaining the object template includes: creating an object template; the creation method includes: locating the object in the layout and cropping the layout of the object as the prototype layout of the template; simplifying the prototype layout to obtain the object template. By first locating the object, cropping the layout of the object from the layout as the prototype layout of the template, and then processing it to obtain the object template, the layout processing is further simplified, which helps to improve design efficiency. Obtaining the object template can also involve directly importing a previously created object template for reuse, rather than obtaining it through re-creation; this is not limited here.

[0011] The step of using the object's layout as a prototype layout template includes: determining whether the object is a primitive in the layout; if so, then using the primitive's layout as the prototype layout; if not, then using the object and its graphics within a preset range together as the prototype layout. Primitives in the layout are created by referencing basic primitives or arraying basic primitives or graphics; the basic primitives refer to polygonal structures in a layer.

[0012] The prototype layout is simplified by: deleting the latter part of the winding layer in the prototype layout, and then adding several connecting lines to obtain several new winding layers to bring out the terminals of the object as pins; the connecting lines in the new winding layers include connecting lines with the same path as the connecting lines in the prototype layout and / or newly created connecting lines (using the winding lines in the prototype layout as much as possible); marking the electrodes of the pins using the pin label layer; determining several layers (with distinctive graphic features) in the prototype layout as matching layers, and deleting incomplete graphics in the matching layers to obtain the object template; wherein, the incomplete graphics refer to basic graphic elements that were truncated when the prototype layout was cut from the layout. By simplifying the prototype layout, the layout processing is further simplified and the design efficiency is optimized.

[0013] In other cases, simplifying the prototype layout may also include: after obtaining the object template, deleting all layers in the object template except for the matching layer, the newly added winding layer, and the pin marker layer.

[0014] After copying the winding layer from the object template and adding it to the corresponding position in the layout, the electrodes of the target object pins are defined using the pin marker layer.

[0015] A graphic that matches the graphic of the matching layer refers to a graphic that is completely identical to the graphic of the matching layer, or a graphic that is a mirror image of the graphic of the matching layer in either of two mutually orthogonal directions. The graphic that is a mirror image of the graphic of the matching layer in either of two mutually orthogonal directions can be a mirror image of the graphic of the matching layer along the X-axis in a Cartesian coordinate system, or a mirror image of the graphic of the matching layer along the Y-axis.

[0016] Using the matching layer of the object template, a graphic matching search is performed within the matching range (Template Match Search Range) centered on the positioning point in the layout. Specific steps include: Step a): Setting matching parameters: Setting the coordinates of the matching point (coordinates (DeviceX, DeviceY)), the preset matching range (Template Match Search Range), and the allowable range for matching coordinate errors (Template MatchCoordinate Tolerance) in the matching layer of the object template; Step b): Aligning the matching point with the positioning point in the layout, and performing graphic matching using the matching layer of the object template: If the matching is successful, the matching search is completed; if the matching fails, the subsequent steps continue; Step c): Moving the matching point within the allowable range for matching coordinate errors centered on the positioning point, so that the matching layer performs graphic matching within the matching range centered on the positioning point: If the matching is successful, the matching search is completed; if the matching fails, the subsequent steps continue; Step d): Determining whether to adjust the matching parameters: If the matching parameters are adjusted (e.g., expanding the matching range and the allowable range for matching coordinate errors), then proceed to step b); if the matching parameters are not adjusted, then the current matching search ends.

[0017] After capturing the target object's pins based on the object template (by copying the winding layer of the object template and adding it to the corresponding position in the layout to bring out the terminals of the target object to capture its pins), the remaining pins of the target object are automatically captured as well (for example, for transistors, only the source, drain, and gate pins are captured using the object template, while the body pin is captured automatically), thus completing the capture of all pins of the target object. After capturing the target object's pins, it can flexibly determine whether all the required pins have been captured according to the specific needs of the actual application. If not, other pins can be captured further. For example, for transistors, if the source, drain, and gate pins are captured using the object template, it can be selected whether to capture the corresponding body pin simultaneously, or if necessary, the corresponding body pin can be captured using the general automatic capture method to capture all pins. Combining pin capture via the object template with automatic pin capture makes it more flexible for actual production and better meets the needs of specific applications.

[0018] Another aspect of the present invention provides a test chip design method, comprising: step S1. inputting a product chip layout and obtaining objects and their information in the product chip layout based on graphical interpretation; wherein the product chip layout includes a front-end layer and a back-end layer; step S2. creating a back-end layer of the test chip, comprising: arranging several pads on the product chip; selecting several objects as target objects; capturing the pins of the target objects; assigning pads to the pins of the target objects and connecting the pins of the target objects to the assigned pads by routing wires; wherein capturing the pins of the target objects includes obtaining them using a template-based pin capture method provided in one aspect of the present invention; step S3. merging and connecting the front-end layer of the product chip and the back-end layer of the test chip created in step S2 to obtain the layout of the test chip.

[0019] This test chip design is suitable for testing key components or hotspot patterns of product chips in a real physical environment. By using the template-based pin-grabbing method of this invention to grab the pins of the target object, it is possible to automatically grab the pins of various types of objects. It can not only complete the grabbing of the pins of key components to design the layout of the test chip for manufacturing the test chip, but also obtain the test chip for testing in a real physical testing environment, resulting in more reliable test results. Furthermore, the manufacturing process of the test chip is further optimized, which is conducive to improving the manufacturing level and yield of the test chip, and has a positive role in promoting a significant increase in the yield of chip products.

[0020] In step S1, the graphical interpretation includes: using preset feature patterns, matching and identifying corresponding objects based on the feature patterns, and using quantification to characterize object information; the objects include devices and hotspots, where hotspots are structural patterns prone to process defects (such as photolithography defects). By graphically interpreting the layout of the product chip, objects can be automatically and quickly identified and the target objects extracted according to different testing requirements by matching preset feature patterns.

[0021] In step S1, the object information refers to feature information that can affect the object's performance, including information about the object's feature graphics and environmental information between the object's feature graphics and its surrounding graphics. The environmental information includes, for example, relative distance information.

[0022] The test chip design method also establishes an object database to store the objects and object information obtained in step S1; the object information includes: the object's name, location coordinates, and quantified characteristic information.

[0023] In step S2, arranging several pads on the product chip includes: on the test chip, arranging multiple pad groups in a staggered manner with two pad groups spaced apart in a first direction to form several pad sequences along the first direction; on both sides of the pad sequence, determining selectable areas of the pads in the pad sequence for connecting the pads to the test object pins in their selectable areas to form test paths; wherein, the pad group is a pad array; the first direction refers to the row direction or column direction of the pad array in the pad group.

[0024] The step of selecting several objects as target objects includes: selecting only objects within the selectable area.

[0025] The test chip design method has several preset screening rules; in step S2, screening out several objects as target objects also includes selecting applicable screening rules for different objects to screen and obtain target objects.

[0026] The priority order of the selected filtering rules is set according to the testing requirements of the test chip, and the filtering rules are applied according to the priority order to filter out the qualified objects as target objects.

[0027] The pins of the target object include: the terminals of the target object, and a plurality of connecting lines leading out from the terminals; the plurality of connecting lines leading out from the terminals include connecting lines with the same path as the connecting lines in the product chip layout and / or newly created connecting lines.

[0028] In step S2, assigning the pad to the pin includes: selecting the pad closest to the pin from a plurality of pads that conform to the principle of rotatable linearity for assignment. The principle of rotatable linearity includes that the pad is rotatable for the pin, and that all pins are rotatable overall.

[0029] In step S2, assigning the pads to the pins includes: designating two pad groups that are arranged alternately and intermittently as the first pad group and the second pad group, designating the optional area on one side of the pad sequence as the odd-numbered area and the optional area on the other side as the even-numbered area, wherein the odd-numbered area is the optional area of ​​the first pad group and the even-numbered area is the optional area of ​​the second pad group; assigning the pins of the target object located in the odd-numbered area of ​​the pad sequence to the pads of the first pad group in the pad sequence, and assigning the pins of the target object located in the even-numbered area of ​​the pad sequence to the pads of the second pad group in the pad sequence.

[0030] The test chip design method has several preset winding rules; in step S2, the winding is performed according to the corresponding winding rule selected for different pins. Different pins include, for example, general pins, pins sensitive to voltage drop caused by current, and so on. Directly connecting the pins of the target object to the pads in step S2 helps the test chip cover more test items and test conditions.

[0031] Step S2 also includes deleting the back layer of the product chip.

[0032] After step S3, the layout of the test chip obtained in step S3 is verified. If the verification is successful, the design of the test chip is completed.

[0033] The verification includes DRC verification and LVS verification; if all verifications pass, the design of the test chip is complete. DRC verification checks whether the chip conforms to design rules, and LVS verification ensures that the connection of the subsequent windings meets requirements. If all verifications pass, the designed test chip can better meet the advanced customization needs for monitoring product chip yield and performance.

[0034] The present invention also provides a test chip design system, including a storage device; the storage device stores a plurality of instructions, which are adapted to be loaded by a processor and executed by the test chip design method of the present invention.

[0035] The present invention also provides a test chip designed using the test chip design method of the present invention. While keeping the front-end and middle-end process layers (i.e., the front-end layer FEOL) of the product chip unchanged, the layout of the test chip can be obtained by modifying the interconnect layer and the back-end process layer (i.e., creating a new back-end layer BEOL). The test chip designed in this way is suitable for testing the product chip in a real physical environment. The test chip with a test structure that has the same physical environment as the devices or hotspot patterns in the product chip can significantly optimize test accuracy.

[0036] Compared with the prior art, the main beneficial effects of the present invention are:

[0037] 1. The template-based pin-grabbing method of the present invention uses templates to identify and grab the pins of target objects. It offers flexible design, allowing for flexible connection and pin definition according to specific test requirements, without limitations on the type of target object or the number of pins. It can not only identify and grab multiple MOSFETs without direct or other connection relationships, but also automatically identify and grab more complex devices such as DIODES, BJTs, and varactors, or various types of test objects that are not devices. It provides a feasible and effective solution for introducing more types of devices or more complex test structures into test chips.

[0038] 2. The test chip design method of the present invention, by using the template-based object pin grabbing method of the present invention to grab the pins of the target object, can design test chips that can introduce more types of devices and more complex test structures, which cannot be achieved by the traditional general automatic identification device pin method. The steps are simple, the test results are reliable, and it greatly promotes the further optimization of the test chip manufacturing process and the significant improvement of chip product yield.

[0039] 3. The test chip design system and test chip provided by this invention have corresponding advantages, and provide a positive and effective solution for promoting the further development of actual testing technology and the continuous optimization of product manufacturing quality. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the pin-grabbing method according to Embodiment 1 of the present invention.

[0041] Figure 2 This is a schematic diagram of the prototype layout of the template in Embodiment 1 of the present invention.

[0042] Figure 3 This is a schematic diagram of the layout after deleting the latter part of the winding layer in the prototype layout according to Embodiment 1 of the present invention.

[0043] Figure 4In Embodiment 1 of the present invention, Figure 3 The schematic diagram shows a layout where the traces have been rewound and the pins have been connected.

[0044] Figure 5 This is a schematic diagram of the final object template in Embodiment 1 of the present invention.

[0045] Figure 6 This is a schematic diagram of the test chip design method process according to Embodiment 3 of the present invention.

[0046] Figure 7 This is a schematic diagram of the arrangement of pads on the original product chip in Embodiment 3 of the present invention.

[0047] Figure 8 This is a schematic representation of the MOSFET object information stored in the object database of Embodiment 3 of the present invention.

[0048] Figure 9 This is a schematic diagram of the object parameters of the MOSFET in Embodiment 3 of the present invention.

[0049] Figure 10 This is a schematic diagram of the staggered placement of two pad groups in Embodiment 4 of the present invention.

[0050] Figure 11 This is a schematic diagram showing the relationship between the pad group and the optional area in Embodiment 4 of the present invention.

[0051] Figure 12 This is a schematic representation of the target MOSFET information during the screening process in Embodiment 4 of the present invention.

[0052] Figure 13 This is a schematic diagram of the target MOSFET pin acquisition process in Embodiment 4 of the present invention.

[0053] Figure 14 This is a schematic diagram of the process of assigning pads to pins in Embodiment 4 of the present invention. Detailed Implementation

[0054] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings. The operation of the embodiments is depicted in a specific order in the following embodiments; this detailed description of the order is intended to provide a better understanding of the details in the embodiments and to give a comprehensive understanding of the invention. The flowcharts and block diagrams in the drawings illustrate the operational processes that may be implemented according to the methods of the embodiments of the invention, and should not be construed as limiting the scope of the invention.

[0055] Example 1

[0056] In Embodiment 1 of the present invention, as Figure 1As shown, the method for capturing target pins based on a template specifically includes: acquiring a layout file, determining the object whose pins to be captured in the layout, marking it as the target object, and acquiring the object template of the target object; the object template includes a matching layer and a winding layer, the matching layer being a layer used for graphic matching, and the winding layer being a layer of connecting lines used to bring out the terminals of the object; capturing the target object's pins in the layout based on the target object's object template includes: using the matching layer of the object template to perform a matching search in the layout, after finding a graphic that matches the graphic of the matching layer, copying the winding layer of the object template and adding it to the corresponding position in the layout to bring out the terminals of the target object, thereby capturing the target object's pins. In this embodiment, after determining the target object, the positioning point of the target object in the layout is also acquired, and when using the matching layer of the object template to perform a matching search in the layout, the matching search is performed within a preset matching range centered on the positioning point in the layout. The method for obtaining the location points of a target object in a layout includes: pre-setting a layer used for matching and identifying the target object, denoted as a marker layer, or a graphic, denoted as a feature graphic; using the marker layer or feature graphic of the target object to match and identify the target object in the layout, and obtaining the location point coordinate information of the target object. Here, the marker layer refers to: a feature layer used for matching and identifying the target object, or an identifier layer that collects the location point coordinate information of the target object.

[0057] The following provides some feasible examples of the object template creation process to facilitate understanding of object templates by those skilled in the art, but does not limit the object template in any way. In this embodiment, the object template also uses a pin marking layer to mark the electrodes of the pins. The object template is obtained by creating the object template in the following way: locating the object in the layout and cropping the layout of the object as the prototype layout of the template; simplifying the prototype layout to obtain the object template. The specific example process includes: (I) locating the object in the layout and determining whether the object is a graphic element in the layout: if so, cropping the layout of the graphic element as the prototype layout of the template; if not, cropping the object and the graphics within its preset range together as the prototype layout of the template. In this embodiment, the cropping is as follows: Figure 2 The prototype layout is shown. In the example, the primitives of the layout are pre-created by referencing basic primitives or specific primitives, and by arraying basic primitives or specific primitives. (II) Simplify the prototype layout, including: first, delete the back-end wrapping layer in the prototype layout, to obtain the following: Figure 3 The layout shown. According to the test requirements, several connecting lines are added (preferably using the same wiring as the prototype layout) to create several new wiring layers, which are used to bring out the terminals of the object as pins. The pin electrodes are marked using a pin marking layer: source S, two drains D1 and D2, and two gates G1 and G2. See reference [reference needed] for details. Figure 4The specific number of newly added winding layers can be set according to the actual layout design and is not limited. Several layers with recognizable graphic features are identified as matching layers. After deleting incomplete graphics from the matching layers, all other layers in the object template except for the matching layers, newly added winding layers, and pin marker layers are deleted, resulting in the following: Figure 5 The simplified final layout shown serves as the object template. The incomplete graphic in the example contains basic primitives that were truncated when the prototype layout was extracted from the layout. It should be noted that in this embodiment, the object template can be obtained through the process described above. In practical applications, object pins can be retrieved based on the object template, and a pre-made object template can be reused without re-creating it. In some specific embodiments, the storage address of the object template is provided by setting the template address (Layout) in the matching parameters.

[0058] Example 2

[0059] This embodiment aims to enable those skilled in the art to more fully understand the template-based object pin grabbing method of Embodiment 1. This embodiment elaborates on some specific practices of step three in Embodiment 1, but does not limit the invention in any way.

[0060] In this embodiment, the matching layer of the object template is used to perform graphic matching search within the matching range centered on the positioning point in the layout. Specific steps include: Step a): Setting matching parameters: Setting the coordinates (DeviceX, DeviceY) of the matching point in the matching layer of the object template, as well as the preset matching range (Template Match Search Range) and the matching coordinate error tolerance range (Template Match CoordinateTolerance). Step b): Aligning the matching point with the positioning point in the layout, and performing graphic matching using the matching layer of the object template: If the matching is successful, the matching search is completed; if the matching fails, the subsequent steps continue. Step c): Moving the matching point within the matching coordinate error tolerance range centered on the positioning point, so that the matching layer performs graphic matching within the matching range centered on the positioning point: If the matching is successful, the matching search is completed; if the matching fails, the subsequent steps continue. Step d): Determining whether to adjust the matching parameters: If the matching parameters are adjusted (e.g., expanding the matching range and the matching coordinate error tolerance range), then proceed to step b); if the matching parameters are not adjusted, then the current matching search ends.

[0061] When a matching graphic cannot be found within the matching range centered on a positioning point in the layout using the matching layer of the object template, the matching range can be expanded before further matching. In a specific embodiment, the matching parameters can be set at the start of the matching process to limit the matching range by specifying the matching point coordinates (DeviceX, DeviceY), the matching range (Template Match Search Range), and the matching coordinate error tolerance (Template Match CoordinateTolerance). The matching point is the selected starting point in the object template, used to align the positioning point in the layout at the start of the matching process. The matching range serves as the initial matching range. The matching point coordinates refer to the coordinates of the matching point within the object template; in this example, the matching point is represented by coordinates (DeviceX, DeviceY). The matching coordinate error tolerance ensures that the matching range does not expand beyond the preset tolerance range during the matching process.

[0062] The example of a graphic matching the matching layer refers to a graphic that is completely identical to the graphic of the matching layer, or a graphic that is a mirror image of the graphic of the matching layer in either of two mutually orthogonal directions. For ease of understanding, the two mutually orthogonal directions are illustrated using Cartesian coordinates, namely the X and Y directions. The graphic matching the matching layer can be a mirror image of the graphic of the matching layer in the X direction, or a mirror image of the graphic of the matching layer in the Y direction. In practice, this can be controlled at the start of matching by setting the mirror information (Mirror-Check) in the matching parameters, thus controlling whether the object template is mirrored in the X or Y direction during object template matching.

[0063] It should be noted that the template-based method for capturing target pins in this embodiment also provides the option to automatically capture the remaining pins of the target. Specifically, this can be achieved by setting the Auto-Welltie parameter in the matching parameters. For example, if a transistor only captures the source, drain, and gate pins using the target template, this parameter can be set to select whether to simultaneously capture the corresponding body pin. The system determines whether there are any remaining pins to capture based on the actual application and implements the capture accordingly. If so, after capturing the target object's pins based on the target template, the remaining pins of the target object are automatically captured. The combination of template-based capture and automatic capture can capture all pins of the target object; this is not limited to this approach.

[0064] Example 3

[0065] This embodiment provides a test chip design method, such as... Figure 6As shown, the specific steps include: Step S1: Input the product chip layout and obtain the objects and their information in the product chip layout based on graphical interpretation; wherein, the product chip layout includes a front-end layer and a back-end layer; Step S2: Create the back-end layer of the test chip, including: arranging several pads on the product chip; selecting several objects as target objects; capturing the pins of the target objects; assigning pads to the pins of the target objects, and connecting the pins of the target objects to the assigned pads by routing wires; wherein, capturing the pins of the target objects is achieved by the template-based pin capture method exemplified in Embodiments 1 and 2 above; Step S3: Merge and connect the front-end layer of the product chip and the back-end layer of the test chip created in Step S2 to obtain the layout of the test chip.

[0066] In step S1 of this embodiment, the graphical interpretation includes: using preset feature patterns, identifying corresponding objects based on feature pattern matching, and using quantization to characterize the corresponding object information; the objects include devices and hotspot patterns. Hotspot patterns are structural patterns prone to process defects (such as photolithography defects), and examples include interconnect structures, active areas (AA), and single diffusion breaks (SDB). Example devices may include MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), diodes, BJTs (Bipolar Junction Transistors), resistors, capacitors, inductors, and SRAM (Static Random Access Memory). In this embodiment, the situation after arranging pads on the original product chip is as follows... Figure 7 As shown.

[0067] In step S1 of the example, object information refers to feature information that can affect object performance, including information about the object's feature graphics and environmental information between the object's feature graphics and its surrounding graphics. Environmental information includes, for example, relative distance information. In this embodiment, an object database is also established to store the objects and object information obtained in step S1. Figure 8 The object information shown includes: the object's name, location coordinates, and characteristic information of various quantitative representations.

[0068] The following uses a MOSFET as an example to illustrate the specific methods for object identification and object information acquisition. Based on the MOSFET type, two preset feature patterns are used to identify the MOSFET: N-type MOSFET: The N-type gate (ngate) has edges that contact the N-type source and drain (nsd) on both sides, and a P-type body (ptap) is present in the non-NWELL region. P-type MOSFET: The P-type gate (pgate) has edges that contact the P-type source and drain (psd) on both sides, and an N-type body (ntap) is present in the NWELL region. Examples of the MOSFET device-related pattern definitions mentioned above are shown below. N-type active region: ndiff = ((AA and NIMP) not PIMP) not NWELL; P-type active region: pdiff = ((AA and PIMP) not NIMP) and NWELL; N-type gate: ngate = (POLY not EG) and ndiff; P-type gate: pgate = (POLY not EG) and pdiff; N-type source and drain: nsd = ndiff not POLY; P-type source and drain: psd = pdiff not POLY; N-type body: ntap = ((AA and NIMP) not PIMP) and NWELL; P-type body: ptap = ((AA and PIMP) not NIMP) not NWELL. The basic graphic definitions involved in the above feature graphics are illustrated in the following examples: POLY—polysilicon layer; POLYCUT—polysilicon removal layer; EG—edge gate identifier layer; AA—active layer; NIMP—N-type implantation layer; PIMP—P-type implantation layer; NWELL—N-well layer; PSUB—P-substrate; IOMK—thick device identifier layer.

[0069] In this embodiment, the defined intrinsic characteristic parameters and environmental parameters of the MOSFET can be referenced. Figure 9 Examples include L, W, DPL11, DPL12, SA, SB, PEEU, etc., and the specific cases are not limited here.

[0070] Example 4

[0071] This embodiment provides a detailed example of some specific practices in step S2. In this embodiment, arranging several pads on the product chip includes: on the test chip, arranging multiple pad groups in a staggered manner with two pad groups spaced apart in a first direction, forming several pad sequences along the first direction; on both sides of the pad sequence, determining selectable areas for the pads in the sequence, used for connecting the pads to the test pins within their selectable areas to form test paths. Here, a pad group is a pad array; the first direction refers to the row or column direction of the pad array within the pad group. The preset values ​​of the pad design dimensions in the row and column directions are respectively denoted as sizeX and sizeY, and the preset interval values ​​of adjacent pads in the row and column directions are respectively denoted as pitchX and pitchY. Specifically, as follows... Figure 10 As shown, the pad group is a 48×2 pad array, with pads from every two pad groups arranged interleaved in the Y direction. Approximately 232 pad groups can be placed within the chip area (approximately 9mm×9mm), for a total of 22,272 pads. There are four repeating rows for the pad groups in the Y direction and fifty-eight repeating columns in the X direction. The row and column directions can be X and Y, or Y and X, respectively. Figure 10 This is for illustrative purposes only and does not limit the specific arrangement of rows and columns.

[0072] In step S2 of this embodiment, selecting several objects as target objects includes filtering only from objects within the selectable region. The selectable region is the area on both sides of the pad sequence where the pads of two adjacent pad groups are arranged with alternating spacing, that is, the area on both sides of each column of pad sequence arranged along the Y direction in the example. The selectable region can be referenced. Figure 11 DeviceArea, Figure 11 The pad group in the middle represents the pad group.

[0073] The example's filtering process utilizes preset filtering rules. It filters out several objects as target objects and also selects applicable filtering rules for different objects. The example uses several filtering rules to filter different objects to obtain target objects. In this example, the priority order of the selected filtering rules is set according to the actual application requirements of the test chip, and then the filtering rules are applied in priority order to filter out several suitable objects as target objects. The example has more than 30 preset filtering rules, covering MOSFETs, BJTs, DIODEs, resistors, capacitors, SRAMs, hotspots, etc. The following example illustrates a MOSFET filtering rule: for various types of MOSFETs in the DEVICETYPE, target devices that meet the requirements are selected according to the minimum and maximum values ​​of the basic parameters W and L. The example's filtering rules are interested in these selected target devices, covering the extreme values ​​(minimum and maximum values) of the W and L ranges of various MOSFETs in the product chip, used for monitoring the process window. The parameters of the selected target devices can be found in Table 1 below.

[0074] Table 1. Parameters of the Selected Target Device

[0075]

[0076] In the general operation of this embodiment, three sample devices are randomly selected from the candidate devices that meet the screening rules and are of sufficient quantity. If the number of candidate devices that meet the screening rules is less than three, all of them are selected first. The screening rules select a total of the following: Figure 12 The twenty target devices shown.

[0077] In step S2 of this embodiment, the pins of the target object include: terminals of the target object, and several connecting lines leading out from the terminals. For example... Figure 13 As shown, the example automatically identifies and captures the four terminals of the MOSFET: gate, source, drain, and body. Metal leads for these four terminals are then created, and processing is performed to conform to design rules, optimizing the pin routing directions to ensure the four pins exit from four different directions, making subsequent wiring steps easier. Because the actual location of the body is relatively far, [the following steps are not explicitly stated]. Figure 13 The image only shows the automatic identification and capture results of the gate, source, and drain terminals, retaining only the back-end layer. In some cases, the connection lines leading out from the terminals include connection lines with the same path as the connection lines in the original product chip layout and / or newly created connection lines. Generally, connection lines with the same path as the connection lines in the original product chip layout are used as much as possible, but this is not a limitation here.

[0078] In this embodiment, assigning pads to the pins of the target object includes: designating two pad groups arranged in an alternating pattern as the first pad group and the second pad group, respectively. The optional area on one side of the pad sequence is designated as the odd-numbered area, and the optional area on the other side as the even-numbered area. The odd-numbered area is the optional area of ​​the first pad group, and the even-numbered area is the optional area of ​​the second pad group; the pins of the target object located in the odd-numbered area of ​​the pad sequence are assigned to the pads of the first pad group in the pad sequence, and the pins of the target object located in the even-numbered area of ​​the pad sequence are assigned to the pads of the second pad group in the pad sequence. For the optional areas, refer to... Figure 10 and Figure 11 , Figure 10 Two pad groups are set up, one as Pad Group I and the other as Pad Group II, which are spaced and staggered in the Y direction. The optional area on the left side of the pad sequence arranged along the Y direction is designated as the left optional area of ​​Pad Group I, and the optional area on the right side of the pad sequence arranged along the Y direction is designated as the right optional area of ​​Pad Group II. When assigning pads, the pads belonging to Pad Group I are matched with the pins of the target object in the left optional area of ​​Pad Group I of the pad sequence, and the pads belonging to Pad Group II are matched with the pins of the target object in the right optional area of ​​Pad Group II of the pad sequence.

[0079] In step S2 of this embodiment, assigning pads to pins includes selecting the pad closest to the pin from a number of pads that conform to the principle of linearity. That is, when assigning pads to the pins of the target object, the following are followed: 1) Assigning according to the principle of proximity and linearity, where linearity includes that the pad can be wound around the pin, and that all pins are wound around as a whole; 2) Assigning pins of the target object only to the pads within their selectable area.

[0080] In this embodiment, several winding rules are preset. In step S2, the winding is performed by selecting the corresponding winding rule according to different pins. When winding the pins of the target object to the assigned pads, the corresponding winding rule is automatically selected for automatic winding based on different pins (such as general pins, pins sensitive to voltage drop caused by current, etc.).

[0081] In this embodiment, for Figure 13The system automatically winds the four pins of the target MOSFET device: gate, source, drain, and body. The body pin will share the bottom pad with other similar devices, while the remaining three pins will be assigned pads based on flexibility and proximity. Figure 14 The pad assignments are as follows: Gate (G) is assigned to PAD_92; Drain (D) to PAD_94; Source (S) to PAD_96; Body (B) to PAD_2 (shared bottom pad). The MOSFET is located within the selectable area corresponding to the pad groups of PAD_92, PAD_94, and PAD_96. During wiring, Gate (G) and Body (B) use single-wire wiring, while Drain (D) and Source (S) use large-area mesh wiring to reduce IR drop.

[0082] In this embodiment, step S2 further includes deleting the back-end layer (conductive interconnect layer) of the product chip. After step S3, the test chip is verified, for example, by verifying compliance with design rules using DRC and ensuring the back-end wiring connections meet requirements using LVS. If the verification is successful, the design of the test chip is complete, resulting in a high-precision built-in test chip for monitoring the yield and performance of the product chip. The test chip provided in this embodiment selects approximately 6200 target objects within the product chip area, and directly connects the measurement pins of the target objects to adjacent pads. This improves area utilization and, through direct pin connection to pads, covers more test items and conditions.

[0083] This embodiment also provides a test chip design system, including a storage device. The storage device stores multiple instructions adapted for loading and execution by a processor using the test chip design method of this embodiment.

[0084] This embodiment also provides a test chip, which is designed using the test chip design method of this embodiment.

[0085] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

Claims

1. A method for capturing object pins based on templates, characterized in that: include: Obtain the layout file, identify the object whose pins to be captured in the layout, record it as the target object, and obtain the object template of the target object; the object template includes a matching layer and a winding layer, the matching layer is a layer used for graphic matching, and the winding layer is a layer of connecting lines used to lead out the terminals of the object; The method of capturing the pins of a target object in a layout based on an object template of the target object includes: using the matching layer of the object template to perform a matching search in the layout; after finding a pattern that matches the pattern of the matching layer, copying the winding layer of the object template and adding it to the corresponding position in the layout to bring out the terminal of the target object, thereby capturing the pins of the target object.

2. The method for capturing object pins based on templates according to claim 1, characterized in that: After identifying the target object, the location point of the target object in the layout is also obtained. When performing a matching search in the layout using the matching layer of the object template, the matching search is performed within a preset matching range centered on the location point in the layout.

3. The method for capturing object pins based on a template according to claim 2, characterized in that: The method for obtaining the location point of the target object in the map includes: pre-setting a layer for matching and identifying the target object as a marker layer or a graphic as a feature graphic; wherein, the marker layer refers to: a feature layer for matching and identifying the target object, or an identifier layer that collects the location point coordinate information of the target object; The target object is identified by matching its marker layer or feature graphics on the map and the location coordinates of the target object are obtained.

4. The method for capturing object pins based on a template according to claim 1, characterized in that: The object template also includes a layer: a pin marker layer, used to mark the electrodes of the pins.

5. The method for capturing object pins based on a template according to claim 4, characterized in that: The methods for obtaining an object template include: creating an object template; the creation method includes: locating the object in the layout and cropping the layout of the object as the prototype layout of the template; and simplifying the prototype layout to obtain the object template.

6. The method for capturing object pins based on a template according to claim 5, characterized in that: The process of extracting the layout of the object as a prototype layout for the template includes: Determine whether the object is a graphic element in the layout: if yes, then the layout of the graphic element is cropped as the prototype layout; if not, then the object and the graphics within its preset range are cropped together as the prototype layout.

7. The method for capturing object pins based on a template according to claim 5, characterized in that: The prototype layout is simplified, including: Delete the rear winding layer in the prototype layout, and then add several connecting lines to obtain several new winding layers, so as to bring out the terminals of the object as pins; The connecting lines in the newly added winding layer include connecting lines with the same path as the connecting lines in the prototype layout and / or newly created connecting lines. The electrodes of the pins are marked using the pin marking layer; In the prototype layout, several layers with distinctive graphic features are identified as matching layers. After deleting incomplete graphics in the matching layers, the object template is obtained. The incomplete graphic refers to the existence of basic graphic elements that were truncated when the prototype layout was extracted from the layout.

8. The method for capturing object pins based on a template according to claim 7, characterized in that: The simplification of the prototype layout also includes: after obtaining the object template, deleting all layers in the object template except for the matching layer, the newly added winding layer and the pin marker layer.

9. The method for capturing object pins based on a template according to claim 4, characterized in that: After copying the winding layer from the object template and adding it to the corresponding position in the layout, the electrodes of the target object pins are defined using the pin marker layer.

10. The method for capturing object pins based on a template according to claim 1, characterized in that: A graphic that matches the graphic of the matching layer refers to a graphic that is completely identical to the graphic of the matching layer or a graphic that is mirrored in either of two mutually orthogonal directions.

11. The method for capturing object pins based on a template according to claim 2, characterized in that: Using the matching layer of the object template, a graphic matching search is performed within the matching range centered on the positioning point in the layout; the specific steps include: Step a): Set matching parameters: Set the coordinates of the matching point, as well as the preset matching range and the allowable range of matching coordinate error in the matching layer of the object template; Step b): Align the matching points with the positioning points in the layout, and perform graphic matching using the matching layer of the object template: If a match is found, the match search is complete. If the match fails, continue with the next steps; Step c): Move the matching point within the allowable range of matching coordinate error centered on the positioning point, so that the matching layer performs graphic matching within the matching range centered on the positioning point. If a match is found, the match search is complete. If the match fails, continue with the next steps; Step d): Determine whether to adjust the matching parameters: If the matching parameters are adjusted, proceed to step b). If the matching parameters are not adjusted, the current matching search will end.

12. The method for capturing object pins based on a template according to claim 1, characterized in that: After capturing the target object's pins based on the object template, the remaining pins of the target object are also automatically captured to complete the capture of all pins of the target object.

13. A test chip design method, characterized in that: include: Step S1. Input the product chip layout and obtain the objects and their information in the product chip layout based on graphical interpretation; wherein, the product chip layout includes a front-end layer and a back-end layer; Step S2. Create a back-end layer for the test chip, including: arranging several pads on the product chip; selecting several objects as target objects; capturing the pins of the target objects; assigning pads to the pins of the target objects, and routing wires to connect the pins of the target objects to the assigned pads; wherein, capturing the pins of the target objects includes obtaining them using the template-based pin capture method according to any one of claims 1 to 12; Step S3. Merge and connect the front-end layer of the product chip and the back-end layer of the test chip created in step S2 to obtain the layout of the test chip.

14. The test chip design method according to claim 13, characterized in that: In step S1, the graphical interpretation includes: using preset feature patterns, matching and identifying corresponding objects based on the feature patterns, and using quantitative representation to characterize object information; the objects include devices and hotspot patterns, where hotspot patterns are structural patterns that are prone to process defects.

15. The test chip design method according to claim 13, characterized in that: In step S1, the object information refers to the feature information that can affect the performance of the object, including information about the object's feature graphics and the environmental information between the object's feature graphics and its surrounding graphics.

16. The test chip design method according to any one of claims 13-15, characterized in that: An object database is also established to store the objects and object information obtained in step S1; the object information includes: the object's name, location coordinates, and quantitative characteristic information.

17. The test chip design method according to claim 13, characterized in that: In step S2, arranging several pads on the product chip includes: on the test chip, arranging multiple pad groups in a staggered manner with two pad groups spaced apart in a first direction to form several pad sequences along the first direction; on both sides of the pad sequence, determining selectable areas of the pads in the pad sequence for connecting the pads to the test object pins in their selectable areas to form test paths; wherein, the pad group is a pad array; the first direction refers to the row direction or column direction of the pad array in the pad group.

18. The test chip design method according to claim 17, characterized in that: The step of selecting several objects as target objects includes: selecting only objects within the selectable area.

19. The test chip design method according to claim 13, characterized in that: Several filtering rules are preset; In step S2, selecting several objects as target objects also includes selecting applicable filtering rules for different objects to obtain target objects.

20. The test chip design method according to claim 13, characterized in that: The pins of the target object include: the terminals of the target object, and a plurality of connecting lines leading out from the terminals; the plurality of connecting lines leading out from the terminals include connecting lines with the same path as the connecting lines in the product chip layout and / or newly created connecting lines.

21. The test chip design method according to claim 13, characterized in that: In step S2, assigning the pad to the pin includes: selecting the pad closest to the pin from a number of pads that conform to the principle of rotatable linearity for assignment.

22. The test chip design method according to claim 17, characterized in that: In step S2, assigning the pads to the pins includes: designating two pad groups that are arranged alternately and intermittently as the first pad group and the second pad group, designating the optional area on one side of the pad sequence as the odd-numbered area and the optional area on the other side as the even-numbered area, wherein the odd-numbered area is the optional area of ​​the first pad group and the even-numbered area is the optional area of ​​the second pad group; assigning the pins of the target object located in the odd-numbered area of ​​the pad sequence to the pads of the first pad group in the pad sequence, and assigning the pins of the target object located in the even-numbered area of ​​the pad sequence to the pads of the second pad group in the pad sequence.

23. The test chip design method according to claim 13, characterized in that: Several winding rules are preset; in step S2, the winding is performed by selecting the corresponding winding rule according to different pins.

24. The test chip design method according to claim 13, characterized in that: After step S3, the layout of the test chip obtained in step S3 is verified. If the verification is successful, the design of the test chip is completed.

25. A test chip design system, characterized in that: Includes a storage device; the storage device stores multiple instructions adapted for loading and execution by a processor of the test chip design method according to any one of claims 13-24.

26. A test chip, characterized in that: The test chip was designed using the test chip design method described in any one of claims 13-24.

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