An electronic electroplating chip with high aspect ratio through silicon via and preparation method thereof

Abstract

The present invention relates to an electronic electroplating chip of a silicon through hole with a high aspect ratio and a preparation method thereof. The method comprises the following steps: S1, coating a photoresist on the surface of a silicon substrate, exposing the hole position by photolithography exposure and then developing; S2, covering the part of the silicon substrate exposing the hole position with a passivation layer; S3, etching the bottom surface of the passivation layer to expose the silicon substrate corresponding to the bottom surface of the hole position; S4, etching the silicon substrate corresponding to the bottom surface exposing the hole position; S5, repeating steps S2-S4 for multiple times to obtain a silicon through hole of a target depth, cleaning and ashing the photoresist and passivation remaining in the silicon through hole; S6, depositing an insulating layer, a barrier layer and a seed layer on the inner wall of the silicon through hole by an ALD deposition method to obtain a silicon through hole with a high aspect ratio. Through a three-pulse process, passivation-etching-etching is performed cyclically to solve the problem of etching and passivation balance during process modification and ensure the stability of the process. Finally, ALD is selected for the sidewall deposition process to ensure that the inner sidewall of the hole has sufficient coverage.

Description

Technical Field

[0001] The invention relates to the field of through silicon via preparation, and in particular to an electronic electroplating chip of a through silicon via with a high aspect ratio and a preparation method thereof. Background Art

[0002] The current advanced packaging technology mainly includes six important technologies: flip chip packaging, wafer-level chip size packaging, fan-out packaging, 3D wafer-level chip size packaging, 2.5D mid-level packaging, and 3D IC integration. Based on different packaging processes such as bumps, rewiring layers, chip-wafer / wafer-wafer, silicon through-holes, and stacking, different packaging methods are combined. Most of the packaging technologies are closely related to wafer-level packaging, and advanced packaging is also developing towards system integration, high speed, high frequency, three-dimensional and ultra-fine interconnection spacing; among them, 3D wafer-level packaging has attracted much attention. Due to the best space utilization of three-dimensional packaging, it can also greatly improve the integration. For three-dimensional packaging, multiple chips are stacked vertically, so the interconnection method between chips is particularly important. TSV interconnection technology is usually combined with micro-bump technology and chip thinning technology. The vertical signal connection between chips is one of the core technologies of 3DIC.

[0003] In order to reduce the chip area while increasing the interconnection density, the importance of high aspect ratio TSV is becoming increasingly apparent. As the aspect ratio continues to increase, more challenges are posed to the TSV manufacturing process, and many technical indicators need to be considered: (1) TSV shape, size and aspect ratio; (2) TSV etching sidewall morphology and etching damage size; (3) The continuity and thickness of the deposition of the insulating layer, barrier layer, and seed layer; (4) Plating solution capacity and selection of plating current; (5) Plating equipment capacity.

[0004] The prior art has at least one or more of the following defects:

[0005] 1. For TSV etching, the roughness of the side wall needs to be guaranteed. After Bosch etching, scallop-shaped defects will inevitably appear on the side wall. This defect has the most direct impact on the continuity of the side wall insulation layer, barrier layer, and seed layer. At the same time, if the side wall is damaged during the etching process, it will also introduce additional leakage current into the electrical performance test of TSV.

[0006] 2. Regarding the uniformity and continuity of the side wall film deposition, if the uniformity is insufficient, the difference in current density distribution during the electroplating process will increase again, making pinch-off more likely to occur; in terms of side wall continuity, if there is a film fault or insufficient coverage, electroplating will preferentially deposit at the end of the film, resulting in holes.

[0007] 3. The electroplating solution of TSV is mainly composed of inhibitors, accelerators, and levelers. For the electroplating of high aspect ratio TSV, the electroplating solution is required to have a strong ability to inhibit the electroplating of the orifice. At the same time, the selection of appropriate current parameters to provide the appropriate current density for the electroplating process can also prevent the premature closure of the orifice to a certain extent. The electroplating solution in the TSV manufacturing process is also a high-end electronic chemical. Compared with chemicals such as photoresist and CMP polishing liquid, its market size is not large. Electroplating additives, as key materials in chip manufacturing, are basically monopolized by foreign companies, and their high technical difficulty and relatively low market capacity have made most companies lose interest in research. At present, the demand for electroplating solution in some large domestic wafer fabs is increasing year by year. China has now been able to achieve self-sufficiency in basic plating solution (VMS), and accounts for about 60% of the domestic market share. However, in the field of additives required for high-end electroplating, the market share of domestic manufacturers is almost zero, and most of them are in the verification and testing stage, and continuous efforts from all walks of life are still needed.

[0008] There are many factors to consider when opening a new production line for high-density, high-aspect-ratio TSV in a fab factory. The yield issue will cause a sharp increase in the cost of the 3D packaging process. This makes it urgent to simulate and verify the feasibility of the electroplating process before mass production, resulting in a gradual increase in demand for TSV electroplating simulation chips, and even a shortage of supply.

[0009] In view of the above problems existing in the prior art, the purpose of the present invention is to design an electronic electroplating chip with a high aspect ratio through silicon via and a preparation method. Summary of the invention

[0010] In view of the problems existing in the above-mentioned prior art, the present invention provides an electronic electroplating chip with a high aspect ratio through silicon via and a preparation method thereof, which can effectively solve the problems existing in the above-mentioned prior art.

[0011] The technical solution of the present invention is:

[0012] A method for preparing a through silicon via with a high aspect ratio comprises the following steps:

[0013] S1, coating a photoresist on the surface of a silicon substrate, and exposing the holes by photolithography and then developing;

[0014] S2, the part of the silicon substrate where the holes are exposed is covered with a passivation layer;

[0015] S3, etching the bottom surface of the passivation layer to expose the silicon substrate corresponding to the bottom surface of the hole;

[0016] S4, etching the silicon substrate corresponding to the bottom surface exposing the hole;

[0017] S5, repeating steps S2-S4 for multiple times to obtain a through silicon via of a target depth, and cleaning and ashing the photoresist and passivation material remaining in the through silicon via;

[0018] S6, depositing an insulating layer, a barrier layer, and a seed layer on the inner wall of the through silicon via by an ALD deposition method to obtain a through silicon via with a high aspect ratio.

[0019] Furthermore, coating the photoresist on the surface of the silicon substrate includes: defining the depth of the silicon through hole to be prepared as H, the thickness of the coated photoresist as D, then H:D=(48-52):1, and coating the photoresist with a thickness of D on the surface of the silicon substrate.

[0020] Furthermore, the partially covered passivation layer at the exposed hole position of the silicon substrate comprises:

[0021] A polymer is deposited on the inner surface of the portion of the silicon substrate where the pores are exposed to form a passivation layer by a plasma deposition process.

[0022] Furthermore, the process gas containing carbon fluorine gas is deposited and polymerized by a plasma deposition process to form a passivation layer.

[0023] Further, depositing an insulating layer, a barrier layer, and a seed layer on the inner wall of the through silicon via by an ALD deposition method comprises:

[0024] S6.1, evacuating the silicon substrate, introducing an oxygen-containing reaction precursor, and when the surface adsorption of the through silicon via is in an oversaturated state, evacuating the silicon substrate, introducing a catalytic gas, and forming an oxide layer with a thickness of one atomic layer on the inner wall of the through silicon via;

[0025] S6.2, repeating step S6.1 to make the oxide layer reach the target thickness, and completing the deposition of the insulating layer on the inner wall of the through silicon via.

[0026] Furthermore, the oxygen-containing reaction precursor is siloxane, the diameter of the through silicon via is defined as R, and the target thickness of the oxide layer is greater than 0.05R.

[0027] Further, depositing an insulating layer, a barrier layer, and a seed layer on the inner wall of the through silicon via by an ALD deposition method comprises:

[0028] S6.3, evacuating the silicon substrate, introducing a titanium-containing reaction precursor, and when the surface adsorption of the through silicon via is in an oversaturated state, evacuating the silicon substrate, introducing a nitrogen-containing reaction precursor, and forming a titanium nitride layer with a thickness of one atomic layer on the inner wall of the through silicon via;

[0029] S6.4, repeat step S6.3 to make the titanium nitride layer reach the target thickness, and complete the deposition of the barrier layer and the seed layer on the inner wall of the through silicon via.

[0030] Furthermore, the titanium-containing reaction precursor is titanium chloride, the nitrogen-containing reaction precursor is ammonia, and the target thickness of the titanium nitride layer is greater than 40 nm.

[0031] An electronic electroplating chip with a high aspect ratio through silicon via is further provided. The electronic electroplating chip comprises a through silicon via, and the through silicon via is prepared by a method for preparing a through silicon via with a high aspect ratio, and the aspect ratio of the through silicon via is greater than 15:1.

[0032] Furthermore, the duty ratio of the through silicon via is greater than 1:2.

[0033] Therefore, the present invention provides the following effects and / or advantages:

[0034] The method provided in this application uses a three-pulse process to cycle through passivation-etching-etching, thereby solving the problem of balancing etching and passivation when modifying the process and ensuring the stability of the process. Through silicon vias with a high aspect ratio can be stably prepared, and finally the ALD sidewall deposition process is selected to ensure that the sidewalls inside the hole have sufficient coverage, thus realizing the preparation of through silicon vias with a high aspect ratio. The prepared through silicon vias can achieve an aspect ratio of more than 15:1 and a duty cycle of more than 1:2.

[0035] The thickness of the photoresist selected in the present application is (48-52):1, and the depth of the through silicon hole is H: the thickness of the photoresist 101 is (48-52). During etching, it is necessary to ensure that the thickness ensures that the photoresist is not completely bombarded and peeled off before the etching is completed.

[0036] The present application deposits an insulating layer, a barrier layer, and a seed layer on the inner wall of the silicon through hole by the ALD deposition method, wherein the silicon substrate is used as the process basis, silicon dioxide is used as the insulating layer to prevent TSV leakage and signal crosstalk between adjacent TSVs, and TiN is used as the barrier layer 104 to prevent copper and silicon oxide from diffusing and affecting device reliability. At the same time, since TiN itself has conductivity, when the film thickness reaches a certain level, its sheet resistance is low enough to be used as a seed layer for electronic electroplating. Therefore, the silicon through hole prepared by the present application only needs titanium nitride of appropriate thickness to realize the barrier layer and seed layer at the same time.

[0037] It is very suitable for the mass production of high-density, high-aspect ratio TSV electronic electroplating analog chips, providing a material basis for the subsequent development of electroplating solutions.

[0038] This application attempts to solve the problem of preparing high-density, high-aspect ratio TSV electronic electroplating analog chips, so as to achieve the preparation of electroplating analog chips with the lowest cost, provide a chip foundation for subsequent high-density, high-aspect ratio TSV electronic electroplating, promote the development of TSV electroplating liquid, and provide a path for the development and research of domestic electroplating additives. This process has achieved the preparation of high-aspect ratio, high-density analog chips with aspect ratios of 15:1 and 20:1 and duty cycle of 1:1, and only uses TiN direct electroplating process, which is simple in process, low in cost, and high in fault tolerance, and is suitable as a way to prepare TSV electronic electroplating analog chips.

[0039] It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 The present invention provides a schematic flow chart of the method.

[0041] Figure 2 This is a schematic diagram of the result obtained in step S1.

[0042] Figure 3 This is a schematic diagram of the result obtained in step S2.

[0043] Figure 4 This is a schematic diagram of the result obtained in step S3.

[0044] Figure 5 This is a schematic diagram of the result obtained in step S4.

[0045] Figure 6 This is a schematic diagram of the result obtained in step S5.

[0046] Figure 7 This is a schematic diagram of the result obtained in step S6.

[0047] Figure 8 -9 is a physical image of a through silicon via prepared by the method provided by the present invention. DETAILED DESCRIPTION

[0048] In order to facilitate understanding by those skilled in the art, the structure of the present invention is further described in detail with reference to the embodiments and the accompanying drawings. It should be understood that the steps mentioned in this embodiment, unless otherwise specified, can be adjusted in sequence according to actual needs, and can even be executed simultaneously or partially simultaneously.

[0049] In the prior art, the preparation of silicon vias generally adopts the Bosch process, that is, the two steps of etching and passivation are performed alternately in a cycle. In the Bosch process, sulfur hexafluoride can be used for etching. Sulfur hexafluoride is used to provide F ions, and then carbon tetrafluoride is used to provide C and F in a ratio of 1:2 to form a passivation layer. Through the cyclic etching and passivation, the silicon substrate can be etched down layer by layer. Each etching-passivation can prepare a deeper silicon via downward, and the target depth silicon substrate can be obtained after multiple cycles. However, due to the large number of cycles required, it is difficult to achieve stability in the preparation process of silicon vias with a high aspect ratio.

[0050] refer to Figure 1 , a method for preparing a through silicon via with a high aspect ratio, comprising the following steps:

[0051] S1, coating a photoresist 101 on the surface of a silicon substrate 100, and exposing holes by photolithography and then developing;

[0052] This step is a direct adoption of the prior art. The silicon substrate used in this embodiment is as follows Figure 2 As shown, the basic pattern of the TSV array is defined thereon by photolithography. By spin coating a photoresist 101 on the silicon substrate 100, the photoresist is used as a mask for subsequent etching, and its thickness is determined by the final etching depth, and it is necessary to ensure that the verticality of the photoresist 101 is sufficient to avoid excessive deviation in etching. At this point, this step obtains a silicon substrate 100 that exposes the hole positions where the silicon through hole needs to be etched.

[0053] S2, covering the exposed hole portion of the silicon substrate 100 with a passivation layer;

[0054] In S1, a silicon substrate 100 is obtained that exposes the hole position where the silicon through hole is to be etched. This step starts with etching downward at the hole position. First, the exposed portion of the silicon substrate 100 is covered with a passivation layer through a passivation process. This step needs to be performed alternately with the subsequent steps, so the exposed portion of the silicon substrate 100 is also constantly changing. For example, at the beginning, the exposed portion of the silicon substrate 100 is the upper surface of the silicon substrate 100, and in the subsequent etching process, the reference Figure 3 , deeper and deeper through silicon vias will be formed downward on the silicon substrate 100, and the exposed portion of the substrate 100 is the inner wall of the through silicon via.

[0055] S3, etching the bottom surface of the passivation layer 105 to expose the silicon substrate 100 corresponding to the bottom surface of the hole;

[0056] Before this step is performed, the passivation layer 105 is Figure 3As shown, the passivation layer 105 covers the sidewalls and bottom surface of the silicon through hole of the silicon substrate 100, wherein the passivation layer 105 can protect the exposed portion of the silicon substrate 100, and removing the passivation layer 105 can re-expose the portion of the silicon substrate 100 that needs to be etched, and then the silicon substrate 100 can be etched again to reach a deeper depth.

[0057] In this step, only the bottom surface of the passivation layer 105 is etched. Figure 4 As shown, during etching, it is only necessary to etch the passivation layer 105 at the bottom. When the etching in this step just etches away the bottom surface 105 of the passivation layer formed in step S2, it is considered that steps S2 and S3 have reached a balanced state. At this time, the bottom of the silicon via is exposed and is no longer protected by the passivation layer 105, and the passivation layer 105 retained on the side wall of the silicon via can protect the side wall, thereby protecting the side wall of the silicon via from being affected by etching in the subsequent etching process.

[0058] S4, etching the silicon substrate 100 corresponding to the bottom surface exposing the hole;

[0059] This step changes the existing passivation-etching cycle through silicon via preparation method, adds step S4, and under the condition of ensuring the balance of previous S2-S3, only the etching parameters of this step can be changed to change the TSV etching depth without affecting the etching / passivation balance.

[0060] Through this step, when the first S2-S3 are in an ideal state of equilibrium, the etching of S4 is the actual process of etching the silicon substrate 100. By etching downward, a deeper through-silicon via can be obtained.

[0061] S5, repeating steps S2-S4 for multiple times to obtain a through silicon via of a target depth, and cleaning and ashing the photoresist and passivation material remaining in the through silicon via;

[0062] By cycling S2-S4, periodic passivation, etching, and etching are performed to achieve the basic structure of TSV.

[0063] Finally, after the etching is completed, the remaining photoresist 101 and the sidewall passivation layer 105 are cleaned and ashed. S2-S5 uses a three-pulse process to cycle passivation-etching-etching to solve the balance problem between etching and passivation when modifying the process and ensure the stability of the process. Silicon through holes with high aspect ratios can be stably produced, such as Figure 6 The through silicon via is shown.

[0064] S6, depositing an insulating layer 103, a barrier layer 104, and a seed layer 104 on the inner wall of the through silicon via by an ALD deposition method to obtain Figure 7 High aspect ratio through silicon via shown.

[0065] The TSV prepared in step S5 is just a simple through hole. An insulating layer, a barrier layer, and a seed layer need to be prepared in the TSV to obtain a TSV structure for vertical signal connection between chips.

[0066] This embodiment provides a preparation solution for a high aspect ratio TSV electroplating analog chip, but the traditional PVD and CVD deposition methods are unable to deposit oxide or metal at the bottom of the TSV with an aspect ratio of more than 10:1, resulting in the inability to evenly cover the insulating layer, barrier layer, and seed layer in the hole. In the above case, this embodiment can use ALD for the sidewall deposition process to ensure that the sidewall inside the hole has sufficient coverage.

[0067] Further, coating the surface of the silicon substrate 100 with photoresist includes: defining the depth of the silicon through hole to be prepared as H, the thickness of the coated photoresist 101 as D, then H:D=(48-52):1, and coating the surface of the silicon substrate with photoresist 101 of thickness D.

[0068] As mentioned above, the photoresist 101 is used as a mask for subsequent etching, and its thickness is determined by the final etching depth, and it is necessary to ensure that the verticality of the photoresist 101 is sufficient to avoid excessive deviation in etching. During etching, the silicon substrate is mainly etched, but due to a part of the physical bombardment, the photoresist will also be bombarded and fall off, so during etching, it is necessary to ensure that the photoresist is not completely bombarded and fall off before the etching is completed.

[0069] In this embodiment, the ratio of the depth H of the through silicon via to the thickness D of the photoresist 101 is 50:1, which can ensure the above effect. In other embodiments, 48:1 or 52:1 may also be used.

[0070] Furthermore, the partially covered passivation layer at the exposed hole position of the silicon substrate comprises:

[0071] A polymer is deposited on the inner surface of the portion of the silicon substrate where the pores are exposed to form a passivation layer by a plasma deposition process.

[0072] Furthermore, the process gas containing carbon fluorine gas is deposited and polymerized by a plasma deposition process to form a passivation layer.

[0073] In this embodiment, the passivation layer covering the exposed holes of the silicon substrate is directly adopted from the prior art. In the prior art, a plasma deposition process is generally used for passivation. Plasma chemical vapor deposition (plasma chemical vapor deposition) refers to a technology that uses plasma to activate reaction gases to promote chemical reactions on the substrate surface or near the surface space to form a solid film.

[0074] By performing gas deposition with a carbon-fluorine-containing gas, a passivation layer can be formed on the exposed portion of the silicon substrate and the through silicon via. In this embodiment, the carbon-fluorine-containing gas is C4F8, which provides a passivation layer with a C:F ratio of 1:2.

[0075] Further, depositing an insulating layer, a barrier layer, and a seed layer on the inner wall of the through silicon via by an ALD deposition method comprises:

[0076] S6.1, evacuating the silicon substrate, introducing an oxygen-containing reaction precursor, wherein the oxygen-containing reaction precursor is siloxane, and when the surface adsorption of the through silicon via is in an oversaturated state, evacuating the silicon substrate, introducing a catalytic gas, and forming an oxide layer with a thickness of one atomic layer on the inner wall of the through silicon via;

[0077] In this step, the insulating layer is formed by ALD deposition method. The specific reaction process is: the silicon substrate with silicon through vias is placed in the ALD equipment. When the ALD equipment is in a vacuum state, the reaction precursor is introduced. The reaction precursor is an oxygen-containing reaction precursor. When the surface adsorption is in an oversaturated state, the excess gas is extracted to return to a vacuum state, and then the catalytic gas is introduced. At this time, the surface reacts to generate silicon oxide with a thickness of one atomic layer; then other reaction products are removed.

[0078] S6.2, repeat step S6.1, define the diameter of the silicon through hole as R, and the target thickness of the oxide layer as greater than 0.05R, so that the oxide layer reaches the target thickness, and complete the deposition of the insulating layer on the inner wall of the silicon through hole.

[0079] In this step, the above process is repeated until the target thickness is reached and then stopped. The thickness of the insulating layer 103 is selected according to the actual diameter R of the TSV, and generally needs to be greater than 0.05R to ensure that it will not be broken down and generate leakage current.

[0080] Further, depositing an insulating layer, a barrier layer, and a seed layer on the inner wall of the through silicon via by an ALD deposition method comprises:

[0081] S6.3, evacuating the silicon substrate, introducing a titanium-containing reaction precursor, and when the surface adsorption of the through silicon via is in an oversaturated state, evacuating the silicon substrate, introducing a nitrogen-containing reaction precursor, and forming a titanium nitride layer with a thickness of one atomic layer on the inner wall of the through silicon via;

[0082] This step is basically the same as step S6.1, except that the reaction precursor is different. In order to cover a titanium nitride layer in the silicon through-hole, the reaction precursor also needs to contain titanium and nitrogen elements.

[0083] S6.4, repeat step S6.3 to make the titanium nitride layer reach the target thickness, and complete the deposition of the barrier layer and the seed layer on the inner wall of the through silicon via.

[0084] Furthermore, the titanium-containing reaction precursor is titanium chloride, the nitrogen-containing reaction precursor is ammonia, and the target thickness of the titanium nitride layer is greater than 40 nm.

[0085] The thickness of the barrier layer and seed layer 104 needs to ensure that the sheet resistance is sufficient for successful copper electroplating, and the thickness is usually selected to be greater than 40 nm.

[0086] This step can deposit an insulating layer, a barrier layer, and a seed layer on the inner wall of the silicon through hole by ALD deposition method through S6.1-S6.4. The silicon substrate 100 is used as the process basis, silicon dioxide is used as the insulating layer 103 to prevent TSV leakage and signal crosstalk between adjacent TSVs, and TiN is used as the barrier layer 104 to prevent copper and silicon oxide diffusion from affecting device reliability. At the same time, since TiN itself is conductive, when the film thickness reaches a certain level, its square resistance is low enough to be used as the seed layer 104 for electronic electroplating. Therefore, the silicon through hole prepared in this application only needs titanium nitride of appropriate thickness to realize the barrier layer and seed layer at the same time.

[0087] Since the silicon through hole prepared in this embodiment has a high aspect ratio, it is difficult to ensure the uniformity of the deposited film during the sidewall deposition stage by the general PVD method, and the uniformity of the film will seriously affect the electroplating effect, and further affect the effect of the insulating layer, barrier layer, and seed layer. Therefore, the present invention adopts the ALD deposition process. At the same time, since the traditional ALD process of the Cu seed layer is mostly bubbling type, the deposition efficiency is low, so TiN with a higher deposition rate is used as the seed layer, which shortens the process and saves time and cost.

[0088] An electronic electroplating chip with a high aspect ratio through silicon via is further provided. The electronic electroplating chip comprises a through silicon via, and the through silicon via is prepared by the method for preparing a through silicon via with a high aspect ratio, and the aspect ratio of the through silicon via is greater than 15:1.

[0089] Furthermore, the duty ratio of the through silicon via is greater than 1:2.

[0090] Through the method for preparing silicon vias provided in this embodiment, the silicon vias of the prepared electronic electroplating chip can achieve a depth-to-width ratio of 15:1 or more. At the same time, through the method for preparing silicon vias provided in this embodiment, due to the use of the ALD deposition method, the reaction precursor or catalytic gas can accurately, stably and evenly reach the through hole, so the depth-to-width ratio of the silicon vias prepared in this application can be higher, and the duty cycle can be higher. This technical effect cannot be achieved by the prior art.

[0091] Experimental data

[0092] refer to Figure 8-9. The through silicon via prepared by the method provided in the present application has a depth-to-width ratio of 15:1 or more. Figure 8 The through silicon via shown has a width of 5um, a depth of 100um, an aspect ratio of 20, and a duty cycle of 1:2. Fig. 9 The through silicon via shown has a width of 1.3um, a depth of 20um, an aspect ratio of 15.3, and a duty cycle of 1:2.

[0093] It is proved that the method provided in the present application is feasible, and the aspect ratio of the silicon through hole prepared in the present application can reach above 15:1, and the duty ratio of the silicon through hole prepared in the present application is above 1:2.

[0094] It should be noted that in the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claim. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0095] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0096] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

[0097] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0098] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

Claims

1. A method for preparing a through silicon via with a high aspect ratio, characterized in that: The following steps are involved: S1, coating a photoresist on the surface of a silicon substrate, and exposing the holes by photolithography and then developing; S2, the part of the silicon substrate where the holes are exposed is covered with a passivation layer; S3, etching the bottom surface of the passivation layer to expose the silicon substrate corresponding to the bottom surface of the hole; S4, etching the silicon substrate corresponding to the bottom surface exposing the hole; S5, repeating steps S2-S4 for multiple times to obtain a through silicon via of a target depth, and cleaning and ashing the photoresist and passivation remaining in the through silicon via; S6, depositing an insulating layer, a barrier layer, and a seed layer on the inner wall of the through silicon via by an ALD deposition method to obtain a through silicon via with a high aspect ratio; Depositing an insulating layer, a barrier layer, and a seed layer on the inner wall of the through silicon via by an ALD deposition method comprises: S6.1, evacuating the silicon substrate, introducing an oxygen-containing reaction precursor, and when the surface adsorption of the through silicon via is in an oversaturated state, evacuating the silicon substrate, introducing a catalytic gas, and forming an oxide layer with a thickness of one atomic layer on the inner wall of the through silicon via; S6.2, repeating step S6.1 to make the oxide layer reach the target thickness, defining the diameter of the through silicon via as R, the target thickness of the oxide layer as greater than 0.05R, and completing the deposition of an insulating layer on the inner wall of the through silicon via; S6.3, evacuating the silicon substrate, introducing a titanium-containing reaction precursor, and when the surface adsorption of the through silicon via is in an oversaturated state, evacuating the silicon substrate, introducing a nitrogen-containing reaction precursor, and forming a titanium nitride layer with a thickness of one atomic layer on the inner wall of the through silicon via; S6.4, repeat step S6.3 to make the titanium nitride layer reach the target thickness, the target thickness of the titanium nitride layer is greater than 40nm, and complete the deposition of the barrier layer and the seed layer on the inner wall of the through silicon via.

2. The method for preparing a through silicon via with a high aspect ratio according to claim 1, characterized in that: The coating of photoresist on the surface of the silicon substrate includes: defining the depth of the silicon through hole to be prepared as H, the thickness of the coated photoresist as D, then H:D=(48-52):1, and coating the photoresist with a thickness of D on the surface of the silicon substrate.

3. The method for preparing a through silicon via with a high aspect ratio according to claim 1, characterized in that: The partially covered passivation layer on the exposed hole position of the silicon substrate comprises: A polymer is deposited on the inner surface of the portion of the silicon substrate where the pores are exposed to form a passivation layer by a plasma deposition process.

4. The method for preparing a through silicon via with a high aspect ratio according to claim 3, characterized in that: The process gas containing carbon fluorine gas is deposited and polymerized by a plasma deposition process to form a passivation layer.

5. The method for preparing a through silicon via with a high aspect ratio according to claim 1, characterized in that: The oxygen-containing reaction precursor is siloxane.

6. The method for preparing a through silicon via with a high aspect ratio according to claim 1, characterized in that: The titanium-containing reaction precursor is titanium chloride, and the nitrogen-containing reaction precursor is ammonia.

7. An electronic electroplating chip with high aspect ratio through silicon via, characterized in that: The electronic electroplating chip comprises a through silicon via, which is prepared by the method for preparing a through silicon via with a high aspect ratio according to any one of claims 1 to 6, and the aspect ratio of the through silicon via is greater than 15:

1.

8. The electronic electroplating chip with high aspect ratio through silicon via according to claim 7, characterized in that: The duty ratio of the through silicon via is greater than 1:2.

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