Integrated circuit chip

Abstract

Integrated circuit chips and seal ring structures are provided. An integrated circuit chip according to the present disclosure includes a substrate and a first interconnect layer above the substrate. The first interconnect layer includes a first device region and a first ring region surrounding the first device region. The first ring region includes a first wall completely surrounding the first device region and a second wall completely surrounding the first device region and the first wall. Along an edge of the first device region, the first wall is separated from the second wall by a first intermetal dielectric layer and at least one first dummy metal line. Near a corner of the first device region, the first wall is separated from the second wall by only the first intermetal dielectric layer.

Description

Technical Field

[0001] This invention relates to a semiconductor technology, and more particularly to an integrated circuit chip whose sealing ring structure includes a stress-absorbing structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have led to multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the evolution of ICs, while the geometric dimensions (i.e., the smallest components (or lines) that can be produced using manufacturing processes) have decreased, the functional density (i.e., the number of interconnect devices per chip area) has typically increased. This miniaturization process generally provides benefits by increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit technology advances towards smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs, or multi-gate devices) have been proposed to improve gate control by increasing gate channel coupling, reducing off-state current, and minimizing short-channel effects (SCEs). Multi-gate devices generally refer to devices having gate structures or portions thereof disposed above more than one side of the channel region. Fin-like field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices, and they have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have raised channels wrapped by gates on more than one side (e.g., gates wrapping the top and sidewalls of a semiconductor material “fin” extending from the substrate). Multi-bridge-channel transistors have gate structures extending partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, the multi-bridge channel transistor can also be called a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor.

[0004] Due to scaling down, the structure of finned field-effect transistors or multi-bridge channel transistors can be easily damaged by fogging or stress during monolithization. Hermetical structures have been used to protect semiconductor devices. While existing hermetical structures are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0005] This disclosure provides an integrated circuit chip, including a substrate and a first interconnect layer, in several embodiments. The first interconnect layer is located above the substrate and includes a first device region and a first ring region surrounding the first device region. The first ring region includes a first wall and a second wall. The first wall completely surrounds the first device region. The second wall completely surrounds the first device region and the first wall. Along the edge of the first device region, the first wall and the second wall are separated by a first intermetallic dielectric layer and at least one first dummy metal line. Near a corner of the first device region, the first wall and the second wall are separated only by the first intermetallic dielectric layer.

[0006] This disclosure provides an integrated circuit chip with an interconnect structure including a sealing ring structure. The sealing ring structure includes a first sealing ring wall and a second sealing ring wall. The first sealing ring wall includes four edges and four corners. The second sealing ring wall completely surrounds the first sealing ring wall. Along the four edges of the first sealing ring wall, the first sealing ring wall and the second sealing ring wall are separated by a first intermetallic dielectric layer and at least one first dummy metal line. Along the four corners of the first sealing ring wall, the first sealing ring wall and the second sealing ring wall are separated only by the first intermetallic dielectric layer.

[0007] This disclosure provides an integrated circuit chip, including a substrate and a first interconnect layer, through several embodiments. The substrate includes a device region and a ring region surrounding the device region. The first interconnect layer is disposed on the substrate and includes a first region and a second region. The first region is disposed directly above the device region. The second region is disposed directly above the ring region. The second region includes a closed rectangular ring with four corners and includes four stress-absorbing regions at the four corners. Attached Figure Description

[0008] The following detailed description, along with the accompanying drawings, constitutes a complete disclosure. It should be emphasized that, in accordance with industry practice, the illustrations are not necessarily drawn to scale and are for illustrative purposes only. In fact, the dimensions of components may be arbitrarily enlarged or reduced for clarity.

[0009] Figure 1 A top view of a substrate according to one or more embodiments of the present disclosure is shown.

[0010] Figure 2 The settings according to one or more embodiments of this disclosure are shown. Figure 1 A cross-sectional view of an interconnect structure on a substrate.

[0011] Figure 3 The settings according to one or more embodiments of this disclosure are shown. Figure 1 A top view of an interconnect structure on a substrate.

[0012] Figure 4 The settings according to one or more embodiments of this disclosure are shown. Figure 1 A partially enlarged cross-sectional view of a portion of the interconnect structure above a device region of a substrate.

[0013] Figure 5 The settings according to one or more embodiments of this disclosure are shown. Figure 1 A partially magnified top view of a portion of the interconnect structure above an outer corner region of the substrate.

[0014] Figure 6 The settings according to one or more embodiments of this disclosure are shown. Figure 1 A partially enlarged cross-sectional view of a portion of the interconnect structure above the outer corner region of the substrate.

[0015] Figure 7 The settings according to one or more embodiments of this disclosure are shown. Figure 1 A partially enlarged cross-sectional view of a portion of the interconnect structure above the outer corner region of the substrate.

[0016] Figure 8 The settings according to one or more embodiments of this disclosure are shown. Figure 1 A partially magnified top view of a portion of the interconnect structure above an inner corner region of the substrate.

[0017] Figure 9 The settings according to one or more embodiments of this disclosure are shown. Figure 1 A partially enlarged cross-sectional view of a portion of the interconnect structure above the inner corner region of the substrate.

[0018] Figure 10 The settings according to one or more embodiments of this disclosure are shown. Figure 1 A partially enlarged cross-sectional view of a portion of the interconnect structure above the inner corner region of the substrate.

[0019] The reference numerals in the attached figures are explained as follows:

[0020] 100: Substrate

[0021] 102: Device Area

[0022] 104: Inner Ring Road

[0023] 1042: Fifth sealing ring wall

[0024] 1044: Sixth sealing ring wall

[0025] 104C: Second stress-absorbing zone

[0026] 1042I: Inner wall surface

[0027] 1042O: Outer wall surface

[0028] 106: Inner corner area

[0029] 106-1: First Inner Corner Area

[0030] 106-2: Second Inner Corner Area

[0031] 106-3: Third Inner Corner Area

[0032] 106-4: Fourth Inner Corner Area

[0033] 108: Outer Ring Road

[0034] 1082: First sealing ring wall

[0035] 1084: Second sealing ring wall

[0036] 1086: Third sealing ring wall

[0037] 1088: Fourth sealing ring wall

[0038] 108C: First stress-absorbing zone

[0039] 1082I: Inner wall surface

[0040] 1082O: Outer wall surface

[0041] 110: Outer corner area

[0042] 110-1: First outer corner area

[0043] 110-2: Second outer corner area

[0044] 110-3: Third outer corner area

[0045] 110-4: Fourth outer corner area

[0046] 1142: The fourth group of dummy metal strips

[0047] 1182: First group of dummy metal strips

[0048] 1184: Second group of dummy metal strips

[0049] 1186: The third group of dummy metal strips

[0050] 122: First gap

[0051] 124: Second gap

[0052] 126: Third gap

[0053] 128: First transverse connector

[0054] 130: Second transverse connector

[0055] 132: Fourth Gap

[0056] 150: Interconnection Structure

[0057] 160: First square area

[0058] 180: Second square area

[0059] 200: Integrated circuit chip

[0060] 202: First intermetallic dielectric layer

[0061] 204: First Metal Wire

[0062] 206: Second intermetallic dielectric layer

[0063] 208: First contact hole

[0064] 210: Second metal wire

[0065] 212: Third intermetallic dielectric layer

[0066] 214: Second contact via

[0067] 216: Third metal wire

[0068] 218: Fourth intermetallic dielectric layer

[0069] 220: Third contact via

[0070] 222: Fourth metal wire

[0071] 304: (First) Circular metal wire

[0072] 306: Fourth contact via

[0073] 308: (First) Through-hole strip

[0074] 310: (Second) Ring-shaped metal wire

[0075] 312: Fifth contact hole

[0076] 314: (Second) Through-hole strip

[0077] 316: (Third) Ring-shaped metal wire

[0078] 318: Sixth contact hole

[0079] 320: (Third) Through-hole strip

[0080] 322: (Fourth) Ring-shaped metal wire

[0081] 404: (Fifth) Ring-shaped metal wire

[0082] 406: Seventh contact hole

[0083] 408: (Fourth) Through-hole strip

[0084] 410: (Sixth) Ring-shaped metal wire

[0085] 412: Eighth contact hole

[0086] 414: (Fifth) Through-hole strip

[0087] 416: (Seventh) Ring-shaped metal wire

[0088] 418: Ninth contact via

[0089] 420: Sixth through hole strip

[0090] 422: (Eighth) Ring-shaped metal wire

[0091] X, Y, Z: Direction

[0092] θ: included angle

[0093] G1: First gap width

[0094] G2: Second gap width

[0095] G3: Third gap width

[0096] G4: Fourth gap width

[0097] M0: First metal layer

[0098] M1: Second metal layer

[0099] M2: Third metal layer

[0100] M3: Fourth Metal Layer

[0101] P1: First spacing

[0102] P2: Second spacing

[0103] P5: Fifth Spacing

[0104] W1: First width

[0105] W2: Second width

[0106] W3: Third Width

[0107] W4: Fourth Width

[0108] W5: Fifth Width

[0109] A-A', B-B', C-C', D-D', E-E': lines Detailed Implementation

[0110] The following disclosure provides many different embodiments or examples to implement different features of this application. Specific examples of components and their arrangements are described below to illustrate this disclosure. Of course, these embodiments are merely examples and should not be construed as limiting the scope of this disclosure. For example, the specification may describe a first feature formed on or above a second feature, which may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, repeated reference numerals and / or designations may be used in different examples of this disclosure; this repetition is for simplification and clarity and is not intended to limit the relationship between the various embodiments and / or configurations discussed.

[0111] Furthermore, spatial terms, such as "below," "below," "lower," "above," "higher," etc., are used to facilitate the description of the relationship between one element or feature and another element(s) in the diagram. In addition to the orientation shown in the diagram, these spatial terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial terms used here can be interpreted in the same way.

[0112] When using terms such as "about," "around," etc., to describe numbers or ranges of numbers, the term is intended to encompass numbers within a reasonable range, taking into account the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the number, the number or range of numbers encompasses a reasonable range including the described number, such as within + / –10% of the described number. For example, a material layer having a thickness of "about 5 nanometers" can encompass a size range from 4.25 nanometers to 5.75 nanometers, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / –15%. Furthermore, reference numerals and / or letters may be repeated in various examples within this disclosure. This repetition is for simplicity and clarity and is not intended to limit the relationship between the various embodiments and / or configurations discussed. For the avoidance of doubt, the X, Y, and Z directions in the drawings of this disclosure are perpendicular to each other. Throughout this disclosure, similar reference numerals denote similar features unless otherwise stated.

[0113] Sealing structures are used to prevent semiconductor devices in integrated circuit chips from being damaged by fogging or stress during the monolithic fabrication process of integrated circuit chips. As the industry moves towards smaller device nodes, multi-gate devices (e.g., fin field-effect transistors (FinFETs) and multi-bridge channel (MBC) transistors) have emerged. Although FinFETs and MBC transistors improve gate control and short-channel effects, they are not immune to water and stress. In fact, due to their delicate dimensions and structure, they may be more susceptible to damage without sufficient sealing. In some existing technologies, sealing ring structures are present not only in front-end-of-line (FEOL) and middle-end-of-line (MEOL) structures but also in back-end-of-line (BEOL) structures. As used herein, front-end (FEOL) structures include structural features of transistors or other semiconductor devices fabricated on a semiconductor substrate; middle-end (MEOL) structures include source / drain contact vias or gate contact vias; and back-end (BEOL) structures include interconnect structures. When interconnect structures or their precursors undergo planarization processes, the pattern density on the various metal layers within the interconnect structure is important for preventing dents or uneven surfaces. When the pattern density in the metal layers is substantially non-uniform, dents may occur in areas of lower density. However, it has also been observed that when the pattern density in the interconnect structure is uniform, the sealing ring structure may not adequately absorb stress, leading to adverse damage to the integrated circuit chip.

[0114] This disclosure provides an embodiment of an integrated circuit chip that includes a stress-absorbing structure in its sealing ring structure. According to an embodiment of this disclosure, the integrated circuit chip includes a substrate and an interconnect structure disposed on the substrate. The substrate includes a device region, an inner ring surrounding the device region, and an outer ring surrounding the inner ring. The interconnect structure above the substrate also includes multiple portions perpendicularly corresponding to multiple regions in the substrate. The portions of the interconnect structure disposed directly above the inner and outer rings include multiple sealing ring walls. Although dummy metalbars may be inserted between the sealing ring walls to provide uniform pattern density, they are deliberately omitted from corner areas to provide stress absorption.

[0115] First refer to Figure 1This is a top view of the substrate 100. The substrate 100 includes a device region 102, an inner ring 104 continuously surrounding the device region 102, an outer ring 108 continuously surrounding the inner ring 104, four inner corner regions 106 disposed between the outer corner of the inner ring 104 and the inner corner of the outer ring 108, and four outer corner regions 110 disposed at the outer corner of the outer ring 108. The inner corner regions 106 include a first inner corner region 106-1, a second inner corner region 106-2, a third inner corner region 106-3, and a fourth inner corner region 106-4. For ease of reference, the first inner corner region 106-1, the second inner corner region 106-2, the third inner corner region 106-3, and the fourth inner corner region 106-4 may be collectively referred to as (a plurality of) inner corner regions 106 or individually as an inner corner region 106, depending on the context. The outer corner region 110 includes a first outer corner region 110-1, a second outer corner region 110-2, a third outer corner region 110-3, and a fourth outer corner region 110-4. For ease of reference, the first outer corner region 110-1, the second outer corner region 110-2, the third outer corner region 110-3, and the fourth outer corner region 110-4 may be collectively referred to as (a plurality of) outer corner regions 110 or individually as an outer corner region 110, depending on the context. When viewed along the Z-direction, the substrate 100 may be rectangular in shape. In these embodiments, each inner corner region 106 resembles a right-angled triangle with its right-angle vertex cut off, and each outer corner region 110 is a right-angled triangle. Figure 1 In the illustrated embodiment, each right-angled triangle in the inner corner region 106 or the outer corner region 110 is an isosceles triangle. In other words, the hypotenuse of each outer corner region 110 forms an angle θ with the X or Y direction. The angle θ is 45°. Each of the inner ring 104 and the outer ring 108 is essentially a rectangle with four corners.

[0116] In some embodiments, substrate 100 may be a bulk silicon (Si) substrate. Alternatively, substrate 100 may include elemental semiconductors, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP); or combinations thereof. In some embodiments, substrate 100 includes one or more group III-V materials, one or more group II-VI materials, or combinations thereof. In other cases, substrate 100 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. In still other embodiments, substrate 100 may be a diamond substrate or a sapphire substrate.

[0117] The substrate 100 may include various semiconductor structures, such as an active region, a gate structure disposed over a channel region of the active region, a source / drain feature disposed over a source / drain region of the active region, a source / drain contact disposed over the source / drain feature, and a gate contact via disposed over the gate structure. The active region may include silicon (Si) or a suitable semiconductor material. Each segmented gate structure includes a gate dielectric layer and a gate electrode layer disposed over the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interface layer and a high-k dielectric layer. As used and described herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, such as a dielectric constant greater than that of thermally oxidized silicon (~3.9). The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high dielectric constant gate dielectric layer may include hafnium oxide. Alternatively, the high dielectric constant gate dielectric layer may include other high dielectric constant dielectric materials, such as titanium dioxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. High dielectric constant gate dielectric layers can be formed by atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, oxidation, and / or other suitable methods.

[0118] The gate electrode layer of a segmented gate structure can include a single-layer or multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a substrate, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. As an example, the gate electrode layer can include titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes.

[0119] The source / drain features may include silicon (Si) doped with an n-type dopant such as phosphorus (P) or arsenic (As), or silicon germanium (SiGe) doped with a p-type dopant such as boron (B) or boron difluoride (BF2). The source / drain features may include a barrier layer, a silicide layer, and a metal filler layer disposed above the silicide layer. The barrier layer may include titanium nitride or tantalum nitride. The silicide layer may include titanium silicide, tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide. The silicide layer is connected to the source / drain features to reduce contact resistance. The metal filler layer may include ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), or tungsten (W).

[0120] Figure 2 Showing settings Figure 1A cross-sectional view of an interconnect structure 150 on a substrate 100. The interconnect structure 150 may include more than nine metal wire layers, such as between ten and fourteen metal layers. Each metal layer includes a conductive line embedded in an intermetallic dielectric (IMD) layer. The interconnect structure 150 also includes contact vias that vertically interconnect the conductive lines in the different metal layers. The intermetallic dielectric layer may include materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide, borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The conductive lines and contact vias may include copper (Cu), titanium nitride (TiN), tungsten (W), or ruthenium (Ru). The interconnect structure 150 functionally connects transistors or semiconductor devices in the substrate 100. The interconnect structure 150 and the substrate 100 can be collectively referred to as an integrated circuit (IC) chip.

[0121] The semiconductor structure in substrate 100 forms a transistor, such as a planar transistor or a multi-gate transistor. Examples of multi-gate transistors may include fin-like field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors. FinFETs have raised channels enclosed by gates on more than one side (e.g., the gates enclose the top and sidewalls of a semiconductor material “fin” extending from the substrate). Multi-bridge-channel transistors have gate structures extending partially or completely around the channel region to provide access to the channel region on two or more sides. Because their gate structures surround the channel region, multi-bridge-channel transistors may also be referred to as surrounding-gate transistors (SGTs) or gate-all-around (GAA) transistors. When the transistor in substrate 100 is a planar transistor, the active region may include semiconductor features embedded in the dielectric layer. When the transistor in substrate 100 is a fin field-effect transistor, the active region may include a fin semiconductor structure rising above an isolation feature, and a gate structure disposed above the fin semiconductor structure to engage with two or three surfaces of the fin semiconductor structure. When the transistor in substrate 100 is a multi-bridge channel transistor, the active region may each include a vertical stack of nanostructures, and a gate structure surrounds each nanostructure in the vertical stack of nanostructures. The nanostructures may have different cross-sections. In some cases, the nanostructure has a width substantially similar to its thickness and may be referred to as a nanowire. In other cases, the nanostructure has a width greater than its thickness and may be referred to as a nanosheet.

[0122] Figure 3 A top view of an integrated circuit chip 200 is shown. The integrated circuit chip 200 includes a substrate 100 and interconnect structures 150 disposed on the substrate 100. Figure 3 As shown, the interconnect structure 150 covers various regions of the substrate 100 and includes portions corresponding to the respective regions of the substrate 100 perpendicularly (i.e., along the Z direction). These portions of the interconnect structure 150 will be described in more detail below. For example, the portion of the interconnect structure 150 directly above the device region 102 will be along... Figure 3 The line A-A' in the middle intercepts Figure 4 A more detailed description is provided in the partial sectional view. Figure 5 The first square region 160 is shown, which vertically covers the fourth outer corner region 110-4, a portion of the outer ring 108, and a portion of the fourth inner corner region 106-4. Figure 6 and Figure 7Cross-sectional views of different portions of the first square region 160 are shown. Figure 8 A second square region 180 is shown, which vertically covers the fourth inner corner area 106-4, a portion of the inner ring 104, and a portion of the device area 102. Figure 9 and Figure 10 Cross-sectional views of different portions of the second square region 180 are shown. According to this disclosure, the first square region 160 and / or the second square region 180 may include stress-absorbing regions where dummy metal strips are intentionally omitted. Due to the omission of the dummy metal strips, the stress-absorbing regions have a lower pattern density. Simultaneously, the lower pattern density provides the stress-absorbing regions with the ability to absorb stress generated in subsequent processes (e.g., monolithic processes).

[0123] Figure 4 A partial cross-sectional view of a portion of the interconnect structure 150 directly above the device region 102 is shown. For simplicity of explanation, Figure 4 Only the first four metal layers of the interconnect structure 150 are shown. These first four metal layers are the metal layers closest to the substrate 100 and include a first metal layer M0, a second metal layer M1, a third metal layer M2, and a fourth metal layer M3. In some embodiments, the size of the metal layer above the fourth metal layer M3 can be much larger than the size of the fourth metal layer M3. Figure 4 As shown, the first metal layer M0 includes a first inter-metal dielectric (IMD) layer 202 and a plurality of first metal lines 204 embedded in the first IMD layer 202. The second metal layer M1 includes a second IMD layer 206 and a plurality of second metal lines 210 embedded in the second IMD layer 206. The second metal lines 210 extend longitudinally along the X direction. Each first metal line 210 is electrically coupled to a selected first metal line 204 in the first metal layer M0 through a first contact via 208, which is also embedded in the second IMD layer 206. The third metal layer M2 includes a third IMD layer 212 and a plurality of third metal lines 216 embedded in the third IMD layer 212. The third metal lines 216 extend longitudinally along the Y direction. Each third metal line 216 is electrically coupled to a selected second metal line 210 in the second metal layer M1 through a second contact via 214, which is also embedded in the third IMD layer 212. The fourth metal layer M3 includes a fourth intermetallic dielectric layer 218 and a plurality of fourth metal lines 222 embedded in the fourth intermetallic dielectric layer 218. The fourth metal lines 222 extend longitudinally along the X direction. Each fourth metal line 222 is electrically coupled to a selected third metal line 216 in the third metal layer M2 through a third contact via 220, which is also embedded in the fourth intermetallic dielectric layer 218.

[0124] The first intermetallic dielectric layer 202, the second intermetallic dielectric layer 206, the third intermetallic dielectric layer 212, and the fourth intermetallic dielectric layer 218 may comprise silicon dioxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fused silica glass (FSG), carbon-doped silicon oxide, low-k dielectric materials, or combinations thereof. The first metal line 204, the second metal line 210, the third metal line 216, the fourth metal line 222, the first contact via 208, the second contact via 214, and the third contact via 220 may comprise aluminum, copper, aluminum / silicon / copper alloys, titanium, ruthenium, tungsten, metal silicides, or combinations thereof. In some embodiments, the first metal line 204, the second metal line 210, the third metal line 216, the fourth metal line 222, the first contact via 208, the second contact via 214, and the third contact via 220 may further include a barrier layer to prevent electromigration. The barrier layer may include titanium nitride or tantalum nitride.

[0125] like Figure 4 As shown, in the portion of the interconnect structure 150 directly above device region 102, the metal lines in adjacent metal layers are orthogonal. For example, first metal line 204 and third metal line 216 extend along the Y direction, and second metal line 210 and fourth metal line 222 extend along the X direction. Typically, metal lines disposed in metal layers farther from substrate 100 can have larger dimensions. Although this trend exists in the first four metal layers, the metal lines in the first four metal layers can have relatively similar dimensions. The metal lines in the fifth or sixth metal layer can have much larger dimensions. In the depicted embodiment, each of the first metal lines 204 has a first width W1 along the X direction and is arranged with a first spacing P1. In some cases, the first width W1 can be between about 20 nanometers and about 50 nanometers, and the first spacing P1 can be about twice the first width W1, between about 40 nanometers and about 100 nanometers. Although the width and spacing of the second metal lines 210 are not labeled, they can be similar to the width and spacing of the first metal lines 204. As described above, the metal lines in the metal layers farther from the substrate 100 have larger dimensions. For example, the width of the tenth metal line in the tenth metal layer (M9, not explicitly shown) can be between about 5 micrometers and about 6 micrometers.

[0126] Figure 5An enlarged top view of a first square region 160 is shown, which is directly above a fourth outer corner region 110-4, a corner of an outer ring 108, and a portion of a fourth inner corner region 106. The portion of the interconnect structure 150 directly above the outer ring 108 includes a sealing ring structure comprising a plurality of sealing ring walls, each of which is a closed ring structure surrounding a device region 102. For ease of reference, the portion of the interconnect structure 150 directly above a region of the substrate 100 may be referred to as that region. For example, the portion of the interconnect structure 150 above device region 120 may be referred to as device region 102, and the portion of the interconnect structure 150 directly above the outer ring 108 may be referred to as outer ring 108. In the depicted embodiment, the portion of the interconnect structure 150 directly above the outer ring 108 includes a first sealing ring wall 1082, a second sealing ring wall 1084, a third sealing ring wall 1086, and a fourth sealing ring wall 1088. Please note that although the outer ring 108 is shown as comprising four sealing ring walls, it should be understood that the outer ring 108 may include fewer or more sealing ring walls. Each sealing ring wall comprises multiple metal lines in each metal layer. The multiple metal lines in a sealing ring wall extend substantially parallel to each other and can be considered as a sub-wall structure. Figure 5 As shown, parallel extending metal wires in each sealing ring wall can be laterally connected by a plurality of first lateral connectors 128. The first lateral connectors 128 mechanically connect adjacent metal wires to provide structural reinforcement. Each of the first sealing ring wall 1082, second sealing ring wall 1084, third sealing ring wall 1086, and fourth sealing ring wall 1088 can extend through more than one metal layer in the interconnect structure 150. Figure 4 In the illustrated embodiment, because the metal wires in the first four metal layers are of similar size, the first sealing ring wall 1082, the second sealing ring wall 1084, the third sealing ring wall 1086, and the fourth sealing ring wall 1088 can extend vertically through the first four metal layers. That is, although the metal wires in the higher metal layers (e.g., the fifth or sixth metal layer) may still include closed-loop metal wires that track the outer ring 108, these metal wires may not be vertically aligned with any of the first sealing ring wall 1082, the second sealing ring wall 1084, the third sealing ring wall 1086, and the fourth sealing ring wall 1088.

[0127] Still referencing Figure 5The first sealing ring wall 1082, the second sealing ring wall 1084, the third sealing ring wall 1086, and the fourth sealing ring wall 1088 are not placed back-to-back, but are intentionally spaced apart from each other. As described above, the metal lines in the interconnect structure are disposed in the inter-metal dielectric layer. When the pattern density (i.e., the density of the metal lines) is low in a local area, it may lead to an uneven surface or depressions during the surface planarization process. To prevent depressions, dummy metal strips can be inserted. In the illustrated embodiment, a plurality of first sets of dummy metal strips 1182 are inserted between the first sealing ring wall 1082 and the second sealing ring wall 1084; a plurality of second sets of dummy metal strips 1184 are inserted between the second sealing ring wall 1084 and the third sealing ring wall 1086; and a plurality of third sets of dummy metal strips 1186 are inserted between the third sealing ring wall 1086 and the fourth sealing ring wall 1088. Figure 5 In some embodiments shown, dummy metal strips are strategically omitted at the corners of the outer ring 108 to form a first stress-absorbing region 108C. Since the outer ring 108 is substantially rectangular and has four corners, the integrated circuit chip 200 of this disclosure may include four first stress-absorbing regions 108C. The first stress-absorbing regions 108C include a first gap 122 between the first sealing ring wall 1082 and the second sealing ring wall 1084, a second gap 124 between the second sealing ring wall 1084 and the third sealing ring wall 1086, and a third gap 126 between the third sealing ring wall 1086 and the fourth sealing ring wall 1088. Each of the first gap 122, the second gap 124, and the third gap 126 may be referred to as a gap because they do not contain any metal wires or dummy metal strips. Each of the first gap 122, the second gap 124, and the third gap 126 includes an intermetallic dielectric layer. In the illustrated embodiment, each of the first gap 122, the second gap 124, and the third gap 126 may include a first intermetallic dielectric layer 202, a second intermetallic dielectric layer 206, a third intermetallic dielectric layer 212, and a fourth intermetallic dielectric layer 218.

[0128] Figure 6 Show along Figure 5 A partial cross-sectional view of the interconnect structure 150 directly above the outer ring 108, where line B-B' is located. Although Figure 6 Showing something similar to Figure 4 The first four metal layers, but the metal lines directly above the outer ring 108 are wider and spaced at a greater interval than the metal lines directly above the device area 102. For example... Figure 6As shown, the first metal layer M0 includes a first inter-metal dielectric layer 202 and a plurality of first ring metallines 304 embedded in the first inter-metal dielectric layer 202. The second metal layer M1 includes a second inter-metal dielectric layer 206 and a plurality of second ring metallines 310 embedded in the second inter-metal dielectric layer 206. The third metal layer M2 includes a third inter-metal dielectric layer 212 and a plurality of third ring metallines 316 embedded in the third inter-metal dielectric layer 212. The fourth metal layer M3 includes a fourth inter-metal dielectric layer 218 and a plurality of fourth ring metallines 322 embedded in the fourth inter-metal dielectric layer 218.

[0129] The portion of the interconnect structure directly above the outer ring 108 also includes via bars that are vertically coupled to the annular metal wires in each sealing ring wall. The first sealing ring wall 1082 includes a plurality of first via bars 308 embedded in the second intermetallic dielectric layer 206, a plurality of second via bars 314 embedded in the third intermetallic dielectric layer 212, and a plurality of third via bars 320 embedded in the fourth intermetallic dielectric layer 218. The via bars differ from metal wires and contact vias. The via bars differ from metal wires because they are narrower to ensure satisfactory landing on the underlying metal wires. The via bars differ from contact vias because the via bars are closed-loop rings surrounding the device region 102, while contact vias resemble vertical cones or cylinders. Contact vias may be present in the portion of the interconnect structure directly above the outer ring 108. For example, the fourth contact via 306 may exist in the second intermetallic dielectric layer 206, the fifth contact via 312 may exist in the third intermetallic dielectric layer 212, and the sixth contact via 318 may exist in the fourth intermetallic dielectric layer 218.

[0130] like Figure 6As shown, the annular metal wires and through-hole strips can be vertically aligned to define the sealing ring wall surfaces. Regarding the first sealing ring wall 1082, the outermost of the annular metal wires 304, 310, 316, and 322 is vertically aligned with the outermost of the through-hole strips 308, 314, and 320 to define an outer wall surface 1082O adjacent to the first set of dummy metal strips 1182, and the innermost of the annular metal wires 304, 310, 316, and 322 is vertically aligned with the innermost of the through-hole strips 308, 314, and 320 to define an inner wall surface 1082I. To avoid confusion, the outer wall surface 1082O and the inner wall surface 1082I are continuous and seamless because each annular metal wire and through-hole strip completes a full circle and has a closed loop shape. This also applies to the second sealing ring wall 1084, the third sealing ring wall 1086, and the fourth sealing ring wall 1088. That is, each of the second sealing wall 1084, the third sealing ring wall 1086, and the fourth sealing ring wall 1088 has an outer wall surface and an inner wall surface defined by an annular metal wire and a through-hole strip, the through-hole strip being substantially perpendicularly aligned with the annular metal wire.

[0131] In the illustrated embodiment, the first set of dummy metal strips 1182 has more dummy metal strips than the second set of dummy metal strips 1184 and the third set of dummy metal strips 1186. In some cases, the first set of dummy metal strips 1182 includes 5 dummy metal strips in each of the first four metal layers, the second set of dummy metal strips 1184 includes 1 dummy metal strip in each of the first four metal layers, and the third set of dummy metal strips 1186 includes 1 dummy metal strip in each of the first four metal layers. These differences are not insignificant. In the illustrated embodiment, all structures other than the first set of dummy metal strips 1182 (i.e., the second sealing ring wall 1084, the third sealing ring wall 1086, the fourth sealing ring wall 1088, the second set of dummy metal strips 1184, and the third set of dummy metal strips 1186) are sacrificial structures. During the monolithization process of scribing the integrated circuit chip 200 along the scribe line near the fourth sealing ring wall 1088, if the sacrificial structure suffers substantial damage, the resulting stress may be absorbed by the deformation or breakage of the first set of dummy metal strips 1182, which is structurally weaker than any sealing ring wall with a continuous wall surface. When the integrated circuit chip 200 suffers only minor damage, the stress can be dampened by the second set of dummy metal strips 1184 and the third set of dummy metal strips 1186.

[0132] The annular metal lines in the portion of the interconnect structure 150 above the outer ring 108 are significantly wider than the metal lines directly above the device region 102. In the illustrated embodiment, each first annular metal line 304 has a second width W2, and the first annular metal lines 304 are positioned with a second spacing P2. In some embodiments, the ratio of the second width W2 to the first width W1 is between about 5 and about 15, and the ratio of the second spacing P2 to the first spacing P1 is between about 5 and about 15. In some cases, the second width W2 may be between about 100 nanometers and about 250 nanometers, and the second spacing P2 may be between about 200 nanometers and about 500 nanometers. To ensure that the via strip can satisfactorily fall on the underlying annular metal line, the third width W3 of the via strip may be between about 50% and about 80% of the second width W2. Due to limitations in the shape and patterning method of the contact vias, the fourth width W4 of the contact vias (e.g., the fourth contact via 306, the fifth contact via 312, or the sixth contact via 318) can be between approximately 10% and approximately 30% of the second width W2. Each of the first set of dummy metal strips 1182, the second set of dummy metal strips 1184, and the third set of dummy metal strips 1186 can have a dummy strip width that can be between approximately 50% and approximately 80% of the second width W2. Although dummy strips are used to increase pattern density, it has been observed that the workpiece may warp when the density of metal features in the metal layer is too high. For this reason, the dummy metal strips are intentionally made narrower than the metal lines.

[0133] Figure 7 Show along Figure 5 A partial cross-sectional view of the interconnect structure 150 directly above the outer ring 108, with line C-C' in the middle. (Brief reference) Figure 5 Line C-C' forms an angle θ with the X direction, which is 45° in the illustrated embodiment. Each of the first sealing ring wall 1082, the second sealing ring wall 1084, the third sealing ring wall 1086, and the fourth sealing ring wall 1088 includes a segment perpendicular to line C-C'. Line C-C' passes through the first stress-absorbing region 108C. Figure 7As shown, the first sealing ring wall 1082 and the second sealing ring wall 1084 are spaced apart by a first gap 122; the second sealing ring wall 1084 and the third sealing ring wall 1086 are spaced apart by a second gap 124; and the third sealing ring wall 1086 and the fourth sealing ring wall 1088 are spaced apart by a third gap 126. As described above, the first gap 122, the second gap 124, and the third gap 126 are regions where the annular metal wire or dummy metal strip is completely omitted. The first gap 122, the second gap 124, and the third gap 126 are filled with a first inter-metal dielectric layer 202, a second inter-metal dielectric layer 206, a third inter-metal dielectric layer 212, and a fourth inter-metal dielectric layer 218. The first gap 122 has a first gap width G1, the second gap 124 has a second gap width G2, and the third gap 126 has a third gap width G3. In some embodiments, the first gap width G1, which accommodates more dummy metal strips, is greater than the second gap width G2 and the third gap width G3. In some embodiments, each of the first gap width G1, the second gap width G2, and the third gap width G3 may be between about 300 nanometers and about 2000 nanometers (i.e., 2 micrometers), with the first gap width G1 being the largest. In some embodiments, the first gap width G1 is about 1800 nanometers, the second gap width G2 is about 500 nanometers, and the third gap width G3 is about 500 nanometers. The width ranges of these first gaps 122, second gaps 124, and third gaps 126 are not insignificant. When the gap width is less than 300 nanometers, the benefit of such a gap is negligible because this gap width is too similar to the second gap P2. When the gap width is greater than 2000 nanometers, the depression at such a gap may become so severe that its adverse effects may outweigh its benefits.

[0134] Experimental results show that implementing the first stress-absorbing region 108C in the interconnect structure 150 above the corner of the outer ring 108 provides satisfactory stress absorption without suffering the adverse effects of reduced pattern density. Several factors are at play. First, it has been observed that stress in monolithic processes is greatest near the corners of the integrated circuit chip 200. Therefore, the first stress-absorbing region 108C located near the corner is appropriately positioned to absorb stress to the greatest extent. Second, the corner is farther away from the device region 102 or the portion of the interconnect structure 150 above the device region 102. In this way, when the first stress-absorbing region 108C is implemented, the recessed or uneven surface is formed at a location farther away from the semiconductor device, thereby minimizing the adverse effects of the first stress-absorbing region 108C. It is understood that the boundaries of the first gap 122, the second gap 124, and the third gap 126 may extend more or less into the edge portions extending along the X or Y directions, thereby increasing the length of the various gaps around the integrated circuit chip 200. The length of each gap can be adjusted to better balance stress absorption and the required pattern density.

[0135] In some embodiments where further stress absorption is required, a second stress-absorbing region may be implemented in the portion of the interconnect structure 150 directly above the inner ring 104. Figure 8 An enlarged top view of the second square region 180 is shown, which is located directly above the fourth inner corner region 106-4, a corner of the inner ring 104, and a portion of the device region 102. For ease of reference, the portion of the interconnect structure 150 directly above a region of the substrate 100 can be referred to as that region. For example, the portion of the interconnect structure 150 above the device region 120 can be referred to as the device region 102, and the portion of the interconnect structure 150 directly above the inner ring 104 can be referred to as the inner ring 104. Similar to the outer ring 108, the inner ring 104 is a sealing ring structure comprising a plurality of sealing ring walls, each sealing ring wall being a closed ring structure surrounding the device region 102. Figure 8 In some embodiments shown, the inner ring 104 includes a fifth sealing ring wall 1042 and a sixth sealing ring wall 1044. Note that although the inner ring 104 is shown as including two sealing ring walls, it should be understood that the inner ring 104 may include fewer or more sealing ring walls. Each sealing ring wall includes multiple metal lines in each metal layer. The multiple metal lines in a sealing ring wall extend substantially parallel to each other and can be considered as a sub-wall structure. Figure 8As shown, parallel extending metal wires in each sealing ring wall can be laterally connected by a plurality of second lateral connectors 130. The second lateral connectors 130 mechanically connect adjacent metal wires to provide structural reinforcement. Each of the fifth sealing ring wall 1042 and the sixth sealing ring wall 1044 can extend through more than one metal layer in the interconnection structure 150. Figure 8 In the illustrated embodiment, because the metal wires in the first four metal layers are of similar size, the fifth sealing ring wall 1042 and the sixth sealing ring wall 1044 can extend vertically through the first four metal layers. That is, although the metal wires in the higher metal layers (e.g., the fifth or sixth metal layer) may still include the closed-loop metal wires that track the inner ring 104, these metal wires may not be vertically aligned with either the fifth sealing ring wall 1042 or the sixth sealing ring wall 1044.

[0136] Still referencing Figure 8 The fifth sealing ring wall 1042 and the sixth sealing ring wall 1044 are not placed back-to-back, but are intentionally spaced apart. As described above, the metal lines in the interconnect structure are disposed in the inter-metal dielectric layer. When the pattern density (i.e., the density of the metal lines) is low in a local area, it can lead to an uneven surface or depressions during the surface planarization process. To prevent depressions, dummy metal strips can be inserted. In the illustrated embodiment, a plurality of fourth sets of dummy metal strips 1142 are inserted between the fifth sealing ring wall 1042 and the sixth sealing ring wall 1044. Figure 8 In some embodiments shown, dummy metal strips are strategically omitted at the corners of the inner ring 104 to form a second stress-absorbing region 104C. Since the inner ring 104 is substantially rectangular and has four corners, the integrated circuit chip 200 of this disclosure may include four second stress-absorbing regions 104C. The second stress-absorbing regions 104C include a fourth gap 132 between the fifth sealing ring wall 1042 and the sixth sealing ring wall 1044. The fourth gap 132 may be referred to as a gap because it contains no metal lines or dummy metal strips. The fourth gap 132 still includes an inter-metal dielectric layer. In the illustrated embodiment, the fourth gap 132 includes a first inter-metal dielectric layer 202, a second inter-metal dielectric layer 206, a third inter-metal dielectric layer 212, and a fourth inter-metal dielectric layer 218.

[0137] Figure 9 Show along Figure 8 A partial cross-sectional view of the interconnect structure 150, with line D-D' directly above the inner ring 104. Although Figure 9 Showing something similar to Figure 4 The first four metal layers, but the metal lines directly above the inner ring 104 are wider and spaced at a greater interval than the metal lines directly above the device area 102. For example... Figure 9As shown, the first metal layer M0 includes a first inter-metal dielectric layer 202 and a plurality of fifth annular metal lines 404 embedded in the first inter-metal dielectric layer 202. The second metal layer M1 includes a second inter-metal dielectric layer 206 and a plurality of sixth annular metal lines 410 embedded in the second inter-metal dielectric layer 206. The third metal layer M2 includes a third inter-metal dielectric layer 212 and a plurality of seventh annular metal lines 416 embedded in the third inter-metal dielectric layer 212. The fourth metal layer M3 includes a fourth inter-metal dielectric layer 218 and a plurality of eighth annular metal lines 422 embedded in the fourth inter-metal dielectric layer 218.

[0138] The portion of the interconnect structure directly above the inner ring 104 also includes via bars that are vertically coupled to the annular metal wires in each sealing ring wall. The fifth sealing ring wall 1042 includes a plurality of fourth via bars 408 embedded in the second intermetallic dielectric layer 206, a plurality of fifth via bars 414 embedded in the third intermetallic dielectric layer 212, and a plurality of sixth via bars 420 embedded in the fourth intermetallic dielectric layer 218. The via bars differ from metal wires and contact vias. The via bars differ from metal wires because they are narrower to ensure satisfactory placement on the underlying metal wires. The via bars differ from contact vias because they are closed-loop rings surrounding the device region 102, while contact vias resemble vertical cones or cylinders. Contact vias may be present in the portion of the interconnect structure directly above the inner ring 104. For example, the seventh contact via 406 may exist in the second intermetallic dielectric layer 206, the eighth contact via 412 may exist in the third intermetallic dielectric layer 212, and the ninth contact via 418 may exist in the fourth intermetallic dielectric layer 218.

[0139] like Figure 9 As shown, the annular metal wires and through-hole strips can be vertically aligned to define the sealing ring wall surfaces. Regarding the fifth sealing ring wall 1042, the outermost of the annular metal wires 404, 410, 416, and 422 is vertically aligned with the outermost of the through-hole strips 408, 414, and 420 to define an outer wall surface 1042O adjacent to the fourth set of dummy metal strips 1142, and the innermost of the annular metal wires 404, 410, 416, and 422 is vertically aligned with the innermost of the through-hole strips 408, 414, and 420 to define an inner wall surface 1042I. To avoid confusion, the outer wall surface 1042O and the inner wall surface 1042I are continuous and seamless because each annular metal wire and through-hole strip completes a full circle and has a closed loop shape. This also applies to the sixth sealing ring wall 1044. In other words, the sixth sealing ring wall 1044 has an outer wall surface and an inner wall surface defined by an annular metal wire and a through-hole strip, the through-hole strip being substantially perpendicularly aligned with the annular metal wire.

[0140] The annular metal lines in the portion of the interconnect structure 150 above the inner ring 104 are significantly wider than the metal lines directly above the device region 102. In the illustrated embodiment, each fifth annular metal line 404 has a fifth width W5, and the fifth annular metal lines 404 are arranged with a fifth spacing P5. In some embodiments, the ratio of the fifth width W5 to the first width W1 is between about 5 and about 15, and the ratio of the fifth spacing P5 to the first spacing P1 is between about 5 and about 15. In some cases, the fifth width W5 may be between about 100 nanometers and about 250 nanometers, and the fifth spacing P5 may be between about 200 nanometers and about 500 nanometers. To ensure that the via strips can satisfactorily fall on the underlying annular metal lines, the width of the via strips (i.e., the fourth via strip 408, the fifth via strip 414, and the sixth via strip 420) may be between about 50% and about 80% of the fifth width W5. Due to limitations in the shape and patterning method of the contact vias, the width of the contact vias (e.g., the seventh contact via 406, the eighth contact via 412, or the ninth contact via 418) can be between approximately 10% and approximately 30% of the fifth width W5. In one embodiment, the fifth width W5 is the same as the second width W2, and the fifth spacing P5 is the same as the second spacing P2.

[0141] Figure 10 Show along Figure 8 A partial cross-sectional view of the interconnect structure 150 directly above the inner ring 104, with line E-E' in the middle. (Brief reference) Figure 8 The line E-E' forms an angle θ with the X direction, which is 45° in the illustrated embodiment. Each of the fifth sealing ring wall 1042 and the sixth sealing ring wall 1044 includes a segment perpendicular to the line E-E'. The line E-E' passes through the second stress-absorbing region 104C. Figure 10 As shown, the fifth sealing ring wall 1042 and the sixth sealing ring wall 1044 are separated by a fourth gap 132. As described above, the fourth gap 132 is a region where the annular metal wire or dummy metal strip is completely omitted. The fourth gap 132 is filled with a first inter-metal dielectric layer 202, a second inter-metal dielectric layer 206, a third inter-metal dielectric layer 212, and a fourth inter-metal dielectric layer 218. Figure 10 As shown, the fourth gap 132 has a fourth gap width G4. In some embodiments, the fourth gap width G4 may be between about 300 nanometers and about 2000 nanometers (i.e., 2 micrometers). The width range of the fourth gap 132 is not insignificant. When the gap width is less than 300 nanometers, the benefit of such a gap is negligible because this gap width is too similar to the fifth gap P5. When the gap width is greater than 2000 nanometers, the depression at such a gap may become so severe that its adverse effects may outweigh its benefits.

[0142] Experimental results show that implementing the second stress-absorbing region 104C in the interconnect structure 150 above the corner of the inner ring 104 provides satisfactory stress absorption without suffering the adverse effects of reduced pattern density. Several factors are at play. First, it has been observed that stress in monolithic processes is greatest near the corners of the integrated circuit chip 200. Therefore, the second stress-absorbing region 104C, positioned closer to the corner than the device region 102, is appropriately positioned to absorb stress before it begins to affect the device region 102. Second, the corner is further away from the device region 102 or the portion of the interconnect structure 150 above the device region 102. In this way, when the second stress-absorbing region 104C is implemented, recesses or uneven surfaces are formed at locations further away from the semiconductor device, thereby minimizing the adverse effects of the second stress-absorbing region 104C. Because the second stress-absorbing region 104C is closer to the device region 102 or a portion of the interconnect structure 150 above the device region 102, the pattern density in the second stress-absorbing region 104C is greater than the pattern density in the first stress-absorbing region 108C. This is to ensure that the implementation of the second stress-absorbing region 104C does not adversely affect the device region 102. For similar reasons, the fourth gap width G4 can be smaller than the second gap width G2 and the third gap width G3. In some alternative embodiments, the second stress-absorbing region 104C can be omitted entirely.

[0143] According to some embodiments, this disclosure relates to an integrated circuit chip. The integrated circuit chip includes a substrate and a first interconnect layer. The first interconnect layer is located above the substrate and includes a first device region and a first ring region surrounding the first device region. The first ring region includes a first wall and a second wall. The first wall completely surrounds the first device region. The second wall completely surrounds the first device region and the first wall. Along the edge of the first device region, the first wall and the second wall are separated by a first intermetallic dielectric layer and at least one first dummy metal line. Near the corners of the first device region, the first wall and the second wall are separated only by the first intermetallic dielectric layer.

[0144] In some embodiments, the first wall includes a plurality of first sets of metal lines completely surrounding the first device region, and the second wall includes a plurality of second sets of metal lines completely surrounding the first wall. In some embodiments, the first sets of metal lines are laterally connected by a plurality of first sets of lateral connectors, and the second sets of metal lines are laterally connected by a plurality of second sets of lateral connectors. In some embodiments, the integrated circuit chip further includes a second interconnect layer located above the first interconnect layer. The second interconnect layer includes a second device region and a second ring region surrounding the second device region. The second ring region includes a third wall and a fourth wall. The third wall completely surrounds the second device region. The fourth wall completely surrounds the second device region and the third wall. Along the edge of the second device region, the third wall and the fourth wall are separated by a second intermetallic dielectric layer and at least one second dummy metal line. Near the corners of the second device region, the third wall and the fourth wall are separated only by the second intermetallic dielectric layer. In some embodiments, the second device region is directly disposed above the first device region, the second ring region is directly disposed above the first ring region, the third wall is directly disposed above the first wall, and the fourth wall is directly disposed above the second wall. In some embodiments, the third wall includes a plurality of third sets of metal lines completely surrounding the second device region, and the fourth wall includes a plurality of fourth sets of metal lines completely surrounding the third wall. In some embodiments, the first set of metal lines includes a first metal line adjacent to the first device region and a second metal line adjacent to the second wall, and the third set of metal lines includes a third metal line adjacent to the second device region and a fourth metal line adjacent to the fourth wall, wherein the third metal line is directly disposed above the first metal line and the fourth metal line is directly disposed above the second metal line. In some embodiments, the integrated circuit chip further includes a first via strip and a second via strip, wherein the first via strip is disposed between the first metal line and the third metal line, and the second via strip is disposed between the second metal line and the fourth metal line. In some embodiments, the first via strip extends continuously around the first device region, and the second via strip extends continuously around the first device region.

[0145] According to other embodiments, this disclosure relates to an integrated circuit chip. The integrated circuit chip includes an interconnect structure comprising a sealing ring structure. The sealing ring structure includes a first sealing ring wall and a second sealing ring wall. The first sealing ring wall includes four edges and four corners. The second sealing ring wall completely surrounds the first sealing ring wall. Along the four edges of the first sealing ring wall, the first sealing ring wall and the second sealing ring wall are separated by a first intermetallic dielectric layer and at least one first dummy metal line. Along the four corners of the first sealing ring wall, the first sealing ring wall and the second sealing ring wall are separated only by the first intermetallic dielectric layer.

[0146] In some embodiments, the first closed ring wall includes a plurality of first sets of metal wires extending parallel to each other, and the second closed ring wall includes a plurality of second sets of metal wires extending parallel to each other. In some embodiments, the first sets of metal wires are laterally connected by a plurality of first sets of lateral connectors, and the second sets of metal wires are laterally connected by a plurality of second sets of lateral connectors. In some embodiments, the sealing ring structure further includes a third closed ring wall and a fourth closed ring wall. The third closed ring wall is disposed directly above the first closed ring wall and includes four edges and four corners. The fourth closed ring wall is disposed directly above the second closed ring wall. Along the four edges of the third closed ring wall, the third closed ring wall and the fourth closed ring wall are separated by a second intermetallic dielectric layer and at least one second dummy metal wire. Along the four corners of the third closed ring wall, the third closed ring wall and the fourth closed ring wall are separated only by a second intermetallic dielectric layer. In some embodiments, the third closed ring wall includes a plurality of third sets of metal wires extending parallel to each other, and the fourth closed ring wall includes a plurality of fourth sets of metal wires extending parallel to each other. In some embodiments, the first group of metal lines includes a first innermost metal line and a first outermost metal line, and the third group of metal lines includes a second innermost metal line and a second outermost metal line, wherein the second innermost metal line is directly disposed above the first innermost metal line and the second outermost metal line is directly disposed above the first outermost metal line. In some embodiments, the integrated circuit chip further includes a first through-hole strip and a second through-hole strip. The first through-hole strip is disposed between the second innermost metal line and the first innermost metal line. The second through-hole strip and the second through-hole strip are disposed between the second outermost metal line and the first outermost metal line.

[0147] According to some other embodiments, this disclosure relates to an integrated circuit chip. The integrated circuit chip includes a substrate and a first interconnect layer. The substrate includes a device region and a ring region surrounding the device region. The first interconnect layer is disposed on the substrate and includes a first region and a second region. The first region is disposed directly above the device region. The second region is disposed directly above the ring region. The second region includes a closed rectangular ring with four corners, and the second region includes four stress-absorbing regions at the four corners.

[0148] In some embodiments, the first region includes a plurality of first groups of metal wires, and the second region includes a plurality of second groups of metal wires, wherein the ratio of the width of the second group of metal wires to the width of the first group of metal wires is between 5 and about 15. In some embodiments, the first group of metal wires includes a first spacing, and the second group of metal wires includes a second spacing, wherein the ratio of the second spacing to the first spacing is between 5 and about 15. In some embodiments, each of the four stress-absorbing regions has a width equal to or greater than twice the width of the second spacing and contains no metal wires.

[0149] The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope.

Claims

1. An integrated circuit chip, comprising: One substrate; as well as A first interconnect layer is located above the substrate and includes a first device region and a first ring region surrounding the first device region, the first ring region including: A first wall completely surrounds the area of ​​the first device; as well as A second wall completely surrounds the first device area and the first wall, wherein along an edge of the first device area, the first wall and the second wall are separated by a first intermetallic dielectric layer and at least a first dummy metal line, wherein near a corner of the first device area, the first wall and the second wall are separated only by the first intermetallic dielectric layer, wherein at the edge and corner of the first device area, the distance between the first wall and the second wall is consistent.

2. The integrated circuit chip of claim 1, wherein the first wall comprises a plurality of first sets of metal lines completely surrounding the first device region, and wherein the second wall comprises a plurality of second sets of metal lines completely surrounding the first wall.

3. The integrated circuit chip as claimed in claim 2, wherein the first group of metal lines is laterally connected by a plurality of first group of lateral connectors, and wherein the second group of metal lines is laterally connected by a plurality of second group of lateral connectors.

4. The integrated circuit chip as described in claim 2, further comprising: A second interconnect layer, located above the first interconnect layer, includes a second device region and a second ring region surrounding the second device region, the second ring region including: A third wall, completely surrounding the area of ​​the second device; and A fourth wall completely surrounds the second device area and the third wall, wherein along one edge of the second device area, the third wall and the fourth wall are separated by a second intermetallic dielectric layer and at least one second dummy metal line, wherein near a corner of the second device area, the third wall and the fourth wall are separated only by the second intermetallic dielectric layer.

5. The integrated circuit chip of claim 4, wherein the second device region is directly disposed above the first device region, wherein the second ring region is directly disposed above the first ring region, wherein the third wall is directly disposed above the first wall, and wherein the fourth wall is directly disposed above the second wall.

6. The integrated circuit chip of claim 4, wherein the third wall comprises a plurality of third sets of metal lines completely surrounding the second device region, and wherein the fourth wall comprises a plurality of fourth sets of metal lines completely surrounding the third wall.

7. The integrated circuit chip of claim 6, wherein the first group of metal lines includes a first metal line adjacent to the first device region and a second metal line adjacent to the second wall, wherein the third group of metal lines includes a third metal line adjacent to the second device region and a fourth metal line adjacent to the fourth wall, wherein the third metal line is directly disposed above the first metal line and the fourth metal line is directly disposed above the second metal line.

8. The integrated circuit chip as described in claim 7, further comprising: A first through-hole strip is disposed between the first metal wire and the third metal wire; as well as A second through-hole strip is disposed between the second metal wire and the fourth metal wire.

9. The integrated circuit chip of claim 8, wherein the first via strip extends continuously around the first device region, and wherein the second via strip extends continuously around the first device region.

10. An integrated circuit chip, comprising: An interconnection structure includes a sealing ring structure, the sealing ring structure comprising: A first closed ring wall, comprising four edges and four corners; and A second closed ring wall completely surrounds the first closed ring wall, wherein the first closed ring wall and the second closed ring wall are separated by a first intermetallic dielectric layer and at least a first dummy metal line along the four edges of the first closed ring wall, wherein the first closed ring wall and the second closed ring wall are separated only by the first intermetallic dielectric layer along the four corners of the first closed ring wall, wherein the distance between the first closed ring wall and the second closed ring wall is consistent along the four edges and the four corners of the first closed ring wall.

11. The integrated circuit chip of claim 10, wherein the first closed ring wall comprises a plurality of first sets of metal lines extending parallel to each other, and wherein the second closed ring wall comprises a plurality of second sets of metal lines extending parallel to each other.

12. The integrated circuit chip of claim 11, wherein the first group of metal lines are laterally connected by a plurality of first group of lateral connectors, and wherein the second group of metal lines are laterally connected by a plurality of second group of lateral connectors.

13. The integrated circuit chip of claim 11, wherein the sealing ring structure further comprises: A third closed ring wall is directly disposed above the first closed ring wall and includes four edges and four corners; as well as A fourth closed ring wall is disposed directly above the second closed ring wall, wherein the third closed ring wall and the fourth closed ring wall are separated by a second intermetallic dielectric layer and at least a second dummy metal line along the four edges of the third closed ring wall, wherein the third closed ring wall and the fourth closed ring wall are separated only by the second intermetallic dielectric layer along the four corners of the third closed ring wall.

14. The integrated circuit chip of claim 13, wherein the third closed ring wall comprises a plurality of third sets of metal lines extending parallel to each other, and wherein the fourth closed ring wall comprises a plurality of fourth sets of metal lines extending parallel to each other.

15. The integrated circuit chip of claim 14, wherein the first group of metal lines includes a first innermost metal line and a first outermost metal line, wherein the third group of metal lines includes a second innermost metal line and a second outermost metal line, wherein the second innermost metal line is directly disposed above the first innermost metal line and the second outermost metal line is directly disposed above the first outermost metal line.

16. The integrated circuit chip of claim 15, further comprising: A first through-hole strip is disposed between the second innermost metal wire and the first innermost metal wire; as well as A second through-hole strip is disposed between the second outermost metal wire and the first outermost metal wire.

17. An integrated circuit chip, comprising: A substrate, comprising: A device area; and A ring area, surrounding the area of ​​the device; and A first interconnect layer is disposed on the substrate, the first interconnect layer comprising: A first area, directly positioned above the device area; and A second region, directly positioned above the ring region, wherein the second region comprises a closed rectangular ring with four corners, wherein the second region includes: A first wall, completely surrounding the first area; and A second wall completely surrounds the first region and the first wall, wherein along the four edges of the first region, the first wall and the second wall are separated by a first intermetallic dielectric layer and at least a first dummy metal line, wherein along the four corners of the first region, the first wall and the second wall are separated only by the first intermetallic dielectric layer to form four stress absorption zones, wherein the distance between the first wall and the second wall is consistent along the four edges and the four corners of the first region.

18. The integrated circuit chip of claim 17, wherein the first region includes a plurality of first groups of metal lines, wherein the second region includes a plurality of second groups of metal lines, wherein a ratio of the width of a second group of metal lines to the width of a first group of metal lines is between 5 and 15.

19. The integrated circuit chip of claim 18, wherein the first group of metal lines includes a first spacing, wherein the second group of metal lines includes a second spacing, wherein a ratio of the second spacing to the first spacing is between 5 and 15.

20. The integrated circuit chip of claim 19, wherein each of the four stress-absorbing regions has a width equal to or greater than twice the second spacing, and has no metal lines.

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